drivers/gpio/gpio-pl061.c

   1 /*
   2  * Copyright (C) 2008, 2009 Provigent Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
   9  *
  10  * Data sheet: ARM DDI 0190B, September 2000
  11  */
  12 #include <linux/spinlock.h>
  13 #include <linux/errno.h>
  14 #include <linux/module.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/irqchip/chained_irq.h>
  20 #include <linux/bitops.h>
  21 #include <linux/workqueue.h>
  22 #include <linux/gpio.h>
  23 #include <linux/device.h>
  24 #include <linux/amba/bus.h>
  25 #include <linux/amba/pl061.h>
  26 #include <linux/slab.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/pm.h>
  29
  30 #define GPIODIR 0x400
  31 #define GPIOIS  0x404
  32 #define GPIOIBE 0x408
  33 #define GPIOIEV 0x40C
  34 #define GPIOIE  0x410
  35 #define GPIORIS 0x414
  36 #define GPIOMIS 0x418
  37 #define GPIOIC  0x41C
  38
  39 #define PL061_GPIO_NR   8
  40
  41 #ifdef CONFIG_PM
  42 struct pl061_context_save_regs {
  43         u8 gpio_data;
  44         u8 gpio_dir;
  45         u8 gpio_is;
  46         u8 gpio_ibe;
  47         u8 gpio_iev;
  48         u8 gpio_ie;
  49 };
  50 #endif
  51
  52 struct pl061_gpio {
  53         spinlock_t              lock;
  54
  55         void __iomem            *base;
  56         struct irq_domain       *domain;
  57         struct gpio_chip        gc;
  58
  59 #ifdef CONFIG_PM
  60         struct pl061_context_save_regs csave_regs;
  61 #endif
  62 };
  63
  64 static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
  65 {
  66         /*
  67          * Map back to global GPIO space and request muxing, the direction
  68          * parameter does not matter for this controller.
  69          */
  70         int gpio = chip->base + offset;
  71
  72         return pinctrl_request_gpio(gpio);
  73 }
  74
  75 static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
  76 {
  77         int gpio = chip->base + offset;
  78
  79         pinctrl_free_gpio(gpio);
  80 }
  81
  82 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
  83 {
  84         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
  85         unsigned long flags;
  86         unsigned char gpiodir;
  87
  88         if (offset >= gc->ngpio)
  89                 return -EINVAL;
  90
  91         spin_lock_irqsave(&chip->lock, flags);
  92         gpiodir = readb(chip->base + GPIODIR);
  93         gpiodir &= ~(1 << offset);
  94         writeb(gpiodir, chip->base + GPIODIR);
  95         spin_unlock_irqrestore(&chip->lock, flags);
  96
  97         return 0;
  98 }
  99
 100 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
 101                 int value)
 102 {
 103         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 104         unsigned long flags;
 105         unsigned char gpiodir;
 106
 107         if (offset >= gc->ngpio)
 108                 return -EINVAL;
 109
 110         spin_lock_irqsave(&chip->lock, flags);
 111         writeb(!!value << offset, chip->base + (1 << (offset + 2)));
 112         gpiodir = readb(chip->base + GPIODIR);
 113         gpiodir |= 1 << offset;
 114         writeb(gpiodir, chip->base + GPIODIR);
 115
 116         /*
 117          * gpio value is set again, because pl061 doesn't allow to set value of
 118          * a gpio pin before configuring it in OUT mode.
 119          */
 120         writeb(!!value << offset, chip->base + (1 << (offset + 2)));
 121         spin_unlock_irqrestore(&chip->lock, flags);
 122
 123         return 0;
 124 }
 125
 126 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
 127 {
 128         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 129
 130         return !!readb(chip->base + (1 << (offset + 2)));
 131 }
 132
 133 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
 134 {
 135         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 136
 137         writeb(!!value << offset, chip->base + (1 << (offset + 2)));
 138 }
 139
 140 static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
 141 {
 142         struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
 143
 144         return irq_create_mapping(chip->domain, offset);
 145 }
 146
 147 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
 148 {
 149         struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
 150         int offset = irqd_to_hwirq(d);
 151         unsigned long flags;
 152         u8 gpiois, gpioibe, gpioiev;
 153         u8 bit = BIT(offset);
 154
 155         if (offset < 0 || offset >= PL061_GPIO_NR)
 156                 return -EINVAL;
 157
 158         spin_lock_irqsave(&chip->lock, flags);
 159
 160         gpioiev = readb(chip->base + GPIOIEV);
 161         gpiois = readb(chip->base + GPIOIS);
 162         gpioibe = readb(chip->base + GPIOIBE);
 163
 164         if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 165                 gpiois |= bit;
 166                 if (trigger & IRQ_TYPE_LEVEL_HIGH)
 167                         gpioiev |= bit;
 168                 else
 169                         gpioiev &= ~bit;
 170         } else
 171                 gpiois &= ~bit;
 172
 173         if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
 174                 /* Setting this makes GPIOEV be ignored */
 175                 gpioibe |= bit;
 176         else {
 177                 gpioibe &= ~bit;
 178                 if (trigger & IRQ_TYPE_EDGE_RISING)
 179                         gpioiev |= bit;
 180                 else if (trigger & IRQ_TYPE_EDGE_FALLING)
 181                         gpioiev &= ~bit;
 182         }
 183
 184         writeb(gpiois, chip->base + GPIOIS);
 185         writeb(gpioibe, chip->base + GPIOIBE);
 186         writeb(gpioiev, chip->base + GPIOIEV);
 187
 188         spin_unlock_irqrestore(&chip->lock, flags);
 189
 190         return 0;
 191 }
 192
 193 static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
 194 {
 195         unsigned long pending;
 196         int offset;
 197         struct pl061_gpio *chip = irq_desc_get_handler_data(desc);
 198         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 199
 200         chained_irq_enter(irqchip, desc);
 201
 202         pending = readb(chip->base + GPIOMIS);
 203         writeb(pending, chip->base + GPIOIC);
 204         if (pending) {
 205                 for_each_set_bit(offset, &pending, PL061_GPIO_NR)
 206                         generic_handle_irq(pl061_to_irq(&chip->gc, offset));
 207         }
 208
 209         chained_irq_exit(irqchip, desc);
 210 }
 211
 212 static void pl061_irq_mask(struct irq_data *d)
 213 {
 214         struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
 215         u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
 216         u8 gpioie;
 217
 218         spin_lock(&chip->lock);
 219         gpioie = readb(chip->base + GPIOIE) & ~mask;
 220         writeb(gpioie, chip->base + GPIOIE);
 221         spin_unlock(&chip->lock);
 222 }
 223
 224 static void pl061_irq_unmask(struct irq_data *d)
 225 {
 226         struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
 227         u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
 228         u8 gpioie;
 229
 230         spin_lock(&chip->lock);
 231         gpioie = readb(chip->base + GPIOIE) | mask;
 232         writeb(gpioie, chip->base + GPIOIE);
 233         spin_unlock(&chip->lock);
 234 }
 235
 236 static unsigned int pl061_irq_startup(struct irq_data *d)
 237 {
 238         struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
 239
 240         if (gpio_lock_as_irq(&chip->gc, irqd_to_hwirq(d)))
 241                 dev_err(chip->gc.dev,
 242                         "unable to lock HW IRQ %lu for IRQ\n",
 243                         irqd_to_hwirq(d));
 244         pl061_irq_unmask(d);
 245         return 0;
 246 }
 247
 248 static void pl061_irq_shutdown(struct irq_data *d)
 249 {
 250         struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
 251
 252         pl061_irq_mask(d);
 253         gpio_unlock_as_irq(&chip->gc, irqd_to_hwirq(d));
 254 }
 255
 256 static struct irq_chip pl061_irqchip = {
 257         .name           = "pl061 gpio",
 258         .irq_mask       = pl061_irq_mask,
 259         .irq_unmask     = pl061_irq_unmask,
 260         .irq_set_type   = pl061_irq_type,
 261         .irq_startup    = pl061_irq_startup,
 262         .irq_shutdown   = pl061_irq_shutdown,
 263 };
 264
 265 static int pl061_irq_map(struct irq_domain *d, unsigned int irq,
 266                          irq_hw_number_t hwirq)
 267 {
 268         struct pl061_gpio *chip = d->host_data;
 269
 270         irq_set_chip_and_handler_name(irq, &pl061_irqchip, handle_simple_irq,
 271                                       "pl061");
 272         irq_set_chip_data(irq, chip);
 273         irq_set_irq_type(irq, IRQ_TYPE_NONE);
 274
 275         return 0;
 276 }
 277
 278 static const struct irq_domain_ops pl061_domain_ops = {
 279         .map    = pl061_irq_map,
 280         .xlate  = irq_domain_xlate_twocell,
 281 };
 282
 283 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
 284 {
 285         struct device *dev = &adev->dev;
 286         struct pl061_platform_data *pdata = dev_get_platdata(dev);
 287         struct pl061_gpio *chip;
 288         int ret, irq, i, irq_base;
 289
 290         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
 291         if (chip == NULL)
 292                 return -ENOMEM;
 293
 294         if (pdata) {
 295                 chip->gc.base = pdata->gpio_base;
 296                 irq_base = pdata->irq_base;
 297                 if (irq_base <= 0) {
 298                         dev_err(&adev->dev, "invalid IRQ base in pdata\n");
 299                         return -ENODEV;
 300                 }
 301         } else {
 302                 chip->gc.base = -1;
 303                 irq_base = 0;
 304         }
 305
 306         if (!devm_request_mem_region(dev, adev->res.start,
 307                                      resource_size(&adev->res), "pl061")) {
 308                 dev_err(&adev->dev, "no memory region\n");
 309                 return -EBUSY;
 310         }
 311
 312         chip->base = devm_ioremap(dev, adev->res.start,
 313                                   resource_size(&adev->res));
 314         if (!chip->base) {
 315                 dev_err(&adev->dev, "could not remap memory\n");
 316                 return -ENOMEM;
 317         }
 318
 319         spin_lock_init(&chip->lock);
 320
 321         chip->gc.request = pl061_gpio_request;
 322         chip->gc.free = pl061_gpio_free;
 323         chip->gc.direction_input = pl061_direction_input;
 324         chip->gc.direction_output = pl061_direction_output;
 325         chip->gc.get = pl061_get_value;
 326         chip->gc.set = pl061_set_value;
 327         chip->gc.to_irq = pl061_to_irq;
 328         chip->gc.ngpio = PL061_GPIO_NR;
 329         chip->gc.label = dev_name(dev);
 330         chip->gc.dev = dev;
 331         chip->gc.owner = THIS_MODULE;
 332
 333         ret = gpiochip_add(&chip->gc);
 334         if (ret)
 335                 return ret;
 336
 337         /*
 338          * irq_chip support
 339          */
 340         writeb(0, chip->base + GPIOIE); /* disable irqs */
 341         irq = adev->irq[0];
 342         if (irq < 0) {
 343                 dev_err(&adev->dev, "invalid IRQ\n");
 344                 return -ENODEV;
 345         }
 346
 347         irq_set_chained_handler(irq, pl061_irq_handler);
 348         irq_set_handler_data(irq, chip);
 349
 350         chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
 351                                              irq_base, &pl061_domain_ops, chip);
 352         if (!chip->domain) {
 353                 dev_err(&adev->dev, "no irq domain\n");
 354                 return -ENODEV;
 355         }
 356
 357         for (i = 0; i < PL061_GPIO_NR; i++) {
 358                 if (pdata) {
 359                         if (pdata->directions & (1 << i))
 360                                 pl061_direction_output(&chip->gc, i,
 361                                                 pdata->values & (1 << i));
 362                         else
 363                                 pl061_direction_input(&chip->gc, i);
 364                 }
 365         }
 366
 367         amba_set_drvdata(adev, chip);
 368         dev_info(&adev->dev, "PL061 GPIO chip @%08x registered\n",
 369                 adev->res.start);
 370
 371         return 0;
 372 }
 373
 374 #ifdef CONFIG_PM
 375 static int pl061_suspend(struct device *dev)
 376 {
 377         struct pl061_gpio *chip = dev_get_drvdata(dev);
 378         int offset;
 379
 380         chip->csave_regs.gpio_data = 0;
 381         chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
 382         chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
 383         chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
 384         chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
 385         chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
 386
 387         for (offset = 0; offset < PL061_GPIO_NR; offset++) {
 388                 if (chip->csave_regs.gpio_dir & (1 << offset))
 389                         chip->csave_regs.gpio_data |=
 390                                 pl061_get_value(&chip->gc, offset) << offset;
 391         }
 392
 393         return 0;
 394 }
 395
 396 static int pl061_resume(struct device *dev)
 397 {
 398         struct pl061_gpio *chip = dev_get_drvdata(dev);
 399         int offset;
 400
 401         for (offset = 0; offset < PL061_GPIO_NR; offset++) {
 402                 if (chip->csave_regs.gpio_dir & (1 << offset))
 403                         pl061_direction_output(&chip->gc, offset,
 404                                         chip->csave_regs.gpio_data &
 405                                         (1 << offset));
 406                 else
 407                         pl061_direction_input(&chip->gc, offset);
 408         }
 409
 410         writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
 411         writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
 412         writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
 413         writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
 414
 415         return 0;
 416 }
 417
 418 static const struct dev_pm_ops pl061_dev_pm_ops = {
 419         .suspend = pl061_suspend,
 420         .resume = pl061_resume,
 421         .freeze = pl061_suspend,
 422         .restore = pl061_resume,
 423 };
 424 #endif
 425
 426 static struct amba_id pl061_ids[] = {
 427         {
 428                 .id     = 0x00041061,
 429                 .mask   = 0x000fffff,
 430         },
 431         { 0, 0 },
 432 };
 433
 434 MODULE_DEVICE_TABLE(amba, pl061_ids);
 435
 436 static struct amba_driver pl061_gpio_driver = {
 437         .drv = {
 438                 .name   = "pl061_gpio",
 439 #ifdef CONFIG_PM
 440                 .pm     = &pl061_dev_pm_ops,
 441 #endif
 442         },
 443         .id_table       = pl061_ids,
 444         .probe          = pl061_probe,
 445 };
 446
 447 static int __init pl061_gpio_init(void)
 448 {
 449         return amba_driver_register(&pl061_gpio_driver);
 450 }
 451 module_init(pl061_gpio_init);
 452
 453 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
 454 MODULE_DESCRIPTION("PL061 GPIO driver");
 455 MODULE_LICENSE("GPL");