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Merge branch 'for-3.8' of git://linux-nfs.org/~bfields/linux
[deliverable/linux.git] / drivers / gpio / gpio-samsung.c
1 /*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * SAMSUNG - GPIOlib support
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/irq.h>
19 #include <linux/io.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/spinlock.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/ioport.h>
27 #include <linux/of.h>
28 #include <linux/slab.h>
29 #include <linux/of_address.h>
30
31 #include <asm/irq.h>
32
33 #include <mach/hardware.h>
34 #include <mach/map.h>
35 #include <mach/regs-clock.h>
36 #include <mach/regs-gpio.h>
37
38 #include <plat/cpu.h>
39 #include <plat/gpio-core.h>
40 #include <plat/gpio-cfg.h>
41 #include <plat/gpio-cfg-helpers.h>
42 #include <plat/gpio-fns.h>
43 #include <plat/pm.h>
44
45 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
46 unsigned int off, samsung_gpio_pull_t pull)
47 {
48 void __iomem *reg = chip->base + 0x08;
49 int shift = off * 2;
50 u32 pup;
51
52 pup = __raw_readl(reg);
53 pup &= ~(3 << shift);
54 pup |= pull << shift;
55 __raw_writel(pup, reg);
56
57 return 0;
58 }
59
60 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
61 unsigned int off)
62 {
63 void __iomem *reg = chip->base + 0x08;
64 int shift = off * 2;
65 u32 pup = __raw_readl(reg);
66
67 pup >>= shift;
68 pup &= 0x3;
69
70 return (__force samsung_gpio_pull_t)pup;
71 }
72
73 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
74 unsigned int off, samsung_gpio_pull_t pull)
75 {
76 switch (pull) {
77 case S3C_GPIO_PULL_NONE:
78 pull = 0x01;
79 break;
80 case S3C_GPIO_PULL_UP:
81 pull = 0x00;
82 break;
83 case S3C_GPIO_PULL_DOWN:
84 pull = 0x02;
85 break;
86 }
87 return samsung_gpio_setpull_updown(chip, off, pull);
88 }
89
90 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
91 unsigned int off)
92 {
93 samsung_gpio_pull_t pull;
94
95 pull = samsung_gpio_getpull_updown(chip, off);
96
97 switch (pull) {
98 case 0x00:
99 pull = S3C_GPIO_PULL_UP;
100 break;
101 case 0x01:
102 case 0x03:
103 pull = S3C_GPIO_PULL_NONE;
104 break;
105 case 0x02:
106 pull = S3C_GPIO_PULL_DOWN;
107 break;
108 }
109
110 return pull;
111 }
112
113 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
114 unsigned int off, samsung_gpio_pull_t pull,
115 samsung_gpio_pull_t updown)
116 {
117 void __iomem *reg = chip->base + 0x08;
118 u32 pup = __raw_readl(reg);
119
120 if (pull == updown)
121 pup &= ~(1 << off);
122 else if (pull == S3C_GPIO_PULL_NONE)
123 pup |= (1 << off);
124 else
125 return -EINVAL;
126
127 __raw_writel(pup, reg);
128 return 0;
129 }
130
131 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
132 unsigned int off,
133 samsung_gpio_pull_t updown)
134 {
135 void __iomem *reg = chip->base + 0x08;
136 u32 pup = __raw_readl(reg);
137
138 pup &= (1 << off);
139 return pup ? S3C_GPIO_PULL_NONE : updown;
140 }
141
142 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
143 unsigned int off)
144 {
145 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
146 }
147
148 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
149 unsigned int off, samsung_gpio_pull_t pull)
150 {
151 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
152 }
153
154 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
155 unsigned int off)
156 {
157 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
158 }
159
160 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
161 unsigned int off, samsung_gpio_pull_t pull)
162 {
163 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
164 }
165
166 static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
168 {
169 if (pull == S3C_GPIO_PULL_UP)
170 pull = 3;
171
172 return samsung_gpio_setpull_updown(chip, off, pull);
173 }
174
175 static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
176 unsigned int off)
177 {
178 samsung_gpio_pull_t pull;
179
180 pull = samsung_gpio_getpull_updown(chip, off);
181
182 if (pull == 3)
183 pull = S3C_GPIO_PULL_UP;
184
185 return pull;
186 }
187
188 /*
189 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
190 * @chip: The gpio chip that is being configured.
191 * @off: The offset for the GPIO being configured.
192 * @cfg: The configuration value to set.
193 *
194 * This helper deal with the GPIO cases where the control register
195 * has two bits of configuration per gpio, which have the following
196 * functions:
197 * 00 = input
198 * 01 = output
199 * 1x = special function
200 */
201
202 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
203 unsigned int off, unsigned int cfg)
204 {
205 void __iomem *reg = chip->base;
206 unsigned int shift = off * 2;
207 u32 con;
208
209 if (samsung_gpio_is_cfg_special(cfg)) {
210 cfg &= 0xf;
211 if (cfg > 3)
212 return -EINVAL;
213
214 cfg <<= shift;
215 }
216
217 con = __raw_readl(reg);
218 con &= ~(0x3 << shift);
219 con |= cfg;
220 __raw_writel(con, reg);
221
222 return 0;
223 }
224
225 /*
226 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
227 * @chip: The gpio chip that is being configured.
228 * @off: The offset for the GPIO being configured.
229 *
230 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
231 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
232 * S3C_GPIO_SPECIAL() macro.
233 */
234
235 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
236 unsigned int off)
237 {
238 u32 con;
239
240 con = __raw_readl(chip->base);
241 con >>= off * 2;
242 con &= 3;
243
244 /* this conversion works for IN and OUT as well as special mode */
245 return S3C_GPIO_SPECIAL(con);
246 }
247
248 /*
249 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
250 * @chip: The gpio chip that is being configured.
251 * @off: The offset for the GPIO being configured.
252 * @cfg: The configuration value to set.
253 *
254 * This helper deal with the GPIO cases where the control register has 4 bits
255 * of control per GPIO, generally in the form of:
256 * 0000 = Input
257 * 0001 = Output
258 * others = Special functions (dependent on bank)
259 *
260 * Note, since the code to deal with the case where there are two control
261 * registers instead of one, we do not have a separate set of functions for
262 * each case.
263 */
264
265 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
266 unsigned int off, unsigned int cfg)
267 {
268 void __iomem *reg = chip->base;
269 unsigned int shift = (off & 7) * 4;
270 u32 con;
271
272 if (off < 8 && chip->chip.ngpio > 8)
273 reg -= 4;
274
275 if (samsung_gpio_is_cfg_special(cfg)) {
276 cfg &= 0xf;
277 cfg <<= shift;
278 }
279
280 con = __raw_readl(reg);
281 con &= ~(0xf << shift);
282 con |= cfg;
283 __raw_writel(con, reg);
284
285 return 0;
286 }
287
288 /*
289 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
290 * @chip: The gpio chip that is being configured.
291 * @off: The offset for the GPIO being configured.
292 *
293 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
294 * register setting into a value the software can use, such as could be passed
295 * to samsung_gpio_setcfg_4bit().
296 *
297 * @sa samsung_gpio_getcfg_2bit
298 */
299
300 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
301 unsigned int off)
302 {
303 void __iomem *reg = chip->base;
304 unsigned int shift = (off & 7) * 4;
305 u32 con;
306
307 if (off < 8 && chip->chip.ngpio > 8)
308 reg -= 4;
309
310 con = __raw_readl(reg);
311 con >>= shift;
312 con &= 0xf;
313
314 /* this conversion works for IN and OUT as well as special mode */
315 return S3C_GPIO_SPECIAL(con);
316 }
317
318 #ifdef CONFIG_PLAT_S3C24XX
319 /*
320 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
321 * @chip: The gpio chip that is being configured.
322 * @off: The offset for the GPIO being configured.
323 * @cfg: The configuration value to set.
324 *
325 * This helper deal with the GPIO cases where the control register
326 * has one bit of configuration for the gpio, where setting the bit
327 * means the pin is in special function mode and unset means output.
328 */
329
330 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
331 unsigned int off, unsigned int cfg)
332 {
333 void __iomem *reg = chip->base;
334 unsigned int shift = off;
335 u32 con;
336
337 if (samsung_gpio_is_cfg_special(cfg)) {
338 cfg &= 0xf;
339
340 /* Map output to 0, and SFN2 to 1 */
341 cfg -= 1;
342 if (cfg > 1)
343 return -EINVAL;
344
345 cfg <<= shift;
346 }
347
348 con = __raw_readl(reg);
349 con &= ~(0x1 << shift);
350 con |= cfg;
351 __raw_writel(con, reg);
352
353 return 0;
354 }
355
356 /*
357 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
358 * @chip: The gpio chip that is being configured.
359 * @off: The offset for the GPIO being configured.
360 *
361 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
362 * GPIO configuration value.
363 *
364 * @sa samsung_gpio_getcfg_2bit
365 * @sa samsung_gpio_getcfg_4bit
366 */
367
368 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
369 unsigned int off)
370 {
371 u32 con;
372
373 con = __raw_readl(chip->base);
374 con >>= off;
375 con &= 1;
376 con++;
377
378 return S3C_GPIO_SFN(con);
379 }
380 #endif
381
382 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
383 static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
384 unsigned int off, unsigned int cfg)
385 {
386 void __iomem *reg = chip->base;
387 unsigned int shift;
388 u32 con;
389
390 switch (off) {
391 case 0:
392 case 1:
393 case 2:
394 case 3:
395 case 4:
396 case 5:
397 shift = (off & 7) * 4;
398 reg -= 4;
399 break;
400 case 6:
401 shift = ((off + 1) & 7) * 4;
402 reg -= 4;
403 default:
404 shift = ((off + 1) & 7) * 4;
405 break;
406 }
407
408 if (samsung_gpio_is_cfg_special(cfg)) {
409 cfg &= 0xf;
410 cfg <<= shift;
411 }
412
413 con = __raw_readl(reg);
414 con &= ~(0xf << shift);
415 con |= cfg;
416 __raw_writel(con, reg);
417
418 return 0;
419 }
420 #endif
421
422 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
423 int nr_chips)
424 {
425 for (; nr_chips > 0; nr_chips--, chipcfg++) {
426 if (!chipcfg->set_config)
427 chipcfg->set_config = samsung_gpio_setcfg_4bit;
428 if (!chipcfg->get_config)
429 chipcfg->get_config = samsung_gpio_getcfg_4bit;
430 if (!chipcfg->set_pull)
431 chipcfg->set_pull = samsung_gpio_setpull_updown;
432 if (!chipcfg->get_pull)
433 chipcfg->get_pull = samsung_gpio_getpull_updown;
434 }
435 }
436
437 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
438 .set_config = samsung_gpio_setcfg_2bit,
439 .get_config = samsung_gpio_getcfg_2bit,
440 };
441
442 #ifdef CONFIG_PLAT_S3C24XX
443 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
444 .set_config = s3c24xx_gpio_setcfg_abank,
445 .get_config = s3c24xx_gpio_getcfg_abank,
446 };
447 #endif
448
449 #if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
450 static struct samsung_gpio_cfg exynos_gpio_cfg = {
451 .set_pull = exynos_gpio_setpull,
452 .get_pull = exynos_gpio_getpull,
453 .set_config = samsung_gpio_setcfg_4bit,
454 .get_config = samsung_gpio_getcfg_4bit,
455 };
456 #endif
457
458 #if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
459 static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
460 .cfg_eint = 0x3,
461 .set_config = s5p64x0_gpio_setcfg_rbank,
462 .get_config = samsung_gpio_getcfg_4bit,
463 .set_pull = samsung_gpio_setpull_updown,
464 .get_pull = samsung_gpio_getpull_updown,
465 };
466 #endif
467
468 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
469 [0] = {
470 .cfg_eint = 0x0,
471 },
472 [1] = {
473 .cfg_eint = 0x3,
474 },
475 [2] = {
476 .cfg_eint = 0x7,
477 },
478 [3] = {
479 .cfg_eint = 0xF,
480 },
481 [4] = {
482 .cfg_eint = 0x0,
483 .set_config = samsung_gpio_setcfg_2bit,
484 .get_config = samsung_gpio_getcfg_2bit,
485 },
486 [5] = {
487 .cfg_eint = 0x2,
488 .set_config = samsung_gpio_setcfg_2bit,
489 .get_config = samsung_gpio_getcfg_2bit,
490 },
491 [6] = {
492 .cfg_eint = 0x3,
493 .set_config = samsung_gpio_setcfg_2bit,
494 .get_config = samsung_gpio_getcfg_2bit,
495 },
496 [7] = {
497 .set_config = samsung_gpio_setcfg_2bit,
498 .get_config = samsung_gpio_getcfg_2bit,
499 },
500 [8] = {
501 .set_pull = exynos_gpio_setpull,
502 .get_pull = exynos_gpio_getpull,
503 },
504 [9] = {
505 .cfg_eint = 0x3,
506 .set_pull = exynos_gpio_setpull,
507 .get_pull = exynos_gpio_getpull,
508 }
509 };
510
511 /*
512 * Default routines for controlling GPIO, based on the original S3C24XX
513 * GPIO functions which deal with the case where each gpio bank of the
514 * chip is as following:
515 *
516 * base + 0x00: Control register, 2 bits per gpio
517 * gpio n: 2 bits starting at (2*n)
518 * 00 = input, 01 = output, others mean special-function
519 * base + 0x04: Data register, 1 bit per gpio
520 * bit n: data bit n
521 */
522
523 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
524 {
525 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
526 void __iomem *base = ourchip->base;
527 unsigned long flags;
528 unsigned long con;
529
530 samsung_gpio_lock(ourchip, flags);
531
532 con = __raw_readl(base + 0x00);
533 con &= ~(3 << (offset * 2));
534
535 __raw_writel(con, base + 0x00);
536
537 samsung_gpio_unlock(ourchip, flags);
538 return 0;
539 }
540
541 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
542 unsigned offset, int value)
543 {
544 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
545 void __iomem *base = ourchip->base;
546 unsigned long flags;
547 unsigned long dat;
548 unsigned long con;
549
550 samsung_gpio_lock(ourchip, flags);
551
552 dat = __raw_readl(base + 0x04);
553 dat &= ~(1 << offset);
554 if (value)
555 dat |= 1 << offset;
556 __raw_writel(dat, base + 0x04);
557
558 con = __raw_readl(base + 0x00);
559 con &= ~(3 << (offset * 2));
560 con |= 1 << (offset * 2);
561
562 __raw_writel(con, base + 0x00);
563 __raw_writel(dat, base + 0x04);
564
565 samsung_gpio_unlock(ourchip, flags);
566 return 0;
567 }
568
569 /*
570 * The samsung_gpiolib_4bit routines are to control the gpio banks where
571 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
572 * following example:
573 *
574 * base + 0x00: Control register, 4 bits per gpio
575 * gpio n: 4 bits starting at (4*n)
576 * 0000 = input, 0001 = output, others mean special-function
577 * base + 0x04: Data register, 1 bit per gpio
578 * bit n: data bit n
579 *
580 * Note, since the data register is one bit per gpio and is at base + 0x4
581 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
582 * state of the output.
583 */
584
585 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
586 unsigned int offset)
587 {
588 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
589 void __iomem *base = ourchip->base;
590 unsigned long con;
591
592 con = __raw_readl(base + GPIOCON_OFF);
593 if (ourchip->bitmap_gpio_int & BIT(offset))
594 con |= 0xf << con_4bit_shift(offset);
595 else
596 con &= ~(0xf << con_4bit_shift(offset));
597 __raw_writel(con, base + GPIOCON_OFF);
598
599 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
600
601 return 0;
602 }
603
604 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
605 unsigned int offset, int value)
606 {
607 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
608 void __iomem *base = ourchip->base;
609 unsigned long con;
610 unsigned long dat;
611
612 con = __raw_readl(base + GPIOCON_OFF);
613 con &= ~(0xf << con_4bit_shift(offset));
614 con |= 0x1 << con_4bit_shift(offset);
615
616 dat = __raw_readl(base + GPIODAT_OFF);
617
618 if (value)
619 dat |= 1 << offset;
620 else
621 dat &= ~(1 << offset);
622
623 __raw_writel(dat, base + GPIODAT_OFF);
624 __raw_writel(con, base + GPIOCON_OFF);
625 __raw_writel(dat, base + GPIODAT_OFF);
626
627 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
628
629 return 0;
630 }
631
632 /*
633 * The next set of routines are for the case where the GPIO configuration
634 * registers are 4 bits per GPIO but there is more than one register (the
635 * bank has more than 8 GPIOs.
636 *
637 * This case is the similar to the 4 bit case, but the registers are as
638 * follows:
639 *
640 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
641 * gpio n: 4 bits starting at (4*n)
642 * 0000 = input, 0001 = output, others mean special-function
643 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
644 * gpio n: 4 bits starting at (4*n)
645 * 0000 = input, 0001 = output, others mean special-function
646 * base + 0x08: Data register, 1 bit per gpio
647 * bit n: data bit n
648 *
649 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
650 * routines we store the 'base + 0x4' address so that these routines see
651 * the data register at ourchip->base + 0x04.
652 */
653
654 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
655 unsigned int offset)
656 {
657 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
658 void __iomem *base = ourchip->base;
659 void __iomem *regcon = base;
660 unsigned long con;
661
662 if (offset > 7)
663 offset -= 8;
664 else
665 regcon -= 4;
666
667 con = __raw_readl(regcon);
668 con &= ~(0xf << con_4bit_shift(offset));
669 __raw_writel(con, regcon);
670
671 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
672
673 return 0;
674 }
675
676 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
677 unsigned int offset, int value)
678 {
679 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
680 void __iomem *base = ourchip->base;
681 void __iomem *regcon = base;
682 unsigned long con;
683 unsigned long dat;
684 unsigned con_offset = offset;
685
686 if (con_offset > 7)
687 con_offset -= 8;
688 else
689 regcon -= 4;
690
691 con = __raw_readl(regcon);
692 con &= ~(0xf << con_4bit_shift(con_offset));
693 con |= 0x1 << con_4bit_shift(con_offset);
694
695 dat = __raw_readl(base + GPIODAT_OFF);
696
697 if (value)
698 dat |= 1 << offset;
699 else
700 dat &= ~(1 << offset);
701
702 __raw_writel(dat, base + GPIODAT_OFF);
703 __raw_writel(con, regcon);
704 __raw_writel(dat, base + GPIODAT_OFF);
705
706 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
707
708 return 0;
709 }
710
711 #ifdef CONFIG_PLAT_S3C24XX
712 /* The next set of routines are for the case of s3c24xx bank a */
713
714 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
715 {
716 return -EINVAL;
717 }
718
719 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
720 unsigned offset, int value)
721 {
722 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
723 void __iomem *base = ourchip->base;
724 unsigned long flags;
725 unsigned long dat;
726 unsigned long con;
727
728 local_irq_save(flags);
729
730 con = __raw_readl(base + 0x00);
731 dat = __raw_readl(base + 0x04);
732
733 dat &= ~(1 << offset);
734 if (value)
735 dat |= 1 << offset;
736
737 __raw_writel(dat, base + 0x04);
738
739 con &= ~(1 << offset);
740
741 __raw_writel(con, base + 0x00);
742 __raw_writel(dat, base + 0x04);
743
744 local_irq_restore(flags);
745 return 0;
746 }
747 #endif
748
749 /* The next set of routines are for the case of s5p64x0 bank r */
750
751 static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
752 unsigned int offset)
753 {
754 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
755 void __iomem *base = ourchip->base;
756 void __iomem *regcon = base;
757 unsigned long con;
758 unsigned long flags;
759
760 switch (offset) {
761 case 6:
762 offset += 1;
763 case 0:
764 case 1:
765 case 2:
766 case 3:
767 case 4:
768 case 5:
769 regcon -= 4;
770 break;
771 default:
772 offset -= 7;
773 break;
774 }
775
776 samsung_gpio_lock(ourchip, flags);
777
778 con = __raw_readl(regcon);
779 con &= ~(0xf << con_4bit_shift(offset));
780 __raw_writel(con, regcon);
781
782 samsung_gpio_unlock(ourchip, flags);
783
784 return 0;
785 }
786
787 static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
788 unsigned int offset, int value)
789 {
790 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
791 void __iomem *base = ourchip->base;
792 void __iomem *regcon = base;
793 unsigned long con;
794 unsigned long dat;
795 unsigned long flags;
796 unsigned con_offset = offset;
797
798 switch (con_offset) {
799 case 6:
800 con_offset += 1;
801 case 0:
802 case 1:
803 case 2:
804 case 3:
805 case 4:
806 case 5:
807 regcon -= 4;
808 break;
809 default:
810 con_offset -= 7;
811 break;
812 }
813
814 samsung_gpio_lock(ourchip, flags);
815
816 con = __raw_readl(regcon);
817 con &= ~(0xf << con_4bit_shift(con_offset));
818 con |= 0x1 << con_4bit_shift(con_offset);
819
820 dat = __raw_readl(base + GPIODAT_OFF);
821 if (value)
822 dat |= 1 << offset;
823 else
824 dat &= ~(1 << offset);
825
826 __raw_writel(con, regcon);
827 __raw_writel(dat, base + GPIODAT_OFF);
828
829 samsung_gpio_unlock(ourchip, flags);
830
831 return 0;
832 }
833
834 static void samsung_gpiolib_set(struct gpio_chip *chip,
835 unsigned offset, int value)
836 {
837 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
838 void __iomem *base = ourchip->base;
839 unsigned long flags;
840 unsigned long dat;
841
842 samsung_gpio_lock(ourchip, flags);
843
844 dat = __raw_readl(base + 0x04);
845 dat &= ~(1 << offset);
846 if (value)
847 dat |= 1 << offset;
848 __raw_writel(dat, base + 0x04);
849
850 samsung_gpio_unlock(ourchip, flags);
851 }
852
853 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
854 {
855 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
856 unsigned long val;
857
858 val = __raw_readl(ourchip->base + 0x04);
859 val >>= offset;
860 val &= 1;
861
862 return val;
863 }
864
865 /*
866 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
867 * for use with the configuration calls, and other parts of the s3c gpiolib
868 * support code.
869 *
870 * Not all s3c support code will need this, as some configurations of cpu
871 * may only support one or two different configuration options and have an
872 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
873 * the machine support file should provide its own samsung_gpiolib_getchip()
874 * and any other necessary functions.
875 */
876
877 #ifdef CONFIG_S3C_GPIO_TRACK
878 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
879
880 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
881 {
882 unsigned int gpn;
883 int i;
884
885 gpn = chip->chip.base;
886 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
887 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
888 s3c_gpios[gpn] = chip;
889 }
890 }
891 #endif /* CONFIG_S3C_GPIO_TRACK */
892
893 /*
894 * samsung_gpiolib_add() - add the Samsung gpio_chip.
895 * @chip: The chip to register
896 *
897 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
898 * information and makes the necessary alterations for the platform and
899 * notes the information for use with the configuration systems and any
900 * other parts of the system.
901 */
902
903 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
904 {
905 struct gpio_chip *gc = &chip->chip;
906 int ret;
907
908 BUG_ON(!chip->base);
909 BUG_ON(!gc->label);
910 BUG_ON(!gc->ngpio);
911
912 spin_lock_init(&chip->lock);
913
914 if (!gc->direction_input)
915 gc->direction_input = samsung_gpiolib_2bit_input;
916 if (!gc->direction_output)
917 gc->direction_output = samsung_gpiolib_2bit_output;
918 if (!gc->set)
919 gc->set = samsung_gpiolib_set;
920 if (!gc->get)
921 gc->get = samsung_gpiolib_get;
922
923 #ifdef CONFIG_PM
924 if (chip->pm != NULL) {
925 if (!chip->pm->save || !chip->pm->resume)
926 pr_err("gpio: %s has missing PM functions\n",
927 gc->label);
928 } else
929 pr_err("gpio: %s has no PM function\n", gc->label);
930 #endif
931
932 /* gpiochip_add() prints own failure message on error. */
933 ret = gpiochip_add(gc);
934 if (ret >= 0)
935 s3c_gpiolib_track(chip);
936 }
937
938 #if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
939 static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
940 const struct of_phandle_args *gpiospec, u32 *flags)
941 {
942 unsigned int pin;
943
944 if (WARN_ON(gc->of_gpio_n_cells < 3))
945 return -EINVAL;
946
947 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
948 return -EINVAL;
949
950 if (gpiospec->args[0] > gc->ngpio)
951 return -EINVAL;
952
953 pin = gc->base + gpiospec->args[0];
954
955 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
956 pr_warn("gpio_xlate: failed to set pin function\n");
957 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
958 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
959
960 if (flags)
961 *flags = gpiospec->args[2] >> 16;
962
963 return gpiospec->args[0];
964 }
965
966 static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
967 { .compatible = "samsung,s3c24xx-gpio", },
968 {}
969 };
970
971 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
972 u64 base, u64 offset)
973 {
974 struct gpio_chip *gc = &chip->chip;
975 u64 address;
976
977 if (!of_have_populated_dt())
978 return;
979
980 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
981 gc->of_node = of_find_matching_node_by_address(NULL,
982 s3c24xx_gpio_dt_match, address);
983 if (!gc->of_node) {
984 pr_info("gpio: device tree node not found for gpio controller"
985 " with base address %08llx\n", address);
986 return;
987 }
988 gc->of_gpio_n_cells = 3;
989 gc->of_xlate = s3c24xx_gpio_xlate;
990 }
991 #else
992 static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
993 u64 base, u64 offset)
994 {
995 return;
996 }
997 #endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
998
999 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
1000 int nr_chips, void __iomem *base)
1001 {
1002 int i;
1003 struct gpio_chip *gc = &chip->chip;
1004
1005 for (i = 0 ; i < nr_chips; i++, chip++) {
1006 /* skip banks not present on SoC */
1007 if (chip->chip.base >= S3C_GPIO_END)
1008 continue;
1009
1010 if (!chip->config)
1011 chip->config = &s3c24xx_gpiocfg_default;
1012 if (!chip->pm)
1013 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1014 if ((base != NULL) && (chip->base == NULL))
1015 chip->base = base + ((i) * 0x10);
1016
1017 if (!gc->direction_input)
1018 gc->direction_input = samsung_gpiolib_2bit_input;
1019 if (!gc->direction_output)
1020 gc->direction_output = samsung_gpiolib_2bit_output;
1021
1022 samsung_gpiolib_add(chip);
1023
1024 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1025 }
1026 }
1027
1028 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1029 int nr_chips, void __iomem *base,
1030 unsigned int offset)
1031 {
1032 int i;
1033
1034 for (i = 0 ; i < nr_chips; i++, chip++) {
1035 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1036 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1037
1038 if (!chip->config)
1039 chip->config = &samsung_gpio_cfgs[7];
1040 if (!chip->pm)
1041 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1042 if ((base != NULL) && (chip->base == NULL))
1043 chip->base = base + ((i) * offset);
1044
1045 samsung_gpiolib_add(chip);
1046 }
1047 }
1048
1049 /*
1050 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1051 * @chip: The gpio chip that is being configured.
1052 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1053 *
1054 * This helper deal with the GPIO cases where the control register has 4 bits
1055 * of control per GPIO, generally in the form of:
1056 * 0000 = Input
1057 * 0001 = Output
1058 * others = Special functions (dependent on bank)
1059 *
1060 * Note, since the code to deal with the case where there are two control
1061 * registers instead of one, we do not have a separate set of function
1062 * (samsung_gpiolib_add_4bit2_chips)for each case.
1063 */
1064
1065 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1066 int nr_chips, void __iomem *base)
1067 {
1068 int i;
1069
1070 for (i = 0 ; i < nr_chips; i++, chip++) {
1071 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1072 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1073
1074 if (!chip->config)
1075 chip->config = &samsung_gpio_cfgs[2];
1076 if (!chip->pm)
1077 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1078 if ((base != NULL) && (chip->base == NULL))
1079 chip->base = base + ((i) * 0x20);
1080
1081 chip->bitmap_gpio_int = 0;
1082
1083 samsung_gpiolib_add(chip);
1084 }
1085 }
1086
1087 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1088 int nr_chips)
1089 {
1090 for (; nr_chips > 0; nr_chips--, chip++) {
1091 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1092 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1093
1094 if (!chip->config)
1095 chip->config = &samsung_gpio_cfgs[2];
1096 if (!chip->pm)
1097 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1098
1099 samsung_gpiolib_add(chip);
1100 }
1101 }
1102
1103 static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1104 int nr_chips)
1105 {
1106 for (; nr_chips > 0; nr_chips--, chip++) {
1107 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1108 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1109
1110 if (!chip->pm)
1111 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1112
1113 samsung_gpiolib_add(chip);
1114 }
1115 }
1116
1117 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1118 {
1119 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1120
1121 return samsung_chip->irq_base + offset;
1122 }
1123
1124 #ifdef CONFIG_PLAT_S3C24XX
1125 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1126 {
1127 if (offset < 4)
1128 return IRQ_EINT0 + offset;
1129
1130 if (offset < 8)
1131 return IRQ_EINT4 + offset - 4;
1132
1133 return -EINVAL;
1134 }
1135 #endif
1136
1137 #ifdef CONFIG_PLAT_S3C64XX
1138 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1139 {
1140 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1141 }
1142
1143 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1144 {
1145 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1146 }
1147 #endif
1148
1149 struct samsung_gpio_chip s3c24xx_gpios[] = {
1150 #ifdef CONFIG_PLAT_S3C24XX
1151 {
1152 .config = &s3c24xx_gpiocfg_banka,
1153 .chip = {
1154 .base = S3C2410_GPA(0),
1155 .owner = THIS_MODULE,
1156 .label = "GPIOA",
1157 .ngpio = 24,
1158 .direction_input = s3c24xx_gpiolib_banka_input,
1159 .direction_output = s3c24xx_gpiolib_banka_output,
1160 },
1161 }, {
1162 .chip = {
1163 .base = S3C2410_GPB(0),
1164 .owner = THIS_MODULE,
1165 .label = "GPIOB",
1166 .ngpio = 16,
1167 },
1168 }, {
1169 .chip = {
1170 .base = S3C2410_GPC(0),
1171 .owner = THIS_MODULE,
1172 .label = "GPIOC",
1173 .ngpio = 16,
1174 },
1175 }, {
1176 .chip = {
1177 .base = S3C2410_GPD(0),
1178 .owner = THIS_MODULE,
1179 .label = "GPIOD",
1180 .ngpio = 16,
1181 },
1182 }, {
1183 .chip = {
1184 .base = S3C2410_GPE(0),
1185 .label = "GPIOE",
1186 .owner = THIS_MODULE,
1187 .ngpio = 16,
1188 },
1189 }, {
1190 .chip = {
1191 .base = S3C2410_GPF(0),
1192 .owner = THIS_MODULE,
1193 .label = "GPIOF",
1194 .ngpio = 8,
1195 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1196 },
1197 }, {
1198 .irq_base = IRQ_EINT8,
1199 .chip = {
1200 .base = S3C2410_GPG(0),
1201 .owner = THIS_MODULE,
1202 .label = "GPIOG",
1203 .ngpio = 16,
1204 .to_irq = samsung_gpiolib_to_irq,
1205 },
1206 }, {
1207 .chip = {
1208 .base = S3C2410_GPH(0),
1209 .owner = THIS_MODULE,
1210 .label = "GPIOH",
1211 .ngpio = 11,
1212 },
1213 },
1214 /* GPIOS for the S3C2443 and later devices. */
1215 {
1216 .base = S3C2440_GPJCON,
1217 .chip = {
1218 .base = S3C2410_GPJ(0),
1219 .owner = THIS_MODULE,
1220 .label = "GPIOJ",
1221 .ngpio = 16,
1222 },
1223 }, {
1224 .base = S3C2443_GPKCON,
1225 .chip = {
1226 .base = S3C2410_GPK(0),
1227 .owner = THIS_MODULE,
1228 .label = "GPIOK",
1229 .ngpio = 16,
1230 },
1231 }, {
1232 .base = S3C2443_GPLCON,
1233 .chip = {
1234 .base = S3C2410_GPL(0),
1235 .owner = THIS_MODULE,
1236 .label = "GPIOL",
1237 .ngpio = 15,
1238 },
1239 }, {
1240 .base = S3C2443_GPMCON,
1241 .chip = {
1242 .base = S3C2410_GPM(0),
1243 .owner = THIS_MODULE,
1244 .label = "GPIOM",
1245 .ngpio = 2,
1246 },
1247 },
1248 #endif
1249 };
1250
1251 /*
1252 * GPIO bank summary:
1253 *
1254 * Bank GPIOs Style SlpCon ExtInt Group
1255 * A 8 4Bit Yes 1
1256 * B 7 4Bit Yes 1
1257 * C 8 4Bit Yes 2
1258 * D 5 4Bit Yes 3
1259 * E 5 4Bit Yes None
1260 * F 16 2Bit Yes 4 [1]
1261 * G 7 4Bit Yes 5
1262 * H 10 4Bit[2] Yes 6
1263 * I 16 2Bit Yes None
1264 * J 12 2Bit Yes None
1265 * K 16 4Bit[2] No None
1266 * L 15 4Bit[2] No None
1267 * M 6 4Bit No IRQ_EINT
1268 * N 16 2Bit No IRQ_EINT
1269 * O 16 2Bit Yes 7
1270 * P 15 2Bit Yes 8
1271 * Q 9 2Bit Yes 9
1272 *
1273 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1274 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1275 */
1276
1277 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1278 #ifdef CONFIG_PLAT_S3C64XX
1279 {
1280 .chip = {
1281 .base = S3C64XX_GPA(0),
1282 .ngpio = S3C64XX_GPIO_A_NR,
1283 .label = "GPA",
1284 },
1285 }, {
1286 .chip = {
1287 .base = S3C64XX_GPB(0),
1288 .ngpio = S3C64XX_GPIO_B_NR,
1289 .label = "GPB",
1290 },
1291 }, {
1292 .chip = {
1293 .base = S3C64XX_GPC(0),
1294 .ngpio = S3C64XX_GPIO_C_NR,
1295 .label = "GPC",
1296 },
1297 }, {
1298 .chip = {
1299 .base = S3C64XX_GPD(0),
1300 .ngpio = S3C64XX_GPIO_D_NR,
1301 .label = "GPD",
1302 },
1303 }, {
1304 .config = &samsung_gpio_cfgs[0],
1305 .chip = {
1306 .base = S3C64XX_GPE(0),
1307 .ngpio = S3C64XX_GPIO_E_NR,
1308 .label = "GPE",
1309 },
1310 }, {
1311 .base = S3C64XX_GPG_BASE,
1312 .chip = {
1313 .base = S3C64XX_GPG(0),
1314 .ngpio = S3C64XX_GPIO_G_NR,
1315 .label = "GPG",
1316 },
1317 }, {
1318 .base = S3C64XX_GPM_BASE,
1319 .config = &samsung_gpio_cfgs[1],
1320 .chip = {
1321 .base = S3C64XX_GPM(0),
1322 .ngpio = S3C64XX_GPIO_M_NR,
1323 .label = "GPM",
1324 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1325 },
1326 },
1327 #endif
1328 };
1329
1330 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1331 #ifdef CONFIG_PLAT_S3C64XX
1332 {
1333 .base = S3C64XX_GPH_BASE + 0x4,
1334 .chip = {
1335 .base = S3C64XX_GPH(0),
1336 .ngpio = S3C64XX_GPIO_H_NR,
1337 .label = "GPH",
1338 },
1339 }, {
1340 .base = S3C64XX_GPK_BASE + 0x4,
1341 .config = &samsung_gpio_cfgs[0],
1342 .chip = {
1343 .base = S3C64XX_GPK(0),
1344 .ngpio = S3C64XX_GPIO_K_NR,
1345 .label = "GPK",
1346 },
1347 }, {
1348 .base = S3C64XX_GPL_BASE + 0x4,
1349 .config = &samsung_gpio_cfgs[1],
1350 .chip = {
1351 .base = S3C64XX_GPL(0),
1352 .ngpio = S3C64XX_GPIO_L_NR,
1353 .label = "GPL",
1354 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1355 },
1356 },
1357 #endif
1358 };
1359
1360 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1361 #ifdef CONFIG_PLAT_S3C64XX
1362 {
1363 .base = S3C64XX_GPF_BASE,
1364 .config = &samsung_gpio_cfgs[6],
1365 .chip = {
1366 .base = S3C64XX_GPF(0),
1367 .ngpio = S3C64XX_GPIO_F_NR,
1368 .label = "GPF",
1369 },
1370 }, {
1371 .config = &samsung_gpio_cfgs[7],
1372 .chip = {
1373 .base = S3C64XX_GPI(0),
1374 .ngpio = S3C64XX_GPIO_I_NR,
1375 .label = "GPI",
1376 },
1377 }, {
1378 .config = &samsung_gpio_cfgs[7],
1379 .chip = {
1380 .base = S3C64XX_GPJ(0),
1381 .ngpio = S3C64XX_GPIO_J_NR,
1382 .label = "GPJ",
1383 },
1384 }, {
1385 .config = &samsung_gpio_cfgs[6],
1386 .chip = {
1387 .base = S3C64XX_GPO(0),
1388 .ngpio = S3C64XX_GPIO_O_NR,
1389 .label = "GPO",
1390 },
1391 }, {
1392 .config = &samsung_gpio_cfgs[6],
1393 .chip = {
1394 .base = S3C64XX_GPP(0),
1395 .ngpio = S3C64XX_GPIO_P_NR,
1396 .label = "GPP",
1397 },
1398 }, {
1399 .config = &samsung_gpio_cfgs[6],
1400 .chip = {
1401 .base = S3C64XX_GPQ(0),
1402 .ngpio = S3C64XX_GPIO_Q_NR,
1403 .label = "GPQ",
1404 },
1405 }, {
1406 .base = S3C64XX_GPN_BASE,
1407 .irq_base = IRQ_EINT(0),
1408 .config = &samsung_gpio_cfgs[5],
1409 .chip = {
1410 .base = S3C64XX_GPN(0),
1411 .ngpio = S3C64XX_GPIO_N_NR,
1412 .label = "GPN",
1413 .to_irq = samsung_gpiolib_to_irq,
1414 },
1415 },
1416 #endif
1417 };
1418
1419 /*
1420 * S5P6440 GPIO bank summary:
1421 *
1422 * Bank GPIOs Style SlpCon ExtInt Group
1423 * A 6 4Bit Yes 1
1424 * B 7 4Bit Yes 1
1425 * C 8 4Bit Yes 2
1426 * F 2 2Bit Yes 4 [1]
1427 * G 7 4Bit Yes 5
1428 * H 10 4Bit[2] Yes 6
1429 * I 16 2Bit Yes None
1430 * J 12 2Bit Yes None
1431 * N 16 2Bit No IRQ_EINT
1432 * P 8 2Bit Yes 8
1433 * R 15 4Bit[2] Yes 8
1434 */
1435
1436 static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1437 #ifdef CONFIG_CPU_S5P6440
1438 {
1439 .chip = {
1440 .base = S5P6440_GPA(0),
1441 .ngpio = S5P6440_GPIO_A_NR,
1442 .label = "GPA",
1443 },
1444 }, {
1445 .chip = {
1446 .base = S5P6440_GPB(0),
1447 .ngpio = S5P6440_GPIO_B_NR,
1448 .label = "GPB",
1449 },
1450 }, {
1451 .chip = {
1452 .base = S5P6440_GPC(0),
1453 .ngpio = S5P6440_GPIO_C_NR,
1454 .label = "GPC",
1455 },
1456 }, {
1457 .base = S5P64X0_GPG_BASE,
1458 .chip = {
1459 .base = S5P6440_GPG(0),
1460 .ngpio = S5P6440_GPIO_G_NR,
1461 .label = "GPG",
1462 },
1463 },
1464 #endif
1465 };
1466
1467 static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1468 #ifdef CONFIG_CPU_S5P6440
1469 {
1470 .base = S5P64X0_GPH_BASE + 0x4,
1471 .chip = {
1472 .base = S5P6440_GPH(0),
1473 .ngpio = S5P6440_GPIO_H_NR,
1474 .label = "GPH",
1475 },
1476 },
1477 #endif
1478 };
1479
1480 static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1481 #ifdef CONFIG_CPU_S5P6440
1482 {
1483 .base = S5P64X0_GPR_BASE + 0x4,
1484 .config = &s5p64x0_gpio_cfg_rbank,
1485 .chip = {
1486 .base = S5P6440_GPR(0),
1487 .ngpio = S5P6440_GPIO_R_NR,
1488 .label = "GPR",
1489 },
1490 },
1491 #endif
1492 };
1493
1494 static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1495 #ifdef CONFIG_CPU_S5P6440
1496 {
1497 .base = S5P64X0_GPF_BASE,
1498 .config = &samsung_gpio_cfgs[6],
1499 .chip = {
1500 .base = S5P6440_GPF(0),
1501 .ngpio = S5P6440_GPIO_F_NR,
1502 .label = "GPF",
1503 },
1504 }, {
1505 .base = S5P64X0_GPI_BASE,
1506 .config = &samsung_gpio_cfgs[4],
1507 .chip = {
1508 .base = S5P6440_GPI(0),
1509 .ngpio = S5P6440_GPIO_I_NR,
1510 .label = "GPI",
1511 },
1512 }, {
1513 .base = S5P64X0_GPJ_BASE,
1514 .config = &samsung_gpio_cfgs[4],
1515 .chip = {
1516 .base = S5P6440_GPJ(0),
1517 .ngpio = S5P6440_GPIO_J_NR,
1518 .label = "GPJ",
1519 },
1520 }, {
1521 .base = S5P64X0_GPN_BASE,
1522 .config = &samsung_gpio_cfgs[5],
1523 .chip = {
1524 .base = S5P6440_GPN(0),
1525 .ngpio = S5P6440_GPIO_N_NR,
1526 .label = "GPN",
1527 },
1528 }, {
1529 .base = S5P64X0_GPP_BASE,
1530 .config = &samsung_gpio_cfgs[6],
1531 .chip = {
1532 .base = S5P6440_GPP(0),
1533 .ngpio = S5P6440_GPIO_P_NR,
1534 .label = "GPP",
1535 },
1536 },
1537 #endif
1538 };
1539
1540 /*
1541 * S5P6450 GPIO bank summary:
1542 *
1543 * Bank GPIOs Style SlpCon ExtInt Group
1544 * A 6 4Bit Yes 1
1545 * B 7 4Bit Yes 1
1546 * C 8 4Bit Yes 2
1547 * D 8 4Bit Yes None
1548 * F 2 2Bit Yes None
1549 * G 14 4Bit[2] Yes 5
1550 * H 10 4Bit[2] Yes 6
1551 * I 16 2Bit Yes None
1552 * J 12 2Bit Yes None
1553 * K 5 4Bit Yes None
1554 * N 16 2Bit No IRQ_EINT
1555 * P 11 2Bit Yes 8
1556 * Q 14 2Bit Yes None
1557 * R 15 4Bit[2] Yes None
1558 * S 8 2Bit Yes None
1559 *
1560 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1561 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1562 */
1563
1564 static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1565 #ifdef CONFIG_CPU_S5P6450
1566 {
1567 .chip = {
1568 .base = S5P6450_GPA(0),
1569 .ngpio = S5P6450_GPIO_A_NR,
1570 .label = "GPA",
1571 },
1572 }, {
1573 .chip = {
1574 .base = S5P6450_GPB(0),
1575 .ngpio = S5P6450_GPIO_B_NR,
1576 .label = "GPB",
1577 },
1578 }, {
1579 .chip = {
1580 .base = S5P6450_GPC(0),
1581 .ngpio = S5P6450_GPIO_C_NR,
1582 .label = "GPC",
1583 },
1584 }, {
1585 .chip = {
1586 .base = S5P6450_GPD(0),
1587 .ngpio = S5P6450_GPIO_D_NR,
1588 .label = "GPD",
1589 },
1590 }, {
1591 .base = S5P6450_GPK_BASE,
1592 .chip = {
1593 .base = S5P6450_GPK(0),
1594 .ngpio = S5P6450_GPIO_K_NR,
1595 .label = "GPK",
1596 },
1597 },
1598 #endif
1599 };
1600
1601 static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1602 #ifdef CONFIG_CPU_S5P6450
1603 {
1604 .base = S5P64X0_GPG_BASE + 0x4,
1605 .chip = {
1606 .base = S5P6450_GPG(0),
1607 .ngpio = S5P6450_GPIO_G_NR,
1608 .label = "GPG",
1609 },
1610 }, {
1611 .base = S5P64X0_GPH_BASE + 0x4,
1612 .chip = {
1613 .base = S5P6450_GPH(0),
1614 .ngpio = S5P6450_GPIO_H_NR,
1615 .label = "GPH",
1616 },
1617 },
1618 #endif
1619 };
1620
1621 static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1622 #ifdef CONFIG_CPU_S5P6450
1623 {
1624 .base = S5P64X0_GPR_BASE + 0x4,
1625 .config = &s5p64x0_gpio_cfg_rbank,
1626 .chip = {
1627 .base = S5P6450_GPR(0),
1628 .ngpio = S5P6450_GPIO_R_NR,
1629 .label = "GPR",
1630 },
1631 },
1632 #endif
1633 };
1634
1635 static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1636 #ifdef CONFIG_CPU_S5P6450
1637 {
1638 .base = S5P64X0_GPF_BASE,
1639 .config = &samsung_gpio_cfgs[6],
1640 .chip = {
1641 .base = S5P6450_GPF(0),
1642 .ngpio = S5P6450_GPIO_F_NR,
1643 .label = "GPF",
1644 },
1645 }, {
1646 .base = S5P64X0_GPI_BASE,
1647 .config = &samsung_gpio_cfgs[4],
1648 .chip = {
1649 .base = S5P6450_GPI(0),
1650 .ngpio = S5P6450_GPIO_I_NR,
1651 .label = "GPI",
1652 },
1653 }, {
1654 .base = S5P64X0_GPJ_BASE,
1655 .config = &samsung_gpio_cfgs[4],
1656 .chip = {
1657 .base = S5P6450_GPJ(0),
1658 .ngpio = S5P6450_GPIO_J_NR,
1659 .label = "GPJ",
1660 },
1661 }, {
1662 .base = S5P64X0_GPN_BASE,
1663 .config = &samsung_gpio_cfgs[5],
1664 .chip = {
1665 .base = S5P6450_GPN(0),
1666 .ngpio = S5P6450_GPIO_N_NR,
1667 .label = "GPN",
1668 },
1669 }, {
1670 .base = S5P64X0_GPP_BASE,
1671 .config = &samsung_gpio_cfgs[6],
1672 .chip = {
1673 .base = S5P6450_GPP(0),
1674 .ngpio = S5P6450_GPIO_P_NR,
1675 .label = "GPP",
1676 },
1677 }, {
1678 .base = S5P6450_GPQ_BASE,
1679 .config = &samsung_gpio_cfgs[5],
1680 .chip = {
1681 .base = S5P6450_GPQ(0),
1682 .ngpio = S5P6450_GPIO_Q_NR,
1683 .label = "GPQ",
1684 },
1685 }, {
1686 .base = S5P6450_GPS_BASE,
1687 .config = &samsung_gpio_cfgs[6],
1688 .chip = {
1689 .base = S5P6450_GPS(0),
1690 .ngpio = S5P6450_GPIO_S_NR,
1691 .label = "GPS",
1692 },
1693 },
1694 #endif
1695 };
1696
1697 /*
1698 * S5PC100 GPIO bank summary:
1699 *
1700 * Bank GPIOs Style INT Type
1701 * A0 8 4Bit GPIO_INT0
1702 * A1 5 4Bit GPIO_INT1
1703 * B 8 4Bit GPIO_INT2
1704 * C 5 4Bit GPIO_INT3
1705 * D 7 4Bit GPIO_INT4
1706 * E0 8 4Bit GPIO_INT5
1707 * E1 6 4Bit GPIO_INT6
1708 * F0 8 4Bit GPIO_INT7
1709 * F1 8 4Bit GPIO_INT8
1710 * F2 8 4Bit GPIO_INT9
1711 * F3 4 4Bit GPIO_INT10
1712 * G0 8 4Bit GPIO_INT11
1713 * G1 3 4Bit GPIO_INT12
1714 * G2 7 4Bit GPIO_INT13
1715 * G3 7 4Bit GPIO_INT14
1716 * H0 8 4Bit WKUP_INT
1717 * H1 8 4Bit WKUP_INT
1718 * H2 8 4Bit WKUP_INT
1719 * H3 8 4Bit WKUP_INT
1720 * I 8 4Bit GPIO_INT15
1721 * J0 8 4Bit GPIO_INT16
1722 * J1 5 4Bit GPIO_INT17
1723 * J2 8 4Bit GPIO_INT18
1724 * J3 8 4Bit GPIO_INT19
1725 * J4 4 4Bit GPIO_INT20
1726 * K0 8 4Bit None
1727 * K1 6 4Bit None
1728 * K2 8 4Bit None
1729 * K3 8 4Bit None
1730 * L0 8 4Bit None
1731 * L1 8 4Bit None
1732 * L2 8 4Bit None
1733 * L3 8 4Bit None
1734 */
1735
1736 static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1737 #ifdef CONFIG_CPU_S5PC100
1738 {
1739 .chip = {
1740 .base = S5PC100_GPA0(0),
1741 .ngpio = S5PC100_GPIO_A0_NR,
1742 .label = "GPA0",
1743 },
1744 }, {
1745 .chip = {
1746 .base = S5PC100_GPA1(0),
1747 .ngpio = S5PC100_GPIO_A1_NR,
1748 .label = "GPA1",
1749 },
1750 }, {
1751 .chip = {
1752 .base = S5PC100_GPB(0),
1753 .ngpio = S5PC100_GPIO_B_NR,
1754 .label = "GPB",
1755 },
1756 }, {
1757 .chip = {
1758 .base = S5PC100_GPC(0),
1759 .ngpio = S5PC100_GPIO_C_NR,
1760 .label = "GPC",
1761 },
1762 }, {
1763 .chip = {
1764 .base = S5PC100_GPD(0),
1765 .ngpio = S5PC100_GPIO_D_NR,
1766 .label = "GPD",
1767 },
1768 }, {
1769 .chip = {
1770 .base = S5PC100_GPE0(0),
1771 .ngpio = S5PC100_GPIO_E0_NR,
1772 .label = "GPE0",
1773 },
1774 }, {
1775 .chip = {
1776 .base = S5PC100_GPE1(0),
1777 .ngpio = S5PC100_GPIO_E1_NR,
1778 .label = "GPE1",
1779 },
1780 }, {
1781 .chip = {
1782 .base = S5PC100_GPF0(0),
1783 .ngpio = S5PC100_GPIO_F0_NR,
1784 .label = "GPF0",
1785 },
1786 }, {
1787 .chip = {
1788 .base = S5PC100_GPF1(0),
1789 .ngpio = S5PC100_GPIO_F1_NR,
1790 .label = "GPF1",
1791 },
1792 }, {
1793 .chip = {
1794 .base = S5PC100_GPF2(0),
1795 .ngpio = S5PC100_GPIO_F2_NR,
1796 .label = "GPF2",
1797 },
1798 }, {
1799 .chip = {
1800 .base = S5PC100_GPF3(0),
1801 .ngpio = S5PC100_GPIO_F3_NR,
1802 .label = "GPF3",
1803 },
1804 }, {
1805 .chip = {
1806 .base = S5PC100_GPG0(0),
1807 .ngpio = S5PC100_GPIO_G0_NR,
1808 .label = "GPG0",
1809 },
1810 }, {
1811 .chip = {
1812 .base = S5PC100_GPG1(0),
1813 .ngpio = S5PC100_GPIO_G1_NR,
1814 .label = "GPG1",
1815 },
1816 }, {
1817 .chip = {
1818 .base = S5PC100_GPG2(0),
1819 .ngpio = S5PC100_GPIO_G2_NR,
1820 .label = "GPG2",
1821 },
1822 }, {
1823 .chip = {
1824 .base = S5PC100_GPG3(0),
1825 .ngpio = S5PC100_GPIO_G3_NR,
1826 .label = "GPG3",
1827 },
1828 }, {
1829 .chip = {
1830 .base = S5PC100_GPI(0),
1831 .ngpio = S5PC100_GPIO_I_NR,
1832 .label = "GPI",
1833 },
1834 }, {
1835 .chip = {
1836 .base = S5PC100_GPJ0(0),
1837 .ngpio = S5PC100_GPIO_J0_NR,
1838 .label = "GPJ0",
1839 },
1840 }, {
1841 .chip = {
1842 .base = S5PC100_GPJ1(0),
1843 .ngpio = S5PC100_GPIO_J1_NR,
1844 .label = "GPJ1",
1845 },
1846 }, {
1847 .chip = {
1848 .base = S5PC100_GPJ2(0),
1849 .ngpio = S5PC100_GPIO_J2_NR,
1850 .label = "GPJ2",
1851 },
1852 }, {
1853 .chip = {
1854 .base = S5PC100_GPJ3(0),
1855 .ngpio = S5PC100_GPIO_J3_NR,
1856 .label = "GPJ3",
1857 },
1858 }, {
1859 .chip = {
1860 .base = S5PC100_GPJ4(0),
1861 .ngpio = S5PC100_GPIO_J4_NR,
1862 .label = "GPJ4",
1863 },
1864 }, {
1865 .chip = {
1866 .base = S5PC100_GPK0(0),
1867 .ngpio = S5PC100_GPIO_K0_NR,
1868 .label = "GPK0",
1869 },
1870 }, {
1871 .chip = {
1872 .base = S5PC100_GPK1(0),
1873 .ngpio = S5PC100_GPIO_K1_NR,
1874 .label = "GPK1",
1875 },
1876 }, {
1877 .chip = {
1878 .base = S5PC100_GPK2(0),
1879 .ngpio = S5PC100_GPIO_K2_NR,
1880 .label = "GPK2",
1881 },
1882 }, {
1883 .chip = {
1884 .base = S5PC100_GPK3(0),
1885 .ngpio = S5PC100_GPIO_K3_NR,
1886 .label = "GPK3",
1887 },
1888 }, {
1889 .chip = {
1890 .base = S5PC100_GPL0(0),
1891 .ngpio = S5PC100_GPIO_L0_NR,
1892 .label = "GPL0",
1893 },
1894 }, {
1895 .chip = {
1896 .base = S5PC100_GPL1(0),
1897 .ngpio = S5PC100_GPIO_L1_NR,
1898 .label = "GPL1",
1899 },
1900 }, {
1901 .chip = {
1902 .base = S5PC100_GPL2(0),
1903 .ngpio = S5PC100_GPIO_L2_NR,
1904 .label = "GPL2",
1905 },
1906 }, {
1907 .chip = {
1908 .base = S5PC100_GPL3(0),
1909 .ngpio = S5PC100_GPIO_L3_NR,
1910 .label = "GPL3",
1911 },
1912 }, {
1913 .chip = {
1914 .base = S5PC100_GPL4(0),
1915 .ngpio = S5PC100_GPIO_L4_NR,
1916 .label = "GPL4",
1917 },
1918 }, {
1919 .base = (S5P_VA_GPIO + 0xC00),
1920 .irq_base = IRQ_EINT(0),
1921 .chip = {
1922 .base = S5PC100_GPH0(0),
1923 .ngpio = S5PC100_GPIO_H0_NR,
1924 .label = "GPH0",
1925 .to_irq = samsung_gpiolib_to_irq,
1926 },
1927 }, {
1928 .base = (S5P_VA_GPIO + 0xC20),
1929 .irq_base = IRQ_EINT(8),
1930 .chip = {
1931 .base = S5PC100_GPH1(0),
1932 .ngpio = S5PC100_GPIO_H1_NR,
1933 .label = "GPH1",
1934 .to_irq = samsung_gpiolib_to_irq,
1935 },
1936 }, {
1937 .base = (S5P_VA_GPIO + 0xC40),
1938 .irq_base = IRQ_EINT(16),
1939 .chip = {
1940 .base = S5PC100_GPH2(0),
1941 .ngpio = S5PC100_GPIO_H2_NR,
1942 .label = "GPH2",
1943 .to_irq = samsung_gpiolib_to_irq,
1944 },
1945 }, {
1946 .base = (S5P_VA_GPIO + 0xC60),
1947 .irq_base = IRQ_EINT(24),
1948 .chip = {
1949 .base = S5PC100_GPH3(0),
1950 .ngpio = S5PC100_GPIO_H3_NR,
1951 .label = "GPH3",
1952 .to_irq = samsung_gpiolib_to_irq,
1953 },
1954 },
1955 #endif
1956 };
1957
1958 /*
1959 * Followings are the gpio banks in S5PV210/S5PC110
1960 *
1961 * The 'config' member when left to NULL, is initialized to the default
1962 * structure samsung_gpio_cfgs[3] in the init function below.
1963 *
1964 * The 'base' member is also initialized in the init function below.
1965 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1966 * uses the above macro and depends on the banks being listed in order here.
1967 */
1968
1969 static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1970 #ifdef CONFIG_CPU_S5PV210
1971 {
1972 .chip = {
1973 .base = S5PV210_GPA0(0),
1974 .ngpio = S5PV210_GPIO_A0_NR,
1975 .label = "GPA0",
1976 },
1977 }, {
1978 .chip = {
1979 .base = S5PV210_GPA1(0),
1980 .ngpio = S5PV210_GPIO_A1_NR,
1981 .label = "GPA1",
1982 },
1983 }, {
1984 .chip = {
1985 .base = S5PV210_GPB(0),
1986 .ngpio = S5PV210_GPIO_B_NR,
1987 .label = "GPB",
1988 },
1989 }, {
1990 .chip = {
1991 .base = S5PV210_GPC0(0),
1992 .ngpio = S5PV210_GPIO_C0_NR,
1993 .label = "GPC0",
1994 },
1995 }, {
1996 .chip = {
1997 .base = S5PV210_GPC1(0),
1998 .ngpio = S5PV210_GPIO_C1_NR,
1999 .label = "GPC1",
2000 },
2001 }, {
2002 .chip = {
2003 .base = S5PV210_GPD0(0),
2004 .ngpio = S5PV210_GPIO_D0_NR,
2005 .label = "GPD0",
2006 },
2007 }, {
2008 .chip = {
2009 .base = S5PV210_GPD1(0),
2010 .ngpio = S5PV210_GPIO_D1_NR,
2011 .label = "GPD1",
2012 },
2013 }, {
2014 .chip = {
2015 .base = S5PV210_GPE0(0),
2016 .ngpio = S5PV210_GPIO_E0_NR,
2017 .label = "GPE0",
2018 },
2019 }, {
2020 .chip = {
2021 .base = S5PV210_GPE1(0),
2022 .ngpio = S5PV210_GPIO_E1_NR,
2023 .label = "GPE1",
2024 },
2025 }, {
2026 .chip = {
2027 .base = S5PV210_GPF0(0),
2028 .ngpio = S5PV210_GPIO_F0_NR,
2029 .label = "GPF0",
2030 },
2031 }, {
2032 .chip = {
2033 .base = S5PV210_GPF1(0),
2034 .ngpio = S5PV210_GPIO_F1_NR,
2035 .label = "GPF1",
2036 },
2037 }, {
2038 .chip = {
2039 .base = S5PV210_GPF2(0),
2040 .ngpio = S5PV210_GPIO_F2_NR,
2041 .label = "GPF2",
2042 },
2043 }, {
2044 .chip = {
2045 .base = S5PV210_GPF3(0),
2046 .ngpio = S5PV210_GPIO_F3_NR,
2047 .label = "GPF3",
2048 },
2049 }, {
2050 .chip = {
2051 .base = S5PV210_GPG0(0),
2052 .ngpio = S5PV210_GPIO_G0_NR,
2053 .label = "GPG0",
2054 },
2055 }, {
2056 .chip = {
2057 .base = S5PV210_GPG1(0),
2058 .ngpio = S5PV210_GPIO_G1_NR,
2059 .label = "GPG1",
2060 },
2061 }, {
2062 .chip = {
2063 .base = S5PV210_GPG2(0),
2064 .ngpio = S5PV210_GPIO_G2_NR,
2065 .label = "GPG2",
2066 },
2067 }, {
2068 .chip = {
2069 .base = S5PV210_GPG3(0),
2070 .ngpio = S5PV210_GPIO_G3_NR,
2071 .label = "GPG3",
2072 },
2073 }, {
2074 .chip = {
2075 .base = S5PV210_GPI(0),
2076 .ngpio = S5PV210_GPIO_I_NR,
2077 .label = "GPI",
2078 },
2079 }, {
2080 .chip = {
2081 .base = S5PV210_GPJ0(0),
2082 .ngpio = S5PV210_GPIO_J0_NR,
2083 .label = "GPJ0",
2084 },
2085 }, {
2086 .chip = {
2087 .base = S5PV210_GPJ1(0),
2088 .ngpio = S5PV210_GPIO_J1_NR,
2089 .label = "GPJ1",
2090 },
2091 }, {
2092 .chip = {
2093 .base = S5PV210_GPJ2(0),
2094 .ngpio = S5PV210_GPIO_J2_NR,
2095 .label = "GPJ2",
2096 },
2097 }, {
2098 .chip = {
2099 .base = S5PV210_GPJ3(0),
2100 .ngpio = S5PV210_GPIO_J3_NR,
2101 .label = "GPJ3",
2102 },
2103 }, {
2104 .chip = {
2105 .base = S5PV210_GPJ4(0),
2106 .ngpio = S5PV210_GPIO_J4_NR,
2107 .label = "GPJ4",
2108 },
2109 }, {
2110 .chip = {
2111 .base = S5PV210_MP01(0),
2112 .ngpio = S5PV210_GPIO_MP01_NR,
2113 .label = "MP01",
2114 },
2115 }, {
2116 .chip = {
2117 .base = S5PV210_MP02(0),
2118 .ngpio = S5PV210_GPIO_MP02_NR,
2119 .label = "MP02",
2120 },
2121 }, {
2122 .chip = {
2123 .base = S5PV210_MP03(0),
2124 .ngpio = S5PV210_GPIO_MP03_NR,
2125 .label = "MP03",
2126 },
2127 }, {
2128 .chip = {
2129 .base = S5PV210_MP04(0),
2130 .ngpio = S5PV210_GPIO_MP04_NR,
2131 .label = "MP04",
2132 },
2133 }, {
2134 .chip = {
2135 .base = S5PV210_MP05(0),
2136 .ngpio = S5PV210_GPIO_MP05_NR,
2137 .label = "MP05",
2138 },
2139 }, {
2140 .base = (S5P_VA_GPIO + 0xC00),
2141 .irq_base = IRQ_EINT(0),
2142 .chip = {
2143 .base = S5PV210_GPH0(0),
2144 .ngpio = S5PV210_GPIO_H0_NR,
2145 .label = "GPH0",
2146 .to_irq = samsung_gpiolib_to_irq,
2147 },
2148 }, {
2149 .base = (S5P_VA_GPIO + 0xC20),
2150 .irq_base = IRQ_EINT(8),
2151 .chip = {
2152 .base = S5PV210_GPH1(0),
2153 .ngpio = S5PV210_GPIO_H1_NR,
2154 .label = "GPH1",
2155 .to_irq = samsung_gpiolib_to_irq,
2156 },
2157 }, {
2158 .base = (S5P_VA_GPIO + 0xC40),
2159 .irq_base = IRQ_EINT(16),
2160 .chip = {
2161 .base = S5PV210_GPH2(0),
2162 .ngpio = S5PV210_GPIO_H2_NR,
2163 .label = "GPH2",
2164 .to_irq = samsung_gpiolib_to_irq,
2165 },
2166 }, {
2167 .base = (S5P_VA_GPIO + 0xC60),
2168 .irq_base = IRQ_EINT(24),
2169 .chip = {
2170 .base = S5PV210_GPH3(0),
2171 .ngpio = S5PV210_GPIO_H3_NR,
2172 .label = "GPH3",
2173 .to_irq = samsung_gpiolib_to_irq,
2174 },
2175 },
2176 #endif
2177 };
2178
2179 /*
2180 * Followings are the gpio banks in EXYNOS SoCs
2181 *
2182 * The 'config' member when left to NULL, is initialized to the default
2183 * structure exynos_gpio_cfg in the init function below.
2184 *
2185 * The 'base' member is also initialized in the init function below.
2186 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2187 * uses the above macro and depends on the banks being listed in order here.
2188 */
2189
2190 #ifdef CONFIG_ARCH_EXYNOS4
2191 static struct samsung_gpio_chip exynos4_gpios_1[] = {
2192 {
2193 .chip = {
2194 .base = EXYNOS4_GPA0(0),
2195 .ngpio = EXYNOS4_GPIO_A0_NR,
2196 .label = "GPA0",
2197 },
2198 }, {
2199 .chip = {
2200 .base = EXYNOS4_GPA1(0),
2201 .ngpio = EXYNOS4_GPIO_A1_NR,
2202 .label = "GPA1",
2203 },
2204 }, {
2205 .chip = {
2206 .base = EXYNOS4_GPB(0),
2207 .ngpio = EXYNOS4_GPIO_B_NR,
2208 .label = "GPB",
2209 },
2210 }, {
2211 .chip = {
2212 .base = EXYNOS4_GPC0(0),
2213 .ngpio = EXYNOS4_GPIO_C0_NR,
2214 .label = "GPC0",
2215 },
2216 }, {
2217 .chip = {
2218 .base = EXYNOS4_GPC1(0),
2219 .ngpio = EXYNOS4_GPIO_C1_NR,
2220 .label = "GPC1",
2221 },
2222 }, {
2223 .chip = {
2224 .base = EXYNOS4_GPD0(0),
2225 .ngpio = EXYNOS4_GPIO_D0_NR,
2226 .label = "GPD0",
2227 },
2228 }, {
2229 .chip = {
2230 .base = EXYNOS4_GPD1(0),
2231 .ngpio = EXYNOS4_GPIO_D1_NR,
2232 .label = "GPD1",
2233 },
2234 }, {
2235 .chip = {
2236 .base = EXYNOS4_GPE0(0),
2237 .ngpio = EXYNOS4_GPIO_E0_NR,
2238 .label = "GPE0",
2239 },
2240 }, {
2241 .chip = {
2242 .base = EXYNOS4_GPE1(0),
2243 .ngpio = EXYNOS4_GPIO_E1_NR,
2244 .label = "GPE1",
2245 },
2246 }, {
2247 .chip = {
2248 .base = EXYNOS4_GPE2(0),
2249 .ngpio = EXYNOS4_GPIO_E2_NR,
2250 .label = "GPE2",
2251 },
2252 }, {
2253 .chip = {
2254 .base = EXYNOS4_GPE3(0),
2255 .ngpio = EXYNOS4_GPIO_E3_NR,
2256 .label = "GPE3",
2257 },
2258 }, {
2259 .chip = {
2260 .base = EXYNOS4_GPE4(0),
2261 .ngpio = EXYNOS4_GPIO_E4_NR,
2262 .label = "GPE4",
2263 },
2264 }, {
2265 .chip = {
2266 .base = EXYNOS4_GPF0(0),
2267 .ngpio = EXYNOS4_GPIO_F0_NR,
2268 .label = "GPF0",
2269 },
2270 }, {
2271 .chip = {
2272 .base = EXYNOS4_GPF1(0),
2273 .ngpio = EXYNOS4_GPIO_F1_NR,
2274 .label = "GPF1",
2275 },
2276 }, {
2277 .chip = {
2278 .base = EXYNOS4_GPF2(0),
2279 .ngpio = EXYNOS4_GPIO_F2_NR,
2280 .label = "GPF2",
2281 },
2282 }, {
2283 .chip = {
2284 .base = EXYNOS4_GPF3(0),
2285 .ngpio = EXYNOS4_GPIO_F3_NR,
2286 .label = "GPF3",
2287 },
2288 },
2289 };
2290 #endif
2291
2292 #ifdef CONFIG_ARCH_EXYNOS4
2293 static struct samsung_gpio_chip exynos4_gpios_2[] = {
2294 {
2295 .chip = {
2296 .base = EXYNOS4_GPJ0(0),
2297 .ngpio = EXYNOS4_GPIO_J0_NR,
2298 .label = "GPJ0",
2299 },
2300 }, {
2301 .chip = {
2302 .base = EXYNOS4_GPJ1(0),
2303 .ngpio = EXYNOS4_GPIO_J1_NR,
2304 .label = "GPJ1",
2305 },
2306 }, {
2307 .chip = {
2308 .base = EXYNOS4_GPK0(0),
2309 .ngpio = EXYNOS4_GPIO_K0_NR,
2310 .label = "GPK0",
2311 },
2312 }, {
2313 .chip = {
2314 .base = EXYNOS4_GPK1(0),
2315 .ngpio = EXYNOS4_GPIO_K1_NR,
2316 .label = "GPK1",
2317 },
2318 }, {
2319 .chip = {
2320 .base = EXYNOS4_GPK2(0),
2321 .ngpio = EXYNOS4_GPIO_K2_NR,
2322 .label = "GPK2",
2323 },
2324 }, {
2325 .chip = {
2326 .base = EXYNOS4_GPK3(0),
2327 .ngpio = EXYNOS4_GPIO_K3_NR,
2328 .label = "GPK3",
2329 },
2330 }, {
2331 .chip = {
2332 .base = EXYNOS4_GPL0(0),
2333 .ngpio = EXYNOS4_GPIO_L0_NR,
2334 .label = "GPL0",
2335 },
2336 }, {
2337 .chip = {
2338 .base = EXYNOS4_GPL1(0),
2339 .ngpio = EXYNOS4_GPIO_L1_NR,
2340 .label = "GPL1",
2341 },
2342 }, {
2343 .chip = {
2344 .base = EXYNOS4_GPL2(0),
2345 .ngpio = EXYNOS4_GPIO_L2_NR,
2346 .label = "GPL2",
2347 },
2348 }, {
2349 .config = &samsung_gpio_cfgs[8],
2350 .chip = {
2351 .base = EXYNOS4_GPY0(0),
2352 .ngpio = EXYNOS4_GPIO_Y0_NR,
2353 .label = "GPY0",
2354 },
2355 }, {
2356 .config = &samsung_gpio_cfgs[8],
2357 .chip = {
2358 .base = EXYNOS4_GPY1(0),
2359 .ngpio = EXYNOS4_GPIO_Y1_NR,
2360 .label = "GPY1",
2361 },
2362 }, {
2363 .config = &samsung_gpio_cfgs[8],
2364 .chip = {
2365 .base = EXYNOS4_GPY2(0),
2366 .ngpio = EXYNOS4_GPIO_Y2_NR,
2367 .label = "GPY2",
2368 },
2369 }, {
2370 .config = &samsung_gpio_cfgs[8],
2371 .chip = {
2372 .base = EXYNOS4_GPY3(0),
2373 .ngpio = EXYNOS4_GPIO_Y3_NR,
2374 .label = "GPY3",
2375 },
2376 }, {
2377 .config = &samsung_gpio_cfgs[8],
2378 .chip = {
2379 .base = EXYNOS4_GPY4(0),
2380 .ngpio = EXYNOS4_GPIO_Y4_NR,
2381 .label = "GPY4",
2382 },
2383 }, {
2384 .config = &samsung_gpio_cfgs[8],
2385 .chip = {
2386 .base = EXYNOS4_GPY5(0),
2387 .ngpio = EXYNOS4_GPIO_Y5_NR,
2388 .label = "GPY5",
2389 },
2390 }, {
2391 .config = &samsung_gpio_cfgs[8],
2392 .chip = {
2393 .base = EXYNOS4_GPY6(0),
2394 .ngpio = EXYNOS4_GPIO_Y6_NR,
2395 .label = "GPY6",
2396 },
2397 }, {
2398 .config = &samsung_gpio_cfgs[9],
2399 .irq_base = IRQ_EINT(0),
2400 .chip = {
2401 .base = EXYNOS4_GPX0(0),
2402 .ngpio = EXYNOS4_GPIO_X0_NR,
2403 .label = "GPX0",
2404 .to_irq = samsung_gpiolib_to_irq,
2405 },
2406 }, {
2407 .config = &samsung_gpio_cfgs[9],
2408 .irq_base = IRQ_EINT(8),
2409 .chip = {
2410 .base = EXYNOS4_GPX1(0),
2411 .ngpio = EXYNOS4_GPIO_X1_NR,
2412 .label = "GPX1",
2413 .to_irq = samsung_gpiolib_to_irq,
2414 },
2415 }, {
2416 .config = &samsung_gpio_cfgs[9],
2417 .irq_base = IRQ_EINT(16),
2418 .chip = {
2419 .base = EXYNOS4_GPX2(0),
2420 .ngpio = EXYNOS4_GPIO_X2_NR,
2421 .label = "GPX2",
2422 .to_irq = samsung_gpiolib_to_irq,
2423 },
2424 }, {
2425 .config = &samsung_gpio_cfgs[9],
2426 .irq_base = IRQ_EINT(24),
2427 .chip = {
2428 .base = EXYNOS4_GPX3(0),
2429 .ngpio = EXYNOS4_GPIO_X3_NR,
2430 .label = "GPX3",
2431 .to_irq = samsung_gpiolib_to_irq,
2432 },
2433 },
2434 };
2435 #endif
2436
2437 #ifdef CONFIG_ARCH_EXYNOS4
2438 static struct samsung_gpio_chip exynos4_gpios_3[] = {
2439 {
2440 .chip = {
2441 .base = EXYNOS4_GPZ(0),
2442 .ngpio = EXYNOS4_GPIO_Z_NR,
2443 .label = "GPZ",
2444 },
2445 },
2446 };
2447 #endif
2448
2449 #ifdef CONFIG_ARCH_EXYNOS5
2450 static struct samsung_gpio_chip exynos5_gpios_1[] = {
2451 {
2452 .chip = {
2453 .base = EXYNOS5_GPA0(0),
2454 .ngpio = EXYNOS5_GPIO_A0_NR,
2455 .label = "GPA0",
2456 },
2457 }, {
2458 .chip = {
2459 .base = EXYNOS5_GPA1(0),
2460 .ngpio = EXYNOS5_GPIO_A1_NR,
2461 .label = "GPA1",
2462 },
2463 }, {
2464 .chip = {
2465 .base = EXYNOS5_GPA2(0),
2466 .ngpio = EXYNOS5_GPIO_A2_NR,
2467 .label = "GPA2",
2468 },
2469 }, {
2470 .chip = {
2471 .base = EXYNOS5_GPB0(0),
2472 .ngpio = EXYNOS5_GPIO_B0_NR,
2473 .label = "GPB0",
2474 },
2475 }, {
2476 .chip = {
2477 .base = EXYNOS5_GPB1(0),
2478 .ngpio = EXYNOS5_GPIO_B1_NR,
2479 .label = "GPB1",
2480 },
2481 }, {
2482 .chip = {
2483 .base = EXYNOS5_GPB2(0),
2484 .ngpio = EXYNOS5_GPIO_B2_NR,
2485 .label = "GPB2",
2486 },
2487 }, {
2488 .chip = {
2489 .base = EXYNOS5_GPB3(0),
2490 .ngpio = EXYNOS5_GPIO_B3_NR,
2491 .label = "GPB3",
2492 },
2493 }, {
2494 .chip = {
2495 .base = EXYNOS5_GPC0(0),
2496 .ngpio = EXYNOS5_GPIO_C0_NR,
2497 .label = "GPC0",
2498 },
2499 }, {
2500 .chip = {
2501 .base = EXYNOS5_GPC1(0),
2502 .ngpio = EXYNOS5_GPIO_C1_NR,
2503 .label = "GPC1",
2504 },
2505 }, {
2506 .chip = {
2507 .base = EXYNOS5_GPC2(0),
2508 .ngpio = EXYNOS5_GPIO_C2_NR,
2509 .label = "GPC2",
2510 },
2511 }, {
2512 .chip = {
2513 .base = EXYNOS5_GPC3(0),
2514 .ngpio = EXYNOS5_GPIO_C3_NR,
2515 .label = "GPC3",
2516 },
2517 }, {
2518 .chip = {
2519 .base = EXYNOS5_GPD0(0),
2520 .ngpio = EXYNOS5_GPIO_D0_NR,
2521 .label = "GPD0",
2522 },
2523 }, {
2524 .chip = {
2525 .base = EXYNOS5_GPD1(0),
2526 .ngpio = EXYNOS5_GPIO_D1_NR,
2527 .label = "GPD1",
2528 },
2529 }, {
2530 .chip = {
2531 .base = EXYNOS5_GPY0(0),
2532 .ngpio = EXYNOS5_GPIO_Y0_NR,
2533 .label = "GPY0",
2534 },
2535 }, {
2536 .chip = {
2537 .base = EXYNOS5_GPY1(0),
2538 .ngpio = EXYNOS5_GPIO_Y1_NR,
2539 .label = "GPY1",
2540 },
2541 }, {
2542 .chip = {
2543 .base = EXYNOS5_GPY2(0),
2544 .ngpio = EXYNOS5_GPIO_Y2_NR,
2545 .label = "GPY2",
2546 },
2547 }, {
2548 .chip = {
2549 .base = EXYNOS5_GPY3(0),
2550 .ngpio = EXYNOS5_GPIO_Y3_NR,
2551 .label = "GPY3",
2552 },
2553 }, {
2554 .chip = {
2555 .base = EXYNOS5_GPY4(0),
2556 .ngpio = EXYNOS5_GPIO_Y4_NR,
2557 .label = "GPY4",
2558 },
2559 }, {
2560 .chip = {
2561 .base = EXYNOS5_GPY5(0),
2562 .ngpio = EXYNOS5_GPIO_Y5_NR,
2563 .label = "GPY5",
2564 },
2565 }, {
2566 .chip = {
2567 .base = EXYNOS5_GPY6(0),
2568 .ngpio = EXYNOS5_GPIO_Y6_NR,
2569 .label = "GPY6",
2570 },
2571 }, {
2572 .chip = {
2573 .base = EXYNOS5_GPC4(0),
2574 .ngpio = EXYNOS5_GPIO_C4_NR,
2575 .label = "GPC4",
2576 },
2577 }, {
2578 .config = &samsung_gpio_cfgs[9],
2579 .irq_base = IRQ_EINT(0),
2580 .chip = {
2581 .base = EXYNOS5_GPX0(0),
2582 .ngpio = EXYNOS5_GPIO_X0_NR,
2583 .label = "GPX0",
2584 .to_irq = samsung_gpiolib_to_irq,
2585 },
2586 }, {
2587 .config = &samsung_gpio_cfgs[9],
2588 .irq_base = IRQ_EINT(8),
2589 .chip = {
2590 .base = EXYNOS5_GPX1(0),
2591 .ngpio = EXYNOS5_GPIO_X1_NR,
2592 .label = "GPX1",
2593 .to_irq = samsung_gpiolib_to_irq,
2594 },
2595 }, {
2596 .config = &samsung_gpio_cfgs[9],
2597 .irq_base = IRQ_EINT(16),
2598 .chip = {
2599 .base = EXYNOS5_GPX2(0),
2600 .ngpio = EXYNOS5_GPIO_X2_NR,
2601 .label = "GPX2",
2602 .to_irq = samsung_gpiolib_to_irq,
2603 },
2604 }, {
2605 .config = &samsung_gpio_cfgs[9],
2606 .irq_base = IRQ_EINT(24),
2607 .chip = {
2608 .base = EXYNOS5_GPX3(0),
2609 .ngpio = EXYNOS5_GPIO_X3_NR,
2610 .label = "GPX3",
2611 .to_irq = samsung_gpiolib_to_irq,
2612 },
2613 },
2614 };
2615 #endif
2616
2617 #ifdef CONFIG_ARCH_EXYNOS5
2618 static struct samsung_gpio_chip exynos5_gpios_2[] = {
2619 {
2620 .chip = {
2621 .base = EXYNOS5_GPE0(0),
2622 .ngpio = EXYNOS5_GPIO_E0_NR,
2623 .label = "GPE0",
2624 },
2625 }, {
2626 .chip = {
2627 .base = EXYNOS5_GPE1(0),
2628 .ngpio = EXYNOS5_GPIO_E1_NR,
2629 .label = "GPE1",
2630 },
2631 }, {
2632 .chip = {
2633 .base = EXYNOS5_GPF0(0),
2634 .ngpio = EXYNOS5_GPIO_F0_NR,
2635 .label = "GPF0",
2636 },
2637 }, {
2638 .chip = {
2639 .base = EXYNOS5_GPF1(0),
2640 .ngpio = EXYNOS5_GPIO_F1_NR,
2641 .label = "GPF1",
2642 },
2643 }, {
2644 .chip = {
2645 .base = EXYNOS5_GPG0(0),
2646 .ngpio = EXYNOS5_GPIO_G0_NR,
2647 .label = "GPG0",
2648 },
2649 }, {
2650 .chip = {
2651 .base = EXYNOS5_GPG1(0),
2652 .ngpio = EXYNOS5_GPIO_G1_NR,
2653 .label = "GPG1",
2654 },
2655 }, {
2656 .chip = {
2657 .base = EXYNOS5_GPG2(0),
2658 .ngpio = EXYNOS5_GPIO_G2_NR,
2659 .label = "GPG2",
2660 },
2661 }, {
2662 .chip = {
2663 .base = EXYNOS5_GPH0(0),
2664 .ngpio = EXYNOS5_GPIO_H0_NR,
2665 .label = "GPH0",
2666 },
2667 }, {
2668 .chip = {
2669 .base = EXYNOS5_GPH1(0),
2670 .ngpio = EXYNOS5_GPIO_H1_NR,
2671 .label = "GPH1",
2672
2673 },
2674 },
2675 };
2676 #endif
2677
2678 #ifdef CONFIG_ARCH_EXYNOS5
2679 static struct samsung_gpio_chip exynos5_gpios_3[] = {
2680 {
2681 .chip = {
2682 .base = EXYNOS5_GPV0(0),
2683 .ngpio = EXYNOS5_GPIO_V0_NR,
2684 .label = "GPV0",
2685 },
2686 }, {
2687 .chip = {
2688 .base = EXYNOS5_GPV1(0),
2689 .ngpio = EXYNOS5_GPIO_V1_NR,
2690 .label = "GPV1",
2691 },
2692 }, {
2693 .chip = {
2694 .base = EXYNOS5_GPV2(0),
2695 .ngpio = EXYNOS5_GPIO_V2_NR,
2696 .label = "GPV2",
2697 },
2698 }, {
2699 .chip = {
2700 .base = EXYNOS5_GPV3(0),
2701 .ngpio = EXYNOS5_GPIO_V3_NR,
2702 .label = "GPV3",
2703 },
2704 }, {
2705 .chip = {
2706 .base = EXYNOS5_GPV4(0),
2707 .ngpio = EXYNOS5_GPIO_V4_NR,
2708 .label = "GPV4",
2709 },
2710 },
2711 };
2712 #endif
2713
2714 #ifdef CONFIG_ARCH_EXYNOS5
2715 static struct samsung_gpio_chip exynos5_gpios_4[] = {
2716 {
2717 .chip = {
2718 .base = EXYNOS5_GPZ(0),
2719 .ngpio = EXYNOS5_GPIO_Z_NR,
2720 .label = "GPZ",
2721 },
2722 },
2723 };
2724 #endif
2725
2726
2727 #if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2728 static int exynos_gpio_xlate(struct gpio_chip *gc,
2729 const struct of_phandle_args *gpiospec, u32 *flags)
2730 {
2731 unsigned int pin;
2732
2733 if (WARN_ON(gc->of_gpio_n_cells < 4))
2734 return -EINVAL;
2735
2736 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
2737 return -EINVAL;
2738
2739 if (gpiospec->args[0] > gc->ngpio)
2740 return -EINVAL;
2741
2742 pin = gc->base + gpiospec->args[0];
2743
2744 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
2745 pr_warn("gpio_xlate: failed to set pin function\n");
2746 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
2747 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
2748 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
2749 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2750
2751 if (flags)
2752 *flags = gpiospec->args[2] >> 16;
2753
2754 return gpiospec->args[0];
2755 }
2756
2757 static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2758 { .compatible = "samsung,exynos4-gpio", },
2759 {}
2760 };
2761
2762 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2763 u64 base, u64 offset)
2764 {
2765 struct gpio_chip *gc = &chip->chip;
2766 u64 address;
2767
2768 if (!of_have_populated_dt())
2769 return;
2770
2771 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2772 gc->of_node = of_find_matching_node_by_address(NULL,
2773 exynos_gpio_dt_match, address);
2774 if (!gc->of_node) {
2775 pr_info("gpio: device tree node not found for gpio controller"
2776 " with base address %08llx\n", address);
2777 return;
2778 }
2779 gc->of_gpio_n_cells = 4;
2780 gc->of_xlate = exynos_gpio_xlate;
2781 }
2782 #elif defined(CONFIG_ARCH_EXYNOS)
2783 static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2784 u64 base, u64 offset)
2785 {
2786 return;
2787 }
2788 #endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2789
2790 static __init void exynos4_gpiolib_init(void)
2791 {
2792 #ifdef CONFIG_CPU_EXYNOS4210
2793 struct samsung_gpio_chip *chip;
2794 int i, nr_chips;
2795 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2796 int group = 0;
2797 void __iomem *gpx_base;
2798
2799 /* gpio part1 */
2800 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2801 if (gpio_base1 == NULL) {
2802 pr_err("unable to ioremap for gpio_base1\n");
2803 goto err_ioremap1;
2804 }
2805
2806 chip = exynos4_gpios_1;
2807 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2808
2809 for (i = 0; i < nr_chips; i++, chip++) {
2810 if (!chip->config) {
2811 chip->config = &exynos_gpio_cfg;
2812 chip->group = group++;
2813 }
2814 exynos_gpiolib_attach_ofnode(chip,
2815 EXYNOS4_PA_GPIO1, i * 0x20);
2816 }
2817 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2818 nr_chips, gpio_base1);
2819
2820 /* gpio part2 */
2821 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2822 if (gpio_base2 == NULL) {
2823 pr_err("unable to ioremap for gpio_base2\n");
2824 goto err_ioremap2;
2825 }
2826
2827 /* need to set base address for gpx */
2828 chip = &exynos4_gpios_2[16];
2829 gpx_base = gpio_base2 + 0xC00;
2830 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2831 chip->base = gpx_base;
2832
2833 chip = exynos4_gpios_2;
2834 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2835
2836 for (i = 0; i < nr_chips; i++, chip++) {
2837 if (!chip->config) {
2838 chip->config = &exynos_gpio_cfg;
2839 chip->group = group++;
2840 }
2841 exynos_gpiolib_attach_ofnode(chip,
2842 EXYNOS4_PA_GPIO2, i * 0x20);
2843 }
2844 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2845 nr_chips, gpio_base2);
2846
2847 /* gpio part3 */
2848 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2849 if (gpio_base3 == NULL) {
2850 pr_err("unable to ioremap for gpio_base3\n");
2851 goto err_ioremap3;
2852 }
2853
2854 chip = exynos4_gpios_3;
2855 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2856
2857 for (i = 0; i < nr_chips; i++, chip++) {
2858 if (!chip->config) {
2859 chip->config = &exynos_gpio_cfg;
2860 chip->group = group++;
2861 }
2862 exynos_gpiolib_attach_ofnode(chip,
2863 EXYNOS4_PA_GPIO3, i * 0x20);
2864 }
2865 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2866 nr_chips, gpio_base3);
2867
2868 #if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2869 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2870 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2871 #endif
2872
2873 return;
2874
2875 err_ioremap3:
2876 iounmap(gpio_base2);
2877 err_ioremap2:
2878 iounmap(gpio_base1);
2879 err_ioremap1:
2880 return;
2881 #endif /* CONFIG_CPU_EXYNOS4210 */
2882 }
2883
2884 static __init void exynos5_gpiolib_init(void)
2885 {
2886 #ifdef CONFIG_SOC_EXYNOS5250
2887 struct samsung_gpio_chip *chip;
2888 int i, nr_chips;
2889 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2890 int group = 0;
2891 void __iomem *gpx_base;
2892
2893 /* gpio part1 */
2894 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2895 if (gpio_base1 == NULL) {
2896 pr_err("unable to ioremap for gpio_base1\n");
2897 goto err_ioremap1;
2898 }
2899
2900 /* need to set base address for gpc4 */
2901 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
2902
2903 /* need to set base address for gpx */
2904 chip = &exynos5_gpios_1[21];
2905 gpx_base = gpio_base1 + 0xC00;
2906 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2907 chip->base = gpx_base;
2908
2909 chip = exynos5_gpios_1;
2910 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2911
2912 for (i = 0; i < nr_chips; i++, chip++) {
2913 if (!chip->config) {
2914 chip->config = &exynos_gpio_cfg;
2915 chip->group = group++;
2916 }
2917 exynos_gpiolib_attach_ofnode(chip,
2918 EXYNOS5_PA_GPIO1, i * 0x20);
2919 }
2920 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2921 nr_chips, gpio_base1);
2922
2923 /* gpio part2 */
2924 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2925 if (gpio_base2 == NULL) {
2926 pr_err("unable to ioremap for gpio_base2\n");
2927 goto err_ioremap2;
2928 }
2929
2930 chip = exynos5_gpios_2;
2931 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2932
2933 for (i = 0; i < nr_chips; i++, chip++) {
2934 if (!chip->config) {
2935 chip->config = &exynos_gpio_cfg;
2936 chip->group = group++;
2937 }
2938 exynos_gpiolib_attach_ofnode(chip,
2939 EXYNOS5_PA_GPIO2, i * 0x20);
2940 }
2941 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2942 nr_chips, gpio_base2);
2943
2944 /* gpio part3 */
2945 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2946 if (gpio_base3 == NULL) {
2947 pr_err("unable to ioremap for gpio_base3\n");
2948 goto err_ioremap3;
2949 }
2950
2951 /* need to set base address for gpv */
2952 exynos5_gpios_3[0].base = gpio_base3;
2953 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2954 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2955 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2956 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2957
2958 chip = exynos5_gpios_3;
2959 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2960
2961 for (i = 0; i < nr_chips; i++, chip++) {
2962 if (!chip->config) {
2963 chip->config = &exynos_gpio_cfg;
2964 chip->group = group++;
2965 }
2966 exynos_gpiolib_attach_ofnode(chip,
2967 EXYNOS5_PA_GPIO3, i * 0x20);
2968 }
2969 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2970 nr_chips, gpio_base3);
2971
2972 /* gpio part4 */
2973 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2974 if (gpio_base4 == NULL) {
2975 pr_err("unable to ioremap for gpio_base4\n");
2976 goto err_ioremap4;
2977 }
2978
2979 chip = exynos5_gpios_4;
2980 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2981
2982 for (i = 0; i < nr_chips; i++, chip++) {
2983 if (!chip->config) {
2984 chip->config = &exynos_gpio_cfg;
2985 chip->group = group++;
2986 }
2987 exynos_gpiolib_attach_ofnode(chip,
2988 EXYNOS5_PA_GPIO4, i * 0x20);
2989 }
2990 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2991 nr_chips, gpio_base4);
2992 return;
2993
2994 err_ioremap4:
2995 iounmap(gpio_base3);
2996 err_ioremap3:
2997 iounmap(gpio_base2);
2998 err_ioremap2:
2999 iounmap(gpio_base1);
3000 err_ioremap1:
3001 return;
3002
3003 #endif /* CONFIG_SOC_EXYNOS5250 */
3004 }
3005
3006 /* TODO: cleanup soc_is_* */
3007 static __init int samsung_gpiolib_init(void)
3008 {
3009 struct samsung_gpio_chip *chip;
3010 int i, nr_chips;
3011 int group = 0;
3012
3013 #ifdef CONFIG_PINCTRL_SAMSUNG
3014 /*
3015 * This gpio driver includes support for device tree support and there
3016 * are platforms using it. In order to maintain compatibility with those
3017 * platforms, and to allow non-dt Exynos4210 platforms to use this
3018 * gpiolib support, a check is added to find out if there is a active
3019 * pin-controller driver support available. If it is available, this
3020 * gpiolib support is ignored and the gpiolib support available in
3021 * pin-controller driver is used. This is a temporary check and will go
3022 * away when all of the Exynos4210 platforms have switched to using
3023 * device tree and the pin-ctrl driver.
3024 */
3025 struct device_node *pctrl_np;
3026 static const struct of_device_id exynos_pinctrl_ids[] = {
3027 { .compatible = "samsung,pinctrl-exynos4210", },
3028 { .compatible = "samsung,pinctrl-exynos4x12", },
3029 };
3030 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3031 if (pctrl_np && of_device_is_available(pctrl_np))
3032 return -ENODEV;
3033 #endif
3034
3035 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3036
3037 if (soc_is_s3c24xx()) {
3038 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3039 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3040 } else if (soc_is_s3c64xx()) {
3041 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3042 ARRAY_SIZE(s3c64xx_gpios_2bit),
3043 S3C64XX_VA_GPIO + 0xE0, 0x20);
3044 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3045 ARRAY_SIZE(s3c64xx_gpios_4bit),
3046 S3C64XX_VA_GPIO);
3047 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3048 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3049 } else if (soc_is_s5p6440()) {
3050 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3051 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3052 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3053 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3054 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3055 ARRAY_SIZE(s5p6440_gpios_4bit2));
3056 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3057 ARRAY_SIZE(s5p6440_gpios_rbank));
3058 } else if (soc_is_s5p6450()) {
3059 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3060 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3061 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3062 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3063 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3064 ARRAY_SIZE(s5p6450_gpios_4bit2));
3065 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3066 ARRAY_SIZE(s5p6450_gpios_rbank));
3067 } else if (soc_is_s5pc100()) {
3068 group = 0;
3069 chip = s5pc100_gpios_4bit;
3070 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3071
3072 for (i = 0; i < nr_chips; i++, chip++) {
3073 if (!chip->config) {
3074 chip->config = &samsung_gpio_cfgs[3];
3075 chip->group = group++;
3076 }
3077 }
3078 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3079 #if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3080 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3081 #endif
3082 } else if (soc_is_s5pv210()) {
3083 group = 0;
3084 chip = s5pv210_gpios_4bit;
3085 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3086
3087 for (i = 0; i < nr_chips; i++, chip++) {
3088 if (!chip->config) {
3089 chip->config = &samsung_gpio_cfgs[3];
3090 chip->group = group++;
3091 }
3092 }
3093 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3094 #if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3095 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3096 #endif
3097 } else if (soc_is_exynos4210()) {
3098 exynos4_gpiolib_init();
3099 } else if (soc_is_exynos5250()) {
3100 exynos5_gpiolib_init();
3101 } else {
3102 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3103 return -ENODEV;
3104 }
3105
3106 return 0;
3107 }
3108 core_initcall(samsung_gpiolib_init);
3109
3110 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3111 {
3112 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3113 unsigned long flags;
3114 int offset;
3115 int ret;
3116
3117 if (!chip)
3118 return -EINVAL;
3119
3120 offset = pin - chip->chip.base;
3121
3122 samsung_gpio_lock(chip, flags);
3123 ret = samsung_gpio_do_setcfg(chip, offset, config);
3124 samsung_gpio_unlock(chip, flags);
3125
3126 return ret;
3127 }
3128 EXPORT_SYMBOL(s3c_gpio_cfgpin);
3129
3130 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3131 unsigned int cfg)
3132 {
3133 int ret;
3134
3135 for (; nr > 0; nr--, start++) {
3136 ret = s3c_gpio_cfgpin(start, cfg);
3137 if (ret != 0)
3138 return ret;
3139 }
3140
3141 return 0;
3142 }
3143 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3144
3145 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3146 unsigned int cfg, samsung_gpio_pull_t pull)
3147 {
3148 int ret;
3149
3150 for (; nr > 0; nr--, start++) {
3151 s3c_gpio_setpull(start, pull);
3152 ret = s3c_gpio_cfgpin(start, cfg);
3153 if (ret != 0)
3154 return ret;
3155 }
3156
3157 return 0;
3158 }
3159 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3160
3161 unsigned s3c_gpio_getcfg(unsigned int pin)
3162 {
3163 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3164 unsigned long flags;
3165 unsigned ret = 0;
3166 int offset;
3167
3168 if (chip) {
3169 offset = pin - chip->chip.base;
3170
3171 samsung_gpio_lock(chip, flags);
3172 ret = samsung_gpio_do_getcfg(chip, offset);
3173 samsung_gpio_unlock(chip, flags);
3174 }
3175
3176 return ret;
3177 }
3178 EXPORT_SYMBOL(s3c_gpio_getcfg);
3179
3180 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3181 {
3182 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3183 unsigned long flags;
3184 int offset, ret;
3185
3186 if (!chip)
3187 return -EINVAL;
3188
3189 offset = pin - chip->chip.base;
3190
3191 samsung_gpio_lock(chip, flags);
3192 ret = samsung_gpio_do_setpull(chip, offset, pull);
3193 samsung_gpio_unlock(chip, flags);
3194
3195 return ret;
3196 }
3197 EXPORT_SYMBOL(s3c_gpio_setpull);
3198
3199 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3200 {
3201 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3202 unsigned long flags;
3203 int offset;
3204 u32 pup = 0;
3205
3206 if (chip) {
3207 offset = pin - chip->chip.base;
3208
3209 samsung_gpio_lock(chip, flags);
3210 pup = samsung_gpio_do_getpull(chip, offset);
3211 samsung_gpio_unlock(chip, flags);
3212 }
3213
3214 return (__force samsung_gpio_pull_t)pup;
3215 }
3216 EXPORT_SYMBOL(s3c_gpio_getpull);
3217
3218 #ifdef CONFIG_S5P_GPIO_DRVSTR
3219 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3220 {
3221 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3222 unsigned int off;
3223 void __iomem *reg;
3224 int shift;
3225 u32 drvstr;
3226
3227 if (!chip)
3228 return -EINVAL;
3229
3230 off = pin - chip->chip.base;
3231 shift = off * 2;
3232 reg = chip->base + 0x0C;
3233
3234 drvstr = __raw_readl(reg);
3235 drvstr = drvstr >> shift;
3236 drvstr &= 0x3;
3237
3238 return (__force s5p_gpio_drvstr_t)drvstr;
3239 }
3240 EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3241
3242 int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3243 {
3244 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3245 unsigned int off;
3246 void __iomem *reg;
3247 int shift;
3248 u32 tmp;
3249
3250 if (!chip)
3251 return -EINVAL;
3252
3253 off = pin - chip->chip.base;
3254 shift = off * 2;
3255 reg = chip->base + 0x0C;
3256
3257 tmp = __raw_readl(reg);
3258 tmp &= ~(0x3 << shift);
3259 tmp |= drvstr << shift;
3260
3261 __raw_writel(tmp, reg);
3262
3263 return 0;
3264 }
3265 EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3266 #endif /* CONFIG_S5P_GPIO_DRVSTR */
3267
3268 #ifdef CONFIG_PLAT_S3C24XX
3269 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3270 {
3271 unsigned long flags;
3272 unsigned long misccr;
3273
3274 local_irq_save(flags);
3275 misccr = __raw_readl(S3C24XX_MISCCR);
3276 misccr &= ~clear;
3277 misccr ^= change;
3278 __raw_writel(misccr, S3C24XX_MISCCR);
3279 local_irq_restore(flags);
3280
3281 return misccr;
3282 }
3283 EXPORT_SYMBOL(s3c2410_modify_misccr);
3284 #endif
Linux kernel - Deliverables
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