2 * Copyright (C) ST-Ericsson SA 2010
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/gpio.h>
13 #include <linux/interrupt.h>
15 #include <linux/mfd/stmpe.h>
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
21 enum { REG_RE
, REG_FE
, REG_IE
};
23 #define CACHE_NR_REGS 3
24 /* No variant has more than 24 GPIOs */
25 #define CACHE_NR_BANKS (24 / 8)
28 struct gpio_chip chip
;
31 struct mutex irq_lock
;
32 unsigned norequest_mask
;
33 /* Caches of interrupt control registers for bus_lock */
34 u8 regs
[CACHE_NR_REGS
][CACHE_NR_BANKS
];
35 u8 oldregs
[CACHE_NR_REGS
][CACHE_NR_BANKS
];
38 static inline struct stmpe_gpio
*to_stmpe_gpio(struct gpio_chip
*chip
)
40 return container_of(chip
, struct stmpe_gpio
, chip
);
43 static int stmpe_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
45 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(chip
);
46 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
47 u8 reg
= stmpe
->regs
[STMPE_IDX_GPMR_LSB
] - (offset
/ 8);
48 u8 mask
= 1 << (offset
% 8);
51 ret
= stmpe_reg_read(stmpe
, reg
);
55 return !!(ret
& mask
);
58 static void stmpe_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int val
)
60 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(chip
);
61 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
62 int which
= val
? STMPE_IDX_GPSR_LSB
: STMPE_IDX_GPCR_LSB
;
63 u8 reg
= stmpe
->regs
[which
] - (offset
/ 8);
64 u8 mask
= 1 << (offset
% 8);
67 * Some variants have single register for gpio set/clear functionality.
68 * For them we need to write 0 to clear and 1 to set.
70 if (stmpe
->regs
[STMPE_IDX_GPSR_LSB
] == stmpe
->regs
[STMPE_IDX_GPCR_LSB
])
71 stmpe_set_bits(stmpe
, reg
, mask
, val
? mask
: 0);
73 stmpe_reg_write(stmpe
, reg
, mask
);
76 static int stmpe_gpio_direction_output(struct gpio_chip
*chip
,
77 unsigned offset
, int val
)
79 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(chip
);
80 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
81 u8 reg
= stmpe
->regs
[STMPE_IDX_GPDR_LSB
] - (offset
/ 8);
82 u8 mask
= 1 << (offset
% 8);
84 stmpe_gpio_set(chip
, offset
, val
);
86 return stmpe_set_bits(stmpe
, reg
, mask
, mask
);
89 static int stmpe_gpio_direction_input(struct gpio_chip
*chip
,
92 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(chip
);
93 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
94 u8 reg
= stmpe
->regs
[STMPE_IDX_GPDR_LSB
] - (offset
/ 8);
95 u8 mask
= 1 << (offset
% 8);
97 return stmpe_set_bits(stmpe
, reg
, mask
, 0);
100 static int stmpe_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
102 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(chip
);
103 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
105 if (stmpe_gpio
->norequest_mask
& (1 << offset
))
108 return stmpe_set_altfunc(stmpe
, 1 << offset
, STMPE_BLOCK_GPIO
);
111 static struct gpio_chip template_chip
= {
113 .owner
= THIS_MODULE
,
114 .direction_input
= stmpe_gpio_direction_input
,
115 .get
= stmpe_gpio_get
,
116 .direction_output
= stmpe_gpio_direction_output
,
117 .set
= stmpe_gpio_set
,
118 .request
= stmpe_gpio_request
,
122 static int stmpe_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
124 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
125 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(gc
);
126 int offset
= d
->hwirq
;
127 int regoffset
= offset
/ 8;
128 int mask
= 1 << (offset
% 8);
130 if (type
== IRQ_TYPE_LEVEL_LOW
|| type
== IRQ_TYPE_LEVEL_HIGH
)
133 /* STMPE801 doesn't have RE and FE registers */
134 if (stmpe_gpio
->stmpe
->partnum
== STMPE801
)
137 if (type
== IRQ_TYPE_EDGE_RISING
)
138 stmpe_gpio
->regs
[REG_RE
][regoffset
] |= mask
;
140 stmpe_gpio
->regs
[REG_RE
][regoffset
] &= ~mask
;
142 if (type
== IRQ_TYPE_EDGE_FALLING
)
143 stmpe_gpio
->regs
[REG_FE
][regoffset
] |= mask
;
145 stmpe_gpio
->regs
[REG_FE
][regoffset
] &= ~mask
;
150 static void stmpe_gpio_irq_lock(struct irq_data
*d
)
152 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
153 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(gc
);
155 mutex_lock(&stmpe_gpio
->irq_lock
);
158 static void stmpe_gpio_irq_sync_unlock(struct irq_data
*d
)
160 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
161 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(gc
);
162 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
163 int num_banks
= DIV_ROUND_UP(stmpe
->num_gpios
, 8);
164 static const u8 regmap
[] = {
165 [REG_RE
] = STMPE_IDX_GPRER_LSB
,
166 [REG_FE
] = STMPE_IDX_GPFER_LSB
,
167 [REG_IE
] = STMPE_IDX_IEGPIOR_LSB
,
171 for (i
= 0; i
< CACHE_NR_REGS
; i
++) {
172 /* STMPE801 doesn't have RE and FE registers */
173 if ((stmpe
->partnum
== STMPE801
) &&
177 for (j
= 0; j
< num_banks
; j
++) {
178 u8 old
= stmpe_gpio
->oldregs
[i
][j
];
179 u8
new = stmpe_gpio
->regs
[i
][j
];
184 stmpe_gpio
->oldregs
[i
][j
] = new;
185 stmpe_reg_write(stmpe
, stmpe
->regs
[regmap
[i
]] - j
, new);
189 mutex_unlock(&stmpe_gpio
->irq_lock
);
192 static void stmpe_gpio_irq_mask(struct irq_data
*d
)
194 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
195 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(gc
);
196 int offset
= d
->hwirq
;
197 int regoffset
= offset
/ 8;
198 int mask
= 1 << (offset
% 8);
200 stmpe_gpio
->regs
[REG_IE
][regoffset
] &= ~mask
;
203 static void stmpe_gpio_irq_unmask(struct irq_data
*d
)
205 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(d
);
206 struct stmpe_gpio
*stmpe_gpio
= to_stmpe_gpio(gc
);
207 int offset
= d
->hwirq
;
208 int regoffset
= offset
/ 8;
209 int mask
= 1 << (offset
% 8);
211 stmpe_gpio
->regs
[REG_IE
][regoffset
] |= mask
;
214 static struct irq_chip stmpe_gpio_irq_chip
= {
215 .name
= "stmpe-gpio",
216 .irq_bus_lock
= stmpe_gpio_irq_lock
,
217 .irq_bus_sync_unlock
= stmpe_gpio_irq_sync_unlock
,
218 .irq_mask
= stmpe_gpio_irq_mask
,
219 .irq_unmask
= stmpe_gpio_irq_unmask
,
220 .irq_set_type
= stmpe_gpio_irq_set_type
,
223 static irqreturn_t
stmpe_gpio_irq(int irq
, void *dev
)
225 struct stmpe_gpio
*stmpe_gpio
= dev
;
226 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
227 u8 statmsbreg
= stmpe
->regs
[STMPE_IDX_ISGPIOR_MSB
];
228 int num_banks
= DIV_ROUND_UP(stmpe
->num_gpios
, 8);
229 u8 status
[num_banks
];
233 ret
= stmpe_block_read(stmpe
, statmsbreg
, num_banks
, status
);
237 for (i
= 0; i
< num_banks
; i
++) {
238 int bank
= num_banks
- i
- 1;
239 unsigned int enabled
= stmpe_gpio
->regs
[REG_IE
][bank
];
240 unsigned int stat
= status
[i
];
247 int bit
= __ffs(stat
);
248 int line
= bank
* 8 + bit
;
249 int child_irq
= irq_find_mapping(stmpe_gpio
->chip
.irqdomain
,
252 handle_nested_irq(child_irq
);
256 stmpe_reg_write(stmpe
, statmsbreg
+ i
, status
[i
]);
258 /* Edge detect register is not present on 801 */
259 if (stmpe
->partnum
!= STMPE801
)
260 stmpe_reg_write(stmpe
, stmpe
->regs
[STMPE_IDX_GPEDR_MSB
]
267 static int stmpe_gpio_probe(struct platform_device
*pdev
)
269 struct stmpe
*stmpe
= dev_get_drvdata(pdev
->dev
.parent
);
270 struct device_node
*np
= pdev
->dev
.of_node
;
271 struct stmpe_gpio_platform_data
*pdata
;
272 struct stmpe_gpio
*stmpe_gpio
;
276 pdata
= stmpe
->pdata
->gpio
;
278 irq
= platform_get_irq(pdev
, 0);
280 stmpe_gpio
= kzalloc(sizeof(struct stmpe_gpio
), GFP_KERNEL
);
284 mutex_init(&stmpe_gpio
->irq_lock
);
286 stmpe_gpio
->dev
= &pdev
->dev
;
287 stmpe_gpio
->stmpe
= stmpe
;
288 stmpe_gpio
->chip
= template_chip
;
289 stmpe_gpio
->chip
.ngpio
= stmpe
->num_gpios
;
290 stmpe_gpio
->chip
.dev
= &pdev
->dev
;
292 stmpe_gpio
->chip
.of_node
= np
;
294 stmpe_gpio
->chip
.base
= -1;
297 stmpe_gpio
->norequest_mask
= pdata
->norequest_mask
;
299 of_property_read_u32(np
, "st,norequest-mask",
300 &stmpe_gpio
->norequest_mask
);
304 "device configured in no-irq mode: "
305 "irqs are not available\n");
307 ret
= stmpe_enable(stmpe
, STMPE_BLOCK_GPIO
);
312 ret
= devm_request_threaded_irq(&pdev
->dev
, irq
, NULL
,
313 stmpe_gpio_irq
, IRQF_ONESHOT
,
314 "stmpe-gpio", stmpe_gpio
);
316 dev_err(&pdev
->dev
, "unable to get irq: %d\n", ret
);
319 ret
= gpiochip_irqchip_add(&stmpe_gpio
->chip
,
320 &stmpe_gpio_irq_chip
,
326 "could not connect irqchip to gpiochip\n");
331 ret
= gpiochip_add(&stmpe_gpio
->chip
);
333 dev_err(&pdev
->dev
, "unable to add gpiochip: %d\n", ret
);
337 if (pdata
&& pdata
->setup
)
338 pdata
->setup(stmpe
, stmpe_gpio
->chip
.base
);
340 platform_set_drvdata(pdev
, stmpe_gpio
);
345 stmpe_disable(stmpe
, STMPE_BLOCK_GPIO
);
351 static int stmpe_gpio_remove(struct platform_device
*pdev
)
353 struct stmpe_gpio
*stmpe_gpio
= platform_get_drvdata(pdev
);
354 struct stmpe
*stmpe
= stmpe_gpio
->stmpe
;
355 struct stmpe_gpio_platform_data
*pdata
= stmpe
->pdata
->gpio
;
357 if (pdata
&& pdata
->remove
)
358 pdata
->remove(stmpe
, stmpe_gpio
->chip
.base
);
360 gpiochip_remove(&stmpe_gpio
->chip
);
362 stmpe_disable(stmpe
, STMPE_BLOCK_GPIO
);
369 static struct platform_driver stmpe_gpio_driver
= {
370 .driver
.name
= "stmpe-gpio",
371 .driver
.owner
= THIS_MODULE
,
372 .probe
= stmpe_gpio_probe
,
373 .remove
= stmpe_gpio_remove
,
376 static int __init
stmpe_gpio_init(void)
378 return platform_driver_register(&stmpe_gpio_driver
);
380 subsys_initcall(stmpe_gpio_init
);
382 static void __exit
stmpe_gpio_exit(void)
384 platform_driver_unregister(&stmpe_gpio_driver
);
386 module_exit(stmpe_gpio_exit
);
388 MODULE_LICENSE("GPL v2");
389 MODULE_DESCRIPTION("STMPExxxx GPIO driver");
390 MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");