drivers/gpio/gpio-tegra.c

   1 /*
   2  * arch/arm/mach-tegra/gpio.c
   3  *
   4  * Copyright (c) 2010 Google, Inc
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/irq.h>
  22 #include <linux/interrupt.h>
  23
  24 #include <linux/io.h>
  25 #include <linux/gpio.h>
  26 #include <linux/of.h>
  27
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/gpio-tegra.h>
  31 #include <mach/iomap.h>
  32 #include <mach/suspend.h>
  33
  34 #define GPIO_BANK(x)            ((x) >> 5)
  35 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  36 #define GPIO_BIT(x)             ((x) & 0x7)
  37
  38 #define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
  39                                  GPIO_BANK(x) * 0x80 +          \
  40                                  GPIO_PORT(x) * 4)
  41
  42 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  43 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  44 #define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  45 #define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  46 #define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  47 #define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  48 #define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  49 #define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  50
  51 #define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
  52 #define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
  53 #define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
  54 #define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
  55 #define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
  56 #define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
  57
  58 #define GPIO_INT_LVL_MASK               0x010101
  59 #define GPIO_INT_LVL_EDGE_RISING        0x000101
  60 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
  61 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
  62 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  63 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
  64
  65 struct tegra_gpio_bank {
  66         int bank;
  67         int irq;
  68         spinlock_t lvl_lock[4];
  69 #ifdef CONFIG_PM
  70         u32 cnf[4];
  71         u32 out[4];
  72         u32 oe[4];
  73         u32 int_enb[4];
  74         u32 int_lvl[4];
  75 #endif
  76 };
  77
  78
  79 static struct tegra_gpio_bank tegra_gpio_banks[] = {
  80         {.bank = 0, .irq = INT_GPIO1},
  81         {.bank = 1, .irq = INT_GPIO2},
  82         {.bank = 2, .irq = INT_GPIO3},
  83         {.bank = 3, .irq = INT_GPIO4},
  84         {.bank = 4, .irq = INT_GPIO5},
  85         {.bank = 5, .irq = INT_GPIO6},
  86         {.bank = 6, .irq = INT_GPIO7},
  87 };
  88
  89 static int tegra_gpio_compose(int bank, int port, int bit)
  90 {
  91         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  92 }
  93
  94 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
  95 {
  96         u32 val;
  97
  98         val = 0x100 << GPIO_BIT(gpio);
  99         if (value)
 100                 val |= 1 << GPIO_BIT(gpio);
 101         __raw_writel(val, reg);
 102 }
 103
 104 void tegra_gpio_enable(int gpio)
 105 {
 106         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 107 }
 108
 109 void tegra_gpio_disable(int gpio)
 110 {
 111         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 112 }
 113
 114 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 115 {
 116         tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 117 }
 118
 119 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 120 {
 121         return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 122 }
 123
 124 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 125 {
 126         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 127         return 0;
 128 }
 129
 130 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 131                                         int value)
 132 {
 133         tegra_gpio_set(chip, offset, value);
 134         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 135         return 0;
 136 }
 137
 138 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 139 {
 140         return TEGRA_GPIO_TO_IRQ(offset);
 141 }
 142
 143 static struct gpio_chip tegra_gpio_chip = {
 144         .label                  = "tegra-gpio",
 145         .direction_input        = tegra_gpio_direction_input,
 146         .get                    = tegra_gpio_get,
 147         .direction_output       = tegra_gpio_direction_output,
 148         .set                    = tegra_gpio_set,
 149         .to_irq                 = tegra_gpio_to_irq,
 150         .base                   = 0,
 151         .ngpio                  = TEGRA_NR_GPIOS,
 152 };
 153
 154 static void tegra_gpio_irq_ack(struct irq_data *d)
 155 {
 156         int gpio = d->irq - INT_GPIO_BASE;
 157
 158         __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 159 }
 160
 161 static void tegra_gpio_irq_mask(struct irq_data *d)
 162 {
 163         int gpio = d->irq - INT_GPIO_BASE;
 164
 165         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 166 }
 167
 168 static void tegra_gpio_irq_unmask(struct irq_data *d)
 169 {
 170         int gpio = d->irq - INT_GPIO_BASE;
 171
 172         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 173 }
 174
 175 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 176 {
 177         int gpio = d->irq - INT_GPIO_BASE;
 178         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 179         int port = GPIO_PORT(gpio);
 180         int lvl_type;
 181         int val;
 182         unsigned long flags;
 183
 184         switch (type & IRQ_TYPE_SENSE_MASK) {
 185         case IRQ_TYPE_EDGE_RISING:
 186                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
 187                 break;
 188
 189         case IRQ_TYPE_EDGE_FALLING:
 190                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 191                 break;
 192
 193         case IRQ_TYPE_EDGE_BOTH:
 194                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 195                 break;
 196
 197         case IRQ_TYPE_LEVEL_HIGH:
 198                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 199                 break;
 200
 201         case IRQ_TYPE_LEVEL_LOW:
 202                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 203                 break;
 204
 205         default:
 206                 return -EINVAL;
 207         }
 208
 209         spin_lock_irqsave(&bank->lvl_lock[port], flags);
 210
 211         val = __raw_readl(GPIO_INT_LVL(gpio));
 212         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 213         val |= lvl_type << GPIO_BIT(gpio);
 214         __raw_writel(val, GPIO_INT_LVL(gpio));
 215
 216         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 217
 218         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 219                 __irq_set_handler_locked(d->irq, handle_level_irq);
 220         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 221                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 222
 223         return 0;
 224 }
 225
 226 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 227 {
 228         struct tegra_gpio_bank *bank;
 229         int port;
 230         int pin;
 231         int unmasked = 0;
 232         struct irq_chip *chip = irq_desc_get_chip(desc);
 233
 234         chained_irq_enter(chip, desc);
 235
 236         bank = irq_get_handler_data(irq);
 237
 238         for (port = 0; port < 4; port++) {
 239                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
 240                 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
 241                         __raw_readl(GPIO_INT_ENB(gpio));
 242                 u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
 243
 244                 for_each_set_bit(pin, &sta, 8) {
 245                         __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
 246
 247                         /* if gpio is edge triggered, clear condition
 248                          * before executing the hander so that we don't
 249                          * miss edges
 250                          */
 251                         if (lvl & (0x100 << pin)) {
 252                                 unmasked = 1;
 253                                 chained_irq_exit(chip, desc);
 254                         }
 255
 256                         generic_handle_irq(gpio_to_irq(gpio + pin));
 257                 }
 258         }
 259
 260         if (!unmasked)
 261                 chained_irq_exit(chip, desc);
 262
 263 }
 264
 265 #ifdef CONFIG_PM
 266 void tegra_gpio_resume(void)
 267 {
 268         unsigned long flags;
 269         int b;
 270         int p;
 271
 272         local_irq_save(flags);
 273
 274         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
 275                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 276
 277                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 278                         unsigned int gpio = (b<<5) | (p<<3);
 279                         __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
 280                         __raw_writel(bank->out[p], GPIO_OUT(gpio));
 281                         __raw_writel(bank->oe[p], GPIO_OE(gpio));
 282                         __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 283                         __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 284                 }
 285         }
 286
 287         local_irq_restore(flags);
 288 }
 289
 290 void tegra_gpio_suspend(void)
 291 {
 292         unsigned long flags;
 293         int b;
 294         int p;
 295
 296         local_irq_save(flags);
 297         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
 298                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 299
 300                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 301                         unsigned int gpio = (b<<5) | (p<<3);
 302                         bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
 303                         bank->out[p] = __raw_readl(GPIO_OUT(gpio));
 304                         bank->oe[p] = __raw_readl(GPIO_OE(gpio));
 305                         bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
 306                         bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
 307                 }
 308         }
 309         local_irq_restore(flags);
 310 }
 311
 312 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 313 {
 314         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 315         return irq_set_irq_wake(bank->irq, enable);
 316 }
 317 #endif
 318
 319 static struct irq_chip tegra_gpio_irq_chip = {
 320         .name           = "GPIO",
 321         .irq_ack        = tegra_gpio_irq_ack,
 322         .irq_mask       = tegra_gpio_irq_mask,
 323         .irq_unmask     = tegra_gpio_irq_unmask,
 324         .irq_set_type   = tegra_gpio_irq_set_type,
 325 #ifdef CONFIG_PM
 326         .irq_set_wake   = tegra_gpio_wake_enable,
 327 #endif
 328 };
 329
 330
 331 /* This lock class tells lockdep that GPIO irqs are in a different
 332  * category than their parents, so it won't report false recursion.
 333  */
 334 static struct lock_class_key gpio_lock_class;
 335
 336 static int __init tegra_gpio_init(void)
 337 {
 338         struct tegra_gpio_bank *bank;
 339         int gpio;
 340         int i;
 341         int j;
 342
 343         for (i = 0; i < 7; i++) {
 344                 for (j = 0; j < 4; j++) {
 345                         int gpio = tegra_gpio_compose(i, j, 0);
 346                         __raw_writel(0x00, GPIO_INT_ENB(gpio));
 347                 }
 348         }
 349
 350 #ifdef CONFIG_OF_GPIO
 351         /*
 352          * This isn't ideal, but it gets things hooked up until this
 353          * driver is converted into a platform_device
 354          */
 355         tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
 356                                                 "nvidia,tegra20-gpio");
 357 #endif /* CONFIG_OF_GPIO */
 358
 359         gpiochip_add(&tegra_gpio_chip);
 360
 361         for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
 362                 int irq = TEGRA_GPIO_TO_IRQ(gpio);
 363                 /* No validity check; all Tegra GPIOs are valid IRQs */
 364
 365                 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
 366
 367                 irq_set_lockdep_class(irq, &gpio_lock_class);
 368                 irq_set_chip_data(irq, bank);
 369                 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
 370                                          handle_simple_irq);
 371                 set_irq_flags(irq, IRQF_VALID);
 372         }
 373
 374         for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
 375                 bank = &tegra_gpio_banks[i];
 376
 377                 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 378                 irq_set_handler_data(bank->irq, bank);
 379
 380                 for (j = 0; j < 4; j++)
 381                         spin_lock_init(&bank->lvl_lock[j]);
 382         }
 383
 384         return 0;
 385 }
 386
 387 postcore_initcall(tegra_gpio_init);
 388
 389 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
 390 {
 391         int i;
 392
 393         for (i = 0; i < num; i++) {
 394                 int gpio = table[i].gpio;
 395
 396                 if (table[i].enable)
 397                         tegra_gpio_enable(gpio);
 398                 else
 399                         tegra_gpio_disable(gpio);
 400         }
 401 }
 402
 403 #ifdef  CONFIG_DEBUG_FS
 404
 405 #include <linux/debugfs.h>
 406 #include <linux/seq_file.h>
 407
 408 static int dbg_gpio_show(struct seq_file *s, void *unused)
 409 {
 410         int i;
 411         int j;
 412
 413         for (i = 0; i < 7; i++) {
 414                 for (j = 0; j < 4; j++) {
 415                         int gpio = tegra_gpio_compose(i, j, 0);
 416                         seq_printf(s,
 417                                 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 418                                 i, j,
 419                                 __raw_readl(GPIO_CNF(gpio)),
 420                                 __raw_readl(GPIO_OE(gpio)),
 421                                 __raw_readl(GPIO_OUT(gpio)),
 422                                 __raw_readl(GPIO_IN(gpio)),
 423                                 __raw_readl(GPIO_INT_STA(gpio)),
 424                                 __raw_readl(GPIO_INT_ENB(gpio)),
 425                                 __raw_readl(GPIO_INT_LVL(gpio)));
 426                 }
 427         }
 428         return 0;
 429 }
 430
 431 static int dbg_gpio_open(struct inode *inode, struct file *file)
 432 {
 433         return single_open(file, dbg_gpio_show, &inode->i_private);
 434 }
 435
 436 static const struct file_operations debug_fops = {
 437         .open           = dbg_gpio_open,
 438         .read           = seq_read,
 439         .llseek         = seq_lseek,
 440         .release        = single_release,
 441 };
 442
 443 static int __init tegra_gpio_debuginit(void)
 444 {
 445         (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 446                                         NULL, NULL, &debug_fops);
 447         return 0;
 448 }
 449 late_initcall(tegra_gpio_debuginit);
 450 #endif