drivers/gpio/gpio-xlp.c

   1 /*
   2  * Copyright (C) 2003-2015 Broadcom Corporation
   3  * All Rights Reserved
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/gpio.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/of_device.h>
  18 #include <linux/module.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irqchip/chained_irq.h>
  22
  23 /*
  24  * XLP GPIO has multiple 32 bit registers for each feature where each register
  25  * controls 32 pins. So, pins up to 64 require 2 32-bit registers and up to 96
  26  * require 3 32-bit registers for each feature.
  27  * Here we only define offset of the first register for each feature. Offset of
  28  * the registers for pins greater than 32 can be calculated as following(Use
  29  * GPIO_INT_STAT as example):
  30  *
  31  * offset = (gpio / XLP_GPIO_REGSZ) * 4;
  32  * reg_addr = addr + offset;
  33  *
  34  * where addr is base address of the that feature register and gpio is the pin.
  35  */
  36 #define GPIO_OUTPUT_EN          0x00
  37 #define GPIO_PADDRV             0x08
  38 #define GPIO_INT_EN00           0x18
  39 #define GPIO_INT_EN10           0x20
  40 #define GPIO_INT_EN20           0x28
  41 #define GPIO_INT_EN30           0x30
  42 #define GPIO_INT_POL            0x38
  43 #define GPIO_INT_TYPE           0x40
  44 #define GPIO_INT_STAT           0x48
  45
  46 #define GPIO_9XX_BYTESWAP       0X00
  47 #define GPIO_9XX_CTRL           0X04
  48 #define GPIO_9XX_OUTPUT_EN      0x14
  49 #define GPIO_9XX_PADDRV         0x24
  50 /*
  51  * Only for 4 interrupt enable reg are defined for now,
  52  * total reg available are 12.
  53  */
  54 #define GPIO_9XX_INT_EN00       0x44
  55 #define GPIO_9XX_INT_EN10       0x54
  56 #define GPIO_9XX_INT_EN20       0x64
  57 #define GPIO_9XX_INT_EN30       0x74
  58 #define GPIO_9XX_INT_POL        0x104
  59 #define GPIO_9XX_INT_TYPE       0x114
  60 #define GPIO_9XX_INT_STAT       0x124
  61
  62 #define GPIO_3XX_INT_EN00       0x18
  63 #define GPIO_3XX_INT_EN10       0x20
  64 #define GPIO_3XX_INT_EN20       0x28
  65 #define GPIO_3XX_INT_EN30       0x30
  66 #define GPIO_3XX_INT_POL        0x78
  67 #define GPIO_3XX_INT_TYPE       0x80
  68 #define GPIO_3XX_INT_STAT       0x88
  69
  70 /* Interrupt type register mask */
  71 #define XLP_GPIO_IRQ_TYPE_LVL   0x0
  72 #define XLP_GPIO_IRQ_TYPE_EDGE  0x1
  73
  74 /* Interrupt polarity register mask */
  75 #define XLP_GPIO_IRQ_POL_HIGH   0x0
  76 #define XLP_GPIO_IRQ_POL_LOW    0x1
  77
  78 #define XLP_GPIO_REGSZ          32
  79 #define XLP_GPIO_IRQ_BASE       768
  80 #define XLP_MAX_NR_GPIO         96
  81
  82 /* XLP variants supported by this driver */
  83 enum {
  84         XLP_GPIO_VARIANT_XLP832 = 1,
  85         XLP_GPIO_VARIANT_XLP316,
  86         XLP_GPIO_VARIANT_XLP208,
  87         XLP_GPIO_VARIANT_XLP980,
  88         XLP_GPIO_VARIANT_XLP532,
  89         GPIO_VARIANT_VULCAN
  90 };
  91
  92 struct xlp_gpio_priv {
  93         struct gpio_chip chip;
  94         DECLARE_BITMAP(gpio_enabled_mask, XLP_MAX_NR_GPIO);
  95         void __iomem *gpio_intr_en;     /* pointer to first intr enable reg */
  96         void __iomem *gpio_intr_stat;   /* pointer to first intr status reg */
  97         void __iomem *gpio_intr_type;   /* pointer to first intr type reg */
  98         void __iomem *gpio_intr_pol;    /* pointer to first intr polarity reg */
  99         void __iomem *gpio_out_en;      /* pointer to first output enable reg */
 100         void __iomem *gpio_paddrv;      /* pointer to first pad drive reg */
 101         spinlock_t lock;
 102 };
 103
 104 static int xlp_gpio_get_reg(void __iomem *addr, unsigned gpio)
 105 {
 106         u32 pos, regset;
 107
 108         pos = gpio % XLP_GPIO_REGSZ;
 109         regset = (gpio / XLP_GPIO_REGSZ) * 4;
 110         return !!(readl(addr + regset) & BIT(pos));
 111 }
 112
 113 static void xlp_gpio_set_reg(void __iomem *addr, unsigned gpio, int state)
 114 {
 115         u32 value, pos, regset;
 116
 117         pos = gpio % XLP_GPIO_REGSZ;
 118         regset = (gpio / XLP_GPIO_REGSZ) * 4;
 119         value = readl(addr + regset);
 120
 121         if (state)
 122                 value |= BIT(pos);
 123         else
 124                 value &= ~BIT(pos);
 125
 126         writel(value, addr + regset);
 127 }
 128
 129 static void xlp_gpio_irq_disable(struct irq_data *d)
 130 {
 131         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 132         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 133         unsigned long flags;
 134
 135         spin_lock_irqsave(&priv->lock, flags);
 136         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
 137         __clear_bit(d->hwirq, priv->gpio_enabled_mask);
 138         spin_unlock_irqrestore(&priv->lock, flags);
 139 }
 140
 141 static void xlp_gpio_irq_mask_ack(struct irq_data *d)
 142 {
 143         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 144         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 145         unsigned long flags;
 146
 147         spin_lock_irqsave(&priv->lock, flags);
 148         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
 149         xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
 150         __clear_bit(d->hwirq, priv->gpio_enabled_mask);
 151         spin_unlock_irqrestore(&priv->lock, flags);
 152 }
 153
 154 static void xlp_gpio_irq_unmask(struct irq_data *d)
 155 {
 156         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 157         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 158         unsigned long flags;
 159
 160         spin_lock_irqsave(&priv->lock, flags);
 161         xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
 162         __set_bit(d->hwirq, priv->gpio_enabled_mask);
 163         spin_unlock_irqrestore(&priv->lock, flags);
 164 }
 165
 166 static int xlp_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 167 {
 168         struct gpio_chip *gc  = irq_data_get_irq_chip_data(d);
 169         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 170         int pol, irq_type;
 171
 172         switch (type) {
 173         case IRQ_TYPE_EDGE_RISING:
 174                 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
 175                 pol = XLP_GPIO_IRQ_POL_HIGH;
 176                 break;
 177         case IRQ_TYPE_EDGE_FALLING:
 178                 irq_type = XLP_GPIO_IRQ_TYPE_EDGE;
 179                 pol = XLP_GPIO_IRQ_POL_LOW;
 180                 break;
 181         case IRQ_TYPE_LEVEL_HIGH:
 182                 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
 183                 pol = XLP_GPIO_IRQ_POL_HIGH;
 184                 break;
 185         case IRQ_TYPE_LEVEL_LOW:
 186                 irq_type = XLP_GPIO_IRQ_TYPE_LVL;
 187                 pol = XLP_GPIO_IRQ_POL_LOW;
 188                 break;
 189         default:
 190                 return -EINVAL;
 191         }
 192
 193         xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
 194         xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
 195
 196         return 0;
 197 }
 198
 199 static struct irq_chip xlp_gpio_irq_chip = {
 200         .name           = "XLP-GPIO",
 201         .irq_mask_ack   = xlp_gpio_irq_mask_ack,
 202         .irq_disable    = xlp_gpio_irq_disable,
 203         .irq_set_type   = xlp_gpio_set_irq_type,
 204         .irq_unmask     = xlp_gpio_irq_unmask,
 205         .flags          = IRQCHIP_ONESHOT_SAFE,
 206 };
 207
 208 static void xlp_gpio_generic_handler(struct irq_desc *desc)
 209 {
 210         struct xlp_gpio_priv *priv = irq_desc_get_handler_data(desc);
 211         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 212         int gpio, regoff;
 213         u32 gpio_stat;
 214
 215         regoff = -1;
 216         gpio_stat = 0;
 217
 218         chained_irq_enter(irqchip, desc);
 219         for_each_set_bit(gpio, priv->gpio_enabled_mask, XLP_MAX_NR_GPIO) {
 220                 if (regoff != gpio / XLP_GPIO_REGSZ) {
 221                         regoff = gpio / XLP_GPIO_REGSZ;
 222                         gpio_stat = readl(priv->gpio_intr_stat + regoff * 4);
 223                 }
 224
 225                 if (gpio_stat & BIT(gpio % XLP_GPIO_REGSZ))
 226                         generic_handle_irq(irq_find_mapping(
 227                                                 priv->chip.irqdomain, gpio));
 228         }
 229         chained_irq_exit(irqchip, desc);
 230 }
 231
 232 static int xlp_gpio_dir_output(struct gpio_chip *gc, unsigned gpio, int state)
 233 {
 234         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 235
 236         BUG_ON(gpio >= gc->ngpio);
 237         xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x1);
 238
 239         return 0;
 240 }
 241
 242 static int xlp_gpio_dir_input(struct gpio_chip *gc, unsigned gpio)
 243 {
 244         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 245
 246         BUG_ON(gpio >= gc->ngpio);
 247         xlp_gpio_set_reg(priv->gpio_out_en, gpio, 0x0);
 248
 249         return 0;
 250 }
 251
 252 static int xlp_gpio_get(struct gpio_chip *gc, unsigned gpio)
 253 {
 254         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 255
 256         BUG_ON(gpio >= gc->ngpio);
 257         return xlp_gpio_get_reg(priv->gpio_paddrv, gpio);
 258 }
 259
 260 static void xlp_gpio_set(struct gpio_chip *gc, unsigned gpio, int state)
 261 {
 262         struct xlp_gpio_priv *priv = gpiochip_get_data(gc);
 263
 264         BUG_ON(gpio >= gc->ngpio);
 265         xlp_gpio_set_reg(priv->gpio_paddrv, gpio, state);
 266 }
 267
 268 static const struct of_device_id xlp_gpio_of_ids[] = {
 269         {
 270                 .compatible = "netlogic,xlp832-gpio",
 271                 .data       = (void *)XLP_GPIO_VARIANT_XLP832,
 272         },
 273         {
 274                 .compatible = "netlogic,xlp316-gpio",
 275                 .data       = (void *)XLP_GPIO_VARIANT_XLP316,
 276         },
 277         {
 278                 .compatible = "netlogic,xlp208-gpio",
 279                 .data       = (void *)XLP_GPIO_VARIANT_XLP208,
 280         },
 281         {
 282                 .compatible = "netlogic,xlp980-gpio",
 283                 .data       = (void *)XLP_GPIO_VARIANT_XLP980,
 284         },
 285         {
 286                 .compatible = "netlogic,xlp532-gpio",
 287                 .data       = (void *)XLP_GPIO_VARIANT_XLP532,
 288         },
 289         {
 290                 .compatible = "brcm,vulcan-gpio",
 291                 .data       = (void *)GPIO_VARIANT_VULCAN,
 292         },
 293         { /* sentinel */ },
 294 };
 295 MODULE_DEVICE_TABLE(of, xlp_gpio_of_ids);
 296
 297 static int xlp_gpio_probe(struct platform_device *pdev)
 298 {
 299         struct gpio_chip *gc;
 300         struct resource *iores;
 301         struct xlp_gpio_priv *priv;
 302         const struct of_device_id *of_id;
 303         void __iomem *gpio_base;
 304         int irq_base, irq, err;
 305         int ngpio;
 306         u32 soc_type;
 307
 308         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 309         if (!iores)
 310                 return -ENODEV;
 311
 312         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 313         if (!priv)
 314                 return -ENOMEM;
 315
 316         gpio_base = devm_ioremap_resource(&pdev->dev, iores);
 317         if (IS_ERR(gpio_base))
 318                 return PTR_ERR(gpio_base);
 319
 320         irq = platform_get_irq(pdev, 0);
 321         if (irq < 0)
 322                 return irq;
 323
 324         of_id = of_match_device(xlp_gpio_of_ids, &pdev->dev);
 325         if (!of_id) {
 326                 dev_err(&pdev->dev, "Failed to get soc type!\n");
 327                 return -ENODEV;
 328         }
 329
 330         soc_type = (uintptr_t) of_id->data;
 331
 332         switch (soc_type) {
 333         case XLP_GPIO_VARIANT_XLP832:
 334                 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
 335                 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
 336                 priv->gpio_intr_stat = gpio_base + GPIO_INT_STAT;
 337                 priv->gpio_intr_type = gpio_base + GPIO_INT_TYPE;
 338                 priv->gpio_intr_pol = gpio_base + GPIO_INT_POL;
 339                 priv->gpio_intr_en = gpio_base + GPIO_INT_EN00;
 340                 ngpio = 41;
 341                 break;
 342         case XLP_GPIO_VARIANT_XLP208:
 343         case XLP_GPIO_VARIANT_XLP316:
 344                 priv->gpio_out_en = gpio_base + GPIO_OUTPUT_EN;
 345                 priv->gpio_paddrv = gpio_base + GPIO_PADDRV;
 346                 priv->gpio_intr_stat = gpio_base + GPIO_3XX_INT_STAT;
 347                 priv->gpio_intr_type = gpio_base + GPIO_3XX_INT_TYPE;
 348                 priv->gpio_intr_pol = gpio_base + GPIO_3XX_INT_POL;
 349                 priv->gpio_intr_en = gpio_base + GPIO_3XX_INT_EN00;
 350
 351                 ngpio = (soc_type == XLP_GPIO_VARIANT_XLP208) ? 42 : 57;
 352                 break;
 353         case XLP_GPIO_VARIANT_XLP980:
 354         case XLP_GPIO_VARIANT_XLP532:
 355         case GPIO_VARIANT_VULCAN:
 356                 priv->gpio_out_en = gpio_base + GPIO_9XX_OUTPUT_EN;
 357                 priv->gpio_paddrv = gpio_base + GPIO_9XX_PADDRV;
 358                 priv->gpio_intr_stat = gpio_base + GPIO_9XX_INT_STAT;
 359                 priv->gpio_intr_type = gpio_base + GPIO_9XX_INT_TYPE;
 360                 priv->gpio_intr_pol = gpio_base + GPIO_9XX_INT_POL;
 361                 priv->gpio_intr_en = gpio_base + GPIO_9XX_INT_EN00;
 362
 363                 if (soc_type == XLP_GPIO_VARIANT_XLP980)
 364                         ngpio = 66;
 365                 else if (soc_type == XLP_GPIO_VARIANT_XLP532)
 366                         ngpio = 67;
 367                 else
 368                         ngpio = 70;
 369                 break;
 370         default:
 371                 dev_err(&pdev->dev, "Unknown Processor type!\n");
 372                 return -ENODEV;
 373         }
 374
 375         bitmap_zero(priv->gpio_enabled_mask, XLP_MAX_NR_GPIO);
 376
 377         gc = &priv->chip;
 378
 379         gc->owner = THIS_MODULE;
 380         gc->label = dev_name(&pdev->dev);
 381         gc->base = 0;
 382         gc->parent = &pdev->dev;
 383         gc->ngpio = ngpio;
 384         gc->of_node = pdev->dev.of_node;
 385         gc->direction_output = xlp_gpio_dir_output;
 386         gc->direction_input = xlp_gpio_dir_input;
 387         gc->set = xlp_gpio_set;
 388         gc->get = xlp_gpio_get;
 389
 390         spin_lock_init(&priv->lock);
 391         /* XLP has fixed IRQ range for GPIO interrupts */
 392         if (soc_type == GPIO_VARIANT_VULCAN)
 393                 irq_base = irq_alloc_descs(-1, 0, gc->ngpio, 0);
 394         else
 395                 irq_base = irq_alloc_descs(-1, XLP_GPIO_IRQ_BASE, gc->ngpio, 0);
 396         if (irq_base < 0) {
 397                 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
 398                 return irq_base;
 399         }
 400
 401         err = gpiochip_add_data(gc, priv);
 402         if (err < 0)
 403                 goto out_free_desc;
 404
 405         err = gpiochip_irqchip_add(gc, &xlp_gpio_irq_chip, irq_base,
 406                                 handle_level_irq, IRQ_TYPE_NONE);
 407         if (err) {
 408                 dev_err(&pdev->dev, "Could not connect irqchip to gpiochip!\n");
 409                 goto out_gpio_remove;
 410         }
 411
 412         gpiochip_set_chained_irqchip(gc, &xlp_gpio_irq_chip, irq,
 413                         xlp_gpio_generic_handler);
 414
 415         dev_info(&pdev->dev, "registered %d GPIOs\n", gc->ngpio);
 416
 417         return 0;
 418
 419 out_gpio_remove:
 420         gpiochip_remove(gc);
 421 out_free_desc:
 422         irq_free_descs(irq_base, gc->ngpio);
 423         return err;
 424 }
 425
 426 static struct platform_driver xlp_gpio_driver = {
 427         .driver         = {
 428                 .name   = "xlp-gpio",
 429                 .of_match_table = xlp_gpio_of_ids,
 430         },
 431         .probe          = xlp_gpio_probe,
 432 };
 433 module_platform_driver(xlp_gpio_driver);
 434
 435 MODULE_AUTHOR("Kamlakant Patel <kamlakant.patel@broadcom.com>");
 436 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
 437 MODULE_DESCRIPTION("Netlogic XLP GPIO Driver");
 438 MODULE_LICENSE("GPL v2");