2 * Xilinx Zynq GPIO device driver
4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option) any later
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
22 #define DRIVER_NAME "zynq-gpio"
25 #define ZYNQ_GPIO_MAX_BANK 4
27 #define ZYNQ_GPIO_BANK0_NGPIO 32
28 #define ZYNQ_GPIO_BANK1_NGPIO 22
29 #define ZYNQ_GPIO_BANK2_NGPIO 32
30 #define ZYNQ_GPIO_BANK3_NGPIO 32
32 #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
33 ZYNQ_GPIO_BANK1_NGPIO + \
34 ZYNQ_GPIO_BANK2_NGPIO + \
35 ZYNQ_GPIO_BANK3_NGPIO)
37 #define ZYNQ_GPIO_BANK0_PIN_MIN 0
38 #define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
39 ZYNQ_GPIO_BANK0_NGPIO - 1)
40 #define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
41 #define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
42 ZYNQ_GPIO_BANK1_NGPIO - 1)
43 #define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
44 #define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
45 ZYNQ_GPIO_BANK2_NGPIO - 1)
46 #define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
47 #define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
48 ZYNQ_GPIO_BANK3_NGPIO - 1)
51 /* Register offsets for the GPIO device */
52 /* LSW Mask & Data -WO */
53 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
54 /* MSW Mask & Data -WO */
55 #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
56 /* Data Register-RW */
57 #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
58 /* Direction mode reg-RW */
59 #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
60 /* Output enable reg-RW */
61 #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
62 /* Interrupt mask reg-RO */
63 #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
64 /* Interrupt enable reg-WO */
65 #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
66 /* Interrupt disable reg-WO */
67 #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
68 /* Interrupt status reg-RO */
69 #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
70 /* Interrupt type reg-RW */
71 #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
72 /* Interrupt polarity reg-RW */
73 #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
74 /* Interrupt on any, reg-RW */
75 #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
77 /* Disable all interrupts mask */
78 #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
80 /* Mid pin number of a bank */
81 #define ZYNQ_GPIO_MID_PIN_NUM 16
83 /* GPIO upper 16 bit mask */
84 #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
87 * struct zynq_gpio - gpio device private data structure
88 * @chip: instance of the gpio_chip
89 * @base_addr: base address of the GPIO device
90 * @clk: clock resource for this controller
93 struct gpio_chip chip
;
94 void __iomem
*base_addr
;
98 static struct irq_chip zynq_gpio_level_irqchip
;
99 static struct irq_chip zynq_gpio_edge_irqchip
;
102 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
103 * for a given pin in the GPIO device
104 * @pin_num: gpio pin number within the device
105 * @bank_num: an output parameter used to return the bank number of the gpio
107 * @bank_pin_num: an output parameter used to return pin number within a bank
108 * for the given gpio pin
110 * Returns the bank number and pin offset within the bank.
112 static inline void zynq_gpio_get_bank_pin(unsigned int pin_num
,
113 unsigned int *bank_num
,
114 unsigned int *bank_pin_num
)
117 case ZYNQ_GPIO_BANK0_PIN_MIN
... ZYNQ_GPIO_BANK0_PIN_MAX
:
119 *bank_pin_num
= pin_num
;
121 case ZYNQ_GPIO_BANK1_PIN_MIN
... ZYNQ_GPIO_BANK1_PIN_MAX
:
123 *bank_pin_num
= pin_num
- ZYNQ_GPIO_BANK1_PIN_MIN
;
125 case ZYNQ_GPIO_BANK2_PIN_MIN
... ZYNQ_GPIO_BANK2_PIN_MAX
:
127 *bank_pin_num
= pin_num
- ZYNQ_GPIO_BANK2_PIN_MIN
;
129 case ZYNQ_GPIO_BANK3_PIN_MIN
... ZYNQ_GPIO_BANK3_PIN_MAX
:
131 *bank_pin_num
= pin_num
- ZYNQ_GPIO_BANK3_PIN_MIN
;
134 WARN(true, "invalid GPIO pin number: %u", pin_num
);
142 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
143 * @chip: gpio_chip instance to be worked on
144 * @pin: gpio pin number within the device
146 * This function reads the state of the specified pin of the GPIO device.
148 * Return: 0 if the pin is low, 1 if pin is high.
150 static int zynq_gpio_get_value(struct gpio_chip
*chip
, unsigned int pin
)
153 unsigned int bank_num
, bank_pin_num
;
154 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
156 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
158 data
= readl_relaxed(gpio
->base_addr
+
159 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num
));
161 return (data
>> bank_pin_num
) & 1;
165 * zynq_gpio_set_value - Modify the state of the pin with specified value
166 * @chip: gpio_chip instance to be worked on
167 * @pin: gpio pin number within the device
168 * @state: value used to modify the state of the specified pin
170 * This function calculates the register offset (i.e to lower 16 bits or
171 * upper 16 bits) based on the given pin number and sets the state of a
172 * gpio pin to the specified value. The state is either 0 or non-zero.
174 static void zynq_gpio_set_value(struct gpio_chip
*chip
, unsigned int pin
,
177 unsigned int reg_offset
, bank_num
, bank_pin_num
;
178 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
180 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
182 if (bank_pin_num
>= ZYNQ_GPIO_MID_PIN_NUM
) {
183 /* only 16 data bits in bit maskable reg */
184 bank_pin_num
-= ZYNQ_GPIO_MID_PIN_NUM
;
185 reg_offset
= ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num
);
187 reg_offset
= ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num
);
191 * get the 32 bit value to be written to the mask/data register where
192 * the upper 16 bits is the mask and lower 16 bits is the data
195 state
= ~(1 << (bank_pin_num
+ ZYNQ_GPIO_MID_PIN_NUM
)) &
196 ((state
<< bank_pin_num
) | ZYNQ_GPIO_UPPER_MASK
);
198 writel_relaxed(state
, gpio
->base_addr
+ reg_offset
);
202 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
203 * @chip: gpio_chip instance to be worked on
204 * @pin: gpio pin number within the device
206 * This function uses the read-modify-write sequence to set the direction of
207 * the gpio pin as input.
211 static int zynq_gpio_dir_in(struct gpio_chip
*chip
, unsigned int pin
)
214 unsigned int bank_num
, bank_pin_num
;
215 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
217 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
219 /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
220 if (bank_num
== 0 && (bank_pin_num
== 7 || bank_pin_num
== 8))
223 /* clear the bit in direction mode reg to set the pin as input */
224 reg
= readl_relaxed(gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
225 reg
&= ~BIT(bank_pin_num
);
226 writel_relaxed(reg
, gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
232 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
233 * @chip: gpio_chip instance to be worked on
234 * @pin: gpio pin number within the device
235 * @state: value to be written to specified pin
237 * This function sets the direction of specified GPIO pin as output, configures
238 * the Output Enable register for the pin and uses zynq_gpio_set to set
239 * the state of the pin to the value specified.
243 static int zynq_gpio_dir_out(struct gpio_chip
*chip
, unsigned int pin
,
247 unsigned int bank_num
, bank_pin_num
;
248 struct zynq_gpio
*gpio
= container_of(chip
, struct zynq_gpio
, chip
);
250 zynq_gpio_get_bank_pin(pin
, &bank_num
, &bank_pin_num
);
252 /* set the GPIO pin as output */
253 reg
= readl_relaxed(gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
254 reg
|= BIT(bank_pin_num
);
255 writel_relaxed(reg
, gpio
->base_addr
+ ZYNQ_GPIO_DIRM_OFFSET(bank_num
));
257 /* configure the output enable reg for the pin */
258 reg
= readl_relaxed(gpio
->base_addr
+ ZYNQ_GPIO_OUTEN_OFFSET(bank_num
));
259 reg
|= BIT(bank_pin_num
);
260 writel_relaxed(reg
, gpio
->base_addr
+ ZYNQ_GPIO_OUTEN_OFFSET(bank_num
));
262 /* set the state of the pin */
263 zynq_gpio_set_value(chip
, pin
, state
);
268 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
269 * @irq_data: per irq and chip data passed down to chip functions
271 * This function calculates gpio pin number from irq number and sets the
272 * bit in the Interrupt Disable register of the corresponding bank to disable
273 * interrupts for that pin.
275 static void zynq_gpio_irq_mask(struct irq_data
*irq_data
)
277 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
278 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
280 device_pin_num
= irq_data
->hwirq
;
281 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
282 writel_relaxed(BIT(bank_pin_num
),
283 gpio
->base_addr
+ ZYNQ_GPIO_INTDIS_OFFSET(bank_num
));
287 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
288 * @irq_data: irq data containing irq number of gpio pin for the interrupt
291 * This function calculates the gpio pin number from irq number and sets the
292 * bit in the Interrupt Enable register of the corresponding bank to enable
293 * interrupts for that pin.
295 static void zynq_gpio_irq_unmask(struct irq_data
*irq_data
)
297 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
298 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
300 device_pin_num
= irq_data
->hwirq
;
301 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
302 writel_relaxed(BIT(bank_pin_num
),
303 gpio
->base_addr
+ ZYNQ_GPIO_INTEN_OFFSET(bank_num
));
307 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
308 * @irq_data: irq data containing irq number of gpio pin for the interrupt
311 * This function calculates gpio pin number from irq number and sets the bit
312 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
314 static void zynq_gpio_irq_ack(struct irq_data
*irq_data
)
316 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
317 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
319 device_pin_num
= irq_data
->hwirq
;
320 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
321 writel_relaxed(BIT(bank_pin_num
),
322 gpio
->base_addr
+ ZYNQ_GPIO_INTSTS_OFFSET(bank_num
));
326 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
327 * @irq_data: irq data containing irq number of gpio pin for the interrupt
330 * Clears the INTSTS bit and unmasks the given interrrupt.
332 static void zynq_gpio_irq_enable(struct irq_data
*irq_data
)
335 * The Zynq GPIO controller does not disable interrupt detection when
336 * the interrupt is masked and only disables the propagation of the
337 * interrupt. This means when the controller detects an interrupt
338 * condition while the interrupt is logically disabled it will propagate
339 * that interrupt event once the interrupt is enabled. This will cause
340 * the interrupt consumer to see spurious interrupts to prevent this
341 * first make sure that the interrupt is not asserted and then enable
344 zynq_gpio_irq_ack(irq_data
);
345 zynq_gpio_irq_unmask(irq_data
);
349 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
350 * @irq_data: irq data containing irq number of gpio pin
351 * @type: interrupt type that is to be set for the gpio pin
353 * This function gets the gpio pin number and its bank from the gpio pin number
354 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
356 * Return: 0, negative error otherwise.
357 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
358 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
359 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
360 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
361 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
363 static int zynq_gpio_set_irq_type(struct irq_data
*irq_data
, unsigned int type
)
365 u32 int_type
, int_pol
, int_any
;
366 unsigned int device_pin_num
, bank_num
, bank_pin_num
;
367 struct zynq_gpio
*gpio
= irq_data_get_irq_chip_data(irq_data
);
369 device_pin_num
= irq_data
->hwirq
;
370 zynq_gpio_get_bank_pin(device_pin_num
, &bank_num
, &bank_pin_num
);
372 int_type
= readl_relaxed(gpio
->base_addr
+
373 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num
));
374 int_pol
= readl_relaxed(gpio
->base_addr
+
375 ZYNQ_GPIO_INTPOL_OFFSET(bank_num
));
376 int_any
= readl_relaxed(gpio
->base_addr
+
377 ZYNQ_GPIO_INTANY_OFFSET(bank_num
));
380 * based on the type requested, configure the INT_TYPE, INT_POLARITY
381 * and INT_ANY registers
384 case IRQ_TYPE_EDGE_RISING
:
385 int_type
|= BIT(bank_pin_num
);
386 int_pol
|= BIT(bank_pin_num
);
387 int_any
&= ~BIT(bank_pin_num
);
389 case IRQ_TYPE_EDGE_FALLING
:
390 int_type
|= BIT(bank_pin_num
);
391 int_pol
&= ~BIT(bank_pin_num
);
392 int_any
&= ~BIT(bank_pin_num
);
394 case IRQ_TYPE_EDGE_BOTH
:
395 int_type
|= BIT(bank_pin_num
);
396 int_any
|= BIT(bank_pin_num
);
398 case IRQ_TYPE_LEVEL_HIGH
:
399 int_type
&= ~BIT(bank_pin_num
);
400 int_pol
|= BIT(bank_pin_num
);
402 case IRQ_TYPE_LEVEL_LOW
:
403 int_type
&= ~BIT(bank_pin_num
);
404 int_pol
&= ~BIT(bank_pin_num
);
410 writel_relaxed(int_type
,
411 gpio
->base_addr
+ ZYNQ_GPIO_INTTYPE_OFFSET(bank_num
));
412 writel_relaxed(int_pol
,
413 gpio
->base_addr
+ ZYNQ_GPIO_INTPOL_OFFSET(bank_num
));
414 writel_relaxed(int_any
,
415 gpio
->base_addr
+ ZYNQ_GPIO_INTANY_OFFSET(bank_num
));
417 if (type
& IRQ_TYPE_LEVEL_MASK
) {
418 __irq_set_chip_handler_name_locked(irq_data
->irq
,
419 &zynq_gpio_level_irqchip
, handle_fasteoi_irq
, NULL
);
421 __irq_set_chip_handler_name_locked(irq_data
->irq
,
422 &zynq_gpio_edge_irqchip
, handle_level_irq
, NULL
);
428 static int zynq_gpio_set_wake(struct irq_data
*data
, unsigned int on
)
431 zynq_gpio_irq_unmask(data
);
433 zynq_gpio_irq_mask(data
);
438 /* irq chip descriptor */
439 static struct irq_chip zynq_gpio_level_irqchip
= {
441 .irq_enable
= zynq_gpio_irq_enable
,
442 .irq_eoi
= zynq_gpio_irq_ack
,
443 .irq_mask
= zynq_gpio_irq_mask
,
444 .irq_unmask
= zynq_gpio_irq_unmask
,
445 .irq_set_type
= zynq_gpio_set_irq_type
,
446 .irq_set_wake
= zynq_gpio_set_wake
,
447 .flags
= IRQCHIP_EOI_THREADED
| IRQCHIP_EOI_IF_HANDLED
,
450 static struct irq_chip zynq_gpio_edge_irqchip
= {
452 .irq_enable
= zynq_gpio_irq_enable
,
453 .irq_ack
= zynq_gpio_irq_ack
,
454 .irq_mask
= zynq_gpio_irq_mask
,
455 .irq_unmask
= zynq_gpio_irq_unmask
,
456 .irq_set_type
= zynq_gpio_set_irq_type
,
457 .irq_set_wake
= zynq_gpio_set_wake
,
461 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
462 * @irq: irq number of the gpio bank where interrupt has occurred
463 * @desc: irq descriptor instance of the 'irq'
465 * This function reads the Interrupt Status Register of each bank to get the
466 * gpio pin number which has triggered an interrupt. It then acks the triggered
467 * interrupt and calls the pin specific handler set by the higher layer
468 * application for that pin.
469 * Note: A bug is reported if no handler is set for the gpio pin.
471 static void zynq_gpio_irqhandler(unsigned int irq
, struct irq_desc
*desc
)
473 u32 int_sts
, int_enb
;
474 unsigned int bank_num
;
475 struct zynq_gpio
*gpio
= irq_get_handler_data(irq
);
476 struct irq_chip
*irqchip
= irq_desc_get_chip(desc
);
478 chained_irq_enter(irqchip
, desc
);
480 for (bank_num
= 0; bank_num
< ZYNQ_GPIO_MAX_BANK
; bank_num
++) {
481 int_sts
= readl_relaxed(gpio
->base_addr
+
482 ZYNQ_GPIO_INTSTS_OFFSET(bank_num
));
483 int_enb
= readl_relaxed(gpio
->base_addr
+
484 ZYNQ_GPIO_INTMASK_OFFSET(bank_num
));
488 unsigned long pending
= int_sts
;
490 for_each_set_bit(offset
, &pending
, 32) {
491 unsigned int gpio_irq
=
492 irq_find_mapping(gpio
->chip
.irqdomain
,
494 generic_handle_irq(gpio_irq
);
499 chained_irq_exit(irqchip
, desc
);
502 static int __maybe_unused
zynq_gpio_suspend(struct device
*dev
)
504 if (!device_may_wakeup(dev
))
505 return pm_runtime_force_suspend(dev
);
510 static int __maybe_unused
zynq_gpio_resume(struct device
*dev
)
512 if (!device_may_wakeup(dev
))
513 return pm_runtime_force_resume(dev
);
518 static int __maybe_unused
zynq_gpio_runtime_suspend(struct device
*dev
)
520 struct platform_device
*pdev
= to_platform_device(dev
);
521 struct zynq_gpio
*gpio
= platform_get_drvdata(pdev
);
523 clk_disable_unprepare(gpio
->clk
);
528 static int __maybe_unused
zynq_gpio_runtime_resume(struct device
*dev
)
530 struct platform_device
*pdev
= to_platform_device(dev
);
531 struct zynq_gpio
*gpio
= platform_get_drvdata(pdev
);
533 return clk_prepare_enable(gpio
->clk
);
536 static int zynq_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
540 ret
= pm_runtime_get_sync(chip
->dev
);
543 * If the device is already active pm_runtime_get() will return 1 on
544 * success, but gpio_request still needs to return 0.
546 return ret
< 0 ? ret
: 0;
549 static void zynq_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
551 pm_runtime_put(chip
->dev
);
554 static const struct dev_pm_ops zynq_gpio_dev_pm_ops
= {
555 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend
, zynq_gpio_resume
)
556 SET_PM_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend
,
557 zynq_gpio_runtime_resume
, NULL
)
561 * zynq_gpio_probe - Initialization method for a zynq_gpio device
562 * @pdev: platform device instance
564 * This function allocates memory resources for the gpio device and registers
565 * all the banks of the device. It will also set up interrupts for the gpio
567 * Note: Interrupts are disabled for all the banks during initialization.
569 * Return: 0 on success, negative error otherwise.
571 static int zynq_gpio_probe(struct platform_device
*pdev
)
573 int ret
, bank_num
, irq
;
574 struct zynq_gpio
*gpio
;
575 struct gpio_chip
*chip
;
576 struct resource
*res
;
578 gpio
= devm_kzalloc(&pdev
->dev
, sizeof(*gpio
), GFP_KERNEL
);
582 platform_set_drvdata(pdev
, gpio
);
584 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
585 gpio
->base_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
586 if (IS_ERR(gpio
->base_addr
))
587 return PTR_ERR(gpio
->base_addr
);
589 irq
= platform_get_irq(pdev
, 0);
591 dev_err(&pdev
->dev
, "invalid IRQ\n");
595 /* configure the gpio chip */
597 chip
->label
= "zynq_gpio";
598 chip
->owner
= THIS_MODULE
;
599 chip
->dev
= &pdev
->dev
;
600 chip
->get
= zynq_gpio_get_value
;
601 chip
->set
= zynq_gpio_set_value
;
602 chip
->request
= zynq_gpio_request
;
603 chip
->free
= zynq_gpio_free
;
604 chip
->direction_input
= zynq_gpio_dir_in
;
605 chip
->direction_output
= zynq_gpio_dir_out
;
607 chip
->ngpio
= ZYNQ_GPIO_NR_GPIOS
;
609 /* Enable GPIO clock */
610 gpio
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
611 if (IS_ERR(gpio
->clk
)) {
612 dev_err(&pdev
->dev
, "input clock not found.\n");
613 return PTR_ERR(gpio
->clk
);
615 ret
= clk_prepare_enable(gpio
->clk
);
617 dev_err(&pdev
->dev
, "Unable to enable clock.\n");
621 /* report a bug if gpio chip registration fails */
622 ret
= gpiochip_add(chip
);
624 dev_err(&pdev
->dev
, "Failed to add gpio chip\n");
625 goto err_disable_clk
;
628 /* disable interrupts for all banks */
629 for (bank_num
= 0; bank_num
< ZYNQ_GPIO_MAX_BANK
; bank_num
++)
630 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL
, gpio
->base_addr
+
631 ZYNQ_GPIO_INTDIS_OFFSET(bank_num
));
633 ret
= gpiochip_irqchip_add(chip
, &zynq_gpio_edge_irqchip
, 0,
634 handle_level_irq
, IRQ_TYPE_NONE
);
636 dev_err(&pdev
->dev
, "Failed to add irq chip\n");
637 goto err_rm_gpiochip
;
640 gpiochip_set_chained_irqchip(chip
, &zynq_gpio_edge_irqchip
, irq
,
641 zynq_gpio_irqhandler
);
643 pm_runtime_set_active(&pdev
->dev
);
644 pm_runtime_enable(&pdev
->dev
);
646 device_set_wakeup_capable(&pdev
->dev
, 1);
651 if (gpiochip_remove(chip
))
652 dev_err(&pdev
->dev
, "Failed to remove gpio chip\n");
654 clk_disable_unprepare(gpio
->clk
);
660 * zynq_gpio_remove - Driver removal function
661 * @pdev: platform device instance
665 static int zynq_gpio_remove(struct platform_device
*pdev
)
668 struct zynq_gpio
*gpio
= platform_get_drvdata(pdev
);
670 pm_runtime_get_sync(&pdev
->dev
);
672 ret
= gpiochip_remove(&gpio
->chip
);
674 dev_err(&pdev
->dev
, "Failed to remove gpio chip\n");
677 clk_disable_unprepare(gpio
->clk
);
678 device_set_wakeup_capable(&pdev
->dev
, 0);
682 static struct of_device_id zynq_gpio_of_match
[] = {
683 { .compatible
= "xlnx,zynq-gpio-1.0", },
684 { /* end of table */ }
686 MODULE_DEVICE_TABLE(of
, zynq_gpio_of_match
);
688 static struct platform_driver zynq_gpio_driver
= {
691 .owner
= THIS_MODULE
,
692 .pm
= &zynq_gpio_dev_pm_ops
,
693 .of_match_table
= zynq_gpio_of_match
,
695 .probe
= zynq_gpio_probe
,
696 .remove
= zynq_gpio_remove
,
700 * zynq_gpio_init - Initial driver registration call
702 * Return: value from platform_driver_register
704 static int __init
zynq_gpio_init(void)
706 return platform_driver_register(&zynq_gpio_driver
);
708 postcore_initcall(zynq_gpio_init
);
710 MODULE_AUTHOR("Xilinx Inc.");
711 MODULE_DESCRIPTION("Zynq GPIO driver");
712 MODULE_LICENSE("GPL");