2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56 #include "amdgpu_acp.h"
58 #include "gpu_scheduler.h"
63 extern int amdgpu_modeset
;
64 extern int amdgpu_vram_limit
;
65 extern int amdgpu_gart_size
;
66 extern int amdgpu_benchmarking
;
67 extern int amdgpu_testing
;
68 extern int amdgpu_audio
;
69 extern int amdgpu_disp_priority
;
70 extern int amdgpu_hw_i2c
;
71 extern int amdgpu_pcie_gen2
;
72 extern int amdgpu_msi
;
73 extern int amdgpu_lockup_timeout
;
74 extern int amdgpu_dpm
;
75 extern int amdgpu_smc_load_fw
;
76 extern int amdgpu_aspm
;
77 extern int amdgpu_runtime_pm
;
78 extern unsigned amdgpu_ip_block_mask
;
79 extern int amdgpu_bapm
;
80 extern int amdgpu_deep_color
;
81 extern int amdgpu_vm_size
;
82 extern int amdgpu_vm_block_size
;
83 extern int amdgpu_vm_fault_stop
;
84 extern int amdgpu_vm_debug
;
85 extern int amdgpu_sched_jobs
;
86 extern int amdgpu_sched_hw_submission
;
87 extern int amdgpu_powerplay
;
89 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
90 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
91 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
92 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
93 #define AMDGPU_IB_POOL_SIZE 16
94 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
95 #define AMDGPUFB_CONN_LIMIT 4
96 #define AMDGPU_BIOS_NUM_SCRATCH 8
98 /* max number of rings */
99 #define AMDGPU_MAX_RINGS 16
100 #define AMDGPU_MAX_GFX_RINGS 1
101 #define AMDGPU_MAX_COMPUTE_RINGS 8
102 #define AMDGPU_MAX_VCE_RINGS 2
104 /* max number of IP instances */
105 #define AMDGPU_MAX_SDMA_INSTANCES 2
107 /* hardcode that limit for now */
108 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
110 /* hard reset data */
111 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114 #define AMDGPU_RESET_GFX (1 << 0)
115 #define AMDGPU_RESET_COMPUTE (1 << 1)
116 #define AMDGPU_RESET_DMA (1 << 2)
117 #define AMDGPU_RESET_CP (1 << 3)
118 #define AMDGPU_RESET_GRBM (1 << 4)
119 #define AMDGPU_RESET_DMA1 (1 << 5)
120 #define AMDGPU_RESET_RLC (1 << 6)
121 #define AMDGPU_RESET_SEM (1 << 7)
122 #define AMDGPU_RESET_IH (1 << 8)
123 #define AMDGPU_RESET_VMC (1 << 9)
124 #define AMDGPU_RESET_MC (1 << 10)
125 #define AMDGPU_RESET_DISPLAY (1 << 11)
126 #define AMDGPU_RESET_UVD (1 << 12)
127 #define AMDGPU_RESET_VCE (1 << 13)
128 #define AMDGPU_RESET_VCE1 (1 << 14)
131 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
132 #define AMDGPU_CG_BLOCK_MC (1 << 1)
133 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
134 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
135 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
136 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
137 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
140 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
141 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
142 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
143 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
144 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
145 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
146 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
147 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
148 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
149 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
150 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
151 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
152 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
153 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
154 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
155 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
156 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
159 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
160 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
161 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
162 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
163 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
164 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
165 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
166 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
167 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
168 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
169 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
171 /* GFX current status */
172 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
173 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
174 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
175 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
176 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
178 /* max cursor sizes (in pixels) */
179 #define CIK_CURSOR_WIDTH 128
180 #define CIK_CURSOR_HEIGHT 128
182 struct amdgpu_device
;
187 struct amdgpu_cs_parser
;
189 struct amdgpu_irq_src
;
193 AMDGPU_CP_IRQ_GFX_EOP
= 0,
194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
206 enum amdgpu_sdma_irq
{
207 AMDGPU_SDMA_IRQ_TRAP0
= 0,
208 AMDGPU_SDMA_IRQ_TRAP1
,
213 enum amdgpu_thermal_irq
{
214 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
215 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
217 AMDGPU_THERMAL_IRQ_LAST
220 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
221 enum amd_ip_block_type block_type
,
222 enum amd_clockgating_state state
);
223 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
224 enum amd_ip_block_type block_type
,
225 enum amd_powergating_state state
);
227 struct amdgpu_ip_block_version
{
228 enum amd_ip_block_type type
;
232 const struct amd_ip_funcs
*funcs
;
235 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
236 enum amd_ip_block_type type
,
237 u32 major
, u32 minor
);
239 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
240 struct amdgpu_device
*adev
,
241 enum amd_ip_block_type type
);
243 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
244 struct amdgpu_buffer_funcs
{
245 /* maximum bytes in a single operation */
246 uint32_t copy_max_bytes
;
248 /* number of dw to reserve per operation */
249 unsigned copy_num_dw
;
251 /* used for buffer migration */
252 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
253 /* src addr in bytes */
255 /* dst addr in bytes */
257 /* number of byte to transfer */
258 uint32_t byte_count
);
260 /* maximum bytes in a single operation */
261 uint32_t fill_max_bytes
;
263 /* number of dw to reserve per operation */
264 unsigned fill_num_dw
;
266 /* used for buffer clearing */
267 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
268 /* value to write to memory */
270 /* dst addr in bytes */
272 /* number of byte to fill */
273 uint32_t byte_count
);
276 /* provided by hw blocks that can write ptes, e.g., sdma */
277 struct amdgpu_vm_pte_funcs
{
278 /* copy pte entries from GART */
279 void (*copy_pte
)(struct amdgpu_ib
*ib
,
280 uint64_t pe
, uint64_t src
,
282 /* write pte one entry at a time with addr mapping */
283 void (*write_pte
)(struct amdgpu_ib
*ib
,
284 const dma_addr_t
*pages_addr
, uint64_t pe
,
285 uint64_t addr
, unsigned count
,
286 uint32_t incr
, uint32_t flags
);
287 /* for linear pte/pde updates without addr mapping */
288 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
290 uint64_t addr
, unsigned count
,
291 uint32_t incr
, uint32_t flags
);
294 /* provided by the gmc block */
295 struct amdgpu_gart_funcs
{
296 /* flush the vm tlb via mmio */
297 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
299 /* write pte/pde updates using the cpu */
300 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
301 void *cpu_pt_addr
, /* cpu addr of page table */
302 uint32_t gpu_page_idx
, /* pte/pde to update */
303 uint64_t addr
, /* addr to write into pte/pde */
304 uint32_t flags
); /* access flags */
307 /* provided by the ih block */
308 struct amdgpu_ih_funcs
{
309 /* ring read/write ptr handling, called from interrupt context */
310 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
311 void (*decode_iv
)(struct amdgpu_device
*adev
,
312 struct amdgpu_iv_entry
*entry
);
313 void (*set_rptr
)(struct amdgpu_device
*adev
);
316 /* provided by hw blocks that expose a ring buffer for commands */
317 struct amdgpu_ring_funcs
{
318 /* ring read/write ptr handling */
319 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
320 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
321 void (*set_wptr
)(struct amdgpu_ring
*ring
);
322 /* validating and patching of IBs */
323 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
324 /* command emit functions */
325 void (*emit_ib
)(struct amdgpu_ring
*ring
,
326 struct amdgpu_ib
*ib
);
327 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
328 uint64_t seq
, unsigned flags
);
329 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
331 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
332 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
333 uint32_t gds_base
, uint32_t gds_size
,
334 uint32_t gws_base
, uint32_t gws_size
,
335 uint32_t oa_base
, uint32_t oa_size
);
336 /* testing functions */
337 int (*test_ring
)(struct amdgpu_ring
*ring
);
338 int (*test_ib
)(struct amdgpu_ring
*ring
);
339 /* insert NOP packets */
340 void (*insert_nop
)(struct amdgpu_ring
*ring
, uint32_t count
);
341 /* pad the indirect buffer to the necessary number of dw */
342 void (*pad_ib
)(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
);
348 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
349 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
354 struct amdgpu_dummy_page
{
358 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
359 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
366 #define AMDGPU_MAX_PPLL 3
368 struct amdgpu_clock
{
369 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
370 struct amdgpu_pll spll
;
371 struct amdgpu_pll mpll
;
373 uint32_t default_mclk
;
374 uint32_t default_sclk
;
375 uint32_t default_dispclk
;
376 uint32_t current_dispclk
;
378 uint32_t max_pixel_clock
;
384 struct amdgpu_fence_driver
{
386 volatile uint32_t *cpu_addr
;
387 /* sync_seq is protected by ring emission lock */
391 struct amdgpu_irq_src
*irq_src
;
393 struct timer_list fallback_timer
;
394 wait_queue_head_t fence_queue
;
397 /* some special values for the owner field */
398 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
399 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
401 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
402 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
404 struct amdgpu_fence
{
408 struct amdgpu_ring
*ring
;
411 /* filp or special value for fence creator */
414 wait_queue_t fence_wake
;
417 struct amdgpu_user_fence
{
419 struct amdgpu_bo
*bo
;
420 /* write-back address offset to bo start */
424 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
425 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
426 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
428 int amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
);
429 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
430 struct amdgpu_irq_src
*irq_src
,
432 void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev
);
433 void amdgpu_fence_driver_resume(struct amdgpu_device
*adev
);
434 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, void *owner
,
435 struct amdgpu_fence
**fence
);
436 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
437 int amdgpu_fence_wait_next(struct amdgpu_ring
*ring
);
438 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
439 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
445 struct ttm_bo_global_ref bo_global_ref
;
446 struct drm_global_reference mem_global_ref
;
447 struct ttm_bo_device bdev
;
448 bool mem_global_referenced
;
451 #if defined(CONFIG_DEBUG_FS)
456 /* buffer handling */
457 const struct amdgpu_buffer_funcs
*buffer_funcs
;
458 struct amdgpu_ring
*buffer_funcs_ring
;
461 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
465 struct reservation_object
*resv
,
466 struct fence
**fence
);
467 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
469 struct amdgpu_bo_list_entry
{
470 struct amdgpu_bo
*robj
;
471 struct ttm_validate_buffer tv
;
472 struct amdgpu_bo_va
*bo_va
;
476 struct amdgpu_bo_va_mapping
{
477 struct list_head list
;
478 struct interval_tree_node it
;
483 /* bo virtual addresses in a specific vm */
484 struct amdgpu_bo_va
{
486 /* protected by bo being reserved */
487 struct list_head bo_list
;
488 struct fence
*last_pt_update
;
491 /* protected by vm mutex and spinlock */
492 struct list_head vm_status
;
494 /* mappings for this bo_va */
495 struct list_head invalids
;
496 struct list_head valids
;
498 /* constant after initialization */
499 struct amdgpu_vm
*vm
;
500 struct amdgpu_bo
*bo
;
503 #define AMDGPU_GEM_DOMAIN_MAX 0x3
506 /* Protected by gem.mutex */
507 struct list_head list
;
508 /* Protected by tbo.reserved */
509 u32 prefered_domains
;
511 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
512 struct ttm_placement placement
;
513 struct ttm_buffer_object tbo
;
514 struct ttm_bo_kmap_obj kmap
;
522 /* list of all virtual address to which this bo
526 /* Constant after initialization */
527 struct amdgpu_device
*adev
;
528 struct drm_gem_object gem_base
;
529 struct amdgpu_bo
*parent
;
531 struct ttm_bo_kmap_obj dma_buf_vmap
;
533 struct amdgpu_mn
*mn
;
534 struct list_head mn_list
;
536 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
538 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
539 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
540 struct drm_file
*file_priv
);
541 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
542 struct drm_file
*file_priv
);
543 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
544 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
545 struct drm_gem_object
*amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
546 struct dma_buf_attachment
*attach
,
547 struct sg_table
*sg
);
548 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
549 struct drm_gem_object
*gobj
,
551 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
552 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
553 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
554 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
555 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
556 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
558 /* sub-allocation manager, it has to be protected by another lock.
559 * By conception this is an helper for other part of the driver
560 * like the indirect buffer or semaphore, which both have their
563 * Principe is simple, we keep a list of sub allocation in offset
564 * order (first entry has offset == 0, last entry has the highest
567 * When allocating new object we first check if there is room at
568 * the end total_size - (last_object_offset + last_object_size) >=
569 * alloc_size. If so we allocate new object there.
571 * When there is not enough room at the end, we start waiting for
572 * each sub object until we reach object_offset+object_size >=
573 * alloc_size, this object then become the sub object we return.
575 * Alignment can't be bigger than page size.
577 * Hole are not considered for allocation to keep things simple.
578 * Assumption is that there won't be hole (all object on same
581 struct amdgpu_sa_manager
{
582 wait_queue_head_t wq
;
583 struct amdgpu_bo
*bo
;
584 struct list_head
*hole
;
585 struct list_head flist
[AMDGPU_MAX_RINGS
];
586 struct list_head olist
;
596 /* sub-allocation buffer */
597 struct amdgpu_sa_bo
{
598 struct list_head olist
;
599 struct list_head flist
;
600 struct amdgpu_sa_manager
*manager
;
611 struct list_head objects
;
614 int amdgpu_gem_init(struct amdgpu_device
*adev
);
615 void amdgpu_gem_fini(struct amdgpu_device
*adev
);
616 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
617 int alignment
, u32 initial_domain
,
618 u64 flags
, bool kernel
,
619 struct drm_gem_object
**obj
);
621 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
622 struct drm_device
*dev
,
623 struct drm_mode_create_dumb
*args
);
624 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
625 struct drm_device
*dev
,
626 uint32_t handle
, uint64_t *offset_p
);
631 DECLARE_HASHTABLE(fences
, 4);
632 struct fence
*last_vm_update
;
635 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
636 int amdgpu_sync_fence(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
638 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
639 struct amdgpu_sync
*sync
,
640 struct reservation_object
*resv
,
642 struct fence
*amdgpu_sync_get_fence(struct amdgpu_sync
*sync
);
643 int amdgpu_sync_wait(struct amdgpu_sync
*sync
);
644 void amdgpu_sync_free(struct amdgpu_sync
*sync
);
647 * GART structures, functions & helpers
651 #define AMDGPU_GPU_PAGE_SIZE 4096
652 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
653 #define AMDGPU_GPU_PAGE_SHIFT 12
654 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
657 dma_addr_t table_addr
;
658 struct amdgpu_bo
*robj
;
660 unsigned num_gpu_pages
;
661 unsigned num_cpu_pages
;
664 dma_addr_t
*pages_addr
;
666 const struct amdgpu_gart_funcs
*gart_funcs
;
669 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
670 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
671 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
672 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
673 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
674 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
675 int amdgpu_gart_init(struct amdgpu_device
*adev
);
676 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
677 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, unsigned offset
,
679 int amdgpu_gart_bind(struct amdgpu_device
*adev
, unsigned offset
,
680 int pages
, struct page
**pagelist
,
681 dma_addr_t
*dma_addr
, uint32_t flags
);
684 * GPU MC structures, functions & helpers
687 resource_size_t aper_size
;
688 resource_size_t aper_base
;
689 resource_size_t agp_base
;
690 /* for some chips with <= 32MB we need to lie
691 * about vram size near mc fb location */
693 u64 visible_vram_size
;
704 const struct firmware
*fw
; /* MC firmware */
706 struct amdgpu_irq_src vm_fault
;
711 * GPU doorbell structures, functions & helpers
713 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
715 AMDGPU_DOORBELL_KIQ
= 0x000,
716 AMDGPU_DOORBELL_HIQ
= 0x001,
717 AMDGPU_DOORBELL_DIQ
= 0x002,
718 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
719 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
720 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
721 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
722 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
723 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
724 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
725 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
726 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
727 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
728 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
729 AMDGPU_DOORBELL_IH
= 0x1E8,
730 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
731 AMDGPU_DOORBELL_INVALID
= 0xFFFF
732 } AMDGPU_DOORBELL_ASSIGNMENT
;
734 struct amdgpu_doorbell
{
736 resource_size_t base
;
737 resource_size_t size
;
739 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
742 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
743 phys_addr_t
*aperture_base
,
744 size_t *aperture_size
,
745 size_t *start_offset
);
751 struct amdgpu_flip_work
{
752 struct work_struct flip_work
;
753 struct work_struct unpin_work
;
754 struct amdgpu_device
*adev
;
757 struct drm_pending_vblank_event
*event
;
758 struct amdgpu_bo
*old_rbo
;
760 unsigned shared_count
;
761 struct fence
**shared
;
770 struct amdgpu_sa_bo
*sa_bo
;
774 struct amdgpu_fence
*fence
;
775 struct amdgpu_user_fence
*user
;
777 struct amdgpu_vm
*vm
;
778 struct amdgpu_ctx
*ctx
;
779 uint32_t gds_base
, gds_size
;
780 uint32_t gws_base
, gws_size
;
781 uint32_t oa_base
, oa_size
;
783 /* resulting sequence number */
787 enum amdgpu_ring_type
{
788 AMDGPU_RING_TYPE_GFX
,
789 AMDGPU_RING_TYPE_COMPUTE
,
790 AMDGPU_RING_TYPE_SDMA
,
791 AMDGPU_RING_TYPE_UVD
,
795 extern struct amd_sched_backend_ops amdgpu_sched_ops
;
797 int amdgpu_job_alloc(struct amdgpu_device
*adev
, unsigned num_ibs
,
798 struct amdgpu_job
**job
);
799 int amdgpu_job_alloc_with_ib(struct amdgpu_device
*adev
, unsigned size
,
800 struct amdgpu_job
**job
);
801 void amdgpu_job_free(struct amdgpu_job
*job
);
802 int amdgpu_job_submit(struct amdgpu_job
*job
, struct amdgpu_ring
*ring
,
803 struct amd_sched_entity
*entity
, void *owner
,
807 struct amdgpu_device
*adev
;
808 const struct amdgpu_ring_funcs
*funcs
;
809 struct amdgpu_fence_driver fence_drv
;
810 struct amd_gpu_scheduler sched
;
812 spinlock_t fence_lock
;
813 struct amdgpu_bo
*ring_obj
;
814 volatile uint32_t *ring
;
816 u64 next_rptr_gpu_addr
;
817 volatile u32
*next_rptr_cpu_addr
;
832 struct amdgpu_bo
*mqd_obj
;
836 unsigned next_rptr_offs
;
838 struct amdgpu_ctx
*current_ctx
;
839 enum amdgpu_ring_type type
;
847 /* maximum number of VMIDs */
848 #define AMDGPU_NUM_VM 16
850 /* number of entries in page table */
851 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
853 /* PTBs (Page Table Blocks) need to be aligned to 32K */
854 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
855 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
856 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
858 #define AMDGPU_PTE_VALID (1 << 0)
859 #define AMDGPU_PTE_SYSTEM (1 << 1)
860 #define AMDGPU_PTE_SNOOPED (1 << 2)
863 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
865 #define AMDGPU_PTE_READABLE (1 << 5)
866 #define AMDGPU_PTE_WRITEABLE (1 << 6)
868 /* PTE (Page Table Entry) fragment field for different page sizes */
869 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
870 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
871 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
873 /* How to programm VM fault handling */
874 #define AMDGPU_VM_FAULT_STOP_NEVER 0
875 #define AMDGPU_VM_FAULT_STOP_FIRST 1
876 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
878 struct amdgpu_vm_pt
{
879 struct amdgpu_bo_list_entry entry
;
883 struct amdgpu_vm_id
{
885 uint64_t pd_gpu_addr
;
886 /* last flushed PD/PT update */
887 struct fence
*flushed_updates
;
891 /* tree of virtual addresses mapped */
895 /* protecting invalidated */
896 spinlock_t status_lock
;
898 /* BOs moved, but not yet updated in the PT */
899 struct list_head invalidated
;
901 /* BOs cleared in the PT because of a move */
902 struct list_head cleared
;
904 /* BO mappings freed, but not yet updated in the PT */
905 struct list_head freed
;
907 /* contains the page directory */
908 struct amdgpu_bo
*page_directory
;
909 unsigned max_pde_used
;
910 struct fence
*page_directory_fence
;
912 /* array of page tables, one for each page directory entry */
913 struct amdgpu_vm_pt
*page_tables
;
915 /* for id and flush management per ring */
916 struct amdgpu_vm_id ids
[AMDGPU_MAX_RINGS
];
918 /* protecting freed */
919 spinlock_t freed_lock
;
921 /* Scheduler entity for page table updates */
922 struct amd_sched_entity entity
;
925 struct amdgpu_vm_manager_id
{
926 struct list_head list
;
927 struct fence
*active
;
931 struct amdgpu_vm_manager
{
932 /* Handling of VMIDs */
935 struct list_head ids_lru
;
936 struct amdgpu_vm_manager_id ids
[AMDGPU_NUM_VM
];
939 /* vram base address for page table entry */
940 u64 vram_base_offset
;
943 /* vm pte handling */
944 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
945 struct amdgpu_ring
*vm_pte_rings
[AMDGPU_MAX_RINGS
];
946 unsigned vm_pte_num_rings
;
947 atomic_t vm_pte_next_ring
;
950 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
);
951 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
);
952 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
953 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
954 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
955 struct list_head
*validated
,
956 struct amdgpu_bo_list_entry
*entry
);
957 void amdgpu_vm_get_pt_bos(struct amdgpu_vm
*vm
, struct list_head
*duplicates
);
958 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
959 struct amdgpu_vm
*vm
);
960 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
961 struct amdgpu_sync
*sync
, struct fence
*fence
);
962 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
963 struct amdgpu_vm
*vm
,
964 struct fence
*updates
);
965 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
);
966 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
967 struct amdgpu_vm
*vm
);
968 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
969 struct amdgpu_vm
*vm
);
970 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
971 struct amdgpu_sync
*sync
);
972 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
973 struct amdgpu_bo_va
*bo_va
,
974 struct ttm_mem_reg
*mem
);
975 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
976 struct amdgpu_bo
*bo
);
977 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
978 struct amdgpu_bo
*bo
);
979 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
980 struct amdgpu_vm
*vm
,
981 struct amdgpu_bo
*bo
);
982 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
983 struct amdgpu_bo_va
*bo_va
,
984 uint64_t addr
, uint64_t offset
,
985 uint64_t size
, uint32_t flags
);
986 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
987 struct amdgpu_bo_va
*bo_va
,
989 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
990 struct amdgpu_bo_va
*bo_va
);
993 * context related structures
996 struct amdgpu_ctx_ring
{
998 struct fence
**fences
;
999 struct amd_sched_entity entity
;
1003 struct kref refcount
;
1004 struct amdgpu_device
*adev
;
1005 unsigned reset_counter
;
1006 spinlock_t ring_lock
;
1007 struct fence
**fences
;
1008 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
1011 struct amdgpu_ctx_mgr
{
1012 struct amdgpu_device
*adev
;
1014 /* protected by lock */
1015 struct idr ctx_handles
;
1018 int amdgpu_ctx_init(struct amdgpu_device
*adev
, enum amd_sched_priority pri
,
1019 struct amdgpu_ctx
*ctx
);
1020 void amdgpu_ctx_fini(struct amdgpu_ctx
*ctx
);
1022 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
1023 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
1025 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
1026 struct fence
*fence
);
1027 struct fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
1028 struct amdgpu_ring
*ring
, uint64_t seq
);
1030 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
1031 struct drm_file
*filp
);
1033 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
1034 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
1037 * file private structure
1040 struct amdgpu_fpriv
{
1041 struct amdgpu_vm vm
;
1042 struct mutex bo_list_lock
;
1043 struct idr bo_list_handles
;
1044 struct amdgpu_ctx_mgr ctx_mgr
;
1051 struct amdgpu_bo_list
{
1053 struct amdgpu_bo
*gds_obj
;
1054 struct amdgpu_bo
*gws_obj
;
1055 struct amdgpu_bo
*oa_obj
;
1057 unsigned num_entries
;
1058 struct amdgpu_bo_list_entry
*array
;
1061 struct amdgpu_bo_list
*
1062 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1063 void amdgpu_bo_list_get_list(struct amdgpu_bo_list
*list
,
1064 struct list_head
*validated
);
1065 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1066 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1071 #include "clearstate_defs.h"
1074 /* for power gating */
1075 struct amdgpu_bo
*save_restore_obj
;
1076 uint64_t save_restore_gpu_addr
;
1077 volatile uint32_t *sr_ptr
;
1078 const u32
*reg_list
;
1080 /* for clear state */
1081 struct amdgpu_bo
*clear_state_obj
;
1082 uint64_t clear_state_gpu_addr
;
1083 volatile uint32_t *cs_ptr
;
1084 const struct cs_section_def
*cs_data
;
1085 u32 clear_state_size
;
1087 struct amdgpu_bo
*cp_table_obj
;
1088 uint64_t cp_table_gpu_addr
;
1089 volatile uint32_t *cp_table_ptr
;
1094 struct amdgpu_bo
*hpd_eop_obj
;
1095 u64 hpd_eop_gpu_addr
;
1102 * GPU scratch registers structures, functions & helpers
1104 struct amdgpu_scratch
{
1112 * GFX configurations
1114 struct amdgpu_gca_config
{
1115 unsigned max_shader_engines
;
1116 unsigned max_tile_pipes
;
1117 unsigned max_cu_per_sh
;
1118 unsigned max_sh_per_se
;
1119 unsigned max_backends_per_se
;
1120 unsigned max_texture_channel_caches
;
1122 unsigned max_gs_threads
;
1123 unsigned max_hw_contexts
;
1124 unsigned sc_prim_fifo_size_frontend
;
1125 unsigned sc_prim_fifo_size_backend
;
1126 unsigned sc_hiz_tile_fifo_size
;
1127 unsigned sc_earlyz_tile_fifo_size
;
1129 unsigned num_tile_pipes
;
1130 unsigned backend_enable_mask
;
1131 unsigned mem_max_burst_length_bytes
;
1132 unsigned mem_row_size_in_kb
;
1133 unsigned shader_engine_tile_size
;
1135 unsigned multi_gpu_tile_size
;
1136 unsigned mc_arb_ramcfg
;
1137 unsigned gb_addr_config
;
1139 uint32_t tile_mode_array
[32];
1140 uint32_t macrotile_mode_array
[16];
1144 struct mutex gpu_clock_mutex
;
1145 struct amdgpu_gca_config config
;
1146 struct amdgpu_rlc rlc
;
1147 struct amdgpu_mec mec
;
1148 struct amdgpu_scratch scratch
;
1149 const struct firmware
*me_fw
; /* ME firmware */
1150 uint32_t me_fw_version
;
1151 const struct firmware
*pfp_fw
; /* PFP firmware */
1152 uint32_t pfp_fw_version
;
1153 const struct firmware
*ce_fw
; /* CE firmware */
1154 uint32_t ce_fw_version
;
1155 const struct firmware
*rlc_fw
; /* RLC firmware */
1156 uint32_t rlc_fw_version
;
1157 const struct firmware
*mec_fw
; /* MEC firmware */
1158 uint32_t mec_fw_version
;
1159 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1160 uint32_t mec2_fw_version
;
1161 uint32_t me_feature_version
;
1162 uint32_t ce_feature_version
;
1163 uint32_t pfp_feature_version
;
1164 uint32_t rlc_feature_version
;
1165 uint32_t mec_feature_version
;
1166 uint32_t mec2_feature_version
;
1167 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1168 unsigned num_gfx_rings
;
1169 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1170 unsigned num_compute_rings
;
1171 struct amdgpu_irq_src eop_irq
;
1172 struct amdgpu_irq_src priv_reg_irq
;
1173 struct amdgpu_irq_src priv_inst_irq
;
1175 uint32_t gfx_current_status
;
1177 unsigned ce_ram_size
;
1180 int amdgpu_ib_get(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1181 unsigned size
, struct amdgpu_ib
*ib
);
1182 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
);
1183 int amdgpu_ib_schedule(struct amdgpu_ring
*ring
, unsigned num_ibs
,
1184 struct amdgpu_ib
*ib
, void *owner
,
1185 struct fence
*last_vm_update
,
1187 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1188 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1189 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1190 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1191 void amdgpu_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
);
1192 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
);
1193 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1194 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1195 unsigned amdgpu_ring_backup(struct amdgpu_ring
*ring
,
1197 int amdgpu_ring_restore(struct amdgpu_ring
*ring
,
1198 unsigned size
, uint32_t *data
);
1199 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1200 unsigned ring_size
, u32 nop
, u32 align_mask
,
1201 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1202 enum amdgpu_ring_type ring_type
);
1203 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1204 struct amdgpu_ring
*amdgpu_ring_from_fence(struct fence
*f
);
1209 struct amdgpu_cs_chunk
{
1215 struct amdgpu_cs_parser
{
1216 struct amdgpu_device
*adev
;
1217 struct drm_file
*filp
;
1218 struct amdgpu_ctx
*ctx
;
1222 struct amdgpu_cs_chunk
*chunks
;
1224 /* scheduler job object */
1225 struct amdgpu_job
*job
;
1227 /* buffer objects */
1228 struct ww_acquire_ctx ticket
;
1229 struct amdgpu_bo_list
*bo_list
;
1230 struct amdgpu_bo_list_entry vm_pd
;
1231 struct list_head validated
;
1232 struct fence
*fence
;
1233 uint64_t bytes_moved_threshold
;
1234 uint64_t bytes_moved
;
1237 struct amdgpu_bo_list_entry uf_entry
;
1241 struct amd_sched_job base
;
1242 struct amdgpu_device
*adev
;
1243 struct amdgpu_ring
*ring
;
1244 struct amdgpu_sync sync
;
1245 struct amdgpu_ib
*ibs
;
1248 struct amdgpu_user_fence uf
;
1250 #define to_amdgpu_job(sched_job) \
1251 container_of((sched_job), struct amdgpu_job, base)
1253 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
,
1254 uint32_t ib_idx
, int idx
)
1256 return p
->job
->ibs
[ib_idx
].ptr
[idx
];
1259 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser
*p
,
1260 uint32_t ib_idx
, int idx
,
1263 p
->job
->ibs
[ib_idx
].ptr
[idx
] = value
;
1269 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1272 struct amdgpu_bo
*wb_obj
;
1273 volatile uint32_t *wb
;
1275 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1276 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1279 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1280 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1284 enum amdgpu_int_thermal_type
{
1286 THERMAL_TYPE_EXTERNAL
,
1287 THERMAL_TYPE_EXTERNAL_GPIO
,
1290 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1291 THERMAL_TYPE_EVERGREEN
,
1295 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1300 enum amdgpu_dpm_auto_throttle_src
{
1301 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1302 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1305 enum amdgpu_dpm_event_src
{
1306 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1307 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1308 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1309 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1310 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1313 #define AMDGPU_MAX_VCE_LEVELS 6
1315 enum amdgpu_vce_level
{
1316 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1317 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1318 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1319 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1320 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1321 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1325 u32 caps
; /* vbios flags */
1326 u32
class; /* vbios flags */
1327 u32 class2
; /* vbios flags */
1335 enum amdgpu_vce_level vce_level
;
1340 struct amdgpu_dpm_thermal
{
1341 /* thermal interrupt work */
1342 struct work_struct work
;
1343 /* low temperature threshold */
1345 /* high temperature threshold */
1347 /* was last interrupt low to high or high to low */
1349 /* interrupt source */
1350 struct amdgpu_irq_src irq
;
1353 enum amdgpu_clk_action
1359 struct amdgpu_blacklist_clocks
1363 enum amdgpu_clk_action action
;
1366 struct amdgpu_clock_and_voltage_limits
{
1373 struct amdgpu_clock_array
{
1378 struct amdgpu_clock_voltage_dependency_entry
{
1383 struct amdgpu_clock_voltage_dependency_table
{
1385 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1388 union amdgpu_cac_leakage_entry
{
1400 struct amdgpu_cac_leakage_table
{
1402 union amdgpu_cac_leakage_entry
*entries
;
1405 struct amdgpu_phase_shedding_limits_entry
{
1411 struct amdgpu_phase_shedding_limits_table
{
1413 struct amdgpu_phase_shedding_limits_entry
*entries
;
1416 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1422 struct amdgpu_uvd_clock_voltage_dependency_table
{
1424 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1427 struct amdgpu_vce_clock_voltage_dependency_entry
{
1433 struct amdgpu_vce_clock_voltage_dependency_table
{
1435 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1438 struct amdgpu_ppm_table
{
1440 u16 cpu_core_number
;
1442 u32 small_ac_platform_tdp
;
1444 u32 small_ac_platform_tdc
;
1451 struct amdgpu_cac_tdp_table
{
1453 u16 configurable_tdp
;
1455 u16 battery_power_limit
;
1456 u16 small_power_limit
;
1457 u16 low_cac_leakage
;
1458 u16 high_cac_leakage
;
1459 u16 maximum_power_delivery_limit
;
1462 struct amdgpu_dpm_dynamic_state
{
1463 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1464 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1465 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1466 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1467 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1468 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1469 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1470 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1471 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1472 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1473 struct amdgpu_clock_array valid_sclk_values
;
1474 struct amdgpu_clock_array valid_mclk_values
;
1475 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1476 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1477 u32 mclk_sclk_ratio
;
1478 u32 sclk_mclk_delta
;
1479 u16 vddc_vddci_delta
;
1480 u16 min_vddc_for_pcie_gen2
;
1481 struct amdgpu_cac_leakage_table cac_leakage_table
;
1482 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1483 struct amdgpu_ppm_table
*ppm_table
;
1484 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1487 struct amdgpu_dpm_fan
{
1498 u16 default_max_fan_pwm
;
1499 u16 default_fan_output_sensitivity
;
1500 u16 fan_output_sensitivity
;
1501 bool ucode_fan_control
;
1504 enum amdgpu_pcie_gen
{
1505 AMDGPU_PCIE_GEN1
= 0,
1506 AMDGPU_PCIE_GEN2
= 1,
1507 AMDGPU_PCIE_GEN3
= 2,
1508 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1511 enum amdgpu_dpm_forced_level
{
1512 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1513 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1514 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1515 AMDGPU_DPM_FORCED_LEVEL_MANUAL
= 3,
1518 struct amdgpu_vce_state
{
1529 struct amdgpu_dpm_funcs
{
1530 int (*get_temperature
)(struct amdgpu_device
*adev
);
1531 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1532 int (*set_power_state
)(struct amdgpu_device
*adev
);
1533 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1534 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1535 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1536 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1537 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1538 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1539 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1540 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1541 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1542 void (*powergate_vce
)(struct amdgpu_device
*adev
, bool gate
);
1543 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1544 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1545 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1546 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1547 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1551 struct amdgpu_ps
*ps
;
1552 /* number of valid power states */
1554 /* current power state that is active */
1555 struct amdgpu_ps
*current_ps
;
1556 /* requested power state */
1557 struct amdgpu_ps
*requested_ps
;
1558 /* boot up power state */
1559 struct amdgpu_ps
*boot_ps
;
1560 /* default uvd power state */
1561 struct amdgpu_ps
*uvd_ps
;
1562 /* vce requirements */
1563 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1564 enum amdgpu_vce_level vce_level
;
1565 enum amd_pm_state_type state
;
1566 enum amd_pm_state_type user_state
;
1568 u32 voltage_response_time
;
1569 u32 backbias_response_time
;
1571 u32 new_active_crtcs
;
1572 int new_active_crtc_count
;
1573 u32 current_active_crtcs
;
1574 int current_active_crtc_count
;
1575 struct amdgpu_dpm_dynamic_state dyn_state
;
1576 struct amdgpu_dpm_fan fan
;
1579 u32 near_tdp_limit_adjusted
;
1580 u32 sq_ramping_threshold
;
1584 u16 load_line_slope
;
1587 /* special states active */
1588 bool thermal_active
;
1591 /* thermal handling */
1592 struct amdgpu_dpm_thermal thermal
;
1594 enum amdgpu_dpm_forced_level forced_level
;
1603 struct amdgpu_i2c_chan
*i2c_bus
;
1604 /* internal thermal controller on rv6xx+ */
1605 enum amdgpu_int_thermal_type int_thermal_type
;
1606 struct device
*int_hwmon_dev
;
1607 /* fan control parameters */
1609 u8 fan_pulses_per_revolution
;
1614 bool sysfs_initialized
;
1615 struct amdgpu_dpm dpm
;
1616 const struct firmware
*fw
; /* SMC firmware */
1617 uint32_t fw_version
;
1618 const struct amdgpu_dpm_funcs
*funcs
;
1619 uint32_t pcie_gen_mask
;
1620 uint32_t pcie_mlw_mask
;
1621 struct amd_pp_display_configuration pm_display_cfg
;/* set by DAL */
1624 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
);
1629 #define AMDGPU_MAX_UVD_HANDLES 10
1630 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1631 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1632 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1635 struct amdgpu_bo
*vcpu_bo
;
1638 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1639 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1640 struct delayed_work idle_work
;
1641 const struct firmware
*fw
; /* UVD firmware */
1642 struct amdgpu_ring ring
;
1643 struct amdgpu_irq_src irq
;
1644 bool address_64_bit
;
1650 #define AMDGPU_MAX_VCE_HANDLES 16
1651 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1653 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1654 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1657 struct amdgpu_bo
*vcpu_bo
;
1659 unsigned fw_version
;
1660 unsigned fb_version
;
1661 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1662 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1663 uint32_t img_size
[AMDGPU_MAX_VCE_HANDLES
];
1664 struct delayed_work idle_work
;
1665 const struct firmware
*fw
; /* VCE firmware */
1666 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1667 struct amdgpu_irq_src irq
;
1668 unsigned harvest_config
;
1674 struct amdgpu_sdma_instance
{
1676 const struct firmware
*fw
;
1677 uint32_t fw_version
;
1678 uint32_t feature_version
;
1680 struct amdgpu_ring ring
;
1684 struct amdgpu_sdma
{
1685 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1686 struct amdgpu_irq_src trap_irq
;
1687 struct amdgpu_irq_src illegal_inst_irq
;
1694 struct amdgpu_firmware
{
1695 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1697 struct amdgpu_bo
*fw_buf
;
1698 unsigned int fw_size
;
1704 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1710 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1711 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1712 struct amdgpu_ring
*cpA
,
1713 struct amdgpu_ring
*cpB
);
1714 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1719 #if defined(CONFIG_MMU_NOTIFIER)
1720 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1721 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1723 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1727 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1733 struct amdgpu_debugfs
{
1734 struct drm_info_list
*files
;
1738 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1739 struct drm_info_list
*files
,
1741 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1743 #if defined(CONFIG_DEBUG_FS)
1744 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1745 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1749 * amdgpu smumgr functions
1751 struct amdgpu_smumgr_funcs
{
1752 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1753 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1754 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1760 struct amdgpu_smumgr
{
1761 struct amdgpu_bo
*toc_buf
;
1762 struct amdgpu_bo
*smu_buf
;
1763 /* asic priv smu data */
1765 spinlock_t smu_lock
;
1766 /* smumgr functions */
1767 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1768 /* ucode loading complete flag */
1773 * ASIC specific register table accessible by UMD
1775 struct amdgpu_allowed_register_entry
{
1776 uint32_t reg_offset
;
1781 struct amdgpu_cu_info
{
1782 uint32_t number
; /* total active CU number */
1783 uint32_t ao_cu_mask
;
1784 uint32_t bitmap
[4][4];
1789 * ASIC specific functions.
1791 struct amdgpu_asic_funcs
{
1792 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1793 bool (*read_bios_from_rom
)(struct amdgpu_device
*adev
,
1794 u8
*bios
, u32 length_bytes
);
1795 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1796 u32 sh_num
, u32 reg_offset
, u32
*value
);
1797 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1798 int (*reset
)(struct amdgpu_device
*adev
);
1799 /* wait for mc_idle */
1800 int (*wait_for_mc_idle
)(struct amdgpu_device
*adev
);
1801 /* get the reference clock */
1802 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1803 /* get the gpu clock counter */
1804 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1805 int (*get_cu_info
)(struct amdgpu_device
*adev
, struct amdgpu_cu_info
*info
);
1806 /* MM block clocks */
1807 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1808 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1814 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1815 struct drm_file
*filp
);
1816 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1817 struct drm_file
*filp
);
1819 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1820 struct drm_file
*filp
);
1821 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1822 struct drm_file
*filp
);
1823 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1824 struct drm_file
*filp
);
1825 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1826 struct drm_file
*filp
);
1827 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1828 struct drm_file
*filp
);
1829 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1830 struct drm_file
*filp
);
1831 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1832 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1834 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1835 struct drm_file
*filp
);
1837 /* VRAM scratch page for HDP bug, default vram page */
1838 struct amdgpu_vram_scratch
{
1839 struct amdgpu_bo
*robj
;
1840 volatile uint32_t *ptr
;
1847 struct amdgpu_atif_notification_cfg
{
1852 struct amdgpu_atif_notifications
{
1853 bool display_switch
;
1854 bool expansion_mode_change
;
1856 bool forced_power_state
;
1857 bool system_power_state
;
1858 bool display_conf_change
;
1860 bool brightness_change
;
1861 bool dgpu_display_event
;
1864 struct amdgpu_atif_functions
{
1866 bool sbios_requests
;
1867 bool select_active_disp
;
1869 bool get_tv_standard
;
1870 bool set_tv_standard
;
1871 bool get_panel_expansion_mode
;
1872 bool set_panel_expansion_mode
;
1873 bool temperature_change
;
1874 bool graphics_device_types
;
1877 struct amdgpu_atif
{
1878 struct amdgpu_atif_notifications notifications
;
1879 struct amdgpu_atif_functions functions
;
1880 struct amdgpu_atif_notification_cfg notification_cfg
;
1881 struct amdgpu_encoder
*encoder_for_bl
;
1884 struct amdgpu_atcs_functions
{
1888 bool pcie_bus_width
;
1891 struct amdgpu_atcs
{
1892 struct amdgpu_atcs_functions functions
;
1898 void *amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1899 void amdgpu_cgs_destroy_device(void *cgs_device
);
1905 void *amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1906 void amdgpu_cgs_destroy_device(void *cgs_device
);
1909 /* GPU virtualization */
1910 struct amdgpu_virtualization
{
1911 bool supports_sr_iov
;
1915 * Core structure, functions and helpers.
1917 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1918 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1920 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1921 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1923 struct amdgpu_ip_block_status
{
1929 struct amdgpu_device
{
1931 struct drm_device
*ddev
;
1932 struct pci_dev
*pdev
;
1934 #ifdef CONFIG_DRM_AMD_ACP
1935 struct amdgpu_acp acp
;
1939 enum amd_asic_type asic_type
;
1942 uint32_t external_rev_id
;
1943 unsigned long flags
;
1945 const struct amdgpu_asic_funcs
*asic_funcs
;
1950 struct work_struct reset_work
;
1951 struct notifier_block acpi_nb
;
1952 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1953 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1954 unsigned debugfs_count
;
1955 #if defined(CONFIG_DEBUG_FS)
1956 struct dentry
*debugfs_regs
;
1958 struct amdgpu_atif atif
;
1959 struct amdgpu_atcs atcs
;
1960 struct mutex srbm_mutex
;
1961 /* GRBM index mutex. Protects concurrent access to GRBM index */
1962 struct mutex grbm_idx_mutex
;
1963 struct dev_pm_domain vga_pm_domain
;
1964 bool have_disp_power_ref
;
1969 uint16_t bios_header_start
;
1970 struct amdgpu_bo
*stollen_vga_memory
;
1971 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
1973 /* Register/doorbell mmio */
1974 resource_size_t rmmio_base
;
1975 resource_size_t rmmio_size
;
1976 void __iomem
*rmmio
;
1977 /* protects concurrent MM_INDEX/DATA based register access */
1978 spinlock_t mmio_idx_lock
;
1979 /* protects concurrent SMC based register access */
1980 spinlock_t smc_idx_lock
;
1981 amdgpu_rreg_t smc_rreg
;
1982 amdgpu_wreg_t smc_wreg
;
1983 /* protects concurrent PCIE register access */
1984 spinlock_t pcie_idx_lock
;
1985 amdgpu_rreg_t pcie_rreg
;
1986 amdgpu_wreg_t pcie_wreg
;
1987 /* protects concurrent UVD register access */
1988 spinlock_t uvd_ctx_idx_lock
;
1989 amdgpu_rreg_t uvd_ctx_rreg
;
1990 amdgpu_wreg_t uvd_ctx_wreg
;
1991 /* protects concurrent DIDT register access */
1992 spinlock_t didt_idx_lock
;
1993 amdgpu_rreg_t didt_rreg
;
1994 amdgpu_wreg_t didt_wreg
;
1995 /* protects concurrent ENDPOINT (audio) register access */
1996 spinlock_t audio_endpt_idx_lock
;
1997 amdgpu_block_rreg_t audio_endpt_rreg
;
1998 amdgpu_block_wreg_t audio_endpt_wreg
;
1999 void __iomem
*rio_mem
;
2000 resource_size_t rio_mem_size
;
2001 struct amdgpu_doorbell doorbell
;
2003 /* clock/pll info */
2004 struct amdgpu_clock clock
;
2007 struct amdgpu_mc mc
;
2008 struct amdgpu_gart gart
;
2009 struct amdgpu_dummy_page dummy_page
;
2010 struct amdgpu_vm_manager vm_manager
;
2012 /* memory management */
2013 struct amdgpu_mman mman
;
2014 struct amdgpu_gem gem
;
2015 struct amdgpu_vram_scratch vram_scratch
;
2016 struct amdgpu_wb wb
;
2017 atomic64_t vram_usage
;
2018 atomic64_t vram_vis_usage
;
2019 atomic64_t gtt_usage
;
2020 atomic64_t num_bytes_moved
;
2021 atomic_t gpu_reset_counter
;
2024 struct amdgpu_mode_info mode_info
;
2025 struct work_struct hotplug_work
;
2026 struct amdgpu_irq_src crtc_irq
;
2027 struct amdgpu_irq_src pageflip_irq
;
2028 struct amdgpu_irq_src hpd_irq
;
2031 unsigned fence_context
;
2033 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
2035 struct amdgpu_sa_manager ring_tmp_bo
;
2038 struct amdgpu_irq irq
;
2041 struct amd_powerplay powerplay
;
2043 bool pp_force_state_enabled
;
2046 struct amdgpu_pm pm
;
2051 struct amdgpu_smumgr smu
;
2054 struct amdgpu_gfx gfx
;
2057 struct amdgpu_sdma sdma
;
2061 struct amdgpu_uvd uvd
;
2064 struct amdgpu_vce vce
;
2067 struct amdgpu_firmware firmware
;
2070 struct amdgpu_gds gds
;
2072 const struct amdgpu_ip_block_version
*ip_blocks
;
2074 struct amdgpu_ip_block_status
*ip_block_status
;
2075 struct mutex mn_lock
;
2076 DECLARE_HASHTABLE(mn_hash
, 7);
2078 /* tracking pinned memory */
2082 /* amdkfd interface */
2083 struct kfd_dev
*kfd
;
2085 /* kernel conext for IB submission */
2086 struct amdgpu_ctx kernel_ctx
;
2088 struct amdgpu_virtualization virtualization
;
2091 bool amdgpu_device_is_px(struct drm_device
*dev
);
2092 int amdgpu_device_init(struct amdgpu_device
*adev
,
2093 struct drm_device
*ddev
,
2094 struct pci_dev
*pdev
,
2096 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2097 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2099 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2100 bool always_indirect
);
2101 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2102 bool always_indirect
);
2103 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2104 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2106 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2107 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2112 extern const struct fence_ops amdgpu_fence_ops
;
2113 static inline struct amdgpu_fence
*to_amdgpu_fence(struct fence
*f
)
2115 struct amdgpu_fence
*__f
= container_of(f
, struct amdgpu_fence
, base
);
2117 if (__f
->base
.ops
== &amdgpu_fence_ops
)
2124 * Registers read & write functions.
2126 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2127 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2128 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2129 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2130 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2131 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2132 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2133 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2134 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2135 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2136 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2137 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2138 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2139 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2140 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2141 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2142 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2143 #define WREG32_P(reg, val, mask) \
2145 uint32_t tmp_ = RREG32(reg); \
2147 tmp_ |= ((val) & ~(mask)); \
2148 WREG32(reg, tmp_); \
2150 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2151 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2152 #define WREG32_PLL_P(reg, val, mask) \
2154 uint32_t tmp_ = RREG32_PLL(reg); \
2156 tmp_ |= ((val) & ~(mask)); \
2157 WREG32_PLL(reg, tmp_); \
2159 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2160 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2161 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2163 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2164 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2166 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2167 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2169 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2170 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2171 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2173 #define REG_GET_FIELD(value, reg, field) \
2174 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2179 #define RBIOS8(i) (adev->bios[i])
2180 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2181 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2186 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2188 if (ring
->count_dw
<= 0)
2189 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2190 ring
->ring
[ring
->wptr
++] = v
;
2191 ring
->wptr
&= ring
->ptr_mask
;
2195 static inline struct amdgpu_sdma_instance
*
2196 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
2198 struct amdgpu_device
*adev
= ring
->adev
;
2201 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
2202 if (&adev
->sdma
.instance
[i
].ring
== ring
)
2205 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
2206 return &adev
->sdma
.instance
[i
];
2214 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2215 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2216 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2217 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2218 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2219 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2220 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2221 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2222 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2223 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2224 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2225 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2226 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2227 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2228 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2229 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2230 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2231 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2232 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2233 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2234 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2235 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2236 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2237 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2238 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2239 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2240 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2241 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2242 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2243 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2244 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2245 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2246 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2247 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2248 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2249 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2250 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2251 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2252 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2253 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2254 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2255 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2256 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2257 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2258 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2259 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2260 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2261 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2262 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2263 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2264 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2265 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2266 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2267 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2268 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2269 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2271 #define amdgpu_dpm_get_temperature(adev) \
2272 ((adev)->pp_enabled ? \
2273 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2274 (adev)->pm.funcs->get_temperature((adev)))
2276 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2277 ((adev)->pp_enabled ? \
2278 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2279 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2281 #define amdgpu_dpm_get_fan_control_mode(adev) \
2282 ((adev)->pp_enabled ? \
2283 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2284 (adev)->pm.funcs->get_fan_control_mode((adev)))
2286 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2287 ((adev)->pp_enabled ? \
2288 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2289 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2291 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2292 ((adev)->pp_enabled ? \
2293 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2294 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2296 #define amdgpu_dpm_get_sclk(adev, l) \
2297 ((adev)->pp_enabled ? \
2298 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2299 (adev)->pm.funcs->get_sclk((adev), (l)))
2301 #define amdgpu_dpm_get_mclk(adev, l) \
2302 ((adev)->pp_enabled ? \
2303 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2304 (adev)->pm.funcs->get_mclk((adev), (l)))
2307 #define amdgpu_dpm_force_performance_level(adev, l) \
2308 ((adev)->pp_enabled ? \
2309 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2310 (adev)->pm.funcs->force_performance_level((adev), (l)))
2312 #define amdgpu_dpm_powergate_uvd(adev, g) \
2313 ((adev)->pp_enabled ? \
2314 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2315 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2317 #define amdgpu_dpm_powergate_vce(adev, g) \
2318 ((adev)->pp_enabled ? \
2319 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2320 (adev)->pm.funcs->powergate_vce((adev), (g)))
2322 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2323 ((adev)->pp_enabled ? \
2324 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2325 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2327 #define amdgpu_dpm_get_current_power_state(adev) \
2328 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2330 #define amdgpu_dpm_get_performance_level(adev) \
2331 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2333 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2334 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2336 #define amdgpu_dpm_get_pp_table(adev, table) \
2337 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2339 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2340 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2342 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2343 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2345 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2346 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2348 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2349 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2351 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2353 /* Common functions */
2354 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2355 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2356 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2357 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2359 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2360 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2361 u32 ip_instance
, u32 ring
,
2362 struct amdgpu_ring
**out_ring
);
2363 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2364 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2365 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2367 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
);
2368 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
2370 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2371 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2372 struct ttm_mem_reg
*mem
);
2373 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2374 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2375 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2376 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2377 const u32
*registers
,
2378 const u32 array_size
);
2380 bool amdgpu_device_is_px(struct drm_device
*dev
);
2382 #if defined(CONFIG_VGA_SWITCHEROO)
2383 void amdgpu_register_atpx_handler(void);
2384 void amdgpu_unregister_atpx_handler(void);
2386 static inline void amdgpu_register_atpx_handler(void) {}
2387 static inline void amdgpu_unregister_atpx_handler(void) {}
2393 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2394 extern int amdgpu_max_kms_ioctl
;
2396 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2397 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2398 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2399 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2400 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2401 struct drm_file
*file_priv
);
2402 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2403 struct drm_file
*file_priv
);
2404 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2405 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2406 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
2407 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2408 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2409 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, unsigned int pipe
,
2411 struct timeval
*vblank_time
,
2413 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2417 * functions used by amdgpu_encoder.c
2419 struct amdgpu_afmt_acr
{
2433 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2436 #if defined(CONFIG_ACPI)
2437 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2438 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2439 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2440 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2441 u8 perf_req
, bool advertise
);
2442 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2444 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2445 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2448 struct amdgpu_bo_va_mapping
*
2449 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2450 uint64_t addr
, struct amdgpu_bo
**bo
);
2452 #include "amdgpu_object.h"