2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56 #include "amdgpu_acp.h"
58 #include "gpu_scheduler.h"
63 extern int amdgpu_modeset
;
64 extern int amdgpu_vram_limit
;
65 extern int amdgpu_gart_size
;
66 extern int amdgpu_benchmarking
;
67 extern int amdgpu_testing
;
68 extern int amdgpu_audio
;
69 extern int amdgpu_disp_priority
;
70 extern int amdgpu_hw_i2c
;
71 extern int amdgpu_pcie_gen2
;
72 extern int amdgpu_msi
;
73 extern int amdgpu_lockup_timeout
;
74 extern int amdgpu_dpm
;
75 extern int amdgpu_smc_load_fw
;
76 extern int amdgpu_aspm
;
77 extern int amdgpu_runtime_pm
;
78 extern unsigned amdgpu_ip_block_mask
;
79 extern int amdgpu_bapm
;
80 extern int amdgpu_deep_color
;
81 extern int amdgpu_vm_size
;
82 extern int amdgpu_vm_block_size
;
83 extern int amdgpu_vm_fault_stop
;
84 extern int amdgpu_vm_debug
;
85 extern int amdgpu_sched_jobs
;
86 extern int amdgpu_sched_hw_submission
;
87 extern int amdgpu_powerplay
;
88 extern int amdgpu_powercontainment
;
89 extern unsigned amdgpu_pcie_gen_cap
;
90 extern unsigned amdgpu_pcie_lane_cap
;
91 extern unsigned amdgpu_cg_mask
;
92 extern unsigned amdgpu_pg_mask
;
93 extern char *amdgpu_disable_cu
;
95 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
96 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
97 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
98 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
99 #define AMDGPU_IB_POOL_SIZE 16
100 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
101 #define AMDGPUFB_CONN_LIMIT 4
102 #define AMDGPU_BIOS_NUM_SCRATCH 8
104 /* max number of rings */
105 #define AMDGPU_MAX_RINGS 16
106 #define AMDGPU_MAX_GFX_RINGS 1
107 #define AMDGPU_MAX_COMPUTE_RINGS 8
108 #define AMDGPU_MAX_VCE_RINGS 2
110 /* max number of IP instances */
111 #define AMDGPU_MAX_SDMA_INSTANCES 2
113 /* hardcode that limit for now */
114 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
116 /* hard reset data */
117 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
120 #define AMDGPU_RESET_GFX (1 << 0)
121 #define AMDGPU_RESET_COMPUTE (1 << 1)
122 #define AMDGPU_RESET_DMA (1 << 2)
123 #define AMDGPU_RESET_CP (1 << 3)
124 #define AMDGPU_RESET_GRBM (1 << 4)
125 #define AMDGPU_RESET_DMA1 (1 << 5)
126 #define AMDGPU_RESET_RLC (1 << 6)
127 #define AMDGPU_RESET_SEM (1 << 7)
128 #define AMDGPU_RESET_IH (1 << 8)
129 #define AMDGPU_RESET_VMC (1 << 9)
130 #define AMDGPU_RESET_MC (1 << 10)
131 #define AMDGPU_RESET_DISPLAY (1 << 11)
132 #define AMDGPU_RESET_UVD (1 << 12)
133 #define AMDGPU_RESET_VCE (1 << 13)
134 #define AMDGPU_RESET_VCE1 (1 << 14)
136 /* GFX current status */
137 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
138 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
139 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
140 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
141 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
143 /* max cursor sizes (in pixels) */
144 #define CIK_CURSOR_WIDTH 128
145 #define CIK_CURSOR_HEIGHT 128
147 struct amdgpu_device
;
151 struct amdgpu_cs_parser
;
153 struct amdgpu_irq_src
;
157 AMDGPU_CP_IRQ_GFX_EOP
= 0,
158 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
,
159 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP
,
160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP
,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP
,
162 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP
,
163 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP
,
164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP
,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP
,
170 enum amdgpu_sdma_irq
{
171 AMDGPU_SDMA_IRQ_TRAP0
= 0,
172 AMDGPU_SDMA_IRQ_TRAP1
,
177 enum amdgpu_thermal_irq
{
178 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH
= 0,
179 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW
,
181 AMDGPU_THERMAL_IRQ_LAST
184 int amdgpu_set_clockgating_state(struct amdgpu_device
*adev
,
185 enum amd_ip_block_type block_type
,
186 enum amd_clockgating_state state
);
187 int amdgpu_set_powergating_state(struct amdgpu_device
*adev
,
188 enum amd_ip_block_type block_type
,
189 enum amd_powergating_state state
);
191 struct amdgpu_ip_block_version
{
192 enum amd_ip_block_type type
;
196 const struct amd_ip_funcs
*funcs
;
199 int amdgpu_ip_block_version_cmp(struct amdgpu_device
*adev
,
200 enum amd_ip_block_type type
,
201 u32 major
, u32 minor
);
203 const struct amdgpu_ip_block_version
* amdgpu_get_ip_block(
204 struct amdgpu_device
*adev
,
205 enum amd_ip_block_type type
);
207 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
208 struct amdgpu_buffer_funcs
{
209 /* maximum bytes in a single operation */
210 uint32_t copy_max_bytes
;
212 /* number of dw to reserve per operation */
213 unsigned copy_num_dw
;
215 /* used for buffer migration */
216 void (*emit_copy_buffer
)(struct amdgpu_ib
*ib
,
217 /* src addr in bytes */
219 /* dst addr in bytes */
221 /* number of byte to transfer */
222 uint32_t byte_count
);
224 /* maximum bytes in a single operation */
225 uint32_t fill_max_bytes
;
227 /* number of dw to reserve per operation */
228 unsigned fill_num_dw
;
230 /* used for buffer clearing */
231 void (*emit_fill_buffer
)(struct amdgpu_ib
*ib
,
232 /* value to write to memory */
234 /* dst addr in bytes */
236 /* number of byte to fill */
237 uint32_t byte_count
);
240 /* provided by hw blocks that can write ptes, e.g., sdma */
241 struct amdgpu_vm_pte_funcs
{
242 /* copy pte entries from GART */
243 void (*copy_pte
)(struct amdgpu_ib
*ib
,
244 uint64_t pe
, uint64_t src
,
246 /* write pte one entry at a time with addr mapping */
247 void (*write_pte
)(struct amdgpu_ib
*ib
,
248 const dma_addr_t
*pages_addr
, uint64_t pe
,
249 uint64_t addr
, unsigned count
,
250 uint32_t incr
, uint32_t flags
);
251 /* for linear pte/pde updates without addr mapping */
252 void (*set_pte_pde
)(struct amdgpu_ib
*ib
,
254 uint64_t addr
, unsigned count
,
255 uint32_t incr
, uint32_t flags
);
258 /* provided by the gmc block */
259 struct amdgpu_gart_funcs
{
260 /* flush the vm tlb via mmio */
261 void (*flush_gpu_tlb
)(struct amdgpu_device
*adev
,
263 /* write pte/pde updates using the cpu */
264 int (*set_pte_pde
)(struct amdgpu_device
*adev
,
265 void *cpu_pt_addr
, /* cpu addr of page table */
266 uint32_t gpu_page_idx
, /* pte/pde to update */
267 uint64_t addr
, /* addr to write into pte/pde */
268 uint32_t flags
); /* access flags */
271 /* provided by the ih block */
272 struct amdgpu_ih_funcs
{
273 /* ring read/write ptr handling, called from interrupt context */
274 u32 (*get_wptr
)(struct amdgpu_device
*adev
);
275 void (*decode_iv
)(struct amdgpu_device
*adev
,
276 struct amdgpu_iv_entry
*entry
);
277 void (*set_rptr
)(struct amdgpu_device
*adev
);
280 /* provided by hw blocks that expose a ring buffer for commands */
281 struct amdgpu_ring_funcs
{
282 /* ring read/write ptr handling */
283 u32 (*get_rptr
)(struct amdgpu_ring
*ring
);
284 u32 (*get_wptr
)(struct amdgpu_ring
*ring
);
285 void (*set_wptr
)(struct amdgpu_ring
*ring
);
286 /* validating and patching of IBs */
287 int (*parse_cs
)(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
);
288 /* command emit functions */
289 void (*emit_ib
)(struct amdgpu_ring
*ring
,
290 struct amdgpu_ib
*ib
,
291 unsigned vm_id
, bool ctx_switch
);
292 void (*emit_fence
)(struct amdgpu_ring
*ring
, uint64_t addr
,
293 uint64_t seq
, unsigned flags
);
294 void (*emit_pipeline_sync
)(struct amdgpu_ring
*ring
);
295 void (*emit_vm_flush
)(struct amdgpu_ring
*ring
, unsigned vm_id
,
297 void (*emit_hdp_flush
)(struct amdgpu_ring
*ring
);
298 void (*emit_hdp_invalidate
)(struct amdgpu_ring
*ring
);
299 void (*emit_gds_switch
)(struct amdgpu_ring
*ring
, uint32_t vmid
,
300 uint32_t gds_base
, uint32_t gds_size
,
301 uint32_t gws_base
, uint32_t gws_size
,
302 uint32_t oa_base
, uint32_t oa_size
);
303 /* testing functions */
304 int (*test_ring
)(struct amdgpu_ring
*ring
);
305 int (*test_ib
)(struct amdgpu_ring
*ring
);
306 /* insert NOP packets */
307 void (*insert_nop
)(struct amdgpu_ring
*ring
, uint32_t count
);
308 /* pad the indirect buffer to the necessary number of dw */
309 void (*pad_ib
)(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
);
310 unsigned (*init_cond_exec
)(struct amdgpu_ring
*ring
);
311 void (*patch_cond_exec
)(struct amdgpu_ring
*ring
, unsigned offset
);
317 bool amdgpu_get_bios(struct amdgpu_device
*adev
);
318 bool amdgpu_read_bios(struct amdgpu_device
*adev
);
323 struct amdgpu_dummy_page
{
327 int amdgpu_dummy_page_init(struct amdgpu_device
*adev
);
328 void amdgpu_dummy_page_fini(struct amdgpu_device
*adev
);
335 #define AMDGPU_MAX_PPLL 3
337 struct amdgpu_clock
{
338 struct amdgpu_pll ppll
[AMDGPU_MAX_PPLL
];
339 struct amdgpu_pll spll
;
340 struct amdgpu_pll mpll
;
342 uint32_t default_mclk
;
343 uint32_t default_sclk
;
344 uint32_t default_dispclk
;
345 uint32_t current_dispclk
;
347 uint32_t max_pixel_clock
;
353 struct amdgpu_fence_driver
{
355 volatile uint32_t *cpu_addr
;
356 /* sync_seq is protected by ring emission lock */
360 struct amdgpu_irq_src
*irq_src
;
362 struct timer_list fallback_timer
;
363 unsigned num_fences_mask
;
365 struct fence
**fences
;
368 /* some special values for the owner field */
369 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
370 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
372 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
373 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
375 int amdgpu_fence_driver_init(struct amdgpu_device
*adev
);
376 void amdgpu_fence_driver_fini(struct amdgpu_device
*adev
);
377 void amdgpu_fence_driver_force_completion(struct amdgpu_device
*adev
);
379 int amdgpu_fence_driver_init_ring(struct amdgpu_ring
*ring
,
380 unsigned num_hw_submission
);
381 int amdgpu_fence_driver_start_ring(struct amdgpu_ring
*ring
,
382 struct amdgpu_irq_src
*irq_src
,
384 void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev
);
385 void amdgpu_fence_driver_resume(struct amdgpu_device
*adev
);
386 int amdgpu_fence_emit(struct amdgpu_ring
*ring
, struct fence
**fence
);
387 void amdgpu_fence_process(struct amdgpu_ring
*ring
);
388 int amdgpu_fence_wait_empty(struct amdgpu_ring
*ring
);
389 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring
*ring
);
395 #define AMDGPU_TTM_LRU_SIZE 20
397 struct amdgpu_mman_lru
{
398 struct list_head
*lru
[TTM_NUM_MEM_TYPES
];
399 struct list_head
*swap_lru
;
403 struct ttm_bo_global_ref bo_global_ref
;
404 struct drm_global_reference mem_global_ref
;
405 struct ttm_bo_device bdev
;
406 bool mem_global_referenced
;
409 #if defined(CONFIG_DEBUG_FS)
414 /* buffer handling */
415 const struct amdgpu_buffer_funcs
*buffer_funcs
;
416 struct amdgpu_ring
*buffer_funcs_ring
;
417 /* Scheduler entity for buffer moves */
418 struct amd_sched_entity entity
;
420 /* custom LRU management */
421 struct amdgpu_mman_lru log2_size
[AMDGPU_TTM_LRU_SIZE
];
424 int amdgpu_copy_buffer(struct amdgpu_ring
*ring
,
428 struct reservation_object
*resv
,
429 struct fence
**fence
);
430 int amdgpu_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
432 struct amdgpu_bo_list_entry
{
433 struct amdgpu_bo
*robj
;
434 struct ttm_validate_buffer tv
;
435 struct amdgpu_bo_va
*bo_va
;
437 struct page
**user_pages
;
438 int user_invalidated
;
441 struct amdgpu_bo_va_mapping
{
442 struct list_head list
;
443 struct interval_tree_node it
;
448 /* bo virtual addresses in a specific vm */
449 struct amdgpu_bo_va
{
450 /* protected by bo being reserved */
451 struct list_head bo_list
;
452 struct fence
*last_pt_update
;
455 /* protected by vm mutex and spinlock */
456 struct list_head vm_status
;
458 /* mappings for this bo_va */
459 struct list_head invalids
;
460 struct list_head valids
;
462 /* constant after initialization */
463 struct amdgpu_vm
*vm
;
464 struct amdgpu_bo
*bo
;
467 #define AMDGPU_GEM_DOMAIN_MAX 0x3
470 /* Protected by gem.mutex */
471 struct list_head list
;
472 /* Protected by tbo.reserved */
473 u32 prefered_domains
;
475 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
476 struct ttm_placement placement
;
477 struct ttm_buffer_object tbo
;
478 struct ttm_bo_kmap_obj kmap
;
486 /* list of all virtual address to which this bo
490 /* Constant after initialization */
491 struct amdgpu_device
*adev
;
492 struct drm_gem_object gem_base
;
493 struct amdgpu_bo
*parent
;
495 struct ttm_bo_kmap_obj dma_buf_vmap
;
496 struct amdgpu_mn
*mn
;
497 struct list_head mn_list
;
499 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
501 void amdgpu_gem_object_free(struct drm_gem_object
*obj
);
502 int amdgpu_gem_object_open(struct drm_gem_object
*obj
,
503 struct drm_file
*file_priv
);
504 void amdgpu_gem_object_close(struct drm_gem_object
*obj
,
505 struct drm_file
*file_priv
);
506 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns
);
507 struct sg_table
*amdgpu_gem_prime_get_sg_table(struct drm_gem_object
*obj
);
508 struct drm_gem_object
*
509 amdgpu_gem_prime_import_sg_table(struct drm_device
*dev
,
510 struct dma_buf_attachment
*attach
,
511 struct sg_table
*sg
);
512 struct dma_buf
*amdgpu_gem_prime_export(struct drm_device
*dev
,
513 struct drm_gem_object
*gobj
,
515 int amdgpu_gem_prime_pin(struct drm_gem_object
*obj
);
516 void amdgpu_gem_prime_unpin(struct drm_gem_object
*obj
);
517 struct reservation_object
*amdgpu_gem_prime_res_obj(struct drm_gem_object
*);
518 void *amdgpu_gem_prime_vmap(struct drm_gem_object
*obj
);
519 void amdgpu_gem_prime_vunmap(struct drm_gem_object
*obj
, void *vaddr
);
520 int amdgpu_gem_debugfs_init(struct amdgpu_device
*adev
);
522 /* sub-allocation manager, it has to be protected by another lock.
523 * By conception this is an helper for other part of the driver
524 * like the indirect buffer or semaphore, which both have their
527 * Principe is simple, we keep a list of sub allocation in offset
528 * order (first entry has offset == 0, last entry has the highest
531 * When allocating new object we first check if there is room at
532 * the end total_size - (last_object_offset + last_object_size) >=
533 * alloc_size. If so we allocate new object there.
535 * When there is not enough room at the end, we start waiting for
536 * each sub object until we reach object_offset+object_size >=
537 * alloc_size, this object then become the sub object we return.
539 * Alignment can't be bigger than page size.
541 * Hole are not considered for allocation to keep things simple.
542 * Assumption is that there won't be hole (all object on same
546 #define AMDGPU_SA_NUM_FENCE_LISTS 32
548 struct amdgpu_sa_manager
{
549 wait_queue_head_t wq
;
550 struct amdgpu_bo
*bo
;
551 struct list_head
*hole
;
552 struct list_head flist
[AMDGPU_SA_NUM_FENCE_LISTS
];
553 struct list_head olist
;
561 /* sub-allocation buffer */
562 struct amdgpu_sa_bo
{
563 struct list_head olist
;
564 struct list_head flist
;
565 struct amdgpu_sa_manager
*manager
;
574 void amdgpu_gem_force_release(struct amdgpu_device
*adev
);
575 int amdgpu_gem_object_create(struct amdgpu_device
*adev
, unsigned long size
,
576 int alignment
, u32 initial_domain
,
577 u64 flags
, bool kernel
,
578 struct drm_gem_object
**obj
);
580 int amdgpu_mode_dumb_create(struct drm_file
*file_priv
,
581 struct drm_device
*dev
,
582 struct drm_mode_create_dumb
*args
);
583 int amdgpu_mode_dumb_mmap(struct drm_file
*filp
,
584 struct drm_device
*dev
,
585 uint32_t handle
, uint64_t *offset_p
);
590 DECLARE_HASHTABLE(fences
, 4);
591 struct fence
*last_vm_update
;
594 void amdgpu_sync_create(struct amdgpu_sync
*sync
);
595 int amdgpu_sync_fence(struct amdgpu_device
*adev
, struct amdgpu_sync
*sync
,
597 int amdgpu_sync_resv(struct amdgpu_device
*adev
,
598 struct amdgpu_sync
*sync
,
599 struct reservation_object
*resv
,
601 struct fence
*amdgpu_sync_peek_fence(struct amdgpu_sync
*sync
,
602 struct amdgpu_ring
*ring
);
603 struct fence
*amdgpu_sync_get_fence(struct amdgpu_sync
*sync
);
604 void amdgpu_sync_free(struct amdgpu_sync
*sync
);
605 int amdgpu_sync_init(void);
606 void amdgpu_sync_fini(void);
607 int amdgpu_fence_slab_init(void);
608 void amdgpu_fence_slab_fini(void);
611 * GART structures, functions & helpers
615 #define AMDGPU_GPU_PAGE_SIZE 4096
616 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
617 #define AMDGPU_GPU_PAGE_SHIFT 12
618 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
621 dma_addr_t table_addr
;
622 struct amdgpu_bo
*robj
;
624 unsigned num_gpu_pages
;
625 unsigned num_cpu_pages
;
627 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
631 const struct amdgpu_gart_funcs
*gart_funcs
;
634 int amdgpu_gart_table_ram_alloc(struct amdgpu_device
*adev
);
635 void amdgpu_gart_table_ram_free(struct amdgpu_device
*adev
);
636 int amdgpu_gart_table_vram_alloc(struct amdgpu_device
*adev
);
637 void amdgpu_gart_table_vram_free(struct amdgpu_device
*adev
);
638 int amdgpu_gart_table_vram_pin(struct amdgpu_device
*adev
);
639 void amdgpu_gart_table_vram_unpin(struct amdgpu_device
*adev
);
640 int amdgpu_gart_init(struct amdgpu_device
*adev
);
641 void amdgpu_gart_fini(struct amdgpu_device
*adev
);
642 void amdgpu_gart_unbind(struct amdgpu_device
*adev
, unsigned offset
,
644 int amdgpu_gart_bind(struct amdgpu_device
*adev
, unsigned offset
,
645 int pages
, struct page
**pagelist
,
646 dma_addr_t
*dma_addr
, uint32_t flags
);
649 * GPU MC structures, functions & helpers
652 resource_size_t aper_size
;
653 resource_size_t aper_base
;
654 resource_size_t agp_base
;
655 /* for some chips with <= 32MB we need to lie
656 * about vram size near mc fb location */
658 u64 visible_vram_size
;
669 const struct firmware
*fw
; /* MC firmware */
671 struct amdgpu_irq_src vm_fault
;
676 * GPU doorbell structures, functions & helpers
678 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
680 AMDGPU_DOORBELL_KIQ
= 0x000,
681 AMDGPU_DOORBELL_HIQ
= 0x001,
682 AMDGPU_DOORBELL_DIQ
= 0x002,
683 AMDGPU_DOORBELL_MEC_RING0
= 0x010,
684 AMDGPU_DOORBELL_MEC_RING1
= 0x011,
685 AMDGPU_DOORBELL_MEC_RING2
= 0x012,
686 AMDGPU_DOORBELL_MEC_RING3
= 0x013,
687 AMDGPU_DOORBELL_MEC_RING4
= 0x014,
688 AMDGPU_DOORBELL_MEC_RING5
= 0x015,
689 AMDGPU_DOORBELL_MEC_RING6
= 0x016,
690 AMDGPU_DOORBELL_MEC_RING7
= 0x017,
691 AMDGPU_DOORBELL_GFX_RING0
= 0x020,
692 AMDGPU_DOORBELL_sDMA_ENGINE0
= 0x1E0,
693 AMDGPU_DOORBELL_sDMA_ENGINE1
= 0x1E1,
694 AMDGPU_DOORBELL_IH
= 0x1E8,
695 AMDGPU_DOORBELL_MAX_ASSIGNMENT
= 0x3FF,
696 AMDGPU_DOORBELL_INVALID
= 0xFFFF
697 } AMDGPU_DOORBELL_ASSIGNMENT
;
699 struct amdgpu_doorbell
{
701 resource_size_t base
;
702 resource_size_t size
;
704 u32 num_doorbells
; /* Number of doorbells actually reserved for amdgpu. */
707 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device
*adev
,
708 phys_addr_t
*aperture_base
,
709 size_t *aperture_size
,
710 size_t *start_offset
);
716 struct amdgpu_flip_work
{
717 struct work_struct flip_work
;
718 struct work_struct unpin_work
;
719 struct amdgpu_device
*adev
;
722 struct drm_pending_vblank_event
*event
;
723 struct amdgpu_bo
*old_rbo
;
725 unsigned shared_count
;
726 struct fence
**shared
;
737 struct amdgpu_sa_bo
*sa_bo
;
744 enum amdgpu_ring_type
{
745 AMDGPU_RING_TYPE_GFX
,
746 AMDGPU_RING_TYPE_COMPUTE
,
747 AMDGPU_RING_TYPE_SDMA
,
748 AMDGPU_RING_TYPE_UVD
,
752 extern const struct amd_sched_backend_ops amdgpu_sched_ops
;
754 int amdgpu_job_alloc(struct amdgpu_device
*adev
, unsigned num_ibs
,
755 struct amdgpu_job
**job
, struct amdgpu_vm
*vm
);
756 int amdgpu_job_alloc_with_ib(struct amdgpu_device
*adev
, unsigned size
,
757 struct amdgpu_job
**job
);
759 void amdgpu_job_free(struct amdgpu_job
*job
);
760 int amdgpu_job_submit(struct amdgpu_job
*job
, struct amdgpu_ring
*ring
,
761 struct amd_sched_entity
*entity
, void *owner
,
765 struct amdgpu_device
*adev
;
766 const struct amdgpu_ring_funcs
*funcs
;
767 struct amdgpu_fence_driver fence_drv
;
768 struct amd_gpu_scheduler sched
;
770 spinlock_t fence_lock
;
771 struct amdgpu_bo
*ring_obj
;
772 volatile uint32_t *ring
;
774 u64 next_rptr_gpu_addr
;
775 volatile u32
*next_rptr_cpu_addr
;
790 struct amdgpu_bo
*mqd_obj
;
794 unsigned next_rptr_offs
;
796 uint64_t current_ctx
;
797 enum amdgpu_ring_type type
;
799 unsigned cond_exe_offs
;
800 u64 cond_exe_gpu_addr
;
801 volatile u32
*cond_exe_cpu_addr
;
802 #if defined(CONFIG_DEBUG_FS)
811 /* maximum number of VMIDs */
812 #define AMDGPU_NUM_VM 16
814 /* number of entries in page table */
815 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
817 /* PTBs (Page Table Blocks) need to be aligned to 32K */
818 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
819 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
820 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
822 #define AMDGPU_PTE_VALID (1 << 0)
823 #define AMDGPU_PTE_SYSTEM (1 << 1)
824 #define AMDGPU_PTE_SNOOPED (1 << 2)
827 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
829 #define AMDGPU_PTE_READABLE (1 << 5)
830 #define AMDGPU_PTE_WRITEABLE (1 << 6)
832 /* PTE (Page Table Entry) fragment field for different page sizes */
833 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
834 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
835 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
837 /* How to programm VM fault handling */
838 #define AMDGPU_VM_FAULT_STOP_NEVER 0
839 #define AMDGPU_VM_FAULT_STOP_FIRST 1
840 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
842 struct amdgpu_vm_pt
{
843 struct amdgpu_bo_list_entry entry
;
848 /* tree of virtual addresses mapped */
851 /* protecting invalidated */
852 spinlock_t status_lock
;
854 /* BOs moved, but not yet updated in the PT */
855 struct list_head invalidated
;
857 /* BOs cleared in the PT because of a move */
858 struct list_head cleared
;
860 /* BO mappings freed, but not yet updated in the PT */
861 struct list_head freed
;
863 /* contains the page directory */
864 struct amdgpu_bo
*page_directory
;
865 unsigned max_pde_used
;
866 struct fence
*page_directory_fence
;
867 uint64_t last_eviction_counter
;
869 /* array of page tables, one for each page directory entry */
870 struct amdgpu_vm_pt
*page_tables
;
872 /* for id and flush management per ring */
873 struct amdgpu_vm_id
*ids
[AMDGPU_MAX_RINGS
];
875 /* protecting freed */
876 spinlock_t freed_lock
;
878 /* Scheduler entity for page table updates */
879 struct amd_sched_entity entity
;
885 struct amdgpu_vm_id
{
886 struct list_head list
;
888 struct amdgpu_sync active
;
889 struct fence
*last_flush
;
892 uint64_t pd_gpu_addr
;
893 /* last flushed PD/PT update */
894 struct fence
*flushed_updates
;
904 struct amdgpu_vm_manager
{
905 /* Handling of VMIDs */
908 struct list_head ids_lru
;
909 struct amdgpu_vm_id ids
[AMDGPU_NUM_VM
];
911 /* Handling of VM fences */
913 unsigned seqno
[AMDGPU_MAX_RINGS
];
916 /* vram base address for page table entry */
917 u64 vram_base_offset
;
920 /* vm pte handling */
921 const struct amdgpu_vm_pte_funcs
*vm_pte_funcs
;
922 struct amdgpu_ring
*vm_pte_rings
[AMDGPU_MAX_RINGS
];
923 unsigned vm_pte_num_rings
;
924 atomic_t vm_pte_next_ring
;
925 /* client id counter */
926 atomic64_t client_counter
;
929 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
);
930 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
);
931 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
932 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
);
933 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
934 struct list_head
*validated
,
935 struct amdgpu_bo_list_entry
*entry
);
936 void amdgpu_vm_get_pt_bos(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
937 struct list_head
*duplicates
);
938 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
939 struct amdgpu_vm
*vm
);
940 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
941 struct amdgpu_sync
*sync
, struct fence
*fence
,
942 unsigned *vm_id
, uint64_t *vm_pd_addr
);
943 int amdgpu_vm_flush(struct amdgpu_ring
*ring
,
944 unsigned vm_id
, uint64_t pd_addr
,
945 uint32_t gds_base
, uint32_t gds_size
,
946 uint32_t gws_base
, uint32_t gws_size
,
947 uint32_t oa_base
, uint32_t oa_size
);
948 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
);
949 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
);
950 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
951 struct amdgpu_vm
*vm
);
952 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
953 struct amdgpu_vm
*vm
);
954 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
955 struct amdgpu_sync
*sync
);
956 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
957 struct amdgpu_bo_va
*bo_va
,
958 struct ttm_mem_reg
*mem
);
959 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
960 struct amdgpu_bo
*bo
);
961 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
962 struct amdgpu_bo
*bo
);
963 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
964 struct amdgpu_vm
*vm
,
965 struct amdgpu_bo
*bo
);
966 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
967 struct amdgpu_bo_va
*bo_va
,
968 uint64_t addr
, uint64_t offset
,
969 uint64_t size
, uint32_t flags
);
970 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
971 struct amdgpu_bo_va
*bo_va
,
973 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
974 struct amdgpu_bo_va
*bo_va
);
977 * context related structures
980 struct amdgpu_ctx_ring
{
982 struct fence
**fences
;
983 struct amd_sched_entity entity
;
987 struct kref refcount
;
988 struct amdgpu_device
*adev
;
989 unsigned reset_counter
;
990 spinlock_t ring_lock
;
991 struct fence
**fences
;
992 struct amdgpu_ctx_ring rings
[AMDGPU_MAX_RINGS
];
995 struct amdgpu_ctx_mgr
{
996 struct amdgpu_device
*adev
;
998 /* protected by lock */
999 struct idr ctx_handles
;
1002 struct amdgpu_ctx
*amdgpu_ctx_get(struct amdgpu_fpriv
*fpriv
, uint32_t id
);
1003 int amdgpu_ctx_put(struct amdgpu_ctx
*ctx
);
1005 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx
*ctx
, struct amdgpu_ring
*ring
,
1006 struct fence
*fence
);
1007 struct fence
*amdgpu_ctx_get_fence(struct amdgpu_ctx
*ctx
,
1008 struct amdgpu_ring
*ring
, uint64_t seq
);
1010 int amdgpu_ctx_ioctl(struct drm_device
*dev
, void *data
,
1011 struct drm_file
*filp
);
1013 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr
*mgr
);
1014 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr
*mgr
);
1017 * file private structure
1020 struct amdgpu_fpriv
{
1021 struct amdgpu_vm vm
;
1022 struct mutex bo_list_lock
;
1023 struct idr bo_list_handles
;
1024 struct amdgpu_ctx_mgr ctx_mgr
;
1031 struct amdgpu_bo_list
{
1033 struct amdgpu_bo
*gds_obj
;
1034 struct amdgpu_bo
*gws_obj
;
1035 struct amdgpu_bo
*oa_obj
;
1036 unsigned first_userptr
;
1037 unsigned num_entries
;
1038 struct amdgpu_bo_list_entry
*array
;
1041 struct amdgpu_bo_list
*
1042 amdgpu_bo_list_get(struct amdgpu_fpriv
*fpriv
, int id
);
1043 void amdgpu_bo_list_get_list(struct amdgpu_bo_list
*list
,
1044 struct list_head
*validated
);
1045 void amdgpu_bo_list_put(struct amdgpu_bo_list
*list
);
1046 void amdgpu_bo_list_free(struct amdgpu_bo_list
*list
);
1051 #include "clearstate_defs.h"
1053 struct amdgpu_rlc_funcs
{
1054 void (*enter_safe_mode
)(struct amdgpu_device
*adev
);
1055 void (*exit_safe_mode
)(struct amdgpu_device
*adev
);
1059 /* for power gating */
1060 struct amdgpu_bo
*save_restore_obj
;
1061 uint64_t save_restore_gpu_addr
;
1062 volatile uint32_t *sr_ptr
;
1063 const u32
*reg_list
;
1065 /* for clear state */
1066 struct amdgpu_bo
*clear_state_obj
;
1067 uint64_t clear_state_gpu_addr
;
1068 volatile uint32_t *cs_ptr
;
1069 const struct cs_section_def
*cs_data
;
1070 u32 clear_state_size
;
1072 struct amdgpu_bo
*cp_table_obj
;
1073 uint64_t cp_table_gpu_addr
;
1074 volatile uint32_t *cp_table_ptr
;
1077 /* safe mode for updating CG/PG state */
1079 const struct amdgpu_rlc_funcs
*funcs
;
1081 /* for firmware data */
1082 u32 save_and_restore_offset
;
1083 u32 clear_state_descriptor_offset
;
1084 u32 avail_scratch_ram_locations
;
1085 u32 reg_restore_list_size
;
1086 u32 reg_list_format_start
;
1087 u32 reg_list_format_separate_start
;
1088 u32 starting_offsets_start
;
1089 u32 reg_list_format_size_bytes
;
1090 u32 reg_list_size_bytes
;
1092 u32
*register_list_format
;
1093 u32
*register_restore
;
1097 struct amdgpu_bo
*hpd_eop_obj
;
1098 u64 hpd_eop_gpu_addr
;
1105 * GPU scratch registers structures, functions & helpers
1107 struct amdgpu_scratch
{
1115 * GFX configurations
1117 struct amdgpu_gca_config
{
1118 unsigned max_shader_engines
;
1119 unsigned max_tile_pipes
;
1120 unsigned max_cu_per_sh
;
1121 unsigned max_sh_per_se
;
1122 unsigned max_backends_per_se
;
1123 unsigned max_texture_channel_caches
;
1125 unsigned max_gs_threads
;
1126 unsigned max_hw_contexts
;
1127 unsigned sc_prim_fifo_size_frontend
;
1128 unsigned sc_prim_fifo_size_backend
;
1129 unsigned sc_hiz_tile_fifo_size
;
1130 unsigned sc_earlyz_tile_fifo_size
;
1132 unsigned num_tile_pipes
;
1133 unsigned backend_enable_mask
;
1134 unsigned mem_max_burst_length_bytes
;
1135 unsigned mem_row_size_in_kb
;
1136 unsigned shader_engine_tile_size
;
1138 unsigned multi_gpu_tile_size
;
1139 unsigned mc_arb_ramcfg
;
1140 unsigned gb_addr_config
;
1143 uint32_t tile_mode_array
[32];
1144 uint32_t macrotile_mode_array
[16];
1147 struct amdgpu_cu_info
{
1148 uint32_t number
; /* total active CU number */
1149 uint32_t ao_cu_mask
;
1150 uint32_t bitmap
[4][4];
1154 struct mutex gpu_clock_mutex
;
1155 struct amdgpu_gca_config config
;
1156 struct amdgpu_rlc rlc
;
1157 struct amdgpu_mec mec
;
1158 struct amdgpu_scratch scratch
;
1159 const struct firmware
*me_fw
; /* ME firmware */
1160 uint32_t me_fw_version
;
1161 const struct firmware
*pfp_fw
; /* PFP firmware */
1162 uint32_t pfp_fw_version
;
1163 const struct firmware
*ce_fw
; /* CE firmware */
1164 uint32_t ce_fw_version
;
1165 const struct firmware
*rlc_fw
; /* RLC firmware */
1166 uint32_t rlc_fw_version
;
1167 const struct firmware
*mec_fw
; /* MEC firmware */
1168 uint32_t mec_fw_version
;
1169 const struct firmware
*mec2_fw
; /* MEC2 firmware */
1170 uint32_t mec2_fw_version
;
1171 uint32_t me_feature_version
;
1172 uint32_t ce_feature_version
;
1173 uint32_t pfp_feature_version
;
1174 uint32_t rlc_feature_version
;
1175 uint32_t mec_feature_version
;
1176 uint32_t mec2_feature_version
;
1177 struct amdgpu_ring gfx_ring
[AMDGPU_MAX_GFX_RINGS
];
1178 unsigned num_gfx_rings
;
1179 struct amdgpu_ring compute_ring
[AMDGPU_MAX_COMPUTE_RINGS
];
1180 unsigned num_compute_rings
;
1181 struct amdgpu_irq_src eop_irq
;
1182 struct amdgpu_irq_src priv_reg_irq
;
1183 struct amdgpu_irq_src priv_inst_irq
;
1185 uint32_t gfx_current_status
;
1187 unsigned ce_ram_size
;
1188 struct amdgpu_cu_info cu_info
;
1191 int amdgpu_ib_get(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
1192 unsigned size
, struct amdgpu_ib
*ib
);
1193 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
,
1195 int amdgpu_ib_schedule(struct amdgpu_ring
*ring
, unsigned num_ibs
,
1196 struct amdgpu_ib
*ib
, struct fence
*last_vm_update
,
1197 struct amdgpu_job
*job
, struct fence
**f
);
1198 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
);
1199 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
);
1200 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
);
1201 int amdgpu_ring_alloc(struct amdgpu_ring
*ring
, unsigned ndw
);
1202 void amdgpu_ring_insert_nop(struct amdgpu_ring
*ring
, uint32_t count
);
1203 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
);
1204 void amdgpu_ring_commit(struct amdgpu_ring
*ring
);
1205 void amdgpu_ring_undo(struct amdgpu_ring
*ring
);
1206 unsigned amdgpu_ring_backup(struct amdgpu_ring
*ring
,
1208 int amdgpu_ring_restore(struct amdgpu_ring
*ring
,
1209 unsigned size
, uint32_t *data
);
1210 int amdgpu_ring_init(struct amdgpu_device
*adev
, struct amdgpu_ring
*ring
,
1211 unsigned ring_size
, u32 nop
, u32 align_mask
,
1212 struct amdgpu_irq_src
*irq_src
, unsigned irq_type
,
1213 enum amdgpu_ring_type ring_type
);
1214 void amdgpu_ring_fini(struct amdgpu_ring
*ring
);
1219 struct amdgpu_cs_chunk
{
1225 struct amdgpu_cs_parser
{
1226 struct amdgpu_device
*adev
;
1227 struct drm_file
*filp
;
1228 struct amdgpu_ctx
*ctx
;
1232 struct amdgpu_cs_chunk
*chunks
;
1234 /* scheduler job object */
1235 struct amdgpu_job
*job
;
1237 /* buffer objects */
1238 struct ww_acquire_ctx ticket
;
1239 struct amdgpu_bo_list
*bo_list
;
1240 struct amdgpu_bo_list_entry vm_pd
;
1241 struct list_head validated
;
1242 struct fence
*fence
;
1243 uint64_t bytes_moved_threshold
;
1244 uint64_t bytes_moved
;
1247 struct amdgpu_bo_list_entry uf_entry
;
1251 struct amd_sched_job base
;
1252 struct amdgpu_device
*adev
;
1253 struct amdgpu_vm
*vm
;
1254 struct amdgpu_ring
*ring
;
1255 struct amdgpu_sync sync
;
1256 struct amdgpu_ib
*ibs
;
1257 struct fence
*fence
; /* the hw fence */
1262 uint64_t vm_pd_addr
;
1263 uint32_t gds_base
, gds_size
;
1264 uint32_t gws_base
, gws_size
;
1265 uint32_t oa_base
, oa_size
;
1267 /* user fence handling */
1268 struct amdgpu_bo
*uf_bo
;
1270 uint64_t uf_sequence
;
1273 #define to_amdgpu_job(sched_job) \
1274 container_of((sched_job), struct amdgpu_job, base)
1276 static inline u32
amdgpu_get_ib_value(struct amdgpu_cs_parser
*p
,
1277 uint32_t ib_idx
, int idx
)
1279 return p
->job
->ibs
[ib_idx
].ptr
[idx
];
1282 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser
*p
,
1283 uint32_t ib_idx
, int idx
,
1286 p
->job
->ibs
[ib_idx
].ptr
[idx
] = value
;
1292 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1295 struct amdgpu_bo
*wb_obj
;
1296 volatile uint32_t *wb
;
1298 u32 num_wb
; /* Number of wb slots actually reserved for amdgpu. */
1299 unsigned long used
[DIV_ROUND_UP(AMDGPU_MAX_WB
, BITS_PER_LONG
)];
1302 int amdgpu_wb_get(struct amdgpu_device
*adev
, u32
*wb
);
1303 void amdgpu_wb_free(struct amdgpu_device
*adev
, u32 wb
);
1307 enum amdgpu_int_thermal_type
{
1309 THERMAL_TYPE_EXTERNAL
,
1310 THERMAL_TYPE_EXTERNAL_GPIO
,
1313 THERMAL_TYPE_ADT7473_WITH_INTERNAL
,
1314 THERMAL_TYPE_EVERGREEN
,
1318 THERMAL_TYPE_EMC2103_WITH_INTERNAL
,
1323 enum amdgpu_dpm_auto_throttle_src
{
1324 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL
,
1325 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1328 enum amdgpu_dpm_event_src
{
1329 AMDGPU_DPM_EVENT_SRC_ANALOG
= 0,
1330 AMDGPU_DPM_EVENT_SRC_EXTERNAL
= 1,
1331 AMDGPU_DPM_EVENT_SRC_DIGITAL
= 2,
1332 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
= 3,
1333 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
= 4
1336 #define AMDGPU_MAX_VCE_LEVELS 6
1338 enum amdgpu_vce_level
{
1339 AMDGPU_VCE_LEVEL_AC_ALL
= 0, /* AC, All cases */
1340 AMDGPU_VCE_LEVEL_DC_EE
= 1, /* DC, entropy encoding */
1341 AMDGPU_VCE_LEVEL_DC_LL_LOW
= 2, /* DC, low latency queue, res <= 720 */
1342 AMDGPU_VCE_LEVEL_DC_LL_HIGH
= 3, /* DC, low latency queue, 1080 >= res > 720 */
1343 AMDGPU_VCE_LEVEL_DC_GP_LOW
= 4, /* DC, general purpose queue, res <= 720 */
1344 AMDGPU_VCE_LEVEL_DC_GP_HIGH
= 5, /* DC, general purpose queue, 1080 >= res > 720 */
1348 u32 caps
; /* vbios flags */
1349 u32
class; /* vbios flags */
1350 u32 class2
; /* vbios flags */
1358 enum amdgpu_vce_level vce_level
;
1363 struct amdgpu_dpm_thermal
{
1364 /* thermal interrupt work */
1365 struct work_struct work
;
1366 /* low temperature threshold */
1368 /* high temperature threshold */
1370 /* was last interrupt low to high or high to low */
1372 /* interrupt source */
1373 struct amdgpu_irq_src irq
;
1376 enum amdgpu_clk_action
1382 struct amdgpu_blacklist_clocks
1386 enum amdgpu_clk_action action
;
1389 struct amdgpu_clock_and_voltage_limits
{
1396 struct amdgpu_clock_array
{
1401 struct amdgpu_clock_voltage_dependency_entry
{
1406 struct amdgpu_clock_voltage_dependency_table
{
1408 struct amdgpu_clock_voltage_dependency_entry
*entries
;
1411 union amdgpu_cac_leakage_entry
{
1423 struct amdgpu_cac_leakage_table
{
1425 union amdgpu_cac_leakage_entry
*entries
;
1428 struct amdgpu_phase_shedding_limits_entry
{
1434 struct amdgpu_phase_shedding_limits_table
{
1436 struct amdgpu_phase_shedding_limits_entry
*entries
;
1439 struct amdgpu_uvd_clock_voltage_dependency_entry
{
1445 struct amdgpu_uvd_clock_voltage_dependency_table
{
1447 struct amdgpu_uvd_clock_voltage_dependency_entry
*entries
;
1450 struct amdgpu_vce_clock_voltage_dependency_entry
{
1456 struct amdgpu_vce_clock_voltage_dependency_table
{
1458 struct amdgpu_vce_clock_voltage_dependency_entry
*entries
;
1461 struct amdgpu_ppm_table
{
1463 u16 cpu_core_number
;
1465 u32 small_ac_platform_tdp
;
1467 u32 small_ac_platform_tdc
;
1474 struct amdgpu_cac_tdp_table
{
1476 u16 configurable_tdp
;
1478 u16 battery_power_limit
;
1479 u16 small_power_limit
;
1480 u16 low_cac_leakage
;
1481 u16 high_cac_leakage
;
1482 u16 maximum_power_delivery_limit
;
1485 struct amdgpu_dpm_dynamic_state
{
1486 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk
;
1487 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk
;
1488 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk
;
1489 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk
;
1490 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk
;
1491 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table
;
1492 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table
;
1493 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table
;
1494 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table
;
1495 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk
;
1496 struct amdgpu_clock_array valid_sclk_values
;
1497 struct amdgpu_clock_array valid_mclk_values
;
1498 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc
;
1499 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac
;
1500 u32 mclk_sclk_ratio
;
1501 u32 sclk_mclk_delta
;
1502 u16 vddc_vddci_delta
;
1503 u16 min_vddc_for_pcie_gen2
;
1504 struct amdgpu_cac_leakage_table cac_leakage_table
;
1505 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table
;
1506 struct amdgpu_ppm_table
*ppm_table
;
1507 struct amdgpu_cac_tdp_table
*cac_tdp_table
;
1510 struct amdgpu_dpm_fan
{
1521 u16 default_max_fan_pwm
;
1522 u16 default_fan_output_sensitivity
;
1523 u16 fan_output_sensitivity
;
1524 bool ucode_fan_control
;
1527 enum amdgpu_pcie_gen
{
1528 AMDGPU_PCIE_GEN1
= 0,
1529 AMDGPU_PCIE_GEN2
= 1,
1530 AMDGPU_PCIE_GEN3
= 2,
1531 AMDGPU_PCIE_GEN_INVALID
= 0xffff
1534 enum amdgpu_dpm_forced_level
{
1535 AMDGPU_DPM_FORCED_LEVEL_AUTO
= 0,
1536 AMDGPU_DPM_FORCED_LEVEL_LOW
= 1,
1537 AMDGPU_DPM_FORCED_LEVEL_HIGH
= 2,
1538 AMDGPU_DPM_FORCED_LEVEL_MANUAL
= 3,
1541 struct amdgpu_vce_state
{
1552 struct amdgpu_dpm_funcs
{
1553 int (*get_temperature
)(struct amdgpu_device
*adev
);
1554 int (*pre_set_power_state
)(struct amdgpu_device
*adev
);
1555 int (*set_power_state
)(struct amdgpu_device
*adev
);
1556 void (*post_set_power_state
)(struct amdgpu_device
*adev
);
1557 void (*display_configuration_changed
)(struct amdgpu_device
*adev
);
1558 u32 (*get_sclk
)(struct amdgpu_device
*adev
, bool low
);
1559 u32 (*get_mclk
)(struct amdgpu_device
*adev
, bool low
);
1560 void (*print_power_state
)(struct amdgpu_device
*adev
, struct amdgpu_ps
*ps
);
1561 void (*debugfs_print_current_performance_level
)(struct amdgpu_device
*adev
, struct seq_file
*m
);
1562 int (*force_performance_level
)(struct amdgpu_device
*adev
, enum amdgpu_dpm_forced_level level
);
1563 bool (*vblank_too_short
)(struct amdgpu_device
*adev
);
1564 void (*powergate_uvd
)(struct amdgpu_device
*adev
, bool gate
);
1565 void (*powergate_vce
)(struct amdgpu_device
*adev
, bool gate
);
1566 void (*enable_bapm
)(struct amdgpu_device
*adev
, bool enable
);
1567 void (*set_fan_control_mode
)(struct amdgpu_device
*adev
, u32 mode
);
1568 u32 (*get_fan_control_mode
)(struct amdgpu_device
*adev
);
1569 int (*set_fan_speed_percent
)(struct amdgpu_device
*adev
, u32 speed
);
1570 int (*get_fan_speed_percent
)(struct amdgpu_device
*adev
, u32
*speed
);
1571 int (*force_clock_level
)(struct amdgpu_device
*adev
, enum pp_clock_type type
, uint32_t mask
);
1572 int (*print_clock_levels
)(struct amdgpu_device
*adev
, enum pp_clock_type type
, char *buf
);
1573 int (*get_sclk_od
)(struct amdgpu_device
*adev
);
1574 int (*set_sclk_od
)(struct amdgpu_device
*adev
, uint32_t value
);
1575 int (*get_mclk_od
)(struct amdgpu_device
*adev
);
1576 int (*set_mclk_od
)(struct amdgpu_device
*adev
, uint32_t value
);
1580 struct amdgpu_ps
*ps
;
1581 /* number of valid power states */
1583 /* current power state that is active */
1584 struct amdgpu_ps
*current_ps
;
1585 /* requested power state */
1586 struct amdgpu_ps
*requested_ps
;
1587 /* boot up power state */
1588 struct amdgpu_ps
*boot_ps
;
1589 /* default uvd power state */
1590 struct amdgpu_ps
*uvd_ps
;
1591 /* vce requirements */
1592 struct amdgpu_vce_state vce_states
[AMDGPU_MAX_VCE_LEVELS
];
1593 enum amdgpu_vce_level vce_level
;
1594 enum amd_pm_state_type state
;
1595 enum amd_pm_state_type user_state
;
1597 u32 voltage_response_time
;
1598 u32 backbias_response_time
;
1600 u32 new_active_crtcs
;
1601 int new_active_crtc_count
;
1602 u32 current_active_crtcs
;
1603 int current_active_crtc_count
;
1604 struct amdgpu_dpm_dynamic_state dyn_state
;
1605 struct amdgpu_dpm_fan fan
;
1608 u32 near_tdp_limit_adjusted
;
1609 u32 sq_ramping_threshold
;
1613 u16 load_line_slope
;
1616 /* special states active */
1617 bool thermal_active
;
1620 /* thermal handling */
1621 struct amdgpu_dpm_thermal thermal
;
1623 enum amdgpu_dpm_forced_level forced_level
;
1632 struct amdgpu_i2c_chan
*i2c_bus
;
1633 /* internal thermal controller on rv6xx+ */
1634 enum amdgpu_int_thermal_type int_thermal_type
;
1635 struct device
*int_hwmon_dev
;
1636 /* fan control parameters */
1638 u8 fan_pulses_per_revolution
;
1643 bool sysfs_initialized
;
1644 struct amdgpu_dpm dpm
;
1645 const struct firmware
*fw
; /* SMC firmware */
1646 uint32_t fw_version
;
1647 const struct amdgpu_dpm_funcs
*funcs
;
1648 uint32_t pcie_gen_mask
;
1649 uint32_t pcie_mlw_mask
;
1650 struct amd_pp_display_configuration pm_display_cfg
;/* set by DAL */
1653 void amdgpu_get_pcie_info(struct amdgpu_device
*adev
);
1658 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1659 #define AMDGPU_MAX_UVD_HANDLES 40
1660 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1661 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1662 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1663 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1666 struct amdgpu_bo
*vcpu_bo
;
1669 unsigned fw_version
;
1671 unsigned max_handles
;
1672 atomic_t handles
[AMDGPU_MAX_UVD_HANDLES
];
1673 struct drm_file
*filp
[AMDGPU_MAX_UVD_HANDLES
];
1674 struct delayed_work idle_work
;
1675 const struct firmware
*fw
; /* UVD firmware */
1676 struct amdgpu_ring ring
;
1677 struct amdgpu_irq_src irq
;
1678 bool address_64_bit
;
1679 struct amd_sched_entity entity
;
1685 #define AMDGPU_MAX_VCE_HANDLES 16
1686 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1688 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1689 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1692 struct amdgpu_bo
*vcpu_bo
;
1694 unsigned fw_version
;
1695 unsigned fb_version
;
1696 atomic_t handles
[AMDGPU_MAX_VCE_HANDLES
];
1697 struct drm_file
*filp
[AMDGPU_MAX_VCE_HANDLES
];
1698 uint32_t img_size
[AMDGPU_MAX_VCE_HANDLES
];
1699 struct delayed_work idle_work
;
1700 const struct firmware
*fw
; /* VCE firmware */
1701 struct amdgpu_ring ring
[AMDGPU_MAX_VCE_RINGS
];
1702 struct amdgpu_irq_src irq
;
1703 unsigned harvest_config
;
1704 struct amd_sched_entity entity
;
1710 struct amdgpu_sdma_instance
{
1712 const struct firmware
*fw
;
1713 uint32_t fw_version
;
1714 uint32_t feature_version
;
1716 struct amdgpu_ring ring
;
1720 struct amdgpu_sdma
{
1721 struct amdgpu_sdma_instance instance
[AMDGPU_MAX_SDMA_INSTANCES
];
1722 struct amdgpu_irq_src trap_irq
;
1723 struct amdgpu_irq_src illegal_inst_irq
;
1730 struct amdgpu_firmware
{
1731 struct amdgpu_firmware_info ucode
[AMDGPU_UCODE_ID_MAXIMUM
];
1733 struct amdgpu_bo
*fw_buf
;
1734 unsigned int fw_size
;
1740 void amdgpu_benchmark(struct amdgpu_device
*adev
, int test_number
);
1746 void amdgpu_test_moves(struct amdgpu_device
*adev
);
1747 void amdgpu_test_ring_sync(struct amdgpu_device
*adev
,
1748 struct amdgpu_ring
*cpA
,
1749 struct amdgpu_ring
*cpB
);
1750 void amdgpu_test_syncing(struct amdgpu_device
*adev
);
1755 #if defined(CONFIG_MMU_NOTIFIER)
1756 int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
);
1757 void amdgpu_mn_unregister(struct amdgpu_bo
*bo
);
1759 static inline int amdgpu_mn_register(struct amdgpu_bo
*bo
, unsigned long addr
)
1763 static inline void amdgpu_mn_unregister(struct amdgpu_bo
*bo
) {}
1769 struct amdgpu_debugfs
{
1770 const struct drm_info_list
*files
;
1774 int amdgpu_debugfs_add_files(struct amdgpu_device
*adev
,
1775 const struct drm_info_list
*files
,
1777 int amdgpu_debugfs_fence_init(struct amdgpu_device
*adev
);
1779 #if defined(CONFIG_DEBUG_FS)
1780 int amdgpu_debugfs_init(struct drm_minor
*minor
);
1781 void amdgpu_debugfs_cleanup(struct drm_minor
*minor
);
1784 int amdgpu_debugfs_firmware_init(struct amdgpu_device
*adev
);
1787 * amdgpu smumgr functions
1789 struct amdgpu_smumgr_funcs
{
1790 int (*check_fw_load_finish
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1791 int (*request_smu_load_fw
)(struct amdgpu_device
*adev
);
1792 int (*request_smu_specific_fw
)(struct amdgpu_device
*adev
, uint32_t fwtype
);
1798 struct amdgpu_smumgr
{
1799 struct amdgpu_bo
*toc_buf
;
1800 struct amdgpu_bo
*smu_buf
;
1801 /* asic priv smu data */
1803 spinlock_t smu_lock
;
1804 /* smumgr functions */
1805 const struct amdgpu_smumgr_funcs
*smumgr_funcs
;
1806 /* ucode loading complete flag */
1811 * ASIC specific register table accessible by UMD
1813 struct amdgpu_allowed_register_entry
{
1814 uint32_t reg_offset
;
1820 * ASIC specific functions.
1822 struct amdgpu_asic_funcs
{
1823 bool (*read_disabled_bios
)(struct amdgpu_device
*adev
);
1824 bool (*read_bios_from_rom
)(struct amdgpu_device
*adev
,
1825 u8
*bios
, u32 length_bytes
);
1826 int (*read_register
)(struct amdgpu_device
*adev
, u32 se_num
,
1827 u32 sh_num
, u32 reg_offset
, u32
*value
);
1828 void (*set_vga_state
)(struct amdgpu_device
*adev
, bool state
);
1829 int (*reset
)(struct amdgpu_device
*adev
);
1830 /* wait for mc_idle */
1831 int (*wait_for_mc_idle
)(struct amdgpu_device
*adev
);
1832 /* get the reference clock */
1833 u32 (*get_xclk
)(struct amdgpu_device
*adev
);
1834 /* get the gpu clock counter */
1835 uint64_t (*get_gpu_clock_counter
)(struct amdgpu_device
*adev
);
1836 /* MM block clocks */
1837 int (*set_uvd_clocks
)(struct amdgpu_device
*adev
, u32 vclk
, u32 dclk
);
1838 int (*set_vce_clocks
)(struct amdgpu_device
*adev
, u32 evclk
, u32 ecclk
);
1839 /* query virtual capabilities */
1840 u32 (*get_virtual_caps
)(struct amdgpu_device
*adev
);
1846 int amdgpu_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1847 struct drm_file
*filp
);
1848 int amdgpu_bo_list_ioctl(struct drm_device
*dev
, void *data
,
1849 struct drm_file
*filp
);
1851 int amdgpu_gem_info_ioctl(struct drm_device
*dev
, void *data
,
1852 struct drm_file
*filp
);
1853 int amdgpu_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
1854 struct drm_file
*filp
);
1855 int amdgpu_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1856 struct drm_file
*filp
);
1857 int amdgpu_gem_wait_idle_ioctl(struct drm_device
*dev
, void *data
,
1858 struct drm_file
*filp
);
1859 int amdgpu_gem_va_ioctl(struct drm_device
*dev
, void *data
,
1860 struct drm_file
*filp
);
1861 int amdgpu_gem_op_ioctl(struct drm_device
*dev
, void *data
,
1862 struct drm_file
*filp
);
1863 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1864 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
);
1866 int amdgpu_gem_metadata_ioctl(struct drm_device
*dev
, void *data
,
1867 struct drm_file
*filp
);
1869 /* VRAM scratch page for HDP bug, default vram page */
1870 struct amdgpu_vram_scratch
{
1871 struct amdgpu_bo
*robj
;
1872 volatile uint32_t *ptr
;
1879 struct amdgpu_atif_notification_cfg
{
1884 struct amdgpu_atif_notifications
{
1885 bool display_switch
;
1886 bool expansion_mode_change
;
1888 bool forced_power_state
;
1889 bool system_power_state
;
1890 bool display_conf_change
;
1892 bool brightness_change
;
1893 bool dgpu_display_event
;
1896 struct amdgpu_atif_functions
{
1898 bool sbios_requests
;
1899 bool select_active_disp
;
1901 bool get_tv_standard
;
1902 bool set_tv_standard
;
1903 bool get_panel_expansion_mode
;
1904 bool set_panel_expansion_mode
;
1905 bool temperature_change
;
1906 bool graphics_device_types
;
1909 struct amdgpu_atif
{
1910 struct amdgpu_atif_notifications notifications
;
1911 struct amdgpu_atif_functions functions
;
1912 struct amdgpu_atif_notification_cfg notification_cfg
;
1913 struct amdgpu_encoder
*encoder_for_bl
;
1916 struct amdgpu_atcs_functions
{
1920 bool pcie_bus_width
;
1923 struct amdgpu_atcs
{
1924 struct amdgpu_atcs_functions functions
;
1930 struct cgs_device
*amdgpu_cgs_create_device(struct amdgpu_device
*adev
);
1931 void amdgpu_cgs_destroy_device(struct cgs_device
*cgs_device
);
1934 /* GPU virtualization */
1935 #define AMDGPU_VIRT_CAPS_SRIOV_EN (1 << 0)
1936 #define AMDGPU_VIRT_CAPS_IS_VF (1 << 1)
1937 struct amdgpu_virtualization
{
1938 bool supports_sr_iov
;
1944 * Core structure, functions and helpers.
1946 typedef uint32_t (*amdgpu_rreg_t
)(struct amdgpu_device
*, uint32_t);
1947 typedef void (*amdgpu_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1949 typedef uint32_t (*amdgpu_block_rreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t);
1950 typedef void (*amdgpu_block_wreg_t
)(struct amdgpu_device
*, uint32_t, uint32_t, uint32_t);
1952 struct amdgpu_ip_block_status
{
1958 struct amdgpu_device
{
1960 struct drm_device
*ddev
;
1961 struct pci_dev
*pdev
;
1963 #ifdef CONFIG_DRM_AMD_ACP
1964 struct amdgpu_acp acp
;
1968 enum amd_asic_type asic_type
;
1971 uint32_t external_rev_id
;
1972 unsigned long flags
;
1974 const struct amdgpu_asic_funcs
*asic_funcs
;
1978 struct work_struct reset_work
;
1979 struct notifier_block acpi_nb
;
1980 struct amdgpu_i2c_chan
*i2c_bus
[AMDGPU_MAX_I2C_BUS
];
1981 struct amdgpu_debugfs debugfs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1982 unsigned debugfs_count
;
1983 #if defined(CONFIG_DEBUG_FS)
1984 struct dentry
*debugfs_regs
[AMDGPU_DEBUGFS_MAX_COMPONENTS
];
1986 struct amdgpu_atif atif
;
1987 struct amdgpu_atcs atcs
;
1988 struct mutex srbm_mutex
;
1989 /* GRBM index mutex. Protects concurrent access to GRBM index */
1990 struct mutex grbm_idx_mutex
;
1991 struct dev_pm_domain vga_pm_domain
;
1992 bool have_disp_power_ref
;
1997 struct amdgpu_bo
*stollen_vga_memory
;
1998 uint32_t bios_scratch
[AMDGPU_BIOS_NUM_SCRATCH
];
2000 /* Register/doorbell mmio */
2001 resource_size_t rmmio_base
;
2002 resource_size_t rmmio_size
;
2003 void __iomem
*rmmio
;
2004 /* protects concurrent MM_INDEX/DATA based register access */
2005 spinlock_t mmio_idx_lock
;
2006 /* protects concurrent SMC based register access */
2007 spinlock_t smc_idx_lock
;
2008 amdgpu_rreg_t smc_rreg
;
2009 amdgpu_wreg_t smc_wreg
;
2010 /* protects concurrent PCIE register access */
2011 spinlock_t pcie_idx_lock
;
2012 amdgpu_rreg_t pcie_rreg
;
2013 amdgpu_wreg_t pcie_wreg
;
2014 /* protects concurrent UVD register access */
2015 spinlock_t uvd_ctx_idx_lock
;
2016 amdgpu_rreg_t uvd_ctx_rreg
;
2017 amdgpu_wreg_t uvd_ctx_wreg
;
2018 /* protects concurrent DIDT register access */
2019 spinlock_t didt_idx_lock
;
2020 amdgpu_rreg_t didt_rreg
;
2021 amdgpu_wreg_t didt_wreg
;
2022 /* protects concurrent ENDPOINT (audio) register access */
2023 spinlock_t audio_endpt_idx_lock
;
2024 amdgpu_block_rreg_t audio_endpt_rreg
;
2025 amdgpu_block_wreg_t audio_endpt_wreg
;
2026 void __iomem
*rio_mem
;
2027 resource_size_t rio_mem_size
;
2028 struct amdgpu_doorbell doorbell
;
2030 /* clock/pll info */
2031 struct amdgpu_clock clock
;
2034 struct amdgpu_mc mc
;
2035 struct amdgpu_gart gart
;
2036 struct amdgpu_dummy_page dummy_page
;
2037 struct amdgpu_vm_manager vm_manager
;
2039 /* memory management */
2040 struct amdgpu_mman mman
;
2041 struct amdgpu_vram_scratch vram_scratch
;
2042 struct amdgpu_wb wb
;
2043 atomic64_t vram_usage
;
2044 atomic64_t vram_vis_usage
;
2045 atomic64_t gtt_usage
;
2046 atomic64_t num_bytes_moved
;
2047 atomic64_t num_evictions
;
2048 atomic_t gpu_reset_counter
;
2051 struct amdgpu_mode_info mode_info
;
2052 struct work_struct hotplug_work
;
2053 struct amdgpu_irq_src crtc_irq
;
2054 struct amdgpu_irq_src pageflip_irq
;
2055 struct amdgpu_irq_src hpd_irq
;
2060 struct amdgpu_ring
*rings
[AMDGPU_MAX_RINGS
];
2062 struct amdgpu_sa_manager ring_tmp_bo
;
2065 struct amdgpu_irq irq
;
2068 struct amd_powerplay powerplay
;
2070 bool pp_force_state_enabled
;
2073 struct amdgpu_pm pm
;
2078 struct amdgpu_smumgr smu
;
2081 struct amdgpu_gfx gfx
;
2084 struct amdgpu_sdma sdma
;
2087 struct amdgpu_uvd uvd
;
2090 struct amdgpu_vce vce
;
2093 struct amdgpu_firmware firmware
;
2096 struct amdgpu_gds gds
;
2098 const struct amdgpu_ip_block_version
*ip_blocks
;
2100 struct amdgpu_ip_block_status
*ip_block_status
;
2101 struct mutex mn_lock
;
2102 DECLARE_HASHTABLE(mn_hash
, 7);
2104 /* tracking pinned memory */
2106 u64 invisible_pin_size
;
2109 /* amdkfd interface */
2110 struct kfd_dev
*kfd
;
2112 struct amdgpu_virtualization virtualization
;
2115 bool amdgpu_device_is_px(struct drm_device
*dev
);
2116 int amdgpu_device_init(struct amdgpu_device
*adev
,
2117 struct drm_device
*ddev
,
2118 struct pci_dev
*pdev
,
2120 void amdgpu_device_fini(struct amdgpu_device
*adev
);
2121 int amdgpu_gpu_wait_for_idle(struct amdgpu_device
*adev
);
2123 uint32_t amdgpu_mm_rreg(struct amdgpu_device
*adev
, uint32_t reg
,
2124 bool always_indirect
);
2125 void amdgpu_mm_wreg(struct amdgpu_device
*adev
, uint32_t reg
, uint32_t v
,
2126 bool always_indirect
);
2127 u32
amdgpu_io_rreg(struct amdgpu_device
*adev
, u32 reg
);
2128 void amdgpu_io_wreg(struct amdgpu_device
*adev
, u32 reg
, u32 v
);
2130 u32
amdgpu_mm_rdoorbell(struct amdgpu_device
*adev
, u32 index
);
2131 void amdgpu_mm_wdoorbell(struct amdgpu_device
*adev
, u32 index
, u32 v
);
2134 * Registers read & write functions.
2136 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2137 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2138 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2139 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2140 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2141 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2142 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2143 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2144 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2145 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2146 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2147 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2148 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2149 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2150 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2151 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2152 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2153 #define WREG32_P(reg, val, mask) \
2155 uint32_t tmp_ = RREG32(reg); \
2157 tmp_ |= ((val) & ~(mask)); \
2158 WREG32(reg, tmp_); \
2160 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2161 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2162 #define WREG32_PLL_P(reg, val, mask) \
2164 uint32_t tmp_ = RREG32_PLL(reg); \
2166 tmp_ |= ((val) & ~(mask)); \
2167 WREG32_PLL(reg, tmp_); \
2169 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2170 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2171 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2173 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2174 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2176 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2177 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2179 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2180 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2181 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2183 #define REG_GET_FIELD(value, reg, field) \
2184 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2189 #define RBIOS8(i) (adev->bios[i])
2190 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2191 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2196 static inline void amdgpu_ring_write(struct amdgpu_ring
*ring
, uint32_t v
)
2198 if (ring
->count_dw
<= 0)
2199 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2200 ring
->ring
[ring
->wptr
++] = v
;
2201 ring
->wptr
&= ring
->ptr_mask
;
2205 static inline struct amdgpu_sdma_instance
*
2206 amdgpu_get_sdma_instance(struct amdgpu_ring
*ring
)
2208 struct amdgpu_device
*adev
= ring
->adev
;
2211 for (i
= 0; i
< adev
->sdma
.num_instances
; i
++)
2212 if (&adev
->sdma
.instance
[i
].ring
== ring
)
2215 if (i
< AMDGPU_MAX_SDMA_INSTANCES
)
2216 return &adev
->sdma
.instance
[i
];
2224 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2225 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2226 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2227 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2228 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2229 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2230 #define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))
2231 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2232 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2233 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2234 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2235 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2236 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2237 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2238 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2239 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2240 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2241 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2242 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2243 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2244 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2245 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2246 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
2247 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2248 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2249 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2250 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2251 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2252 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2253 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2254 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2255 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2256 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2257 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2258 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2259 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2260 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2261 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2262 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2263 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2264 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2265 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2266 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2267 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2268 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2269 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2270 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2271 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2272 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2273 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2274 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2275 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2276 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2277 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2278 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2279 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2280 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2281 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2282 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2283 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2285 #define amdgpu_dpm_get_temperature(adev) \
2286 ((adev)->pp_enabled ? \
2287 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2288 (adev)->pm.funcs->get_temperature((adev)))
2290 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2291 ((adev)->pp_enabled ? \
2292 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2293 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2295 #define amdgpu_dpm_get_fan_control_mode(adev) \
2296 ((adev)->pp_enabled ? \
2297 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2298 (adev)->pm.funcs->get_fan_control_mode((adev)))
2300 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2301 ((adev)->pp_enabled ? \
2302 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2303 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2305 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2306 ((adev)->pp_enabled ? \
2307 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2308 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2310 #define amdgpu_dpm_get_sclk(adev, l) \
2311 ((adev)->pp_enabled ? \
2312 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2313 (adev)->pm.funcs->get_sclk((adev), (l)))
2315 #define amdgpu_dpm_get_mclk(adev, l) \
2316 ((adev)->pp_enabled ? \
2317 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2318 (adev)->pm.funcs->get_mclk((adev), (l)))
2321 #define amdgpu_dpm_force_performance_level(adev, l) \
2322 ((adev)->pp_enabled ? \
2323 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2324 (adev)->pm.funcs->force_performance_level((adev), (l)))
2326 #define amdgpu_dpm_powergate_uvd(adev, g) \
2327 ((adev)->pp_enabled ? \
2328 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2329 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2331 #define amdgpu_dpm_powergate_vce(adev, g) \
2332 ((adev)->pp_enabled ? \
2333 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2334 (adev)->pm.funcs->powergate_vce((adev), (g)))
2336 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2337 ((adev)->pp_enabled ? \
2338 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2339 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2341 #define amdgpu_dpm_get_current_power_state(adev) \
2342 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2344 #define amdgpu_dpm_get_performance_level(adev) \
2345 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2347 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2348 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2350 #define amdgpu_dpm_get_pp_table(adev, table) \
2351 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2353 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2354 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2356 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2357 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2359 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2360 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2362 #define amdgpu_dpm_get_sclk_od(adev) \
2363 (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
2365 #define amdgpu_dpm_set_sclk_od(adev, value) \
2366 (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
2368 #define amdgpu_dpm_get_mclk_od(adev) \
2369 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
2371 #define amdgpu_dpm_set_mclk_od(adev, value) \
2372 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
2374 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2375 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2377 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2379 /* Common functions */
2380 int amdgpu_gpu_reset(struct amdgpu_device
*adev
);
2381 void amdgpu_pci_config_reset(struct amdgpu_device
*adev
);
2382 bool amdgpu_card_posted(struct amdgpu_device
*adev
);
2383 void amdgpu_update_display_priority(struct amdgpu_device
*adev
);
2385 int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
);
2386 int amdgpu_cs_get_ring(struct amdgpu_device
*adev
, u32 ip_type
,
2387 u32 ip_instance
, u32 ring
,
2388 struct amdgpu_ring
**out_ring
);
2389 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
);
2390 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
);
2391 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt
*ttm
, struct page
**pages
);
2392 int amdgpu_ttm_tt_set_userptr(struct ttm_tt
*ttm
, uint64_t addr
,
2394 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt
*ttm
);
2395 struct mm_struct
*amdgpu_ttm_tt_get_usermm(struct ttm_tt
*ttm
);
2396 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt
*ttm
, unsigned long start
,
2398 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt
*ttm
,
2399 int *last_invalidated
);
2400 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt
*ttm
);
2401 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device
*adev
, struct ttm_tt
*ttm
,
2402 struct ttm_mem_reg
*mem
);
2403 void amdgpu_vram_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
, u64 base
);
2404 void amdgpu_gtt_location(struct amdgpu_device
*adev
, struct amdgpu_mc
*mc
);
2405 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device
*adev
, u64 size
);
2406 void amdgpu_program_register_sequence(struct amdgpu_device
*adev
,
2407 const u32
*registers
,
2408 const u32 array_size
);
2410 bool amdgpu_device_is_px(struct drm_device
*dev
);
2412 #if defined(CONFIG_VGA_SWITCHEROO)
2413 void amdgpu_register_atpx_handler(void);
2414 void amdgpu_unregister_atpx_handler(void);
2415 bool amdgpu_has_atpx_dgpu_power_cntl(void);
2416 bool amdgpu_is_atpx_hybrid(void);
2418 static inline void amdgpu_register_atpx_handler(void) {}
2419 static inline void amdgpu_unregister_atpx_handler(void) {}
2420 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
2421 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
2427 extern const struct drm_ioctl_desc amdgpu_ioctls_kms
[];
2428 extern const int amdgpu_max_kms_ioctl
;
2430 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
);
2431 int amdgpu_driver_unload_kms(struct drm_device
*dev
);
2432 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
);
2433 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
);
2434 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
2435 struct drm_file
*file_priv
);
2436 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
2437 struct drm_file
*file_priv
);
2438 int amdgpu_suspend_kms(struct drm_device
*dev
, bool suspend
, bool fbcon
);
2439 int amdgpu_resume_kms(struct drm_device
*dev
, bool resume
, bool fbcon
);
2440 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, unsigned int pipe
);
2441 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2442 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, unsigned int pipe
);
2443 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, unsigned int pipe
,
2445 struct timeval
*vblank_time
,
2447 long amdgpu_kms_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2451 * functions used by amdgpu_encoder.c
2453 struct amdgpu_afmt_acr
{
2467 struct amdgpu_afmt_acr
amdgpu_afmt_acr(uint32_t clock
);
2470 #if defined(CONFIG_ACPI)
2471 int amdgpu_acpi_init(struct amdgpu_device
*adev
);
2472 void amdgpu_acpi_fini(struct amdgpu_device
*adev
);
2473 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device
*adev
);
2474 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device
*adev
,
2475 u8 perf_req
, bool advertise
);
2476 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device
*adev
);
2478 static inline int amdgpu_acpi_init(struct amdgpu_device
*adev
) { return 0; }
2479 static inline void amdgpu_acpi_fini(struct amdgpu_device
*adev
) { }
2482 struct amdgpu_bo_va_mapping
*
2483 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
2484 uint64_t addr
, struct amdgpu_bo
**bo
);
2486 #include "amdgpu_object.h"