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drm/amdgpu: move the context from the IBs into the job
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
38
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
55 #include "amd_powerplay.h"
56 #include "amdgpu_acp.h"
57
58 #include "gpu_scheduler.h"
59
60 /*
61 * Modules parameters.
62 */
63 extern int amdgpu_modeset;
64 extern int amdgpu_vram_limit;
65 extern int amdgpu_gart_size;
66 extern int amdgpu_benchmarking;
67 extern int amdgpu_testing;
68 extern int amdgpu_audio;
69 extern int amdgpu_disp_priority;
70 extern int amdgpu_hw_i2c;
71 extern int amdgpu_pcie_gen2;
72 extern int amdgpu_msi;
73 extern int amdgpu_lockup_timeout;
74 extern int amdgpu_dpm;
75 extern int amdgpu_smc_load_fw;
76 extern int amdgpu_aspm;
77 extern int amdgpu_runtime_pm;
78 extern unsigned amdgpu_ip_block_mask;
79 extern int amdgpu_bapm;
80 extern int amdgpu_deep_color;
81 extern int amdgpu_vm_size;
82 extern int amdgpu_vm_block_size;
83 extern int amdgpu_vm_fault_stop;
84 extern int amdgpu_vm_debug;
85 extern int amdgpu_sched_jobs;
86 extern int amdgpu_sched_hw_submission;
87 extern int amdgpu_powerplay;
88 extern unsigned amdgpu_pcie_gen_cap;
89 extern unsigned amdgpu_pcie_lane_cap;
90
91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
95 #define AMDGPU_IB_POOL_SIZE 16
96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
97 #define AMDGPUFB_CONN_LIMIT 4
98 #define AMDGPU_BIOS_NUM_SCRATCH 8
99
100 /* max number of rings */
101 #define AMDGPU_MAX_RINGS 16
102 #define AMDGPU_MAX_GFX_RINGS 1
103 #define AMDGPU_MAX_COMPUTE_RINGS 8
104 #define AMDGPU_MAX_VCE_RINGS 2
105
106 /* max number of IP instances */
107 #define AMDGPU_MAX_SDMA_INSTANCES 2
108
109 /* hardcode that limit for now */
110 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
111
112 /* hard reset data */
113 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
114
115 /* reset flags */
116 #define AMDGPU_RESET_GFX (1 << 0)
117 #define AMDGPU_RESET_COMPUTE (1 << 1)
118 #define AMDGPU_RESET_DMA (1 << 2)
119 #define AMDGPU_RESET_CP (1 << 3)
120 #define AMDGPU_RESET_GRBM (1 << 4)
121 #define AMDGPU_RESET_DMA1 (1 << 5)
122 #define AMDGPU_RESET_RLC (1 << 6)
123 #define AMDGPU_RESET_SEM (1 << 7)
124 #define AMDGPU_RESET_IH (1 << 8)
125 #define AMDGPU_RESET_VMC (1 << 9)
126 #define AMDGPU_RESET_MC (1 << 10)
127 #define AMDGPU_RESET_DISPLAY (1 << 11)
128 #define AMDGPU_RESET_UVD (1 << 12)
129 #define AMDGPU_RESET_VCE (1 << 13)
130 #define AMDGPU_RESET_VCE1 (1 << 14)
131
132 /* GFX current status */
133 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
134 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
135 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
136 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
137 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
138
139 /* max cursor sizes (in pixels) */
140 #define CIK_CURSOR_WIDTH 128
141 #define CIK_CURSOR_HEIGHT 128
142
143 struct amdgpu_device;
144 struct amdgpu_ib;
145 struct amdgpu_vm;
146 struct amdgpu_ring;
147 struct amdgpu_cs_parser;
148 struct amdgpu_job;
149 struct amdgpu_irq_src;
150 struct amdgpu_fpriv;
151
152 enum amdgpu_cp_irq {
153 AMDGPU_CP_IRQ_GFX_EOP = 0,
154 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
155 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
156 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
157 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
158 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
159 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
160 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
162
163 AMDGPU_CP_IRQ_LAST
164 };
165
166 enum amdgpu_sdma_irq {
167 AMDGPU_SDMA_IRQ_TRAP0 = 0,
168 AMDGPU_SDMA_IRQ_TRAP1,
169
170 AMDGPU_SDMA_IRQ_LAST
171 };
172
173 enum amdgpu_thermal_irq {
174 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
175 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
176
177 AMDGPU_THERMAL_IRQ_LAST
178 };
179
180 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
181 enum amd_ip_block_type block_type,
182 enum amd_clockgating_state state);
183 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
184 enum amd_ip_block_type block_type,
185 enum amd_powergating_state state);
186
187 struct amdgpu_ip_block_version {
188 enum amd_ip_block_type type;
189 u32 major;
190 u32 minor;
191 u32 rev;
192 const struct amd_ip_funcs *funcs;
193 };
194
195 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
196 enum amd_ip_block_type type,
197 u32 major, u32 minor);
198
199 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
200 struct amdgpu_device *adev,
201 enum amd_ip_block_type type);
202
203 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
204 struct amdgpu_buffer_funcs {
205 /* maximum bytes in a single operation */
206 uint32_t copy_max_bytes;
207
208 /* number of dw to reserve per operation */
209 unsigned copy_num_dw;
210
211 /* used for buffer migration */
212 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
213 /* src addr in bytes */
214 uint64_t src_offset,
215 /* dst addr in bytes */
216 uint64_t dst_offset,
217 /* number of byte to transfer */
218 uint32_t byte_count);
219
220 /* maximum bytes in a single operation */
221 uint32_t fill_max_bytes;
222
223 /* number of dw to reserve per operation */
224 unsigned fill_num_dw;
225
226 /* used for buffer clearing */
227 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
228 /* value to write to memory */
229 uint32_t src_data,
230 /* dst addr in bytes */
231 uint64_t dst_offset,
232 /* number of byte to fill */
233 uint32_t byte_count);
234 };
235
236 /* provided by hw blocks that can write ptes, e.g., sdma */
237 struct amdgpu_vm_pte_funcs {
238 /* copy pte entries from GART */
239 void (*copy_pte)(struct amdgpu_ib *ib,
240 uint64_t pe, uint64_t src,
241 unsigned count);
242 /* write pte one entry at a time with addr mapping */
243 void (*write_pte)(struct amdgpu_ib *ib,
244 const dma_addr_t *pages_addr, uint64_t pe,
245 uint64_t addr, unsigned count,
246 uint32_t incr, uint32_t flags);
247 /* for linear pte/pde updates without addr mapping */
248 void (*set_pte_pde)(struct amdgpu_ib *ib,
249 uint64_t pe,
250 uint64_t addr, unsigned count,
251 uint32_t incr, uint32_t flags);
252 };
253
254 /* provided by the gmc block */
255 struct amdgpu_gart_funcs {
256 /* flush the vm tlb via mmio */
257 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
258 uint32_t vmid);
259 /* write pte/pde updates using the cpu */
260 int (*set_pte_pde)(struct amdgpu_device *adev,
261 void *cpu_pt_addr, /* cpu addr of page table */
262 uint32_t gpu_page_idx, /* pte/pde to update */
263 uint64_t addr, /* addr to write into pte/pde */
264 uint32_t flags); /* access flags */
265 };
266
267 /* provided by the ih block */
268 struct amdgpu_ih_funcs {
269 /* ring read/write ptr handling, called from interrupt context */
270 u32 (*get_wptr)(struct amdgpu_device *adev);
271 void (*decode_iv)(struct amdgpu_device *adev,
272 struct amdgpu_iv_entry *entry);
273 void (*set_rptr)(struct amdgpu_device *adev);
274 };
275
276 /* provided by hw blocks that expose a ring buffer for commands */
277 struct amdgpu_ring_funcs {
278 /* ring read/write ptr handling */
279 u32 (*get_rptr)(struct amdgpu_ring *ring);
280 u32 (*get_wptr)(struct amdgpu_ring *ring);
281 void (*set_wptr)(struct amdgpu_ring *ring);
282 /* validating and patching of IBs */
283 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
284 /* command emit functions */
285 void (*emit_ib)(struct amdgpu_ring *ring,
286 struct amdgpu_ib *ib, bool ctx_switch);
287 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
288 uint64_t seq, unsigned flags);
289 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
290 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
291 uint64_t pd_addr);
292 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
293 void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
294 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
295 uint32_t gds_base, uint32_t gds_size,
296 uint32_t gws_base, uint32_t gws_size,
297 uint32_t oa_base, uint32_t oa_size);
298 /* testing functions */
299 int (*test_ring)(struct amdgpu_ring *ring);
300 int (*test_ib)(struct amdgpu_ring *ring);
301 /* insert NOP packets */
302 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
303 /* pad the indirect buffer to the necessary number of dw */
304 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
305 unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
306 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
307 };
308
309 /*
310 * BIOS.
311 */
312 bool amdgpu_get_bios(struct amdgpu_device *adev);
313 bool amdgpu_read_bios(struct amdgpu_device *adev);
314
315 /*
316 * Dummy page
317 */
318 struct amdgpu_dummy_page {
319 struct page *page;
320 dma_addr_t addr;
321 };
322 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
323 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
324
325
326 /*
327 * Clocks
328 */
329
330 #define AMDGPU_MAX_PPLL 3
331
332 struct amdgpu_clock {
333 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
334 struct amdgpu_pll spll;
335 struct amdgpu_pll mpll;
336 /* 10 Khz units */
337 uint32_t default_mclk;
338 uint32_t default_sclk;
339 uint32_t default_dispclk;
340 uint32_t current_dispclk;
341 uint32_t dp_extclk;
342 uint32_t max_pixel_clock;
343 };
344
345 /*
346 * Fences.
347 */
348 struct amdgpu_fence_driver {
349 uint64_t gpu_addr;
350 volatile uint32_t *cpu_addr;
351 /* sync_seq is protected by ring emission lock */
352 uint32_t sync_seq;
353 atomic_t last_seq;
354 bool initialized;
355 struct amdgpu_irq_src *irq_src;
356 unsigned irq_type;
357 struct timer_list fallback_timer;
358 unsigned num_fences_mask;
359 spinlock_t lock;
360 struct fence **fences;
361 };
362
363 /* some special values for the owner field */
364 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
365 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
366
367 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
368 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
369
370 struct amdgpu_user_fence {
371 /* write-back bo */
372 struct amdgpu_bo *bo;
373 /* write-back address offset to bo start */
374 uint32_t offset;
375 };
376
377 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
378 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
379 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
380
381 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
382 unsigned num_hw_submission);
383 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
384 struct amdgpu_irq_src *irq_src,
385 unsigned irq_type);
386 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
387 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
388 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
389 void amdgpu_fence_process(struct amdgpu_ring *ring);
390 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
391 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
392
393 /*
394 * TTM.
395 */
396
397 #define AMDGPU_TTM_LRU_SIZE 20
398
399 struct amdgpu_mman_lru {
400 struct list_head *lru[TTM_NUM_MEM_TYPES];
401 struct list_head *swap_lru;
402 };
403
404 struct amdgpu_mman {
405 struct ttm_bo_global_ref bo_global_ref;
406 struct drm_global_reference mem_global_ref;
407 struct ttm_bo_device bdev;
408 bool mem_global_referenced;
409 bool initialized;
410
411 #if defined(CONFIG_DEBUG_FS)
412 struct dentry *vram;
413 struct dentry *gtt;
414 #endif
415
416 /* buffer handling */
417 const struct amdgpu_buffer_funcs *buffer_funcs;
418 struct amdgpu_ring *buffer_funcs_ring;
419 /* Scheduler entity for buffer moves */
420 struct amd_sched_entity entity;
421
422 /* custom LRU management */
423 struct amdgpu_mman_lru log2_size[AMDGPU_TTM_LRU_SIZE];
424 };
425
426 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
427 uint64_t src_offset,
428 uint64_t dst_offset,
429 uint32_t byte_count,
430 struct reservation_object *resv,
431 struct fence **fence);
432 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
433
434 struct amdgpu_bo_list_entry {
435 struct amdgpu_bo *robj;
436 struct ttm_validate_buffer tv;
437 struct amdgpu_bo_va *bo_va;
438 uint32_t priority;
439 struct page **user_pages;
440 int user_invalidated;
441 };
442
443 struct amdgpu_bo_va_mapping {
444 struct list_head list;
445 struct interval_tree_node it;
446 uint64_t offset;
447 uint32_t flags;
448 };
449
450 /* bo virtual addresses in a specific vm */
451 struct amdgpu_bo_va {
452 /* protected by bo being reserved */
453 struct list_head bo_list;
454 struct fence *last_pt_update;
455 unsigned ref_count;
456
457 /* protected by vm mutex and spinlock */
458 struct list_head vm_status;
459
460 /* mappings for this bo_va */
461 struct list_head invalids;
462 struct list_head valids;
463
464 /* constant after initialization */
465 struct amdgpu_vm *vm;
466 struct amdgpu_bo *bo;
467 };
468
469 #define AMDGPU_GEM_DOMAIN_MAX 0x3
470
471 struct amdgpu_bo {
472 /* Protected by gem.mutex */
473 struct list_head list;
474 /* Protected by tbo.reserved */
475 u32 prefered_domains;
476 u32 allowed_domains;
477 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
478 struct ttm_placement placement;
479 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap;
481 u64 flags;
482 unsigned pin_count;
483 void *kptr;
484 u64 tiling_flags;
485 u64 metadata_flags;
486 void *metadata;
487 u32 metadata_size;
488 /* list of all virtual address to which this bo
489 * is associated to
490 */
491 struct list_head va;
492 /* Constant after initialization */
493 struct amdgpu_device *adev;
494 struct drm_gem_object gem_base;
495 struct amdgpu_bo *parent;
496
497 struct ttm_bo_kmap_obj dma_buf_vmap;
498 struct amdgpu_mn *mn;
499 struct list_head mn_list;
500 };
501 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
502
503 void amdgpu_gem_object_free(struct drm_gem_object *obj);
504 int amdgpu_gem_object_open(struct drm_gem_object *obj,
505 struct drm_file *file_priv);
506 void amdgpu_gem_object_close(struct drm_gem_object *obj,
507 struct drm_file *file_priv);
508 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
509 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
510 struct drm_gem_object *
511 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
512 struct dma_buf_attachment *attach,
513 struct sg_table *sg);
514 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
515 struct drm_gem_object *gobj,
516 int flags);
517 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
518 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
519 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
520 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
521 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
522 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
523
524 /* sub-allocation manager, it has to be protected by another lock.
525 * By conception this is an helper for other part of the driver
526 * like the indirect buffer or semaphore, which both have their
527 * locking.
528 *
529 * Principe is simple, we keep a list of sub allocation in offset
530 * order (first entry has offset == 0, last entry has the highest
531 * offset).
532 *
533 * When allocating new object we first check if there is room at
534 * the end total_size - (last_object_offset + last_object_size) >=
535 * alloc_size. If so we allocate new object there.
536 *
537 * When there is not enough room at the end, we start waiting for
538 * each sub object until we reach object_offset+object_size >=
539 * alloc_size, this object then become the sub object we return.
540 *
541 * Alignment can't be bigger than page size.
542 *
543 * Hole are not considered for allocation to keep things simple.
544 * Assumption is that there won't be hole (all object on same
545 * alignment).
546 */
547
548 #define AMDGPU_SA_NUM_FENCE_LISTS 32
549
550 struct amdgpu_sa_manager {
551 wait_queue_head_t wq;
552 struct amdgpu_bo *bo;
553 struct list_head *hole;
554 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
555 struct list_head olist;
556 unsigned size;
557 uint64_t gpu_addr;
558 void *cpu_ptr;
559 uint32_t domain;
560 uint32_t align;
561 };
562
563 /* sub-allocation buffer */
564 struct amdgpu_sa_bo {
565 struct list_head olist;
566 struct list_head flist;
567 struct amdgpu_sa_manager *manager;
568 unsigned soffset;
569 unsigned eoffset;
570 struct fence *fence;
571 };
572
573 /*
574 * GEM objects.
575 */
576 void amdgpu_gem_force_release(struct amdgpu_device *adev);
577 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
578 int alignment, u32 initial_domain,
579 u64 flags, bool kernel,
580 struct drm_gem_object **obj);
581
582 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
583 struct drm_device *dev,
584 struct drm_mode_create_dumb *args);
585 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
586 struct drm_device *dev,
587 uint32_t handle, uint64_t *offset_p);
588 /*
589 * Synchronization
590 */
591 struct amdgpu_sync {
592 DECLARE_HASHTABLE(fences, 4);
593 struct fence *last_vm_update;
594 };
595
596 void amdgpu_sync_create(struct amdgpu_sync *sync);
597 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
598 struct fence *f);
599 int amdgpu_sync_resv(struct amdgpu_device *adev,
600 struct amdgpu_sync *sync,
601 struct reservation_object *resv,
602 void *owner);
603 bool amdgpu_sync_is_idle(struct amdgpu_sync *sync);
604 int amdgpu_sync_cycle_fences(struct amdgpu_sync *dst, struct amdgpu_sync *src,
605 struct fence *fence);
606 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
607 int amdgpu_sync_wait(struct amdgpu_sync *sync);
608 void amdgpu_sync_free(struct amdgpu_sync *sync);
609 int amdgpu_sync_init(void);
610 void amdgpu_sync_fini(void);
611
612 /*
613 * GART structures, functions & helpers
614 */
615 struct amdgpu_mc;
616
617 #define AMDGPU_GPU_PAGE_SIZE 4096
618 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
619 #define AMDGPU_GPU_PAGE_SHIFT 12
620 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
621
622 struct amdgpu_gart {
623 dma_addr_t table_addr;
624 struct amdgpu_bo *robj;
625 void *ptr;
626 unsigned num_gpu_pages;
627 unsigned num_cpu_pages;
628 unsigned table_size;
629 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
630 struct page **pages;
631 #endif
632 bool ready;
633 const struct amdgpu_gart_funcs *gart_funcs;
634 };
635
636 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
637 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
638 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
639 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
640 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
641 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
642 int amdgpu_gart_init(struct amdgpu_device *adev);
643 void amdgpu_gart_fini(struct amdgpu_device *adev);
644 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
645 int pages);
646 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
647 int pages, struct page **pagelist,
648 dma_addr_t *dma_addr, uint32_t flags);
649
650 /*
651 * GPU MC structures, functions & helpers
652 */
653 struct amdgpu_mc {
654 resource_size_t aper_size;
655 resource_size_t aper_base;
656 resource_size_t agp_base;
657 /* for some chips with <= 32MB we need to lie
658 * about vram size near mc fb location */
659 u64 mc_vram_size;
660 u64 visible_vram_size;
661 u64 gtt_size;
662 u64 gtt_start;
663 u64 gtt_end;
664 u64 vram_start;
665 u64 vram_end;
666 unsigned vram_width;
667 u64 real_vram_size;
668 int vram_mtrr;
669 u64 gtt_base_align;
670 u64 mc_mask;
671 const struct firmware *fw; /* MC firmware */
672 uint32_t fw_version;
673 struct amdgpu_irq_src vm_fault;
674 uint32_t vram_type;
675 };
676
677 /*
678 * GPU doorbell structures, functions & helpers
679 */
680 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
681 {
682 AMDGPU_DOORBELL_KIQ = 0x000,
683 AMDGPU_DOORBELL_HIQ = 0x001,
684 AMDGPU_DOORBELL_DIQ = 0x002,
685 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
686 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
687 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
688 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
689 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
690 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
691 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
692 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
693 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
694 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
695 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
696 AMDGPU_DOORBELL_IH = 0x1E8,
697 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
698 AMDGPU_DOORBELL_INVALID = 0xFFFF
699 } AMDGPU_DOORBELL_ASSIGNMENT;
700
701 struct amdgpu_doorbell {
702 /* doorbell mmio */
703 resource_size_t base;
704 resource_size_t size;
705 u32 __iomem *ptr;
706 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
707 };
708
709 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
710 phys_addr_t *aperture_base,
711 size_t *aperture_size,
712 size_t *start_offset);
713
714 /*
715 * IRQS.
716 */
717
718 struct amdgpu_flip_work {
719 struct work_struct flip_work;
720 struct work_struct unpin_work;
721 struct amdgpu_device *adev;
722 int crtc_id;
723 uint64_t base;
724 struct drm_pending_vblank_event *event;
725 struct amdgpu_bo *old_rbo;
726 struct fence *excl;
727 unsigned shared_count;
728 struct fence **shared;
729 struct fence_cb cb;
730 bool async;
731 };
732
733
734 /*
735 * CP & rings.
736 */
737
738 struct amdgpu_ib {
739 struct amdgpu_sa_bo *sa_bo;
740 uint32_t length_dw;
741 uint64_t gpu_addr;
742 uint32_t *ptr;
743 struct amdgpu_user_fence *user;
744 unsigned vm_id;
745 uint64_t vm_pd_addr;
746 uint32_t gds_base, gds_size;
747 uint32_t gws_base, gws_size;
748 uint32_t oa_base, oa_size;
749 uint32_t flags;
750 /* resulting sequence number */
751 uint64_t sequence;
752 };
753
754 enum amdgpu_ring_type {
755 AMDGPU_RING_TYPE_GFX,
756 AMDGPU_RING_TYPE_COMPUTE,
757 AMDGPU_RING_TYPE_SDMA,
758 AMDGPU_RING_TYPE_UVD,
759 AMDGPU_RING_TYPE_VCE
760 };
761
762 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
763
764 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
765 struct amdgpu_job **job, struct amdgpu_vm *vm);
766 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
767 struct amdgpu_job **job);
768
769 void amdgpu_job_free(struct amdgpu_job *job);
770 void amdgpu_job_free_func(struct kref *refcount);
771 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
772 struct amd_sched_entity *entity, void *owner,
773 struct fence **f);
774 void amdgpu_job_timeout_func(struct work_struct *work);
775
776 struct amdgpu_ring {
777 struct amdgpu_device *adev;
778 const struct amdgpu_ring_funcs *funcs;
779 struct amdgpu_fence_driver fence_drv;
780 struct amd_gpu_scheduler sched;
781
782 spinlock_t fence_lock;
783 struct amdgpu_bo *ring_obj;
784 volatile uint32_t *ring;
785 unsigned rptr_offs;
786 u64 next_rptr_gpu_addr;
787 volatile u32 *next_rptr_cpu_addr;
788 unsigned wptr;
789 unsigned wptr_old;
790 unsigned ring_size;
791 unsigned max_dw;
792 int count_dw;
793 uint64_t gpu_addr;
794 uint32_t align_mask;
795 uint32_t ptr_mask;
796 bool ready;
797 u32 nop;
798 u32 idx;
799 u32 me;
800 u32 pipe;
801 u32 queue;
802 struct amdgpu_bo *mqd_obj;
803 u32 doorbell_index;
804 bool use_doorbell;
805 unsigned wptr_offs;
806 unsigned next_rptr_offs;
807 unsigned fence_offs;
808 uint64_t current_ctx;
809 enum amdgpu_ring_type type;
810 char name[16];
811 unsigned cond_exe_offs;
812 u64 cond_exe_gpu_addr;
813 volatile u32 *cond_exe_cpu_addr;
814 };
815
816 /*
817 * VM
818 */
819
820 /* maximum number of VMIDs */
821 #define AMDGPU_NUM_VM 16
822
823 /* number of entries in page table */
824 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
825
826 /* PTBs (Page Table Blocks) need to be aligned to 32K */
827 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
828 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
829 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
830
831 #define AMDGPU_PTE_VALID (1 << 0)
832 #define AMDGPU_PTE_SYSTEM (1 << 1)
833 #define AMDGPU_PTE_SNOOPED (1 << 2)
834
835 /* VI only */
836 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
837
838 #define AMDGPU_PTE_READABLE (1 << 5)
839 #define AMDGPU_PTE_WRITEABLE (1 << 6)
840
841 /* PTE (Page Table Entry) fragment field for different page sizes */
842 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
843 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
844 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
845
846 /* How to programm VM fault handling */
847 #define AMDGPU_VM_FAULT_STOP_NEVER 0
848 #define AMDGPU_VM_FAULT_STOP_FIRST 1
849 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2
850
851 struct amdgpu_vm_pt {
852 struct amdgpu_bo_list_entry entry;
853 uint64_t addr;
854 };
855
856 struct amdgpu_vm {
857 /* tree of virtual addresses mapped */
858 struct rb_root va;
859
860 /* protecting invalidated */
861 spinlock_t status_lock;
862
863 /* BOs moved, but not yet updated in the PT */
864 struct list_head invalidated;
865
866 /* BOs cleared in the PT because of a move */
867 struct list_head cleared;
868
869 /* BO mappings freed, but not yet updated in the PT */
870 struct list_head freed;
871
872 /* contains the page directory */
873 struct amdgpu_bo *page_directory;
874 unsigned max_pde_used;
875 struct fence *page_directory_fence;
876
877 /* array of page tables, one for each page directory entry */
878 struct amdgpu_vm_pt *page_tables;
879
880 /* for id and flush management per ring */
881 struct amdgpu_vm_id *ids[AMDGPU_MAX_RINGS];
882
883 /* protecting freed */
884 spinlock_t freed_lock;
885
886 /* Scheduler entity for page table updates */
887 struct amd_sched_entity entity;
888
889 /* client id */
890 u64 client_id;
891 };
892
893 struct amdgpu_vm_id {
894 struct list_head list;
895 struct fence *first;
896 struct amdgpu_sync active;
897 struct fence *last_flush;
898 struct amdgpu_ring *last_user;
899 atomic64_t owner;
900
901 uint64_t pd_gpu_addr;
902 /* last flushed PD/PT update */
903 struct fence *flushed_updates;
904
905 uint32_t gds_base;
906 uint32_t gds_size;
907 uint32_t gws_base;
908 uint32_t gws_size;
909 uint32_t oa_base;
910 uint32_t oa_size;
911 };
912
913 struct amdgpu_vm_manager {
914 /* Handling of VMIDs */
915 struct mutex lock;
916 unsigned num_ids;
917 struct list_head ids_lru;
918 struct amdgpu_vm_id ids[AMDGPU_NUM_VM];
919
920 uint32_t max_pfn;
921 /* vram base address for page table entry */
922 u64 vram_base_offset;
923 /* is vm enabled? */
924 bool enabled;
925 /* vm pte handling */
926 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
927 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];
928 unsigned vm_pte_num_rings;
929 atomic_t vm_pte_next_ring;
930 /* client id counter */
931 atomic64_t client_counter;
932 };
933
934 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
935 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
936 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
937 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
938 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
939 struct list_head *validated,
940 struct amdgpu_bo_list_entry *entry);
941 void amdgpu_vm_get_pt_bos(struct amdgpu_vm *vm, struct list_head *duplicates);
942 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev,
943 struct amdgpu_vm *vm);
944 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
945 struct amdgpu_sync *sync, struct fence *fence,
946 unsigned *vm_id, uint64_t *vm_pd_addr);
947 int amdgpu_vm_flush(struct amdgpu_ring *ring,
948 unsigned vm_id, uint64_t pd_addr,
949 uint32_t gds_base, uint32_t gds_size,
950 uint32_t gws_base, uint32_t gws_size,
951 uint32_t oa_base, uint32_t oa_size);
952 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vm_id);
953 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
954 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
955 struct amdgpu_vm *vm);
956 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
957 struct amdgpu_vm *vm);
958 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm,
959 struct amdgpu_sync *sync);
960 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
961 struct amdgpu_bo_va *bo_va,
962 struct ttm_mem_reg *mem);
963 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
964 struct amdgpu_bo *bo);
965 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
966 struct amdgpu_bo *bo);
967 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
968 struct amdgpu_vm *vm,
969 struct amdgpu_bo *bo);
970 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
971 struct amdgpu_bo_va *bo_va,
972 uint64_t addr, uint64_t offset,
973 uint64_t size, uint32_t flags);
974 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
975 struct amdgpu_bo_va *bo_va,
976 uint64_t addr);
977 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
978 struct amdgpu_bo_va *bo_va);
979
980 /*
981 * context related structures
982 */
983
984 struct amdgpu_ctx_ring {
985 uint64_t sequence;
986 struct fence **fences;
987 struct amd_sched_entity entity;
988 };
989
990 struct amdgpu_ctx {
991 struct kref refcount;
992 struct amdgpu_device *adev;
993 unsigned reset_counter;
994 spinlock_t ring_lock;
995 struct fence **fences;
996 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
997 };
998
999 struct amdgpu_ctx_mgr {
1000 struct amdgpu_device *adev;
1001 struct mutex lock;
1002 /* protected by lock */
1003 struct idr ctx_handles;
1004 };
1005
1006 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1007 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1008
1009 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1010 struct fence *fence);
1011 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1012 struct amdgpu_ring *ring, uint64_t seq);
1013
1014 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1015 struct drm_file *filp);
1016
1017 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
1018 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
1019
1020 /*
1021 * file private structure
1022 */
1023
1024 struct amdgpu_fpriv {
1025 struct amdgpu_vm vm;
1026 struct mutex bo_list_lock;
1027 struct idr bo_list_handles;
1028 struct amdgpu_ctx_mgr ctx_mgr;
1029 };
1030
1031 /*
1032 * residency list
1033 */
1034
1035 struct amdgpu_bo_list {
1036 struct mutex lock;
1037 struct amdgpu_bo *gds_obj;
1038 struct amdgpu_bo *gws_obj;
1039 struct amdgpu_bo *oa_obj;
1040 unsigned first_userptr;
1041 unsigned num_entries;
1042 struct amdgpu_bo_list_entry *array;
1043 };
1044
1045 struct amdgpu_bo_list *
1046 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1047 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
1048 struct list_head *validated);
1049 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1050 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1051
1052 /*
1053 * GFX stuff
1054 */
1055 #include "clearstate_defs.h"
1056
1057 struct amdgpu_rlc_funcs {
1058 void (*enter_safe_mode)(struct amdgpu_device *adev);
1059 void (*exit_safe_mode)(struct amdgpu_device *adev);
1060 };
1061
1062 struct amdgpu_rlc {
1063 /* for power gating */
1064 struct amdgpu_bo *save_restore_obj;
1065 uint64_t save_restore_gpu_addr;
1066 volatile uint32_t *sr_ptr;
1067 const u32 *reg_list;
1068 u32 reg_list_size;
1069 /* for clear state */
1070 struct amdgpu_bo *clear_state_obj;
1071 uint64_t clear_state_gpu_addr;
1072 volatile uint32_t *cs_ptr;
1073 const struct cs_section_def *cs_data;
1074 u32 clear_state_size;
1075 /* for cp tables */
1076 struct amdgpu_bo *cp_table_obj;
1077 uint64_t cp_table_gpu_addr;
1078 volatile uint32_t *cp_table_ptr;
1079 u32 cp_table_size;
1080
1081 /* safe mode for updating CG/PG state */
1082 bool in_safe_mode;
1083 const struct amdgpu_rlc_funcs *funcs;
1084
1085 /* for firmware data */
1086 u32 save_and_restore_offset;
1087 u32 clear_state_descriptor_offset;
1088 u32 avail_scratch_ram_locations;
1089 u32 reg_restore_list_size;
1090 u32 reg_list_format_start;
1091 u32 reg_list_format_separate_start;
1092 u32 starting_offsets_start;
1093 u32 reg_list_format_size_bytes;
1094 u32 reg_list_size_bytes;
1095
1096 u32 *register_list_format;
1097 u32 *register_restore;
1098 };
1099
1100 struct amdgpu_mec {
1101 struct amdgpu_bo *hpd_eop_obj;
1102 u64 hpd_eop_gpu_addr;
1103 u32 num_pipe;
1104 u32 num_mec;
1105 u32 num_queue;
1106 };
1107
1108 /*
1109 * GPU scratch registers structures, functions & helpers
1110 */
1111 struct amdgpu_scratch {
1112 unsigned num_reg;
1113 uint32_t reg_base;
1114 bool free[32];
1115 uint32_t reg[32];
1116 };
1117
1118 /*
1119 * GFX configurations
1120 */
1121 struct amdgpu_gca_config {
1122 unsigned max_shader_engines;
1123 unsigned max_tile_pipes;
1124 unsigned max_cu_per_sh;
1125 unsigned max_sh_per_se;
1126 unsigned max_backends_per_se;
1127 unsigned max_texture_channel_caches;
1128 unsigned max_gprs;
1129 unsigned max_gs_threads;
1130 unsigned max_hw_contexts;
1131 unsigned sc_prim_fifo_size_frontend;
1132 unsigned sc_prim_fifo_size_backend;
1133 unsigned sc_hiz_tile_fifo_size;
1134 unsigned sc_earlyz_tile_fifo_size;
1135
1136 unsigned num_tile_pipes;
1137 unsigned backend_enable_mask;
1138 unsigned mem_max_burst_length_bytes;
1139 unsigned mem_row_size_in_kb;
1140 unsigned shader_engine_tile_size;
1141 unsigned num_gpus;
1142 unsigned multi_gpu_tile_size;
1143 unsigned mc_arb_ramcfg;
1144 unsigned gb_addr_config;
1145 unsigned num_rbs;
1146
1147 uint32_t tile_mode_array[32];
1148 uint32_t macrotile_mode_array[16];
1149 };
1150
1151 struct amdgpu_cu_info {
1152 uint32_t number; /* total active CU number */
1153 uint32_t ao_cu_mask;
1154 uint32_t bitmap[4][4];
1155 };
1156
1157 struct amdgpu_gfx {
1158 struct mutex gpu_clock_mutex;
1159 struct amdgpu_gca_config config;
1160 struct amdgpu_rlc rlc;
1161 struct amdgpu_mec mec;
1162 struct amdgpu_scratch scratch;
1163 const struct firmware *me_fw; /* ME firmware */
1164 uint32_t me_fw_version;
1165 const struct firmware *pfp_fw; /* PFP firmware */
1166 uint32_t pfp_fw_version;
1167 const struct firmware *ce_fw; /* CE firmware */
1168 uint32_t ce_fw_version;
1169 const struct firmware *rlc_fw; /* RLC firmware */
1170 uint32_t rlc_fw_version;
1171 const struct firmware *mec_fw; /* MEC firmware */
1172 uint32_t mec_fw_version;
1173 const struct firmware *mec2_fw; /* MEC2 firmware */
1174 uint32_t mec2_fw_version;
1175 uint32_t me_feature_version;
1176 uint32_t ce_feature_version;
1177 uint32_t pfp_feature_version;
1178 uint32_t rlc_feature_version;
1179 uint32_t mec_feature_version;
1180 uint32_t mec2_feature_version;
1181 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1182 unsigned num_gfx_rings;
1183 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1184 unsigned num_compute_rings;
1185 struct amdgpu_irq_src eop_irq;
1186 struct amdgpu_irq_src priv_reg_irq;
1187 struct amdgpu_irq_src priv_inst_irq;
1188 /* gfx status */
1189 uint32_t gfx_current_status;
1190 /* ce ram size*/
1191 unsigned ce_ram_size;
1192 struct amdgpu_cu_info cu_info;
1193 };
1194
1195 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1196 unsigned size, struct amdgpu_ib *ib);
1197 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1198 struct fence *f);
1199 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1200 struct amdgpu_ib *ib, struct fence *last_vm_update,
1201 struct amdgpu_job *job, struct fence **f);
1202 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1203 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1204 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1205 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1206 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
1207 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
1208 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1209 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1210 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1211 uint32_t **data);
1212 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1213 unsigned size, uint32_t *data);
1214 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1215 unsigned ring_size, u32 nop, u32 align_mask,
1216 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1217 enum amdgpu_ring_type ring_type);
1218 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1219
1220 /*
1221 * CS.
1222 */
1223 struct amdgpu_cs_chunk {
1224 uint32_t chunk_id;
1225 uint32_t length_dw;
1226 uint32_t *kdata;
1227 };
1228
1229 struct amdgpu_cs_parser {
1230 struct amdgpu_device *adev;
1231 struct drm_file *filp;
1232 struct amdgpu_ctx *ctx;
1233
1234 /* chunks */
1235 unsigned nchunks;
1236 struct amdgpu_cs_chunk *chunks;
1237
1238 /* scheduler job object */
1239 struct amdgpu_job *job;
1240
1241 /* buffer objects */
1242 struct ww_acquire_ctx ticket;
1243 struct amdgpu_bo_list *bo_list;
1244 struct amdgpu_bo_list_entry vm_pd;
1245 struct list_head validated;
1246 struct fence *fence;
1247 uint64_t bytes_moved_threshold;
1248 uint64_t bytes_moved;
1249
1250 /* user fence */
1251 struct amdgpu_bo_list_entry uf_entry;
1252 };
1253
1254 struct amdgpu_job {
1255 struct amd_sched_job base;
1256 struct amdgpu_device *adev;
1257 struct amdgpu_vm *vm;
1258 struct amdgpu_ring *ring;
1259 struct amdgpu_sync sync;
1260 struct amdgpu_ib *ibs;
1261 struct fence *fence; /* the hw fence */
1262 uint32_t num_ibs;
1263 void *owner;
1264 uint64_t ctx;
1265 struct amdgpu_user_fence uf;
1266 };
1267 #define to_amdgpu_job(sched_job) \
1268 container_of((sched_job), struct amdgpu_job, base)
1269
1270 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1271 uint32_t ib_idx, int idx)
1272 {
1273 return p->job->ibs[ib_idx].ptr[idx];
1274 }
1275
1276 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1277 uint32_t ib_idx, int idx,
1278 uint32_t value)
1279 {
1280 p->job->ibs[ib_idx].ptr[idx] = value;
1281 }
1282
1283 /*
1284 * Writeback
1285 */
1286 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1287
1288 struct amdgpu_wb {
1289 struct amdgpu_bo *wb_obj;
1290 volatile uint32_t *wb;
1291 uint64_t gpu_addr;
1292 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1293 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1294 };
1295
1296 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1297 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1298
1299
1300
1301 enum amdgpu_int_thermal_type {
1302 THERMAL_TYPE_NONE,
1303 THERMAL_TYPE_EXTERNAL,
1304 THERMAL_TYPE_EXTERNAL_GPIO,
1305 THERMAL_TYPE_RV6XX,
1306 THERMAL_TYPE_RV770,
1307 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1308 THERMAL_TYPE_EVERGREEN,
1309 THERMAL_TYPE_SUMO,
1310 THERMAL_TYPE_NI,
1311 THERMAL_TYPE_SI,
1312 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1313 THERMAL_TYPE_CI,
1314 THERMAL_TYPE_KV,
1315 };
1316
1317 enum amdgpu_dpm_auto_throttle_src {
1318 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1319 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1320 };
1321
1322 enum amdgpu_dpm_event_src {
1323 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1324 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1325 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1326 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1327 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1328 };
1329
1330 #define AMDGPU_MAX_VCE_LEVELS 6
1331
1332 enum amdgpu_vce_level {
1333 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1334 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1335 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1336 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1337 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1338 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1339 };
1340
1341 struct amdgpu_ps {
1342 u32 caps; /* vbios flags */
1343 u32 class; /* vbios flags */
1344 u32 class2; /* vbios flags */
1345 /* UVD clocks */
1346 u32 vclk;
1347 u32 dclk;
1348 /* VCE clocks */
1349 u32 evclk;
1350 u32 ecclk;
1351 bool vce_active;
1352 enum amdgpu_vce_level vce_level;
1353 /* asic priv */
1354 void *ps_priv;
1355 };
1356
1357 struct amdgpu_dpm_thermal {
1358 /* thermal interrupt work */
1359 struct work_struct work;
1360 /* low temperature threshold */
1361 int min_temp;
1362 /* high temperature threshold */
1363 int max_temp;
1364 /* was last interrupt low to high or high to low */
1365 bool high_to_low;
1366 /* interrupt source */
1367 struct amdgpu_irq_src irq;
1368 };
1369
1370 enum amdgpu_clk_action
1371 {
1372 AMDGPU_SCLK_UP = 1,
1373 AMDGPU_SCLK_DOWN
1374 };
1375
1376 struct amdgpu_blacklist_clocks
1377 {
1378 u32 sclk;
1379 u32 mclk;
1380 enum amdgpu_clk_action action;
1381 };
1382
1383 struct amdgpu_clock_and_voltage_limits {
1384 u32 sclk;
1385 u32 mclk;
1386 u16 vddc;
1387 u16 vddci;
1388 };
1389
1390 struct amdgpu_clock_array {
1391 u32 count;
1392 u32 *values;
1393 };
1394
1395 struct amdgpu_clock_voltage_dependency_entry {
1396 u32 clk;
1397 u16 v;
1398 };
1399
1400 struct amdgpu_clock_voltage_dependency_table {
1401 u32 count;
1402 struct amdgpu_clock_voltage_dependency_entry *entries;
1403 };
1404
1405 union amdgpu_cac_leakage_entry {
1406 struct {
1407 u16 vddc;
1408 u32 leakage;
1409 };
1410 struct {
1411 u16 vddc1;
1412 u16 vddc2;
1413 u16 vddc3;
1414 };
1415 };
1416
1417 struct amdgpu_cac_leakage_table {
1418 u32 count;
1419 union amdgpu_cac_leakage_entry *entries;
1420 };
1421
1422 struct amdgpu_phase_shedding_limits_entry {
1423 u16 voltage;
1424 u32 sclk;
1425 u32 mclk;
1426 };
1427
1428 struct amdgpu_phase_shedding_limits_table {
1429 u32 count;
1430 struct amdgpu_phase_shedding_limits_entry *entries;
1431 };
1432
1433 struct amdgpu_uvd_clock_voltage_dependency_entry {
1434 u32 vclk;
1435 u32 dclk;
1436 u16 v;
1437 };
1438
1439 struct amdgpu_uvd_clock_voltage_dependency_table {
1440 u8 count;
1441 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1442 };
1443
1444 struct amdgpu_vce_clock_voltage_dependency_entry {
1445 u32 ecclk;
1446 u32 evclk;
1447 u16 v;
1448 };
1449
1450 struct amdgpu_vce_clock_voltage_dependency_table {
1451 u8 count;
1452 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1453 };
1454
1455 struct amdgpu_ppm_table {
1456 u8 ppm_design;
1457 u16 cpu_core_number;
1458 u32 platform_tdp;
1459 u32 small_ac_platform_tdp;
1460 u32 platform_tdc;
1461 u32 small_ac_platform_tdc;
1462 u32 apu_tdp;
1463 u32 dgpu_tdp;
1464 u32 dgpu_ulv_power;
1465 u32 tj_max;
1466 };
1467
1468 struct amdgpu_cac_tdp_table {
1469 u16 tdp;
1470 u16 configurable_tdp;
1471 u16 tdc;
1472 u16 battery_power_limit;
1473 u16 small_power_limit;
1474 u16 low_cac_leakage;
1475 u16 high_cac_leakage;
1476 u16 maximum_power_delivery_limit;
1477 };
1478
1479 struct amdgpu_dpm_dynamic_state {
1480 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1481 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1482 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1483 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1484 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1485 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1486 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1487 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1488 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1489 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1490 struct amdgpu_clock_array valid_sclk_values;
1491 struct amdgpu_clock_array valid_mclk_values;
1492 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1493 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1494 u32 mclk_sclk_ratio;
1495 u32 sclk_mclk_delta;
1496 u16 vddc_vddci_delta;
1497 u16 min_vddc_for_pcie_gen2;
1498 struct amdgpu_cac_leakage_table cac_leakage_table;
1499 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1500 struct amdgpu_ppm_table *ppm_table;
1501 struct amdgpu_cac_tdp_table *cac_tdp_table;
1502 };
1503
1504 struct amdgpu_dpm_fan {
1505 u16 t_min;
1506 u16 t_med;
1507 u16 t_high;
1508 u16 pwm_min;
1509 u16 pwm_med;
1510 u16 pwm_high;
1511 u8 t_hyst;
1512 u32 cycle_delay;
1513 u16 t_max;
1514 u8 control_mode;
1515 u16 default_max_fan_pwm;
1516 u16 default_fan_output_sensitivity;
1517 u16 fan_output_sensitivity;
1518 bool ucode_fan_control;
1519 };
1520
1521 enum amdgpu_pcie_gen {
1522 AMDGPU_PCIE_GEN1 = 0,
1523 AMDGPU_PCIE_GEN2 = 1,
1524 AMDGPU_PCIE_GEN3 = 2,
1525 AMDGPU_PCIE_GEN_INVALID = 0xffff
1526 };
1527
1528 enum amdgpu_dpm_forced_level {
1529 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1530 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1531 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1532 AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
1533 };
1534
1535 struct amdgpu_vce_state {
1536 /* vce clocks */
1537 u32 evclk;
1538 u32 ecclk;
1539 /* gpu clocks */
1540 u32 sclk;
1541 u32 mclk;
1542 u8 clk_idx;
1543 u8 pstate;
1544 };
1545
1546 struct amdgpu_dpm_funcs {
1547 int (*get_temperature)(struct amdgpu_device *adev);
1548 int (*pre_set_power_state)(struct amdgpu_device *adev);
1549 int (*set_power_state)(struct amdgpu_device *adev);
1550 void (*post_set_power_state)(struct amdgpu_device *adev);
1551 void (*display_configuration_changed)(struct amdgpu_device *adev);
1552 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1553 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1554 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1555 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1556 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1557 bool (*vblank_too_short)(struct amdgpu_device *adev);
1558 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1559 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1560 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1561 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1562 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1563 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1564 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1565 };
1566
1567 struct amdgpu_dpm {
1568 struct amdgpu_ps *ps;
1569 /* number of valid power states */
1570 int num_ps;
1571 /* current power state that is active */
1572 struct amdgpu_ps *current_ps;
1573 /* requested power state */
1574 struct amdgpu_ps *requested_ps;
1575 /* boot up power state */
1576 struct amdgpu_ps *boot_ps;
1577 /* default uvd power state */
1578 struct amdgpu_ps *uvd_ps;
1579 /* vce requirements */
1580 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1581 enum amdgpu_vce_level vce_level;
1582 enum amd_pm_state_type state;
1583 enum amd_pm_state_type user_state;
1584 u32 platform_caps;
1585 u32 voltage_response_time;
1586 u32 backbias_response_time;
1587 void *priv;
1588 u32 new_active_crtcs;
1589 int new_active_crtc_count;
1590 u32 current_active_crtcs;
1591 int current_active_crtc_count;
1592 struct amdgpu_dpm_dynamic_state dyn_state;
1593 struct amdgpu_dpm_fan fan;
1594 u32 tdp_limit;
1595 u32 near_tdp_limit;
1596 u32 near_tdp_limit_adjusted;
1597 u32 sq_ramping_threshold;
1598 u32 cac_leakage;
1599 u16 tdp_od_limit;
1600 u32 tdp_adjustment;
1601 u16 load_line_slope;
1602 bool power_control;
1603 bool ac_power;
1604 /* special states active */
1605 bool thermal_active;
1606 bool uvd_active;
1607 bool vce_active;
1608 /* thermal handling */
1609 struct amdgpu_dpm_thermal thermal;
1610 /* forced levels */
1611 enum amdgpu_dpm_forced_level forced_level;
1612 };
1613
1614 struct amdgpu_pm {
1615 struct mutex mutex;
1616 u32 current_sclk;
1617 u32 current_mclk;
1618 u32 default_sclk;
1619 u32 default_mclk;
1620 struct amdgpu_i2c_chan *i2c_bus;
1621 /* internal thermal controller on rv6xx+ */
1622 enum amdgpu_int_thermal_type int_thermal_type;
1623 struct device *int_hwmon_dev;
1624 /* fan control parameters */
1625 bool no_fan;
1626 u8 fan_pulses_per_revolution;
1627 u8 fan_min_rpm;
1628 u8 fan_max_rpm;
1629 /* dpm */
1630 bool dpm_enabled;
1631 bool sysfs_initialized;
1632 struct amdgpu_dpm dpm;
1633 const struct firmware *fw; /* SMC firmware */
1634 uint32_t fw_version;
1635 const struct amdgpu_dpm_funcs *funcs;
1636 uint32_t pcie_gen_mask;
1637 uint32_t pcie_mlw_mask;
1638 struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
1639 };
1640
1641 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1642
1643 /*
1644 * UVD
1645 */
1646 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1647 #define AMDGPU_MAX_UVD_HANDLES 40
1648 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1649 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1650 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1651 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1652
1653 struct amdgpu_uvd {
1654 struct amdgpu_bo *vcpu_bo;
1655 void *cpu_addr;
1656 uint64_t gpu_addr;
1657 unsigned fw_version;
1658 void *saved_bo;
1659 unsigned max_handles;
1660 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1661 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1662 struct delayed_work idle_work;
1663 const struct firmware *fw; /* UVD firmware */
1664 struct amdgpu_ring ring;
1665 struct amdgpu_irq_src irq;
1666 bool address_64_bit;
1667 struct amd_sched_entity entity;
1668 };
1669
1670 /*
1671 * VCE
1672 */
1673 #define AMDGPU_MAX_VCE_HANDLES 16
1674 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1675
1676 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1677 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1678
1679 struct amdgpu_vce {
1680 struct amdgpu_bo *vcpu_bo;
1681 uint64_t gpu_addr;
1682 unsigned fw_version;
1683 unsigned fb_version;
1684 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1685 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1686 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1687 struct delayed_work idle_work;
1688 const struct firmware *fw; /* VCE firmware */
1689 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1690 struct amdgpu_irq_src irq;
1691 unsigned harvest_config;
1692 struct amd_sched_entity entity;
1693 };
1694
1695 /*
1696 * SDMA
1697 */
1698 struct amdgpu_sdma_instance {
1699 /* SDMA firmware */
1700 const struct firmware *fw;
1701 uint32_t fw_version;
1702 uint32_t feature_version;
1703
1704 struct amdgpu_ring ring;
1705 bool burst_nop;
1706 };
1707
1708 struct amdgpu_sdma {
1709 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1710 struct amdgpu_irq_src trap_irq;
1711 struct amdgpu_irq_src illegal_inst_irq;
1712 int num_instances;
1713 };
1714
1715 /*
1716 * Firmware
1717 */
1718 struct amdgpu_firmware {
1719 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1720 bool smu_load;
1721 struct amdgpu_bo *fw_buf;
1722 unsigned int fw_size;
1723 };
1724
1725 /*
1726 * Benchmarking
1727 */
1728 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1729
1730
1731 /*
1732 * Testing
1733 */
1734 void amdgpu_test_moves(struct amdgpu_device *adev);
1735 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1736 struct amdgpu_ring *cpA,
1737 struct amdgpu_ring *cpB);
1738 void amdgpu_test_syncing(struct amdgpu_device *adev);
1739
1740 /*
1741 * MMU Notifier
1742 */
1743 #if defined(CONFIG_MMU_NOTIFIER)
1744 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1745 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1746 #else
1747 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1748 {
1749 return -ENODEV;
1750 }
1751 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1752 #endif
1753
1754 /*
1755 * Debugfs
1756 */
1757 struct amdgpu_debugfs {
1758 const struct drm_info_list *files;
1759 unsigned num_files;
1760 };
1761
1762 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1763 const struct drm_info_list *files,
1764 unsigned nfiles);
1765 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1766
1767 #if defined(CONFIG_DEBUG_FS)
1768 int amdgpu_debugfs_init(struct drm_minor *minor);
1769 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1770 #endif
1771
1772 /*
1773 * amdgpu smumgr functions
1774 */
1775 struct amdgpu_smumgr_funcs {
1776 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1777 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1778 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1779 };
1780
1781 /*
1782 * amdgpu smumgr
1783 */
1784 struct amdgpu_smumgr {
1785 struct amdgpu_bo *toc_buf;
1786 struct amdgpu_bo *smu_buf;
1787 /* asic priv smu data */
1788 void *priv;
1789 spinlock_t smu_lock;
1790 /* smumgr functions */
1791 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1792 /* ucode loading complete flag */
1793 uint32_t fw_flags;
1794 };
1795
1796 /*
1797 * ASIC specific register table accessible by UMD
1798 */
1799 struct amdgpu_allowed_register_entry {
1800 uint32_t reg_offset;
1801 bool untouched;
1802 bool grbm_indexed;
1803 };
1804
1805 /*
1806 * ASIC specific functions.
1807 */
1808 struct amdgpu_asic_funcs {
1809 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1810 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1811 u8 *bios, u32 length_bytes);
1812 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1813 u32 sh_num, u32 reg_offset, u32 *value);
1814 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1815 int (*reset)(struct amdgpu_device *adev);
1816 /* wait for mc_idle */
1817 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1818 /* get the reference clock */
1819 u32 (*get_xclk)(struct amdgpu_device *adev);
1820 /* get the gpu clock counter */
1821 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1822 /* MM block clocks */
1823 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1824 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1825 };
1826
1827 /*
1828 * IOCTL.
1829 */
1830 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1831 struct drm_file *filp);
1832 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1833 struct drm_file *filp);
1834
1835 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1836 struct drm_file *filp);
1837 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1838 struct drm_file *filp);
1839 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1840 struct drm_file *filp);
1841 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1842 struct drm_file *filp);
1843 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1844 struct drm_file *filp);
1845 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1846 struct drm_file *filp);
1847 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1848 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1849
1850 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1851 struct drm_file *filp);
1852
1853 /* VRAM scratch page for HDP bug, default vram page */
1854 struct amdgpu_vram_scratch {
1855 struct amdgpu_bo *robj;
1856 volatile uint32_t *ptr;
1857 u64 gpu_addr;
1858 };
1859
1860 /*
1861 * ACPI
1862 */
1863 struct amdgpu_atif_notification_cfg {
1864 bool enabled;
1865 int command_code;
1866 };
1867
1868 struct amdgpu_atif_notifications {
1869 bool display_switch;
1870 bool expansion_mode_change;
1871 bool thermal_state;
1872 bool forced_power_state;
1873 bool system_power_state;
1874 bool display_conf_change;
1875 bool px_gfx_switch;
1876 bool brightness_change;
1877 bool dgpu_display_event;
1878 };
1879
1880 struct amdgpu_atif_functions {
1881 bool system_params;
1882 bool sbios_requests;
1883 bool select_active_disp;
1884 bool lid_state;
1885 bool get_tv_standard;
1886 bool set_tv_standard;
1887 bool get_panel_expansion_mode;
1888 bool set_panel_expansion_mode;
1889 bool temperature_change;
1890 bool graphics_device_types;
1891 };
1892
1893 struct amdgpu_atif {
1894 struct amdgpu_atif_notifications notifications;
1895 struct amdgpu_atif_functions functions;
1896 struct amdgpu_atif_notification_cfg notification_cfg;
1897 struct amdgpu_encoder *encoder_for_bl;
1898 };
1899
1900 struct amdgpu_atcs_functions {
1901 bool get_ext_state;
1902 bool pcie_perf_req;
1903 bool pcie_dev_rdy;
1904 bool pcie_bus_width;
1905 };
1906
1907 struct amdgpu_atcs {
1908 struct amdgpu_atcs_functions functions;
1909 };
1910
1911 /*
1912 * CGS
1913 */
1914 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1915 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1916
1917
1918 /* GPU virtualization */
1919 struct amdgpu_virtualization {
1920 bool supports_sr_iov;
1921 };
1922
1923 /*
1924 * Core structure, functions and helpers.
1925 */
1926 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1927 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1928
1929 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1930 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1931
1932 struct amdgpu_ip_block_status {
1933 bool valid;
1934 bool sw;
1935 bool hw;
1936 };
1937
1938 struct amdgpu_device {
1939 struct device *dev;
1940 struct drm_device *ddev;
1941 struct pci_dev *pdev;
1942
1943 #ifdef CONFIG_DRM_AMD_ACP
1944 struct amdgpu_acp acp;
1945 #endif
1946
1947 /* ASIC */
1948 enum amd_asic_type asic_type;
1949 uint32_t family;
1950 uint32_t rev_id;
1951 uint32_t external_rev_id;
1952 unsigned long flags;
1953 int usec_timeout;
1954 const struct amdgpu_asic_funcs *asic_funcs;
1955 bool shutdown;
1956 bool need_dma32;
1957 bool accel_working;
1958 struct work_struct reset_work;
1959 struct notifier_block acpi_nb;
1960 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1961 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1962 unsigned debugfs_count;
1963 #if defined(CONFIG_DEBUG_FS)
1964 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1965 #endif
1966 struct amdgpu_atif atif;
1967 struct amdgpu_atcs atcs;
1968 struct mutex srbm_mutex;
1969 /* GRBM index mutex. Protects concurrent access to GRBM index */
1970 struct mutex grbm_idx_mutex;
1971 struct dev_pm_domain vga_pm_domain;
1972 bool have_disp_power_ref;
1973
1974 /* BIOS */
1975 uint8_t *bios;
1976 bool is_atom_bios;
1977 struct amdgpu_bo *stollen_vga_memory;
1978 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1979
1980 /* Register/doorbell mmio */
1981 resource_size_t rmmio_base;
1982 resource_size_t rmmio_size;
1983 void __iomem *rmmio;
1984 /* protects concurrent MM_INDEX/DATA based register access */
1985 spinlock_t mmio_idx_lock;
1986 /* protects concurrent SMC based register access */
1987 spinlock_t smc_idx_lock;
1988 amdgpu_rreg_t smc_rreg;
1989 amdgpu_wreg_t smc_wreg;
1990 /* protects concurrent PCIE register access */
1991 spinlock_t pcie_idx_lock;
1992 amdgpu_rreg_t pcie_rreg;
1993 amdgpu_wreg_t pcie_wreg;
1994 /* protects concurrent UVD register access */
1995 spinlock_t uvd_ctx_idx_lock;
1996 amdgpu_rreg_t uvd_ctx_rreg;
1997 amdgpu_wreg_t uvd_ctx_wreg;
1998 /* protects concurrent DIDT register access */
1999 spinlock_t didt_idx_lock;
2000 amdgpu_rreg_t didt_rreg;
2001 amdgpu_wreg_t didt_wreg;
2002 /* protects concurrent ENDPOINT (audio) register access */
2003 spinlock_t audio_endpt_idx_lock;
2004 amdgpu_block_rreg_t audio_endpt_rreg;
2005 amdgpu_block_wreg_t audio_endpt_wreg;
2006 void __iomem *rio_mem;
2007 resource_size_t rio_mem_size;
2008 struct amdgpu_doorbell doorbell;
2009
2010 /* clock/pll info */
2011 struct amdgpu_clock clock;
2012
2013 /* MC */
2014 struct amdgpu_mc mc;
2015 struct amdgpu_gart gart;
2016 struct amdgpu_dummy_page dummy_page;
2017 struct amdgpu_vm_manager vm_manager;
2018
2019 /* memory management */
2020 struct amdgpu_mman mman;
2021 struct amdgpu_vram_scratch vram_scratch;
2022 struct amdgpu_wb wb;
2023 atomic64_t vram_usage;
2024 atomic64_t vram_vis_usage;
2025 atomic64_t gtt_usage;
2026 atomic64_t num_bytes_moved;
2027 atomic_t gpu_reset_counter;
2028
2029 /* display */
2030 struct amdgpu_mode_info mode_info;
2031 struct work_struct hotplug_work;
2032 struct amdgpu_irq_src crtc_irq;
2033 struct amdgpu_irq_src pageflip_irq;
2034 struct amdgpu_irq_src hpd_irq;
2035
2036 /* rings */
2037 unsigned fence_context;
2038 unsigned num_rings;
2039 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2040 bool ib_pool_ready;
2041 struct amdgpu_sa_manager ring_tmp_bo;
2042
2043 /* interrupts */
2044 struct amdgpu_irq irq;
2045
2046 /* powerplay */
2047 struct amd_powerplay powerplay;
2048 bool pp_enabled;
2049 bool pp_force_state_enabled;
2050
2051 /* dpm */
2052 struct amdgpu_pm pm;
2053 u32 cg_flags;
2054 u32 pg_flags;
2055
2056 /* amdgpu smumgr */
2057 struct amdgpu_smumgr smu;
2058
2059 /* gfx */
2060 struct amdgpu_gfx gfx;
2061
2062 /* sdma */
2063 struct amdgpu_sdma sdma;
2064
2065 /* uvd */
2066 struct amdgpu_uvd uvd;
2067
2068 /* vce */
2069 struct amdgpu_vce vce;
2070
2071 /* firmwares */
2072 struct amdgpu_firmware firmware;
2073
2074 /* GDS */
2075 struct amdgpu_gds gds;
2076
2077 const struct amdgpu_ip_block_version *ip_blocks;
2078 int num_ip_blocks;
2079 struct amdgpu_ip_block_status *ip_block_status;
2080 struct mutex mn_lock;
2081 DECLARE_HASHTABLE(mn_hash, 7);
2082
2083 /* tracking pinned memory */
2084 u64 vram_pin_size;
2085 u64 invisible_pin_size;
2086 u64 gart_pin_size;
2087
2088 /* amdkfd interface */
2089 struct kfd_dev *kfd;
2090
2091 struct amdgpu_virtualization virtualization;
2092 };
2093
2094 bool amdgpu_device_is_px(struct drm_device *dev);
2095 int amdgpu_device_init(struct amdgpu_device *adev,
2096 struct drm_device *ddev,
2097 struct pci_dev *pdev,
2098 uint32_t flags);
2099 void amdgpu_device_fini(struct amdgpu_device *adev);
2100 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2101
2102 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2103 bool always_indirect);
2104 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2105 bool always_indirect);
2106 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2107 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2108
2109 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2110 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2111
2112 /*
2113 * Registers read & write functions.
2114 */
2115 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2116 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2117 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2118 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2119 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2120 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2121 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2122 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2123 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2124 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2125 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2126 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2127 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2128 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2129 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2130 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2131 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2132 #define WREG32_P(reg, val, mask) \
2133 do { \
2134 uint32_t tmp_ = RREG32(reg); \
2135 tmp_ &= (mask); \
2136 tmp_ |= ((val) & ~(mask)); \
2137 WREG32(reg, tmp_); \
2138 } while (0)
2139 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2140 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2141 #define WREG32_PLL_P(reg, val, mask) \
2142 do { \
2143 uint32_t tmp_ = RREG32_PLL(reg); \
2144 tmp_ &= (mask); \
2145 tmp_ |= ((val) & ~(mask)); \
2146 WREG32_PLL(reg, tmp_); \
2147 } while (0)
2148 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2149 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2150 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2151
2152 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2153 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2154
2155 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2156 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2157
2158 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2159 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2160 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2161
2162 #define REG_GET_FIELD(value, reg, field) \
2163 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2164
2165 /*
2166 * BIOS helpers.
2167 */
2168 #define RBIOS8(i) (adev->bios[i])
2169 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2170 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2171
2172 /*
2173 * RING helpers.
2174 */
2175 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2176 {
2177 if (ring->count_dw <= 0)
2178 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2179 ring->ring[ring->wptr++] = v;
2180 ring->wptr &= ring->ptr_mask;
2181 ring->count_dw--;
2182 }
2183
2184 static inline struct amdgpu_sdma_instance *
2185 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
2186 {
2187 struct amdgpu_device *adev = ring->adev;
2188 int i;
2189
2190 for (i = 0; i < adev->sdma.num_instances; i++)
2191 if (&adev->sdma.instance[i].ring == ring)
2192 break;
2193
2194 if (i < AMDGPU_MAX_SDMA_INSTANCES)
2195 return &adev->sdma.instance[i];
2196 else
2197 return NULL;
2198 }
2199
2200 /*
2201 * ASICs macro.
2202 */
2203 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2204 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2205 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2206 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2207 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2208 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2209 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2210 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2211 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
2212 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2213 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2214 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2215 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2216 #define amdgpu_vm_write_pte(adev, ib, pa, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pa), (pe), (addr), (count), (incr), (flags)))
2217 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2218 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2219 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2220 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2221 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2222 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2223 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2224 #define amdgpu_ring_emit_ib(r, ib, c) (r)->funcs->emit_ib((r), (ib), (c))
2225 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
2226 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2227 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2228 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2229 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2230 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
2231 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
2232 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
2233 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
2234 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2235 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2236 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2237 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2238 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2239 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2240 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2241 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2242 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2243 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2244 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2245 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2246 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2247 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
2248 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2249 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2250 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2251 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2252 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2253 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
2254 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
2255 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2256 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2257 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2258 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2259 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2260 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2261 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2262
2263 #define amdgpu_dpm_get_temperature(adev) \
2264 ((adev)->pp_enabled ? \
2265 (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
2266 (adev)->pm.funcs->get_temperature((adev)))
2267
2268 #define amdgpu_dpm_set_fan_control_mode(adev, m) \
2269 ((adev)->pp_enabled ? \
2270 (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
2271 (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
2272
2273 #define amdgpu_dpm_get_fan_control_mode(adev) \
2274 ((adev)->pp_enabled ? \
2275 (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
2276 (adev)->pm.funcs->get_fan_control_mode((adev)))
2277
2278 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
2279 ((adev)->pp_enabled ? \
2280 (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2281 (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
2282
2283 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
2284 ((adev)->pp_enabled ? \
2285 (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
2286 (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
2287
2288 #define amdgpu_dpm_get_sclk(adev, l) \
2289 ((adev)->pp_enabled ? \
2290 (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
2291 (adev)->pm.funcs->get_sclk((adev), (l)))
2292
2293 #define amdgpu_dpm_get_mclk(adev, l) \
2294 ((adev)->pp_enabled ? \
2295 (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
2296 (adev)->pm.funcs->get_mclk((adev), (l)))
2297
2298
2299 #define amdgpu_dpm_force_performance_level(adev, l) \
2300 ((adev)->pp_enabled ? \
2301 (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
2302 (adev)->pm.funcs->force_performance_level((adev), (l)))
2303
2304 #define amdgpu_dpm_powergate_uvd(adev, g) \
2305 ((adev)->pp_enabled ? \
2306 (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
2307 (adev)->pm.funcs->powergate_uvd((adev), (g)))
2308
2309 #define amdgpu_dpm_powergate_vce(adev, g) \
2310 ((adev)->pp_enabled ? \
2311 (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
2312 (adev)->pm.funcs->powergate_vce((adev), (g)))
2313
2314 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) \
2315 ((adev)->pp_enabled ? \
2316 (adev)->powerplay.pp_funcs->print_current_performance_level((adev)->powerplay.pp_handle, (m)) : \
2317 (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)))
2318
2319 #define amdgpu_dpm_get_current_power_state(adev) \
2320 (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
2321
2322 #define amdgpu_dpm_get_performance_level(adev) \
2323 (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
2324
2325 #define amdgpu_dpm_get_pp_num_states(adev, data) \
2326 (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
2327
2328 #define amdgpu_dpm_get_pp_table(adev, table) \
2329 (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
2330
2331 #define amdgpu_dpm_set_pp_table(adev, buf, size) \
2332 (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
2333
2334 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
2335 (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
2336
2337 #define amdgpu_dpm_force_clock_level(adev, type, level) \
2338 (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
2339
2340 #define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
2341 (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
2342
2343 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2344
2345 /* Common functions */
2346 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2347 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2348 bool amdgpu_card_posted(struct amdgpu_device *adev);
2349 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2350
2351 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2352 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2353 u32 ip_instance, u32 ring,
2354 struct amdgpu_ring **out_ring);
2355 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2356 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2357 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
2358 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2359 uint32_t flags);
2360 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2361 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
2362 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
2363 unsigned long end);
2364 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
2365 int *last_invalidated);
2366 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2367 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2368 struct ttm_mem_reg *mem);
2369 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2370 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2371 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2372 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2373 const u32 *registers,
2374 const u32 array_size);
2375
2376 bool amdgpu_device_is_px(struct drm_device *dev);
2377 /* atpx handler */
2378 #if defined(CONFIG_VGA_SWITCHEROO)
2379 void amdgpu_register_atpx_handler(void);
2380 void amdgpu_unregister_atpx_handler(void);
2381 #else
2382 static inline void amdgpu_register_atpx_handler(void) {}
2383 static inline void amdgpu_unregister_atpx_handler(void) {}
2384 #endif
2385
2386 /*
2387 * KMS
2388 */
2389 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2390 extern const int amdgpu_max_kms_ioctl;
2391
2392 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2393 int amdgpu_driver_unload_kms(struct drm_device *dev);
2394 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2395 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2396 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2397 struct drm_file *file_priv);
2398 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2399 struct drm_file *file_priv);
2400 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2401 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2402 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
2403 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2404 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
2405 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
2406 int *max_error,
2407 struct timeval *vblank_time,
2408 unsigned flags);
2409 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2410 unsigned long arg);
2411
2412 /*
2413 * functions used by amdgpu_encoder.c
2414 */
2415 struct amdgpu_afmt_acr {
2416 u32 clock;
2417
2418 int n_32khz;
2419 int cts_32khz;
2420
2421 int n_44_1khz;
2422 int cts_44_1khz;
2423
2424 int n_48khz;
2425 int cts_48khz;
2426
2427 };
2428
2429 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2430
2431 /* amdgpu_acpi.c */
2432 #if defined(CONFIG_ACPI)
2433 int amdgpu_acpi_init(struct amdgpu_device *adev);
2434 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2435 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2436 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2437 u8 perf_req, bool advertise);
2438 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2439 #else
2440 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2441 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2442 #endif
2443
2444 struct amdgpu_bo_va_mapping *
2445 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2446 uint64_t addr, struct amdgpu_bo **bo);
2447
2448 #include "amdgpu_object.h"
2449 #endif
Linux kernel - Deliverables
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