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drm/amdgpu: implement the allocation range (v3)
[deliverable/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_display.c
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include <drm/drmP.h>
27 #include <drm/amdgpu_drm.h>
28 #include "amdgpu.h"
29 #include "amdgpu_i2c.h"
30 #include "atom.h"
31 #include "amdgpu_connectors.h"
32 #include <asm/div64.h>
33
34 #include <linux/pm_runtime.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_edid.h>
37
38
39 static void amdgpu_flip_work_func(struct work_struct *__work)
40 {
41 struct amdgpu_flip_work *work =
42 container_of(__work, struct amdgpu_flip_work, flip_work);
43 struct amdgpu_device *adev = work->adev;
44 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id];
45
46 struct drm_crtc *crtc = &amdgpuCrtc->base;
47 struct amdgpu_fence *fence;
48 unsigned long flags;
49 int r;
50
51 down_read(&adev->exclusive_lock);
52 if (work->fence) {
53 fence = to_amdgpu_fence(work->fence);
54 if (fence) {
55 r = amdgpu_fence_wait(fence, false);
56 if (r == -EDEADLK) {
57 up_read(&adev->exclusive_lock);
58 r = amdgpu_gpu_reset(adev);
59 down_read(&adev->exclusive_lock);
60 }
61 } else
62 r = fence_wait(work->fence, false);
63
64 if (r)
65 DRM_ERROR("failed to wait on page flip fence (%d)!\n", r);
66
67 /* We continue with the page flip even if we failed to wait on
68 * the fence, otherwise the DRM core and userspace will be
69 * confused about which BO the CRTC is scanning out
70 */
71
72 fence_put(work->fence);
73 work->fence = NULL;
74 }
75
76 /* We borrow the event spin lock for protecting flip_status */
77 spin_lock_irqsave(&crtc->dev->event_lock, flags);
78
79 /* set the proper interrupt */
80 amdgpu_irq_get(adev, &adev->pageflip_irq, work->crtc_id);
81 /* do the flip (mmio) */
82 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base);
83 /* set the flip status */
84 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
85
86 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
87 up_read(&adev->exclusive_lock);
88 }
89
90 /*
91 * Handle unpin events outside the interrupt handler proper.
92 */
93 static void amdgpu_unpin_work_func(struct work_struct *__work)
94 {
95 struct amdgpu_flip_work *work =
96 container_of(__work, struct amdgpu_flip_work, unpin_work);
97 int r;
98
99 /* unpin of the old buffer */
100 r = amdgpu_bo_reserve(work->old_rbo, false);
101 if (likely(r == 0)) {
102 r = amdgpu_bo_unpin(work->old_rbo);
103 if (unlikely(r != 0)) {
104 DRM_ERROR("failed to unpin buffer after flip\n");
105 }
106 amdgpu_bo_unreserve(work->old_rbo);
107 } else
108 DRM_ERROR("failed to reserve buffer after flip\n");
109
110 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
111 kfree(work);
112 }
113
114 int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
115 struct drm_framebuffer *fb,
116 struct drm_pending_vblank_event *event,
117 uint32_t page_flip_flags)
118 {
119 struct drm_device *dev = crtc->dev;
120 struct amdgpu_device *adev = dev->dev_private;
121 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
122 struct amdgpu_framebuffer *old_amdgpu_fb;
123 struct amdgpu_framebuffer *new_amdgpu_fb;
124 struct drm_gem_object *obj;
125 struct amdgpu_flip_work *work;
126 struct amdgpu_bo *new_rbo;
127 unsigned long flags;
128 u64 tiling_flags;
129 u64 base;
130 int r;
131
132 work = kzalloc(sizeof *work, GFP_KERNEL);
133 if (work == NULL)
134 return -ENOMEM;
135
136 INIT_WORK(&work->flip_work, amdgpu_flip_work_func);
137 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func);
138
139 work->event = event;
140 work->adev = adev;
141 work->crtc_id = amdgpu_crtc->crtc_id;
142
143 /* schedule unpin of the old buffer */
144 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
145 obj = old_amdgpu_fb->obj;
146
147 /* take a reference to the old object */
148 drm_gem_object_reference(obj);
149 work->old_rbo = gem_to_amdgpu_bo(obj);
150
151 new_amdgpu_fb = to_amdgpu_framebuffer(fb);
152 obj = new_amdgpu_fb->obj;
153 new_rbo = gem_to_amdgpu_bo(obj);
154
155 /* pin the new buffer */
156 r = amdgpu_bo_reserve(new_rbo, false);
157 if (unlikely(r != 0)) {
158 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
159 goto cleanup;
160 }
161
162 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base);
163 if (unlikely(r != 0)) {
164 amdgpu_bo_unreserve(new_rbo);
165 r = -EINVAL;
166 DRM_ERROR("failed to pin new rbo buffer before flip\n");
167 goto cleanup;
168 }
169
170 work->fence = fence_get(reservation_object_get_excl(new_rbo->tbo.resv));
171 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags);
172 amdgpu_bo_unreserve(new_rbo);
173
174 work->base = base;
175
176 r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id);
177 if (r) {
178 DRM_ERROR("failed to get vblank before flip\n");
179 goto pflip_cleanup;
180 }
181
182 /* we borrow the event spin lock for protecting flip_wrok */
183 spin_lock_irqsave(&crtc->dev->event_lock, flags);
184 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) {
185 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
186 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
187 r = -EBUSY;
188 goto vblank_cleanup;
189 }
190
191 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING;
192 amdgpu_crtc->pflip_works = work;
193
194 /* update crtc fb */
195 crtc->primary->fb = fb;
196 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
197 queue_work(amdgpu_crtc->pflip_queue, &work->flip_work);
198 return 0;
199
200 vblank_cleanup:
201 drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id);
202
203 pflip_cleanup:
204 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) {
205 DRM_ERROR("failed to reserve new rbo in error path\n");
206 goto cleanup;
207 }
208 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) {
209 DRM_ERROR("failed to unpin new rbo in error path\n");
210 }
211 amdgpu_bo_unreserve(new_rbo);
212
213 cleanup:
214 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
215 fence_put(work->fence);
216 kfree(work);
217
218 return r;
219 }
220
221 int amdgpu_crtc_set_config(struct drm_mode_set *set)
222 {
223 struct drm_device *dev;
224 struct amdgpu_device *adev;
225 struct drm_crtc *crtc;
226 bool active = false;
227 int ret;
228
229 if (!set || !set->crtc)
230 return -EINVAL;
231
232 dev = set->crtc->dev;
233
234 ret = pm_runtime_get_sync(dev->dev);
235 if (ret < 0)
236 return ret;
237
238 ret = drm_crtc_helper_set_config(set);
239
240 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 if (crtc->enabled)
242 active = true;
243
244 pm_runtime_mark_last_busy(dev->dev);
245
246 adev = dev->dev_private;
247 /* if we have active crtcs and we don't have a power ref,
248 take the current one */
249 if (active && !adev->have_disp_power_ref) {
250 adev->have_disp_power_ref = true;
251 return ret;
252 }
253 /* if we have no active crtcs, then drop the power ref
254 we got before */
255 if (!active && adev->have_disp_power_ref) {
256 pm_runtime_put_autosuspend(dev->dev);
257 adev->have_disp_power_ref = false;
258 }
259
260 /* drop the power reference we got coming in here */
261 pm_runtime_put_autosuspend(dev->dev);
262 return ret;
263 }
264
265 static const char *encoder_names[38] = {
266 "NONE",
267 "INTERNAL_LVDS",
268 "INTERNAL_TMDS1",
269 "INTERNAL_TMDS2",
270 "INTERNAL_DAC1",
271 "INTERNAL_DAC2",
272 "INTERNAL_SDVOA",
273 "INTERNAL_SDVOB",
274 "SI170B",
275 "CH7303",
276 "CH7301",
277 "INTERNAL_DVO1",
278 "EXTERNAL_SDVOA",
279 "EXTERNAL_SDVOB",
280 "TITFP513",
281 "INTERNAL_LVTM1",
282 "VT1623",
283 "HDMI_SI1930",
284 "HDMI_INTERNAL",
285 "INTERNAL_KLDSCP_TMDS1",
286 "INTERNAL_KLDSCP_DVO1",
287 "INTERNAL_KLDSCP_DAC1",
288 "INTERNAL_KLDSCP_DAC2",
289 "SI178",
290 "MVPU_FPGA",
291 "INTERNAL_DDI",
292 "VT1625",
293 "HDMI_SI1932",
294 "DP_AN9801",
295 "DP_DP501",
296 "INTERNAL_UNIPHY",
297 "INTERNAL_KLDSCP_LVTMA",
298 "INTERNAL_UNIPHY1",
299 "INTERNAL_UNIPHY2",
300 "NUTMEG",
301 "TRAVIS",
302 "INTERNAL_VCE",
303 "INTERNAL_UNIPHY3",
304 };
305
306 static const char *hpd_names[6] = {
307 "HPD1",
308 "HPD2",
309 "HPD3",
310 "HPD4",
311 "HPD5",
312 "HPD6",
313 };
314
315 void amdgpu_print_display_setup(struct drm_device *dev)
316 {
317 struct drm_connector *connector;
318 struct amdgpu_connector *amdgpu_connector;
319 struct drm_encoder *encoder;
320 struct amdgpu_encoder *amdgpu_encoder;
321 uint32_t devices;
322 int i = 0;
323
324 DRM_INFO("AMDGPU Display Connectors\n");
325 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
326 amdgpu_connector = to_amdgpu_connector(connector);
327 DRM_INFO("Connector %d:\n", i);
328 DRM_INFO(" %s\n", connector->name);
329 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE)
330 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]);
331 if (amdgpu_connector->ddc_bus) {
332 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
333 amdgpu_connector->ddc_bus->rec.mask_clk_reg,
334 amdgpu_connector->ddc_bus->rec.mask_data_reg,
335 amdgpu_connector->ddc_bus->rec.a_clk_reg,
336 amdgpu_connector->ddc_bus->rec.a_data_reg,
337 amdgpu_connector->ddc_bus->rec.en_clk_reg,
338 amdgpu_connector->ddc_bus->rec.en_data_reg,
339 amdgpu_connector->ddc_bus->rec.y_clk_reg,
340 amdgpu_connector->ddc_bus->rec.y_data_reg);
341 if (amdgpu_connector->router.ddc_valid)
342 DRM_INFO(" DDC Router 0x%x/0x%x\n",
343 amdgpu_connector->router.ddc_mux_control_pin,
344 amdgpu_connector->router.ddc_mux_state);
345 if (amdgpu_connector->router.cd_valid)
346 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
347 amdgpu_connector->router.cd_mux_control_pin,
348 amdgpu_connector->router.cd_mux_state);
349 } else {
350 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
351 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
352 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
353 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
354 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
355 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
356 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
357 }
358 DRM_INFO(" Encoders:\n");
359 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
360 amdgpu_encoder = to_amdgpu_encoder(encoder);
361 devices = amdgpu_encoder->devices & amdgpu_connector->devices;
362 if (devices) {
363 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
364 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
365 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
366 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
367 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
368 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
369 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
370 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
371 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
372 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
373 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
374 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
375 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
376 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
377 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
378 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
379 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
380 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
381 if (devices & ATOM_DEVICE_TV1_SUPPORT)
382 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
383 if (devices & ATOM_DEVICE_CV_SUPPORT)
384 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]);
385 }
386 }
387 i++;
388 }
389 }
390
391 /**
392 * amdgpu_ddc_probe
393 *
394 */
395 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector,
396 bool use_aux)
397 {
398 u8 out = 0x0;
399 u8 buf[8];
400 int ret;
401 struct i2c_msg msgs[] = {
402 {
403 .addr = DDC_ADDR,
404 .flags = 0,
405 .len = 1,
406 .buf = &out,
407 },
408 {
409 .addr = DDC_ADDR,
410 .flags = I2C_M_RD,
411 .len = 8,
412 .buf = buf,
413 }
414 };
415
416 /* on hw with routers, select right port */
417 if (amdgpu_connector->router.ddc_valid)
418 amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
419
420 if (use_aux) {
421 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2);
422 } else {
423 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2);
424 }
425
426 if (ret != 2)
427 /* Couldn't find an accessible DDC on this connector */
428 return false;
429 /* Probe also for valid EDID header
430 * EDID header starts with:
431 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
432 * Only the first 6 bytes must be valid as
433 * drm_edid_block_valid() can fix the last 2 bytes */
434 if (drm_edid_header_is_valid(buf) < 6) {
435 /* Couldn't find an accessible EDID on this
436 * connector */
437 return false;
438 }
439 return true;
440 }
441
442 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb)
443 {
444 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
445
446 if (amdgpu_fb->obj) {
447 drm_gem_object_unreference_unlocked(amdgpu_fb->obj);
448 }
449 drm_framebuffer_cleanup(fb);
450 kfree(amdgpu_fb);
451 }
452
453 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb,
454 struct drm_file *file_priv,
455 unsigned int *handle)
456 {
457 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb);
458
459 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle);
460 }
461
462 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
463 .destroy = amdgpu_user_framebuffer_destroy,
464 .create_handle = amdgpu_user_framebuffer_create_handle,
465 };
466
467 int
468 amdgpu_framebuffer_init(struct drm_device *dev,
469 struct amdgpu_framebuffer *rfb,
470 struct drm_mode_fb_cmd2 *mode_cmd,
471 struct drm_gem_object *obj)
472 {
473 int ret;
474 rfb->obj = obj;
475 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
476 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
477 if (ret) {
478 rfb->obj = NULL;
479 return ret;
480 }
481 return 0;
482 }
483
484 static struct drm_framebuffer *
485 amdgpu_user_framebuffer_create(struct drm_device *dev,
486 struct drm_file *file_priv,
487 struct drm_mode_fb_cmd2 *mode_cmd)
488 {
489 struct drm_gem_object *obj;
490 struct amdgpu_framebuffer *amdgpu_fb;
491 int ret;
492
493 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
494 if (obj == NULL) {
495 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
496 "can't create framebuffer\n", mode_cmd->handles[0]);
497 return ERR_PTR(-ENOENT);
498 }
499
500 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL);
501 if (amdgpu_fb == NULL) {
502 drm_gem_object_unreference_unlocked(obj);
503 return ERR_PTR(-ENOMEM);
504 }
505
506 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj);
507 if (ret) {
508 kfree(amdgpu_fb);
509 drm_gem_object_unreference_unlocked(obj);
510 return ERR_PTR(ret);
511 }
512
513 return &amdgpu_fb->base;
514 }
515
516 static void amdgpu_output_poll_changed(struct drm_device *dev)
517 {
518 struct amdgpu_device *adev = dev->dev_private;
519 amdgpu_fb_output_poll_changed(adev);
520 }
521
522 const struct drm_mode_config_funcs amdgpu_mode_funcs = {
523 .fb_create = amdgpu_user_framebuffer_create,
524 .output_poll_changed = amdgpu_output_poll_changed
525 };
526
527 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] =
528 { { UNDERSCAN_OFF, "off" },
529 { UNDERSCAN_ON, "on" },
530 { UNDERSCAN_AUTO, "auto" },
531 };
532
533 static struct drm_prop_enum_list amdgpu_audio_enum_list[] =
534 { { AMDGPU_AUDIO_DISABLE, "off" },
535 { AMDGPU_AUDIO_ENABLE, "on" },
536 { AMDGPU_AUDIO_AUTO, "auto" },
537 };
538
539 /* XXX support different dither options? spatial, temporal, both, etc. */
540 static struct drm_prop_enum_list amdgpu_dither_enum_list[] =
541 { { AMDGPU_FMT_DITHER_DISABLE, "off" },
542 { AMDGPU_FMT_DITHER_ENABLE, "on" },
543 };
544
545 int amdgpu_modeset_create_props(struct amdgpu_device *adev)
546 {
547 int sz;
548
549 if (adev->is_atom_bios) {
550 adev->mode_info.coherent_mode_property =
551 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1);
552 if (!adev->mode_info.coherent_mode_property)
553 return -ENOMEM;
554 }
555
556 adev->mode_info.load_detect_property =
557 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1);
558 if (!adev->mode_info.load_detect_property)
559 return -ENOMEM;
560
561 drm_mode_create_scaling_mode_property(adev->ddev);
562
563 sz = ARRAY_SIZE(amdgpu_underscan_enum_list);
564 adev->mode_info.underscan_property =
565 drm_property_create_enum(adev->ddev, 0,
566 "underscan",
567 amdgpu_underscan_enum_list, sz);
568
569 adev->mode_info.underscan_hborder_property =
570 drm_property_create_range(adev->ddev, 0,
571 "underscan hborder", 0, 128);
572 if (!adev->mode_info.underscan_hborder_property)
573 return -ENOMEM;
574
575 adev->mode_info.underscan_vborder_property =
576 drm_property_create_range(adev->ddev, 0,
577 "underscan vborder", 0, 128);
578 if (!adev->mode_info.underscan_vborder_property)
579 return -ENOMEM;
580
581 sz = ARRAY_SIZE(amdgpu_audio_enum_list);
582 adev->mode_info.audio_property =
583 drm_property_create_enum(adev->ddev, 0,
584 "audio",
585 amdgpu_audio_enum_list, sz);
586
587 sz = ARRAY_SIZE(amdgpu_dither_enum_list);
588 adev->mode_info.dither_property =
589 drm_property_create_enum(adev->ddev, 0,
590 "dither",
591 amdgpu_dither_enum_list, sz);
592
593 return 0;
594 }
595
596 void amdgpu_update_display_priority(struct amdgpu_device *adev)
597 {
598 /* adjustment options for the display watermarks */
599 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2))
600 adev->mode_info.disp_priority = 0;
601 else
602 adev->mode_info.disp_priority = amdgpu_disp_priority;
603
604 }
605
606 static bool is_hdtv_mode(const struct drm_display_mode *mode)
607 {
608 /* try and guess if this is a tv or a monitor */
609 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
610 (mode->vdisplay == 576) || /* 576p */
611 (mode->vdisplay == 720) || /* 720p */
612 (mode->vdisplay == 1080)) /* 1080p */
613 return true;
614 else
615 return false;
616 }
617
618 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
619 const struct drm_display_mode *mode,
620 struct drm_display_mode *adjusted_mode)
621 {
622 struct drm_device *dev = crtc->dev;
623 struct drm_encoder *encoder;
624 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
625 struct amdgpu_encoder *amdgpu_encoder;
626 struct drm_connector *connector;
627 struct amdgpu_connector *amdgpu_connector;
628 u32 src_v = 1, dst_v = 1;
629 u32 src_h = 1, dst_h = 1;
630
631 amdgpu_crtc->h_border = 0;
632 amdgpu_crtc->v_border = 0;
633
634 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
635 if (encoder->crtc != crtc)
636 continue;
637 amdgpu_encoder = to_amdgpu_encoder(encoder);
638 connector = amdgpu_get_connector_for_encoder(encoder);
639 amdgpu_connector = to_amdgpu_connector(connector);
640
641 /* set scaling */
642 if (amdgpu_encoder->rmx_type == RMX_OFF)
643 amdgpu_crtc->rmx_type = RMX_OFF;
644 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay ||
645 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay)
646 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type;
647 else
648 amdgpu_crtc->rmx_type = RMX_OFF;
649 /* copy native mode */
650 memcpy(&amdgpu_crtc->native_mode,
651 &amdgpu_encoder->native_mode,
652 sizeof(struct drm_display_mode));
653 src_v = crtc->mode.vdisplay;
654 dst_v = amdgpu_crtc->native_mode.vdisplay;
655 src_h = crtc->mode.hdisplay;
656 dst_h = amdgpu_crtc->native_mode.hdisplay;
657
658 /* fix up for overscan on hdmi */
659 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
660 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) ||
661 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) &&
662 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) &&
663 is_hdtv_mode(mode)))) {
664 if (amdgpu_encoder->underscan_hborder != 0)
665 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder;
666 else
667 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16;
668 if (amdgpu_encoder->underscan_vborder != 0)
669 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder;
670 else
671 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16;
672 amdgpu_crtc->rmx_type = RMX_FULL;
673 src_v = crtc->mode.vdisplay;
674 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2);
675 src_h = crtc->mode.hdisplay;
676 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2);
677 }
678 }
679 if (amdgpu_crtc->rmx_type != RMX_OFF) {
680 fixed20_12 a, b;
681 a.full = dfixed_const(src_v);
682 b.full = dfixed_const(dst_v);
683 amdgpu_crtc->vsc.full = dfixed_div(a, b);
684 a.full = dfixed_const(src_h);
685 b.full = dfixed_const(dst_h);
686 amdgpu_crtc->hsc.full = dfixed_div(a, b);
687 } else {
688 amdgpu_crtc->vsc.full = dfixed_const(1);
689 amdgpu_crtc->hsc.full = dfixed_const(1);
690 }
691 return true;
692 }
693
694 /*
695 * Retrieve current video scanout position of crtc on a given gpu, and
696 * an optional accurate timestamp of when query happened.
697 *
698 * \param dev Device to query.
699 * \param crtc Crtc to query.
700 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
701 * \param *vpos Location where vertical scanout position should be stored.
702 * \param *hpos Location where horizontal scanout position should go.
703 * \param *stime Target location for timestamp taken immediately before
704 * scanout position query. Can be NULL to skip timestamp.
705 * \param *etime Target location for timestamp taken immediately after
706 * scanout position query. Can be NULL to skip timestamp.
707 *
708 * Returns vpos as a positive number while in active scanout area.
709 * Returns vpos as a negative number inside vblank, counting the number
710 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
711 * until start of active scanout / end of vblank."
712 *
713 * \return Flags, or'ed together as follows:
714 *
715 * DRM_SCANOUTPOS_VALID = Query successful.
716 * DRM_SCANOUTPOS_INVBL = Inside vblank.
717 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
718 * this flag means that returned position may be offset by a constant but
719 * unknown small number of scanlines wrt. real scanout position.
720 *
721 */
722 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
723 int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
724 {
725 u32 vbl = 0, position = 0;
726 int vbl_start, vbl_end, vtotal, ret = 0;
727 bool in_vbl = true;
728
729 struct amdgpu_device *adev = dev->dev_private;
730
731 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
732
733 /* Get optional system timestamp before query. */
734 if (stime)
735 *stime = ktime_get();
736
737 if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0)
738 ret |= DRM_SCANOUTPOS_VALID;
739
740 /* Get optional system timestamp after query. */
741 if (etime)
742 *etime = ktime_get();
743
744 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
745
746 /* Decode into vertical and horizontal scanout position. */
747 *vpos = position & 0x1fff;
748 *hpos = (position >> 16) & 0x1fff;
749
750 /* Valid vblank area boundaries from gpu retrieved? */
751 if (vbl > 0) {
752 /* Yes: Decode. */
753 ret |= DRM_SCANOUTPOS_ACCURATE;
754 vbl_start = vbl & 0x1fff;
755 vbl_end = (vbl >> 16) & 0x1fff;
756 }
757 else {
758 /* No: Fake something reasonable which gives at least ok results. */
759 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
760 vbl_end = 0;
761 }
762
763 /* Test scanout position against vblank region. */
764 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
765 in_vbl = false;
766
767 /* Check if inside vblank area and apply corrective offsets:
768 * vpos will then be >=0 in video scanout area, but negative
769 * within vblank area, counting down the number of lines until
770 * start of scanout.
771 */
772
773 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
774 if (in_vbl && (*vpos >= vbl_start)) {
775 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
776 *vpos = *vpos - vtotal;
777 }
778
779 /* Correct for shifted end of vbl at vbl_end. */
780 *vpos = *vpos - vbl_end;
781
782 /* In vblank? */
783 if (in_vbl)
784 ret |= DRM_SCANOUTPOS_IN_VBLANK;
785
786 /* Is vpos outside nominal vblank area, but less than
787 * 1/100 of a frame height away from start of vblank?
788 * If so, assume this isn't a massively delayed vblank
789 * interrupt, but a vblank interrupt that fired a few
790 * microseconds before true start of vblank. Compensate
791 * by adding a full frame duration to the final timestamp.
792 * Happens, e.g., on ATI R500, R600.
793 *
794 * We only do this if DRM_CALLED_FROM_VBLIRQ.
795 */
796 if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
797 vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
798 vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
799
800 if (vbl_start - *vpos < vtotal / 100) {
801 *vpos -= vtotal;
802
803 /* Signal this correction as "applied". */
804 ret |= 0x8;
805 }
806 }
807
808 return ret;
809 }
810
811 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc)
812 {
813 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
814 return AMDGPU_CRTC_IRQ_NONE;
815
816 switch (crtc) {
817 case 0:
818 return AMDGPU_CRTC_IRQ_VBLANK1;
819 case 1:
820 return AMDGPU_CRTC_IRQ_VBLANK2;
821 case 2:
822 return AMDGPU_CRTC_IRQ_VBLANK3;
823 case 3:
824 return AMDGPU_CRTC_IRQ_VBLANK4;
825 case 4:
826 return AMDGPU_CRTC_IRQ_VBLANK5;
827 case 5:
828 return AMDGPU_CRTC_IRQ_VBLANK6;
829 default:
830 return AMDGPU_CRTC_IRQ_NONE;
831 }
832 }
Linux kernel - Deliverables
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