2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/amdgpu_drm.h>
36 #define AMDGPU_IB_TEST_TIMEOUT msecs_to_jiffies(1000)
40 * IBs (Indirect Buffers) and areas of GPU accessible memory where
41 * commands are stored. You can put a pointer to the IB in the
42 * command ring and the hw will fetch the commands from the IB
43 * and execute them. Generally userspace acceleration drivers
44 * produce command buffers which are send to the kernel and
45 * put in IBs for execution by the requested ring.
47 static int amdgpu_debugfs_sa_init(struct amdgpu_device
*adev
);
50 * amdgpu_ib_get - request an IB (Indirect Buffer)
52 * @ring: ring index the IB is associated with
53 * @size: requested IB size
54 * @ib: IB object returned
56 * Request an IB (all asics). IBs are allocated using the
58 * Returns 0 on success, error on failure.
60 int amdgpu_ib_get(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
,
61 unsigned size
, struct amdgpu_ib
*ib
)
66 r
= amdgpu_sa_bo_new(&adev
->ring_tmp_bo
,
67 &ib
->sa_bo
, size
, 256);
69 dev_err(adev
->dev
, "failed to get a new IB (%d)\n", r
);
73 ib
->ptr
= amdgpu_sa_bo_cpu_addr(ib
->sa_bo
);
76 ib
->gpu_addr
= amdgpu_sa_bo_gpu_addr(ib
->sa_bo
);
83 * amdgpu_ib_free - free an IB (Indirect Buffer)
85 * @adev: amdgpu_device pointer
86 * @ib: IB object to free
87 * @f: the fence SA bo need wait on for the ib alloation
89 * Free an IB (all asics).
91 void amdgpu_ib_free(struct amdgpu_device
*adev
, struct amdgpu_ib
*ib
,
94 amdgpu_sa_bo_free(adev
, &ib
->sa_bo
, f
);
98 * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring
100 * @adev: amdgpu_device pointer
101 * @num_ibs: number of IBs to schedule
102 * @ibs: IB objects to schedule
103 * @f: fence created during this submission
105 * Schedule an IB on the associated ring (all asics).
106 * Returns 0 on success, error on failure.
108 * On SI, there are two parallel engines fed from the primary ring,
109 * the CE (Constant Engine) and the DE (Drawing Engine). Since
110 * resource descriptors have moved to memory, the CE allows you to
111 * prime the caches while the DE is updating register state so that
112 * the resource descriptors will be already in cache when the draw is
113 * processed. To accomplish this, the userspace driver submits two
114 * IBs, one for the CE and one for the DE. If there is a CE IB (called
115 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
116 * to SI there was just a DE IB.
118 int amdgpu_ib_schedule(struct amdgpu_ring
*ring
, unsigned num_ibs
,
119 struct amdgpu_ib
*ibs
, struct fence
*last_vm_update
,
120 struct amdgpu_job
*job
, struct fence
**f
)
122 struct amdgpu_device
*adev
= ring
->adev
;
123 struct amdgpu_ib
*ib
= &ibs
[0];
124 bool skip_preamble
, need_ctx_switch
;
125 unsigned patch_offset
= ~0;
126 struct amdgpu_vm
*vm
;
135 /* ring tests don't use a job */
145 dev_err(adev
->dev
, "couldn't schedule ib\n");
149 if (vm
&& !job
->vm_id
) {
150 dev_err(adev
->dev
, "VM IB without ID\n");
154 r
= amdgpu_ring_alloc(ring
, 256 * num_ibs
);
156 dev_err(adev
->dev
, "scheduling IB failed (%d).\n", r
);
160 if (ring
->type
== AMDGPU_RING_TYPE_SDMA
&& ring
->funcs
->init_cond_exec
)
161 patch_offset
= amdgpu_ring_init_cond_exec(ring
);
164 r
= amdgpu_vm_flush(ring
, job
);
166 amdgpu_ring_undo(ring
);
171 if (ring
->funcs
->emit_hdp_flush
)
172 amdgpu_ring_emit_hdp_flush(ring
);
174 /* always set cond_exec_polling to CONTINUE */
175 *ring
->cond_exe_cpu_addr
= 1;
177 skip_preamble
= ring
->current_ctx
== ctx
;
178 need_ctx_switch
= ring
->current_ctx
!= ctx
;
179 for (i
= 0; i
< num_ibs
; ++i
) {
182 /* drop preamble IBs if we don't have a context switch */
183 if ((ib
->flags
& AMDGPU_IB_FLAG_PREAMBLE
) && skip_preamble
)
186 amdgpu_ring_emit_ib(ring
, ib
, job
? job
->vm_id
: 0,
188 need_ctx_switch
= false;
191 if (ring
->funcs
->emit_hdp_invalidate
)
192 amdgpu_ring_emit_hdp_invalidate(ring
);
194 r
= amdgpu_fence_emit(ring
, f
);
196 dev_err(adev
->dev
, "failed to emit fence (%d)\n", r
);
197 if (job
&& job
->vm_id
)
198 amdgpu_vm_reset_id(adev
, job
->vm_id
);
199 amdgpu_ring_undo(ring
);
203 /* wrap the last IB with fence */
204 if (job
&& job
->uf_addr
) {
205 amdgpu_ring_emit_fence(ring
, job
->uf_addr
, job
->uf_sequence
,
206 AMDGPU_FENCE_FLAG_64BIT
);
209 if (patch_offset
!= ~0 && ring
->funcs
->patch_cond_exec
)
210 amdgpu_ring_patch_cond_exec(ring
, patch_offset
);
212 ring
->current_ctx
= ctx
;
213 amdgpu_ring_commit(ring
);
218 * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool
220 * @adev: amdgpu_device pointer
222 * Initialize the suballocator to manage a pool of memory
223 * for use as IBs (all asics).
224 * Returns 0 on success, error on failure.
226 int amdgpu_ib_pool_init(struct amdgpu_device
*adev
)
230 if (adev
->ib_pool_ready
) {
233 r
= amdgpu_sa_bo_manager_init(adev
, &adev
->ring_tmp_bo
,
234 AMDGPU_IB_POOL_SIZE
*64*1024,
235 AMDGPU_GPU_PAGE_SIZE
,
236 AMDGPU_GEM_DOMAIN_GTT
);
241 r
= amdgpu_sa_bo_manager_start(adev
, &adev
->ring_tmp_bo
);
246 adev
->ib_pool_ready
= true;
247 if (amdgpu_debugfs_sa_init(adev
)) {
248 dev_err(adev
->dev
, "failed to register debugfs file for SA\n");
254 * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool
256 * @adev: amdgpu_device pointer
258 * Tear down the suballocator managing the pool of memory
259 * for use as IBs (all asics).
261 void amdgpu_ib_pool_fini(struct amdgpu_device
*adev
)
263 if (adev
->ib_pool_ready
) {
264 amdgpu_sa_bo_manager_suspend(adev
, &adev
->ring_tmp_bo
);
265 amdgpu_sa_bo_manager_fini(adev
, &adev
->ring_tmp_bo
);
266 adev
->ib_pool_ready
= false;
271 * amdgpu_ib_ring_tests - test IBs on the rings
273 * @adev: amdgpu_device pointer
275 * Test an IB (Indirect Buffer) on each ring.
276 * If the test fails, disable the ring.
277 * Returns 0 on success, error if the primary GFX ring
280 int amdgpu_ib_ring_tests(struct amdgpu_device
*adev
)
285 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
286 struct amdgpu_ring
*ring
= adev
->rings
[i
];
288 if (!ring
|| !ring
->ready
)
291 r
= amdgpu_ring_test_ib(ring
, AMDGPU_IB_TEST_TIMEOUT
);
295 if (ring
== &adev
->gfx
.gfx_ring
[0]) {
296 /* oh, oh, that's really bad */
297 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r
);
298 adev
->accel_working
= false;
302 /* still not good, but we can live with it */
303 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i
, r
);
314 #if defined(CONFIG_DEBUG_FS)
316 static int amdgpu_debugfs_sa_info(struct seq_file
*m
, void *data
)
318 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
319 struct drm_device
*dev
= node
->minor
->dev
;
320 struct amdgpu_device
*adev
= dev
->dev_private
;
322 amdgpu_sa_bo_dump_debug_info(&adev
->ring_tmp_bo
, m
);
328 static const struct drm_info_list amdgpu_debugfs_sa_list
[] = {
329 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info
, 0, NULL
},
334 static int amdgpu_debugfs_sa_init(struct amdgpu_device
*adev
)
336 #if defined(CONFIG_DEBUG_FS)
337 return amdgpu_debugfs_add_files(adev
, amdgpu_debugfs_sa_list
, 1);