2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
30 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
34 #include <linux/vga_switcheroo.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
38 #if defined(CONFIG_VGA_SWITCHEROO)
39 bool amdgpu_has_atpx(void);
41 static inline bool amdgpu_has_atpx(void) { return false; }
45 * amdgpu_driver_unload_kms - Main unload function for KMS.
47 * @dev: drm dev pointer
49 * This is the main unload function for KMS (all asics).
50 * Returns 0 on success.
52 int amdgpu_driver_unload_kms(struct drm_device
*dev
)
54 struct amdgpu_device
*adev
= dev
->dev_private
;
59 if (adev
->rmmio
== NULL
)
62 pm_runtime_get_sync(dev
->dev
);
64 amdgpu_acpi_fini(adev
);
66 amdgpu_device_fini(adev
);
70 dev
->dev_private
= NULL
;
75 * amdgpu_driver_load_kms - Main load function for KMS.
77 * @dev: drm dev pointer
78 * @flags: device flags
80 * This is the main load function for KMS (all asics).
81 * Returns 0 on success, error on failure.
83 int amdgpu_driver_load_kms(struct drm_device
*dev
, unsigned long flags
)
85 struct amdgpu_device
*adev
;
88 adev
= kzalloc(sizeof(struct amdgpu_device
), GFP_KERNEL
);
92 dev
->dev_private
= (void *)adev
;
94 if ((amdgpu_runtime_pm
!= 0) &&
96 ((flags
& AMDGPU_IS_APU
) == 0))
97 flags
|= AMDGPU_IS_PX
;
99 /* amdgpu_device_init should report only fatal error
100 * like memory allocation failure or iomapping failure,
101 * or memory manager initialization failure, it must
102 * properly initialize the GPU MC controller and permit
105 r
= amdgpu_device_init(adev
, dev
, dev
->pdev
, flags
);
107 dev_err(&dev
->pdev
->dev
, "Fatal error during GPU init\n");
111 /* Call ACPI methods: require modeset init
112 * but failure is not fatal
115 acpi_status
= amdgpu_acpi_init(adev
);
117 dev_dbg(&dev
->pdev
->dev
,
118 "Error during ACPI methods call\n");
121 if (amdgpu_device_is_px(dev
)) {
122 pm_runtime_use_autosuspend(dev
->dev
);
123 pm_runtime_set_autosuspend_delay(dev
->dev
, 5000);
124 pm_runtime_set_active(dev
->dev
);
125 pm_runtime_allow(dev
->dev
);
126 pm_runtime_mark_last_busy(dev
->dev
);
127 pm_runtime_put_autosuspend(dev
->dev
);
132 amdgpu_driver_unload_kms(dev
);
139 * Userspace get information ioctl
142 * amdgpu_info_ioctl - answer a device specific request.
144 * @adev: amdgpu device pointer
145 * @data: request object
148 * This function is used to pass device specific parameters to the userspace
149 * drivers. Examples include: pci device id, pipeline parms, tiling params,
151 * Returns 0 on success, -EINVAL on failure.
153 static int amdgpu_info_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
155 struct amdgpu_device
*adev
= dev
->dev_private
;
156 struct drm_amdgpu_info
*info
= data
;
157 struct amdgpu_mode_info
*minfo
= &adev
->mode_info
;
158 void __user
*out
= (void __user
*)(long)info
->return_pointer
;
159 uint32_t size
= info
->return_size
;
160 struct drm_crtc
*crtc
;
165 if (!info
->return_size
|| !info
->return_pointer
)
168 switch (info
->query
) {
169 case AMDGPU_INFO_ACCEL_WORKING
:
170 ui32
= adev
->accel_working
;
171 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
172 case AMDGPU_INFO_CRTC_FROM_ID
:
173 for (i
= 0, found
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
174 crtc
= (struct drm_crtc
*)minfo
->crtcs
[i
];
175 if (crtc
&& crtc
->base
.id
== info
->mode_crtc
.id
) {
176 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
177 ui32
= amdgpu_crtc
->crtc_id
;
183 DRM_DEBUG_KMS("unknown crtc id %d\n", info
->mode_crtc
.id
);
186 return copy_to_user(out
, &ui32
, min(size
, 4u)) ? -EFAULT
: 0;
187 case AMDGPU_INFO_HW_IP_INFO
: {
188 struct drm_amdgpu_info_hw_ip ip
= {};
189 enum amdgpu_ip_block_type type
;
190 uint32_t ring_mask
= 0;
192 if (info
->query_hw_ip
.ip_instance
>= AMDGPU_HW_IP_INSTANCE_MAX_COUNT
)
195 switch (info
->query_hw_ip
.type
) {
196 case AMDGPU_HW_IP_GFX
:
197 type
= AMDGPU_IP_BLOCK_TYPE_GFX
;
198 for (i
= 0; i
< adev
->gfx
.num_gfx_rings
; i
++)
199 ring_mask
|= ((adev
->gfx
.gfx_ring
[i
].ready
? 1 : 0) << i
);
201 case AMDGPU_HW_IP_COMPUTE
:
202 type
= AMDGPU_IP_BLOCK_TYPE_GFX
;
203 for (i
= 0; i
< adev
->gfx
.num_compute_rings
; i
++)
204 ring_mask
|= ((adev
->gfx
.compute_ring
[i
].ready
? 1 : 0) << i
);
206 case AMDGPU_HW_IP_DMA
:
207 type
= AMDGPU_IP_BLOCK_TYPE_SDMA
;
208 ring_mask
= adev
->sdma
[0].ring
.ready
? 1 : 0;
209 ring_mask
|= ((adev
->sdma
[1].ring
.ready
? 1 : 0) << 1);
211 case AMDGPU_HW_IP_UVD
:
212 type
= AMDGPU_IP_BLOCK_TYPE_UVD
;
213 ring_mask
= adev
->uvd
.ring
.ready
? 1 : 0;
215 case AMDGPU_HW_IP_VCE
:
216 type
= AMDGPU_IP_BLOCK_TYPE_VCE
;
217 for (i
= 0; i
< AMDGPU_MAX_VCE_RINGS
; i
++)
218 ring_mask
|= ((adev
->vce
.ring
[i
].ready
? 1 : 0) << i
);
224 for (i
= 0; i
< adev
->num_ip_blocks
; i
++) {
225 if (adev
->ip_blocks
[i
].type
== type
&&
226 adev
->ip_block_enabled
[i
]) {
227 ip
.hw_ip_version_major
= adev
->ip_blocks
[i
].major
;
228 ip
.hw_ip_version_minor
= adev
->ip_blocks
[i
].minor
;
229 ip
.capabilities_flags
= 0;
230 ip
.available_rings
= ring_mask
;
234 return copy_to_user(out
, &ip
,
235 min((size_t)size
, sizeof(ip
))) ? -EFAULT
: 0;
237 case AMDGPU_INFO_HW_IP_COUNT
: {
238 enum amdgpu_ip_block_type type
;
241 switch (info
->query_hw_ip
.type
) {
242 case AMDGPU_HW_IP_GFX
:
243 type
= AMDGPU_IP_BLOCK_TYPE_GFX
;
245 case AMDGPU_HW_IP_COMPUTE
:
246 type
= AMDGPU_IP_BLOCK_TYPE_GFX
;
248 case AMDGPU_HW_IP_DMA
:
249 type
= AMDGPU_IP_BLOCK_TYPE_SDMA
;
251 case AMDGPU_HW_IP_UVD
:
252 type
= AMDGPU_IP_BLOCK_TYPE_UVD
;
254 case AMDGPU_HW_IP_VCE
:
255 type
= AMDGPU_IP_BLOCK_TYPE_VCE
;
261 for (i
= 0; i
< adev
->num_ip_blocks
; i
++)
262 if (adev
->ip_blocks
[i
].type
== type
&&
263 adev
->ip_block_enabled
[i
] &&
264 count
< AMDGPU_HW_IP_INSTANCE_MAX_COUNT
)
267 return copy_to_user(out
, &count
, min(size
, 4u)) ? -EFAULT
: 0;
269 case AMDGPU_INFO_TIMESTAMP
:
270 ui64
= amdgpu_asic_get_gpu_clock_counter(adev
);
271 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
272 case AMDGPU_INFO_FW_VERSION
: {
273 struct drm_amdgpu_info_firmware fw_info
;
275 /* We only support one instance of each IP block right now. */
276 if (info
->query_fw
.ip_instance
!= 0)
279 switch (info
->query_fw
.fw_type
) {
280 case AMDGPU_INFO_FW_VCE
:
281 fw_info
.ver
= adev
->vce
.fw_version
;
282 fw_info
.feature
= adev
->vce
.fb_version
;
284 case AMDGPU_INFO_FW_UVD
:
288 case AMDGPU_INFO_FW_GMC
:
289 fw_info
.ver
= adev
->mc
.fw_version
;
292 case AMDGPU_INFO_FW_GFX_ME
:
293 fw_info
.ver
= adev
->gfx
.me_fw_version
;
296 case AMDGPU_INFO_FW_GFX_PFP
:
297 fw_info
.ver
= adev
->gfx
.pfp_fw_version
;
300 case AMDGPU_INFO_FW_GFX_CE
:
301 fw_info
.ver
= adev
->gfx
.ce_fw_version
;
304 case AMDGPU_INFO_FW_GFX_RLC
:
305 fw_info
.ver
= adev
->gfx
.rlc_fw_version
;
308 case AMDGPU_INFO_FW_GFX_MEC
:
309 if (info
->query_fw
.index
== 0)
310 fw_info
.ver
= adev
->gfx
.mec_fw_version
;
311 else if (info
->query_fw
.index
== 1)
312 fw_info
.ver
= adev
->gfx
.mec2_fw_version
;
317 case AMDGPU_INFO_FW_SMC
:
318 fw_info
.ver
= adev
->pm
.fw_version
;
321 case AMDGPU_INFO_FW_SDMA
:
322 if (info
->query_fw
.index
>= 2)
324 fw_info
.ver
= adev
->sdma
[info
->query_fw
.index
].fw_version
;
330 return copy_to_user(out
, &fw_info
,
331 min((size_t)size
, sizeof(fw_info
))) ? -EFAULT
: 0;
333 case AMDGPU_INFO_NUM_BYTES_MOVED
:
334 ui64
= atomic64_read(&adev
->num_bytes_moved
);
335 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
336 case AMDGPU_INFO_VRAM_USAGE
:
337 ui64
= atomic64_read(&adev
->vram_usage
);
338 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
339 case AMDGPU_INFO_VIS_VRAM_USAGE
:
340 ui64
= atomic64_read(&adev
->vram_vis_usage
);
341 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
342 case AMDGPU_INFO_GTT_USAGE
:
343 ui64
= atomic64_read(&adev
->gtt_usage
);
344 return copy_to_user(out
, &ui64
, min(size
, 8u)) ? -EFAULT
: 0;
345 case AMDGPU_INFO_GDS_CONFIG
: {
346 struct drm_amdgpu_info_gds gds_info
;
348 memset(&gds_info
, 0, sizeof(gds_info
));
349 gds_info
.gds_gfx_partition_size
= adev
->gds
.mem
.gfx_partition_size
>> AMDGPU_GDS_SHIFT
;
350 gds_info
.compute_partition_size
= adev
->gds
.mem
.cs_partition_size
>> AMDGPU_GDS_SHIFT
;
351 gds_info
.gds_total_size
= adev
->gds
.mem
.total_size
>> AMDGPU_GDS_SHIFT
;
352 gds_info
.gws_per_gfx_partition
= adev
->gds
.gws
.gfx_partition_size
>> AMDGPU_GWS_SHIFT
;
353 gds_info
.gws_per_compute_partition
= adev
->gds
.gws
.cs_partition_size
>> AMDGPU_GWS_SHIFT
;
354 gds_info
.oa_per_gfx_partition
= adev
->gds
.oa
.gfx_partition_size
>> AMDGPU_OA_SHIFT
;
355 gds_info
.oa_per_compute_partition
= adev
->gds
.oa
.cs_partition_size
>> AMDGPU_OA_SHIFT
;
356 return copy_to_user(out
, &gds_info
,
357 min((size_t)size
, sizeof(gds_info
))) ? -EFAULT
: 0;
359 case AMDGPU_INFO_VRAM_GTT
: {
360 struct drm_amdgpu_info_vram_gtt vram_gtt
;
362 vram_gtt
.vram_size
= adev
->mc
.real_vram_size
;
363 vram_gtt
.vram_cpu_accessible_size
= adev
->mc
.visible_vram_size
;
364 vram_gtt
.vram_cpu_accessible_size
-= adev
->vram_pin_size
;
365 vram_gtt
.gtt_size
= adev
->mc
.gtt_size
;
366 vram_gtt
.gtt_size
-= adev
->gart_pin_size
;
367 return copy_to_user(out
, &vram_gtt
,
368 min((size_t)size
, sizeof(vram_gtt
))) ? -EFAULT
: 0;
370 case AMDGPU_INFO_READ_MMR_REG
: {
371 unsigned n
, alloc_size
= info
->read_mmr_reg
.count
* 4;
373 unsigned se_num
= (info
->read_mmr_reg
.instance
>>
374 AMDGPU_INFO_MMR_SE_INDEX_SHIFT
) &
375 AMDGPU_INFO_MMR_SE_INDEX_MASK
;
376 unsigned sh_num
= (info
->read_mmr_reg
.instance
>>
377 AMDGPU_INFO_MMR_SH_INDEX_SHIFT
) &
378 AMDGPU_INFO_MMR_SH_INDEX_MASK
;
380 /* set full masks if the userspace set all bits
381 * in the bitfields */
382 if (se_num
== AMDGPU_INFO_MMR_SE_INDEX_MASK
)
384 if (sh_num
== AMDGPU_INFO_MMR_SH_INDEX_MASK
)
387 regs
= kmalloc(alloc_size
, GFP_KERNEL
);
391 for (i
= 0; i
< info
->read_mmr_reg
.count
; i
++)
392 if (amdgpu_asic_read_register(adev
, se_num
, sh_num
,
393 info
->read_mmr_reg
.dword_offset
+ i
,
395 DRM_DEBUG_KMS("unallowed offset %#x\n",
396 info
->read_mmr_reg
.dword_offset
+ i
);
400 n
= copy_to_user(out
, regs
, min(size
, alloc_size
));
402 return n
? -EFAULT
: 0;
404 case AMDGPU_INFO_DEV_INFO
: {
405 struct drm_amdgpu_info_device dev_info
;
406 struct amdgpu_cu_info cu_info
;
408 dev_info
.device_id
= dev
->pdev
->device
;
409 dev_info
.chip_rev
= adev
->rev_id
;
410 dev_info
.external_rev
= adev
->external_rev_id
;
411 dev_info
.pci_rev
= dev
->pdev
->revision
;
412 dev_info
.family
= adev
->family
;
413 dev_info
.num_shader_engines
= adev
->gfx
.config
.max_shader_engines
;
414 dev_info
.num_shader_arrays_per_engine
= adev
->gfx
.config
.max_sh_per_se
;
415 /* return all clocks in KHz */
416 dev_info
.gpu_counter_freq
= amdgpu_asic_get_xclk(adev
) * 10;
417 if (adev
->pm
.dpm_enabled
)
418 dev_info
.max_engine_clock
=
419 adev
->pm
.dpm
.dyn_state
.max_clock_voltage_on_ac
.sclk
* 10;
421 dev_info
.max_engine_clock
= adev
->pm
.default_sclk
* 10;
422 dev_info
.enabled_rb_pipes_mask
= adev
->gfx
.config
.backend_enable_mask
;
423 dev_info
.num_rb_pipes
= adev
->gfx
.config
.max_backends_per_se
*
424 adev
->gfx
.config
.max_shader_engines
;
425 dev_info
.num_hw_gfx_contexts
= adev
->gfx
.config
.max_hw_contexts
;
427 dev_info
.ids_flags
= 0;
428 if (adev
->flags
& AMDGPU_IS_APU
)
429 dev_info
.ids_flags
|= AMDGPU_IDS_FLAGS_FUSION
;
430 dev_info
.virtual_address_offset
= AMDGPU_VA_RESERVED_SIZE
;
431 dev_info
.virtual_address_max
= (uint64_t)adev
->vm_manager
.max_pfn
* AMDGPU_GPU_PAGE_SIZE
;
432 dev_info
.virtual_address_alignment
= max(PAGE_SIZE
, 0x10000UL
);
433 dev_info
.pte_fragment_size
= (1 << AMDGPU_LOG2_PAGES_PER_FRAG
) *
434 AMDGPU_GPU_PAGE_SIZE
;
435 dev_info
.gart_page_size
= AMDGPU_GPU_PAGE_SIZE
;
437 amdgpu_asic_get_cu_info(adev
, &cu_info
);
438 dev_info
.cu_active_number
= cu_info
.number
;
439 dev_info
.cu_ao_mask
= cu_info
.ao_cu_mask
;
440 memcpy(&dev_info
.cu_bitmap
[0], &cu_info
.bitmap
[0], sizeof(cu_info
.bitmap
));
442 return copy_to_user(out
, &dev_info
,
443 min((size_t)size
, sizeof(dev_info
))) ? -EFAULT
: 0;
446 DRM_DEBUG_KMS("Invalid request %d\n", info
->query
);
454 * Outdated mess for old drm with Xorg being in charge (void function now).
457 * amdgpu_driver_firstopen_kms - drm callback for last close
459 * @dev: drm dev pointer
461 * Switch vga switcheroo state after last close (all asics).
463 void amdgpu_driver_lastclose_kms(struct drm_device
*dev
)
465 vga_switcheroo_process_delayed_switch();
469 * amdgpu_driver_open_kms - drm callback for open
471 * @dev: drm dev pointer
472 * @file_priv: drm file
474 * On device open, init vm on cayman+ (all asics).
475 * Returns 0 on success, error on failure.
477 int amdgpu_driver_open_kms(struct drm_device
*dev
, struct drm_file
*file_priv
)
479 struct amdgpu_device
*adev
= dev
->dev_private
;
480 struct amdgpu_fpriv
*fpriv
;
483 file_priv
->driver_priv
= NULL
;
485 r
= pm_runtime_get_sync(dev
->dev
);
489 fpriv
= kzalloc(sizeof(*fpriv
), GFP_KERNEL
);
490 if (unlikely(!fpriv
))
493 r
= amdgpu_vm_init(adev
, &fpriv
->vm
);
497 mutex_init(&fpriv
->bo_list_lock
);
498 idr_init(&fpriv
->bo_list_handles
);
500 /* init context manager */
501 mutex_init(&fpriv
->ctx_mgr
.lock
);
502 idr_init(&fpriv
->ctx_mgr
.ctx_handles
);
503 fpriv
->ctx_mgr
.adev
= adev
;
505 file_priv
->driver_priv
= fpriv
;
507 pm_runtime_mark_last_busy(dev
->dev
);
508 pm_runtime_put_autosuspend(dev
->dev
);
518 * amdgpu_driver_postclose_kms - drm callback for post close
520 * @dev: drm dev pointer
521 * @file_priv: drm file
523 * On device post close, tear down vm on cayman+ (all asics).
525 void amdgpu_driver_postclose_kms(struct drm_device
*dev
,
526 struct drm_file
*file_priv
)
528 struct amdgpu_device
*adev
= dev
->dev_private
;
529 struct amdgpu_fpriv
*fpriv
= file_priv
->driver_priv
;
530 struct amdgpu_bo_list
*list
;
536 amdgpu_vm_fini(adev
, &fpriv
->vm
);
538 idr_for_each_entry(&fpriv
->bo_list_handles
, list
, handle
)
539 amdgpu_bo_list_free(list
);
541 idr_destroy(&fpriv
->bo_list_handles
);
542 mutex_destroy(&fpriv
->bo_list_lock
);
544 /* release context */
545 amdgpu_ctx_fini(fpriv
);
548 file_priv
->driver_priv
= NULL
;
552 * amdgpu_driver_preclose_kms - drm callback for pre close
554 * @dev: drm dev pointer
555 * @file_priv: drm file
557 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
560 void amdgpu_driver_preclose_kms(struct drm_device
*dev
,
561 struct drm_file
*file_priv
)
563 struct amdgpu_device
*adev
= dev
->dev_private
;
565 amdgpu_uvd_free_handles(adev
, file_priv
);
566 amdgpu_vce_free_handles(adev
, file_priv
);
570 * VBlank related functions.
573 * amdgpu_get_vblank_counter_kms - get frame count
575 * @dev: drm dev pointer
576 * @crtc: crtc to get the frame count from
578 * Gets the frame count on the requested crtc (all asics).
579 * Returns frame count on success, -EINVAL on failure.
581 u32
amdgpu_get_vblank_counter_kms(struct drm_device
*dev
, int crtc
)
583 struct amdgpu_device
*adev
= dev
->dev_private
;
585 if (crtc
< 0 || crtc
>= adev
->mode_info
.num_crtc
) {
586 DRM_ERROR("Invalid crtc %d\n", crtc
);
590 return amdgpu_display_vblank_get_counter(adev
, crtc
);
594 * amdgpu_enable_vblank_kms - enable vblank interrupt
596 * @dev: drm dev pointer
597 * @crtc: crtc to enable vblank interrupt for
599 * Enable the interrupt on the requested crtc (all asics).
600 * Returns 0 on success, -EINVAL on failure.
602 int amdgpu_enable_vblank_kms(struct drm_device
*dev
, int crtc
)
604 struct amdgpu_device
*adev
= dev
->dev_private
;
605 int idx
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
607 return amdgpu_irq_get(adev
, &adev
->crtc_irq
, idx
);
611 * amdgpu_disable_vblank_kms - disable vblank interrupt
613 * @dev: drm dev pointer
614 * @crtc: crtc to disable vblank interrupt for
616 * Disable the interrupt on the requested crtc (all asics).
618 void amdgpu_disable_vblank_kms(struct drm_device
*dev
, int crtc
)
620 struct amdgpu_device
*adev
= dev
->dev_private
;
621 int idx
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
623 amdgpu_irq_put(adev
, &adev
->crtc_irq
, idx
);
627 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp
629 * @dev: drm dev pointer
630 * @crtc: crtc to get the timestamp for
631 * @max_error: max error
632 * @vblank_time: time value
633 * @flags: flags passed to the driver
635 * Gets the timestamp on the requested crtc based on the
636 * scanout position. (all asics).
637 * Returns postive status flags on success, negative error on failure.
639 int amdgpu_get_vblank_timestamp_kms(struct drm_device
*dev
, int crtc
,
641 struct timeval
*vblank_time
,
644 struct drm_crtc
*drmcrtc
;
645 struct amdgpu_device
*adev
= dev
->dev_private
;
647 if (crtc
< 0 || crtc
>= dev
->num_crtcs
) {
648 DRM_ERROR("Invalid crtc %d\n", crtc
);
652 /* Get associated drm_crtc: */
653 drmcrtc
= &adev
->mode_info
.crtcs
[crtc
]->base
;
655 /* Helper routine in DRM core does all the work: */
656 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc
, max_error
,
658 drmcrtc
, &drmcrtc
->hwmode
);
661 const struct drm_ioctl_desc amdgpu_ioctls_kms
[] = {
662 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE
, amdgpu_gem_create_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
663 DRM_IOCTL_DEF_DRV(AMDGPU_CTX
, amdgpu_ctx_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
664 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST
, amdgpu_bo_list_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
666 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP
, amdgpu_gem_mmap_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
667 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE
, amdgpu_gem_wait_idle_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
668 DRM_IOCTL_DEF_DRV(AMDGPU_CS
, amdgpu_cs_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
669 DRM_IOCTL_DEF_DRV(AMDGPU_INFO
, amdgpu_info_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
670 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS
, amdgpu_cs_wait_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
671 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA
, amdgpu_gem_metadata_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
672 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA
, amdgpu_gem_va_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
673 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP
, amdgpu_gem_op_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
674 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR
, amdgpu_gem_userptr_ioctl
, DRM_AUTH
|DRM_UNLOCKED
|DRM_RENDER_ALLOW
),
676 int amdgpu_max_kms_ioctl
= ARRAY_SIZE(amdgpu_ioctls_kms
);