2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/amdgpu_drm.h>
36 #include <drm/drm_cache.h>
38 #include "amdgpu_trace.h"
41 int amdgpu_ttm_init(struct amdgpu_device
*adev
);
42 void amdgpu_ttm_fini(struct amdgpu_device
*adev
);
44 static u64
amdgpu_get_vis_part_size(struct amdgpu_device
*adev
,
45 struct ttm_mem_reg
*mem
)
48 if (mem
->start
<< PAGE_SHIFT
< adev
->mc
.visible_vram_size
) {
49 ret
= (u64
)((mem
->start
<< PAGE_SHIFT
) + mem
->size
) >
50 adev
->mc
.visible_vram_size
?
51 adev
->mc
.visible_vram_size
- (mem
->start
<< PAGE_SHIFT
) :
57 static void amdgpu_update_memory_usage(struct amdgpu_device
*adev
,
58 struct ttm_mem_reg
*old_mem
,
59 struct ttm_mem_reg
*new_mem
)
66 switch (new_mem
->mem_type
) {
68 atomic64_add(new_mem
->size
, &adev
->gtt_usage
);
71 atomic64_add(new_mem
->size
, &adev
->vram_usage
);
72 vis_size
= amdgpu_get_vis_part_size(adev
, new_mem
);
73 atomic64_add(vis_size
, &adev
->vram_vis_usage
);
79 switch (old_mem
->mem_type
) {
81 atomic64_sub(old_mem
->size
, &adev
->gtt_usage
);
84 atomic64_sub(old_mem
->size
, &adev
->vram_usage
);
85 vis_size
= amdgpu_get_vis_part_size(adev
, old_mem
);
86 atomic64_sub(vis_size
, &adev
->vram_vis_usage
);
92 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object
*tbo
)
96 bo
= container_of(tbo
, struct amdgpu_bo
, tbo
);
98 amdgpu_update_memory_usage(bo
->adev
, &bo
->tbo
.mem
, NULL
);
100 drm_gem_object_release(&bo
->gem_base
);
101 amdgpu_bo_unref(&bo
->parent
);
106 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
)
108 if (bo
->destroy
== &amdgpu_ttm_bo_destroy
)
113 static void amdgpu_ttm_placement_init(struct amdgpu_device
*adev
,
114 struct ttm_placement
*placement
,
115 struct ttm_place
*placements
,
116 u32 domain
, u64 flags
)
120 placement
->placement
= placements
;
121 placement
->busy_placement
= placements
;
123 if (domain
& AMDGPU_GEM_DOMAIN_VRAM
) {
124 if (flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
&&
125 adev
->mc
.visible_vram_size
< adev
->mc
.real_vram_size
) {
127 adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
128 placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_UNCACHED
|
129 TTM_PL_FLAG_VRAM
| TTM_PL_FLAG_TOPDOWN
;
131 placements
[c
].fpfn
= 0;
132 placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_UNCACHED
|
134 if (!(flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
))
135 placements
[c
- 1].flags
|= TTM_PL_FLAG_TOPDOWN
;
138 if (domain
& AMDGPU_GEM_DOMAIN_GTT
) {
139 if (flags
& AMDGPU_GEM_CREATE_CPU_GTT_USWC
) {
140 placements
[c
].fpfn
= 0;
141 placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_TT
|
142 TTM_PL_FLAG_UNCACHED
;
144 placements
[c
].fpfn
= 0;
145 placements
[c
++].flags
= TTM_PL_FLAG_CACHED
| TTM_PL_FLAG_TT
;
149 if (domain
& AMDGPU_GEM_DOMAIN_CPU
) {
150 if (flags
& AMDGPU_GEM_CREATE_CPU_GTT_USWC
) {
151 placements
[c
].fpfn
= 0;
152 placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_SYSTEM
|
153 TTM_PL_FLAG_UNCACHED
;
155 placements
[c
].fpfn
= 0;
156 placements
[c
++].flags
= TTM_PL_FLAG_CACHED
| TTM_PL_FLAG_SYSTEM
;
160 if (domain
& AMDGPU_GEM_DOMAIN_GDS
) {
161 placements
[c
].fpfn
= 0;
162 placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
165 if (domain
& AMDGPU_GEM_DOMAIN_GWS
) {
166 placements
[c
].fpfn
= 0;
167 placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
170 if (domain
& AMDGPU_GEM_DOMAIN_OA
) {
171 placements
[c
].fpfn
= 0;
172 placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
177 placements
[c
].fpfn
= 0;
178 placements
[c
++].flags
= TTM_PL_MASK_CACHING
|
181 placement
->num_placement
= c
;
182 placement
->num_busy_placement
= c
;
184 for (i
= 0; i
< c
; i
++) {
185 if ((flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
) &&
186 (placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
189 adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
191 placements
[i
].lpfn
= 0;
195 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
)
197 amdgpu_ttm_placement_init(rbo
->adev
, &rbo
->placement
,
198 rbo
->placements
, domain
, rbo
->flags
);
201 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo
*bo
,
202 struct ttm_placement
*placement
)
204 BUG_ON(placement
->num_placement
> (AMDGPU_GEM_DOMAIN_MAX
+ 1));
206 memcpy(bo
->placements
, placement
->placement
,
207 placement
->num_placement
* sizeof(struct ttm_place
));
208 bo
->placement
.num_placement
= placement
->num_placement
;
209 bo
->placement
.num_busy_placement
= placement
->num_busy_placement
;
210 bo
->placement
.placement
= bo
->placements
;
211 bo
->placement
.busy_placement
= bo
->placements
;
214 int amdgpu_bo_create_restricted(struct amdgpu_device
*adev
,
215 unsigned long size
, int byte_align
,
216 bool kernel
, u32 domain
, u64 flags
,
218 struct ttm_placement
*placement
,
219 struct reservation_object
*resv
,
220 struct amdgpu_bo
**bo_ptr
)
222 struct amdgpu_bo
*bo
;
223 enum ttm_bo_type type
;
224 unsigned long page_align
;
228 page_align
= roundup(byte_align
, PAGE_SIZE
) >> PAGE_SHIFT
;
229 size
= ALIGN(size
, PAGE_SIZE
);
232 type
= ttm_bo_type_kernel
;
234 type
= ttm_bo_type_sg
;
236 type
= ttm_bo_type_device
;
240 acc_size
= ttm_bo_dma_acc_size(&adev
->mman
.bdev
, size
,
241 sizeof(struct amdgpu_bo
));
243 bo
= kzalloc(sizeof(struct amdgpu_bo
), GFP_KERNEL
);
246 r
= drm_gem_object_init(adev
->ddev
, &bo
->gem_base
, size
);
252 INIT_LIST_HEAD(&bo
->list
);
253 INIT_LIST_HEAD(&bo
->va
);
254 bo
->prefered_domains
= domain
& (AMDGPU_GEM_DOMAIN_VRAM
|
255 AMDGPU_GEM_DOMAIN_GTT
|
256 AMDGPU_GEM_DOMAIN_CPU
|
257 AMDGPU_GEM_DOMAIN_GDS
|
258 AMDGPU_GEM_DOMAIN_GWS
|
259 AMDGPU_GEM_DOMAIN_OA
);
260 bo
->allowed_domains
= bo
->prefered_domains
;
261 if (!kernel
&& bo
->allowed_domains
== AMDGPU_GEM_DOMAIN_VRAM
)
262 bo
->allowed_domains
|= AMDGPU_GEM_DOMAIN_GTT
;
266 /* For architectures that don't support WC memory,
267 * mask out the WC flag from the BO
269 if (!drm_arch_can_wc_memory())
270 bo
->flags
&= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC
;
272 amdgpu_fill_placement_to_bo(bo
, placement
);
273 /* Kernel allocation are uninterruptible */
274 r
= ttm_bo_init(&adev
->mman
.bdev
, &bo
->tbo
, size
, type
,
275 &bo
->placement
, page_align
, !kernel
, NULL
,
276 acc_size
, sg
, resv
, &amdgpu_ttm_bo_destroy
);
277 if (unlikely(r
!= 0)) {
282 trace_amdgpu_bo_create(bo
);
287 int amdgpu_bo_create(struct amdgpu_device
*adev
,
288 unsigned long size
, int byte_align
,
289 bool kernel
, u32 domain
, u64 flags
,
291 struct reservation_object
*resv
,
292 struct amdgpu_bo
**bo_ptr
)
294 struct ttm_placement placement
= {0};
295 struct ttm_place placements
[AMDGPU_GEM_DOMAIN_MAX
+ 1];
297 memset(&placements
, 0,
298 (AMDGPU_GEM_DOMAIN_MAX
+ 1) * sizeof(struct ttm_place
));
300 amdgpu_ttm_placement_init(adev
, &placement
,
301 placements
, domain
, flags
);
303 return amdgpu_bo_create_restricted(adev
, size
, byte_align
, kernel
,
304 domain
, flags
, sg
, &placement
,
308 int amdgpu_bo_kmap(struct amdgpu_bo
*bo
, void **ptr
)
313 if (bo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
)
323 r
= reservation_object_wait_timeout_rcu(bo
->tbo
.resv
, false, false,
324 MAX_SCHEDULE_TIMEOUT
);
328 r
= ttm_bo_kmap(&bo
->tbo
, 0, bo
->tbo
.num_pages
, &bo
->kmap
);
332 bo
->kptr
= ttm_kmap_obj_virtual(&bo
->kmap
, &is_iomem
);
339 void amdgpu_bo_kunmap(struct amdgpu_bo
*bo
)
341 if (bo
->kptr
== NULL
)
344 ttm_bo_kunmap(&bo
->kmap
);
347 struct amdgpu_bo
*amdgpu_bo_ref(struct amdgpu_bo
*bo
)
352 ttm_bo_reference(&bo
->tbo
);
356 void amdgpu_bo_unref(struct amdgpu_bo
**bo
)
358 struct ttm_buffer_object
*tbo
;
369 int amdgpu_bo_pin_restricted(struct amdgpu_bo
*bo
, u32 domain
,
370 u64 min_offset
, u64 max_offset
,
376 if (amdgpu_ttm_tt_get_usermm(bo
->tbo
.ttm
))
379 if (WARN_ON_ONCE(min_offset
> max_offset
))
385 *gpu_addr
= amdgpu_bo_gpu_offset(bo
);
387 if (max_offset
!= 0) {
389 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
)
390 domain_start
= bo
->adev
->mc
.vram_start
;
392 domain_start
= bo
->adev
->mc
.gtt_start
;
393 WARN_ON_ONCE(max_offset
<
394 (amdgpu_bo_gpu_offset(bo
) - domain_start
));
399 amdgpu_ttm_placement_from_domain(bo
, domain
);
400 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
401 /* force to pin into visible video ram */
402 if ((bo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
403 !(bo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
) &&
404 (!max_offset
|| max_offset
> bo
->adev
->mc
.visible_vram_size
)) {
405 if (WARN_ON_ONCE(min_offset
>
406 bo
->adev
->mc
.visible_vram_size
))
408 fpfn
= min_offset
>> PAGE_SHIFT
;
409 lpfn
= bo
->adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
411 fpfn
= min_offset
>> PAGE_SHIFT
;
412 lpfn
= max_offset
>> PAGE_SHIFT
;
414 if (fpfn
> bo
->placements
[i
].fpfn
)
415 bo
->placements
[i
].fpfn
= fpfn
;
416 if (!bo
->placements
[i
].lpfn
||
417 (lpfn
&& lpfn
< bo
->placements
[i
].lpfn
))
418 bo
->placements
[i
].lpfn
= lpfn
;
419 bo
->placements
[i
].flags
|= TTM_PL_FLAG_NO_EVICT
;
422 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
423 if (likely(r
== 0)) {
425 if (gpu_addr
!= NULL
)
426 *gpu_addr
= amdgpu_bo_gpu_offset(bo
);
427 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
)
428 bo
->adev
->vram_pin_size
+= amdgpu_bo_size(bo
);
430 bo
->adev
->gart_pin_size
+= amdgpu_bo_size(bo
);
432 dev_err(bo
->adev
->dev
, "%p pin failed\n", bo
);
437 int amdgpu_bo_pin(struct amdgpu_bo
*bo
, u32 domain
, u64
*gpu_addr
)
439 return amdgpu_bo_pin_restricted(bo
, domain
, 0, 0, gpu_addr
);
442 int amdgpu_bo_unpin(struct amdgpu_bo
*bo
)
446 if (!bo
->pin_count
) {
447 dev_warn(bo
->adev
->dev
, "%p unpin not necessary\n", bo
);
453 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
454 bo
->placements
[i
].lpfn
= 0;
455 bo
->placements
[i
].flags
&= ~TTM_PL_FLAG_NO_EVICT
;
457 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
458 if (likely(r
== 0)) {
459 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
460 bo
->adev
->vram_pin_size
-= amdgpu_bo_size(bo
);
462 bo
->adev
->gart_pin_size
-= amdgpu_bo_size(bo
);
464 dev_err(bo
->adev
->dev
, "%p validate failed for unpin\n", bo
);
469 int amdgpu_bo_evict_vram(struct amdgpu_device
*adev
)
471 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
472 if (0 && (adev
->flags
& AMD_IS_APU
)) {
473 /* Useless to evict on IGP chips */
476 return ttm_bo_evict_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
);
479 int amdgpu_bo_init(struct amdgpu_device
*adev
)
481 /* Add an MTRR for the VRAM */
482 adev
->mc
.vram_mtrr
= arch_phys_wc_add(adev
->mc
.aper_base
,
484 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
485 adev
->mc
.mc_vram_size
>> 20,
486 (unsigned long long)adev
->mc
.aper_size
>> 20);
487 DRM_INFO("RAM width %dbits DDR\n",
488 adev
->mc
.vram_width
);
489 return amdgpu_ttm_init(adev
);
492 void amdgpu_bo_fini(struct amdgpu_device
*adev
)
494 amdgpu_ttm_fini(adev
);
495 arch_phys_wc_del(adev
->mc
.vram_mtrr
);
498 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo
*bo
,
499 struct vm_area_struct
*vma
)
501 return ttm_fbdev_mmap(vma
, &bo
->tbo
);
504 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo
*bo
, u64 tiling_flags
)
506 if (AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
) > 6)
509 bo
->tiling_flags
= tiling_flags
;
513 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo
*bo
, u64
*tiling_flags
)
515 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
518 *tiling_flags
= bo
->tiling_flags
;
521 int amdgpu_bo_set_metadata (struct amdgpu_bo
*bo
, void *metadata
,
522 uint32_t metadata_size
, uint64_t flags
)
526 if (!metadata_size
) {
527 if (bo
->metadata_size
) {
529 bo
->metadata_size
= 0;
534 if (metadata
== NULL
)
537 buffer
= kmemdup(metadata
, metadata_size
, GFP_KERNEL
);
542 bo
->metadata_flags
= flags
;
543 bo
->metadata
= buffer
;
544 bo
->metadata_size
= metadata_size
;
549 int amdgpu_bo_get_metadata(struct amdgpu_bo
*bo
, void *buffer
,
550 size_t buffer_size
, uint32_t *metadata_size
,
553 if (!buffer
&& !metadata_size
)
557 if (buffer_size
< bo
->metadata_size
)
560 if (bo
->metadata_size
)
561 memcpy(buffer
, bo
->metadata
, bo
->metadata_size
);
565 *metadata_size
= bo
->metadata_size
;
567 *flags
= bo
->metadata_flags
;
572 void amdgpu_bo_move_notify(struct ttm_buffer_object
*bo
,
573 struct ttm_mem_reg
*new_mem
)
575 struct amdgpu_bo
*rbo
;
577 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo
))
580 rbo
= container_of(bo
, struct amdgpu_bo
, tbo
);
581 amdgpu_vm_bo_invalidate(rbo
->adev
, rbo
);
583 /* update statistics */
587 /* move_notify is called before move happens */
588 amdgpu_update_memory_usage(rbo
->adev
, &bo
->mem
, new_mem
);
591 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object
*bo
)
593 struct amdgpu_device
*adev
;
594 struct amdgpu_bo
*abo
;
595 unsigned long offset
, size
, lpfn
;
598 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo
))
601 abo
= container_of(bo
, struct amdgpu_bo
, tbo
);
603 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
)
606 size
= bo
->mem
.num_pages
<< PAGE_SHIFT
;
607 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
608 if ((offset
+ size
) <= adev
->mc
.visible_vram_size
)
611 /* hurrah the memory is not visible ! */
612 amdgpu_ttm_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_VRAM
);
613 lpfn
= adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
614 for (i
= 0; i
< abo
->placement
.num_placement
; i
++) {
615 /* Force into visible VRAM */
616 if ((abo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
617 (!abo
->placements
[i
].lpfn
|| abo
->placements
[i
].lpfn
> lpfn
))
618 abo
->placements
[i
].lpfn
= lpfn
;
620 r
= ttm_bo_validate(bo
, &abo
->placement
, false, false);
621 if (unlikely(r
== -ENOMEM
)) {
622 amdgpu_ttm_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_GTT
);
623 return ttm_bo_validate(bo
, &abo
->placement
, false, false);
624 } else if (unlikely(r
!= 0)) {
628 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
629 /* this should never happen */
630 if ((offset
+ size
) > adev
->mc
.visible_vram_size
)
637 * amdgpu_bo_fence - add fence to buffer object
639 * @bo: buffer object in question
640 * @fence: fence to add
641 * @shared: true if fence should be added shared
644 void amdgpu_bo_fence(struct amdgpu_bo
*bo
, struct fence
*fence
,
647 struct reservation_object
*resv
= bo
->tbo
.resv
;
650 reservation_object_add_shared_fence(resv
, fence
);
652 reservation_object_add_excl_fence(resv
, fence
);