2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include <drm/amdgpu_drm.h>
37 #include "amdgpu_trace.h"
40 int amdgpu_ttm_init(struct amdgpu_device
*adev
);
41 void amdgpu_ttm_fini(struct amdgpu_device
*adev
);
43 static u64
amdgpu_get_vis_part_size(struct amdgpu_device
*adev
,
44 struct ttm_mem_reg
* mem
)
47 if (mem
->start
<< PAGE_SHIFT
< adev
->mc
.visible_vram_size
) {
48 ret
= (u64
)((mem
->start
<< PAGE_SHIFT
) + mem
->size
) >
49 adev
->mc
.visible_vram_size
?
50 adev
->mc
.visible_vram_size
- (mem
->start
<< PAGE_SHIFT
):
56 static void amdgpu_update_memory_usage(struct amdgpu_device
*adev
,
57 struct ttm_mem_reg
*old_mem
,
58 struct ttm_mem_reg
*new_mem
)
65 switch (new_mem
->mem_type
) {
67 atomic64_add(new_mem
->size
, &adev
->gtt_usage
);
70 atomic64_add(new_mem
->size
, &adev
->vram_usage
);
71 vis_size
= amdgpu_get_vis_part_size(adev
, new_mem
);
72 atomic64_add(vis_size
, &adev
->vram_vis_usage
);
78 switch (old_mem
->mem_type
) {
80 atomic64_sub(old_mem
->size
, &adev
->gtt_usage
);
83 atomic64_sub(old_mem
->size
, &adev
->vram_usage
);
84 vis_size
= amdgpu_get_vis_part_size(adev
, old_mem
);
85 atomic64_sub(vis_size
, &adev
->vram_vis_usage
);
91 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object
*tbo
)
95 bo
= container_of(tbo
, struct amdgpu_bo
, tbo
);
97 amdgpu_update_memory_usage(bo
->adev
, &bo
->tbo
.mem
, NULL
);
98 amdgpu_mn_unregister(bo
);
100 mutex_lock(&bo
->adev
->gem
.mutex
);
101 list_del_init(&bo
->list
);
102 mutex_unlock(&bo
->adev
->gem
.mutex
);
103 drm_gem_object_release(&bo
->gem_base
);
108 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object
*bo
)
110 if (bo
->destroy
== &amdgpu_ttm_bo_destroy
)
115 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo
*rbo
, u32 domain
)
118 rbo
->placement
.placement
= rbo
->placements
;
119 rbo
->placement
.busy_placement
= rbo
->placements
;
121 if (domain
& AMDGPU_GEM_DOMAIN_VRAM
) {
122 if (rbo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
&&
123 rbo
->adev
->mc
.visible_vram_size
< rbo
->adev
->mc
.real_vram_size
) {
124 rbo
->placements
[c
].fpfn
=
125 rbo
->adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
126 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_UNCACHED
|
129 rbo
->placements
[c
].fpfn
= 0;
130 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_UNCACHED
|
134 if (domain
& AMDGPU_GEM_DOMAIN_GTT
) {
135 if (rbo
->flags
& AMDGPU_GEM_CREATE_CPU_GTT_USWC
) {
136 rbo
->placements
[c
].fpfn
= 0;
137 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_TT
|
138 TTM_PL_FLAG_UNCACHED
;
140 rbo
->placements
[c
].fpfn
= 0;
141 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_CACHED
| TTM_PL_FLAG_TT
;
145 if (domain
& AMDGPU_GEM_DOMAIN_CPU
) {
146 if (rbo
->flags
& AMDGPU_GEM_CREATE_CPU_GTT_USWC
) {
147 rbo
->placements
[c
].fpfn
= 0;
148 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_WC
| TTM_PL_FLAG_SYSTEM
|
149 TTM_PL_FLAG_UNCACHED
;
151 rbo
->placements
[c
].fpfn
= 0;
152 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_CACHED
| TTM_PL_FLAG_SYSTEM
;
156 if (domain
& AMDGPU_GEM_DOMAIN_GDS
) {
157 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
160 if (domain
& AMDGPU_GEM_DOMAIN_GWS
) {
161 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
164 if (domain
& AMDGPU_GEM_DOMAIN_OA
) {
165 rbo
->placements
[c
++].flags
= TTM_PL_FLAG_UNCACHED
|
170 rbo
->placements
[c
].fpfn
= 0;
171 rbo
->placements
[c
++].flags
= TTM_PL_MASK_CACHING
|
174 rbo
->placement
.num_placement
= c
;
175 rbo
->placement
.num_busy_placement
= c
;
177 for (i
= 0; i
< c
; i
++) {
178 if ((rbo
->flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
) &&
179 (rbo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
180 !rbo
->placements
[i
].fpfn
)
181 rbo
->placements
[i
].lpfn
=
182 rbo
->adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
184 rbo
->placements
[i
].lpfn
= 0;
188 int amdgpu_bo_create(struct amdgpu_device
*adev
,
189 unsigned long size
, int byte_align
, bool kernel
, u32 domain
, u64 flags
,
190 struct sg_table
*sg
, struct amdgpu_bo
**bo_ptr
)
192 struct amdgpu_bo
*bo
;
193 enum ttm_bo_type type
;
194 unsigned long page_align
;
198 /* VI has a hw bug where VM PTEs have to be allocated in groups of 8.
199 * do this as a temporary workaround
201 if (!(domain
& (AMDGPU_GEM_DOMAIN_GDS
| AMDGPU_GEM_DOMAIN_GWS
| AMDGPU_GEM_DOMAIN_OA
))) {
202 if (adev
->asic_type
>= CHIP_TOPAZ
) {
203 if (byte_align
& 0x7fff)
204 byte_align
= ALIGN(byte_align
, 0x8000);
206 size
= ALIGN(size
, 0x8000);
210 page_align
= roundup(byte_align
, PAGE_SIZE
) >> PAGE_SHIFT
;
211 size
= ALIGN(size
, PAGE_SIZE
);
214 type
= ttm_bo_type_kernel
;
216 type
= ttm_bo_type_sg
;
218 type
= ttm_bo_type_device
;
222 acc_size
= ttm_bo_dma_acc_size(&adev
->mman
.bdev
, size
,
223 sizeof(struct amdgpu_bo
));
225 bo
= kzalloc(sizeof(struct amdgpu_bo
), GFP_KERNEL
);
228 r
= drm_gem_object_init(adev
->ddev
, &bo
->gem_base
, size
);
234 INIT_LIST_HEAD(&bo
->list
);
235 INIT_LIST_HEAD(&bo
->va
);
236 bo
->initial_domain
= domain
& (AMDGPU_GEM_DOMAIN_VRAM
|
237 AMDGPU_GEM_DOMAIN_GTT
|
238 AMDGPU_GEM_DOMAIN_CPU
|
239 AMDGPU_GEM_DOMAIN_GDS
|
240 AMDGPU_GEM_DOMAIN_GWS
|
241 AMDGPU_GEM_DOMAIN_OA
);
244 amdgpu_ttm_placement_from_domain(bo
, domain
);
245 /* Kernel allocation are uninterruptible */
246 down_read(&adev
->pm
.mclk_lock
);
247 r
= ttm_bo_init(&adev
->mman
.bdev
, &bo
->tbo
, size
, type
,
248 &bo
->placement
, page_align
, !kernel
, NULL
,
249 acc_size
, sg
, NULL
, &amdgpu_ttm_bo_destroy
);
250 up_read(&adev
->pm
.mclk_lock
);
251 if (unlikely(r
!= 0)) {
256 trace_amdgpu_bo_create(bo
);
261 int amdgpu_bo_kmap(struct amdgpu_bo
*bo
, void **ptr
)
266 if (bo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
)
275 r
= ttm_bo_kmap(&bo
->tbo
, 0, bo
->tbo
.num_pages
, &bo
->kmap
);
279 bo
->kptr
= ttm_kmap_obj_virtual(&bo
->kmap
, &is_iomem
);
286 void amdgpu_bo_kunmap(struct amdgpu_bo
*bo
)
288 if (bo
->kptr
== NULL
)
291 ttm_bo_kunmap(&bo
->kmap
);
294 struct amdgpu_bo
*amdgpu_bo_ref(struct amdgpu_bo
*bo
)
299 ttm_bo_reference(&bo
->tbo
);
303 void amdgpu_bo_unref(struct amdgpu_bo
**bo
)
305 struct ttm_buffer_object
*tbo
;
316 int amdgpu_bo_pin_restricted(struct amdgpu_bo
*bo
, u32 domain
, u64 max_offset
,
321 if (amdgpu_ttm_tt_has_userptr(bo
->tbo
.ttm
))
327 *gpu_addr
= amdgpu_bo_gpu_offset(bo
);
329 if (max_offset
!= 0) {
332 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
)
333 domain_start
= bo
->adev
->mc
.vram_start
;
335 domain_start
= bo
->adev
->mc
.gtt_start
;
336 WARN_ON_ONCE(max_offset
<
337 (amdgpu_bo_gpu_offset(bo
) - domain_start
));
342 amdgpu_ttm_placement_from_domain(bo
, domain
);
343 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
344 /* force to pin into visible video ram */
345 if ((bo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
346 !(bo
->flags
& AMDGPU_GEM_CREATE_NO_CPU_ACCESS
) &&
347 (!max_offset
|| max_offset
> bo
->adev
->mc
.visible_vram_size
))
348 bo
->placements
[i
].lpfn
=
349 bo
->adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
351 bo
->placements
[i
].lpfn
= max_offset
>> PAGE_SHIFT
;
353 bo
->placements
[i
].flags
|= TTM_PL_FLAG_NO_EVICT
;
356 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
357 if (likely(r
== 0)) {
359 if (gpu_addr
!= NULL
)
360 *gpu_addr
= amdgpu_bo_gpu_offset(bo
);
361 if (domain
== AMDGPU_GEM_DOMAIN_VRAM
)
362 bo
->adev
->vram_pin_size
+= amdgpu_bo_size(bo
);
364 bo
->adev
->gart_pin_size
+= amdgpu_bo_size(bo
);
366 dev_err(bo
->adev
->dev
, "%p pin failed\n", bo
);
371 int amdgpu_bo_pin(struct amdgpu_bo
*bo
, u32 domain
, u64
*gpu_addr
)
373 return amdgpu_bo_pin_restricted(bo
, domain
, 0, gpu_addr
);
376 int amdgpu_bo_unpin(struct amdgpu_bo
*bo
)
380 if (!bo
->pin_count
) {
381 dev_warn(bo
->adev
->dev
, "%p unpin not necessary\n", bo
);
387 for (i
= 0; i
< bo
->placement
.num_placement
; i
++) {
388 bo
->placements
[i
].lpfn
= 0;
389 bo
->placements
[i
].flags
&= ~TTM_PL_FLAG_NO_EVICT
;
391 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);
392 if (likely(r
== 0)) {
393 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
394 bo
->adev
->vram_pin_size
-= amdgpu_bo_size(bo
);
396 bo
->adev
->gart_pin_size
-= amdgpu_bo_size(bo
);
398 dev_err(bo
->adev
->dev
, "%p validate failed for unpin\n", bo
);
403 int amdgpu_bo_evict_vram(struct amdgpu_device
*adev
)
405 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
406 if (0 && (adev
->flags
& AMDGPU_IS_APU
)) {
407 /* Useless to evict on IGP chips */
410 return ttm_bo_evict_mm(&adev
->mman
.bdev
, TTM_PL_VRAM
);
413 void amdgpu_bo_force_delete(struct amdgpu_device
*adev
)
415 struct amdgpu_bo
*bo
, *n
;
417 if (list_empty(&adev
->gem
.objects
)) {
420 dev_err(adev
->dev
, "Userspace still has active objects !\n");
421 list_for_each_entry_safe(bo
, n
, &adev
->gem
.objects
, list
) {
422 mutex_lock(&adev
->ddev
->struct_mutex
);
423 dev_err(adev
->dev
, "%p %p %lu %lu force free\n",
424 &bo
->gem_base
, bo
, (unsigned long)bo
->gem_base
.size
,
425 *((unsigned long *)&bo
->gem_base
.refcount
));
426 mutex_lock(&bo
->adev
->gem
.mutex
);
427 list_del_init(&bo
->list
);
428 mutex_unlock(&bo
->adev
->gem
.mutex
);
429 /* this should unref the ttm bo */
430 drm_gem_object_unreference(&bo
->gem_base
);
431 mutex_unlock(&adev
->ddev
->struct_mutex
);
435 int amdgpu_bo_init(struct amdgpu_device
*adev
)
437 /* Add an MTRR for the VRAM */
438 adev
->mc
.vram_mtrr
= arch_phys_wc_add(adev
->mc
.aper_base
,
440 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
441 adev
->mc
.mc_vram_size
>> 20,
442 (unsigned long long)adev
->mc
.aper_size
>> 20);
443 DRM_INFO("RAM width %dbits DDR\n",
444 adev
->mc
.vram_width
);
445 return amdgpu_ttm_init(adev
);
448 void amdgpu_bo_fini(struct amdgpu_device
*adev
)
450 amdgpu_ttm_fini(adev
);
451 arch_phys_wc_del(adev
->mc
.vram_mtrr
);
454 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo
*bo
,
455 struct vm_area_struct
*vma
)
457 return ttm_fbdev_mmap(vma
, &bo
->tbo
);
460 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo
*bo
, u64 tiling_flags
)
462 if (AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
) > 6)
465 bo
->tiling_flags
= tiling_flags
;
469 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo
*bo
, u64
*tiling_flags
)
471 lockdep_assert_held(&bo
->tbo
.resv
->lock
.base
);
474 *tiling_flags
= bo
->tiling_flags
;
477 int amdgpu_bo_set_metadata (struct amdgpu_bo
*bo
, void *metadata
,
478 uint32_t metadata_size
, uint64_t flags
)
482 if (!metadata_size
) {
483 if (bo
->metadata_size
) {
485 bo
->metadata_size
= 0;
490 if (metadata
== NULL
)
493 buffer
= kzalloc(metadata_size
, GFP_KERNEL
);
497 memcpy(buffer
, metadata
, metadata_size
);
500 bo
->metadata_flags
= flags
;
501 bo
->metadata
= buffer
;
502 bo
->metadata_size
= metadata_size
;
507 int amdgpu_bo_get_metadata(struct amdgpu_bo
*bo
, void *buffer
,
508 size_t buffer_size
, uint32_t *metadata_size
,
511 if (!buffer
&& !metadata_size
)
515 if (buffer_size
< bo
->metadata_size
)
518 if (bo
->metadata_size
)
519 memcpy(buffer
, bo
->metadata
, bo
->metadata_size
);
523 *metadata_size
= bo
->metadata_size
;
525 *flags
= bo
->metadata_flags
;
530 void amdgpu_bo_move_notify(struct ttm_buffer_object
*bo
,
531 struct ttm_mem_reg
*new_mem
)
533 struct amdgpu_bo
*rbo
;
535 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo
))
538 rbo
= container_of(bo
, struct amdgpu_bo
, tbo
);
539 amdgpu_vm_bo_invalidate(rbo
->adev
, rbo
);
541 /* update statistics */
545 /* move_notify is called before move happens */
546 amdgpu_update_memory_usage(rbo
->adev
, &bo
->mem
, new_mem
);
549 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object
*bo
)
551 struct amdgpu_device
*adev
;
552 struct amdgpu_bo
*abo
;
553 unsigned long offset
, size
, lpfn
;
556 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo
))
559 abo
= container_of(bo
, struct amdgpu_bo
, tbo
);
561 if (bo
->mem
.mem_type
!= TTM_PL_VRAM
)
564 size
= bo
->mem
.num_pages
<< PAGE_SHIFT
;
565 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
566 if ((offset
+ size
) <= adev
->mc
.visible_vram_size
)
569 /* hurrah the memory is not visible ! */
570 amdgpu_ttm_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_VRAM
);
571 lpfn
= adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
572 for (i
= 0; i
< abo
->placement
.num_placement
; i
++) {
573 /* Force into visible VRAM */
574 if ((abo
->placements
[i
].flags
& TTM_PL_FLAG_VRAM
) &&
575 (!abo
->placements
[i
].lpfn
|| abo
->placements
[i
].lpfn
> lpfn
))
576 abo
->placements
[i
].lpfn
= lpfn
;
578 r
= ttm_bo_validate(bo
, &abo
->placement
, false, false);
579 if (unlikely(r
== -ENOMEM
)) {
580 amdgpu_ttm_placement_from_domain(abo
, AMDGPU_GEM_DOMAIN_GTT
);
581 return ttm_bo_validate(bo
, &abo
->placement
, false, false);
582 } else if (unlikely(r
!= 0)) {
586 offset
= bo
->mem
.start
<< PAGE_SHIFT
;
587 /* this should never happen */
588 if ((offset
+ size
) > adev
->mc
.visible_vram_size
)
595 * amdgpu_bo_fence - add fence to buffer object
597 * @bo: buffer object in question
598 * @fence: fence to add
599 * @shared: true if fence should be added shared
602 void amdgpu_bo_fence(struct amdgpu_bo
*bo
, struct amdgpu_fence
*fence
,
605 struct reservation_object
*resv
= bo
->tbo
.resv
;
608 reservation_object_add_shared_fence(resv
, &fence
->base
);
610 reservation_object_add_excl_fence(resv
, &fence
->base
);