drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40
  41 int amdgpu_ttm_init(struct amdgpu_device *adev);
  42 void amdgpu_ttm_fini(struct amdgpu_device *adev);
  43
  44 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
  45                                                 struct ttm_mem_reg *mem)
  46 {
  47         if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size)
  48                 return 0;
  49
  50         return ((mem->start << PAGE_SHIFT) + mem->size) >
  51                 adev->mc.visible_vram_size ?
  52                 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
  53                 mem->size;
  54 }
  55
  56 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
  57                        struct ttm_mem_reg *old_mem,
  58                        struct ttm_mem_reg *new_mem)
  59 {
  60         u64 vis_size;
  61         if (!adev)
  62                 return;
  63
  64         if (new_mem) {
  65                 switch (new_mem->mem_type) {
  66                 case TTM_PL_TT:
  67                         atomic64_add(new_mem->size, &adev->gtt_usage);
  68                         break;
  69                 case TTM_PL_VRAM:
  70                         atomic64_add(new_mem->size, &adev->vram_usage);
  71                         vis_size = amdgpu_get_vis_part_size(adev, new_mem);
  72                         atomic64_add(vis_size, &adev->vram_vis_usage);
  73                         break;
  74                 }
  75         }
  76
  77         if (old_mem) {
  78                 switch (old_mem->mem_type) {
  79                 case TTM_PL_TT:
  80                         atomic64_sub(old_mem->size, &adev->gtt_usage);
  81                         break;
  82                 case TTM_PL_VRAM:
  83                         atomic64_sub(old_mem->size, &adev->vram_usage);
  84                         vis_size = amdgpu_get_vis_part_size(adev, old_mem);
  85                         atomic64_sub(vis_size, &adev->vram_vis_usage);
  86                         break;
  87                 }
  88         }
  89 }
  90
  91 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  92 {
  93         struct amdgpu_bo *bo;
  94
  95         bo = container_of(tbo, struct amdgpu_bo, tbo);
  96
  97         amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
  98
  99         drm_gem_object_release(&bo->gem_base);
 100         amdgpu_bo_unref(&bo->parent);
 101         kfree(bo->metadata);
 102         kfree(bo);
 103 }
 104
 105 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 106 {
 107         if (bo->destroy == &amdgpu_ttm_bo_destroy)
 108                 return true;
 109         return false;
 110 }
 111
 112 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 113                                       struct ttm_placement *placement,
 114                                       struct ttm_place *placements,
 115                                       u32 domain, u64 flags)
 116 {
 117         u32 c = 0, i;
 118
 119         placement->placement = placements;
 120         placement->busy_placement = placements;
 121
 122         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 123                 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
 124                         adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 125                         placements[c].fpfn =
 126                                 adev->mc.visible_vram_size >> PAGE_SHIFT;
 127                         placements[c++].flags = TTM_PL_FLAG_WC |
 128                                 TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |
 129                                 TTM_PL_FLAG_TOPDOWN;
 130                 }
 131                 placements[c].fpfn = 0;
 132                 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 133                         TTM_PL_FLAG_VRAM;
 134                 if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
 135                         placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
 136         }
 137
 138         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 139                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 140                         placements[c].fpfn = 0;
 141                         placements[c++].flags = TTM_PL_FLAG_WC |
 142                                 TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
 143                 } else {
 144                         placements[c].fpfn = 0;
 145                         placements[c++].flags = TTM_PL_FLAG_CACHED |
 146                                 TTM_PL_FLAG_TT;
 147                 }
 148         }
 149
 150         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 151                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 152                         placements[c].fpfn = 0;
 153                         placements[c++].flags = TTM_PL_FLAG_WC |
 154                                 TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_UNCACHED;
 155                 } else {
 156                         placements[c].fpfn = 0;
 157                         placements[c++].flags = TTM_PL_FLAG_CACHED |
 158                                 TTM_PL_FLAG_SYSTEM;
 159                 }
 160         }
 161
 162         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 163                 placements[c].fpfn = 0;
 164                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 165                         AMDGPU_PL_FLAG_GDS;
 166         }
 167         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 168                 placements[c].fpfn = 0;
 169                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 170                         AMDGPU_PL_FLAG_GWS;
 171         }
 172         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 173                 placements[c].fpfn = 0;
 174                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 175                         AMDGPU_PL_FLAG_OA;
 176         }
 177
 178         if (!c) {
 179                 placements[c].fpfn = 0;
 180                 placements[c++].flags = TTM_PL_MASK_CACHING |
 181                         TTM_PL_FLAG_SYSTEM;
 182         }
 183         placement->num_placement = c;
 184         placement->num_busy_placement = c;
 185
 186         for (i = 0; i < c; i++) {
 187                 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 188                         (placements[i].flags & TTM_PL_FLAG_VRAM) &&
 189                         !placements[i].fpfn)
 190                         placements[i].lpfn =
 191                                 adev->mc.visible_vram_size >> PAGE_SHIFT;
 192                 else
 193                         placements[i].lpfn = 0;
 194         }
 195 }
 196
 197 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
 198 {
 199         amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
 200                                   rbo->placements, domain, rbo->flags);
 201 }
 202
 203 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
 204                                         struct ttm_placement *placement)
 205 {
 206         BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
 207
 208         memcpy(bo->placements, placement->placement,
 209                placement->num_placement * sizeof(struct ttm_place));
 210         bo->placement.num_placement = placement->num_placement;
 211         bo->placement.num_busy_placement = placement->num_busy_placement;
 212         bo->placement.placement = bo->placements;
 213         bo->placement.busy_placement = bo->placements;
 214 }
 215
 216 /**
 217  * amdgpu_bo_create_kernel - create BO for kernel use
 218  *
 219  * @adev: amdgpu device object
 220  * @size: size for the new BO
 221  * @align: alignment for the new BO
 222  * @domain: where to place it
 223  * @bo_ptr: resulting BO
 224  * @gpu_addr: GPU addr of the pinned BO
 225  * @cpu_addr: optional CPU address mapping
 226  *
 227  * Allocates and pins a BO for kernel internal use.
 228  *
 229  * Returns 0 on success, negative error code otherwise.
 230  */
 231 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 232                             unsigned long size, int align,
 233                             u32 domain, struct amdgpu_bo **bo_ptr,
 234                             u64 *gpu_addr, void **cpu_addr)
 235 {
 236         int r;
 237
 238         r = amdgpu_bo_create(adev, size, align, true, domain,
 239                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 240                              NULL, NULL, bo_ptr);
 241         if (r) {
 242                 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r);
 243                 return r;
 244         }
 245
 246         r = amdgpu_bo_reserve(*bo_ptr, false);
 247         if (r) {
 248                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 249                 goto error_free;
 250         }
 251
 252         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 253         if (r) {
 254                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 255                 goto error_unreserve;
 256         }
 257
 258         if (cpu_addr) {
 259                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 260                 if (r) {
 261                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 262                         goto error_unreserve;
 263                 }
 264         }
 265
 266         amdgpu_bo_unreserve(*bo_ptr);
 267
 268         return 0;
 269
 270 error_unreserve:
 271         amdgpu_bo_unreserve(*bo_ptr);
 272
 273 error_free:
 274         amdgpu_bo_unref(bo_ptr);
 275
 276         return r;
 277 }
 278
 279 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 280                                 unsigned long size, int byte_align,
 281                                 bool kernel, u32 domain, u64 flags,
 282                                 struct sg_table *sg,
 283                                 struct ttm_placement *placement,
 284                                 struct reservation_object *resv,
 285                                 struct amdgpu_bo **bo_ptr)
 286 {
 287         struct amdgpu_bo *bo;
 288         enum ttm_bo_type type;
 289         unsigned long page_align;
 290         size_t acc_size;
 291         int r;
 292
 293         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 294         size = ALIGN(size, PAGE_SIZE);
 295
 296         if (kernel) {
 297                 type = ttm_bo_type_kernel;
 298         } else if (sg) {
 299                 type = ttm_bo_type_sg;
 300         } else {
 301                 type = ttm_bo_type_device;
 302         }
 303         *bo_ptr = NULL;
 304
 305         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 306                                        sizeof(struct amdgpu_bo));
 307
 308         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 309         if (bo == NULL)
 310                 return -ENOMEM;
 311         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 312         if (unlikely(r)) {
 313                 kfree(bo);
 314                 return r;
 315         }
 316         bo->adev = adev;
 317         INIT_LIST_HEAD(&bo->list);
 318         INIT_LIST_HEAD(&bo->va);
 319         bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 320                                          AMDGPU_GEM_DOMAIN_GTT |
 321                                          AMDGPU_GEM_DOMAIN_CPU |
 322                                          AMDGPU_GEM_DOMAIN_GDS |
 323                                          AMDGPU_GEM_DOMAIN_GWS |
 324                                          AMDGPU_GEM_DOMAIN_OA);
 325         bo->allowed_domains = bo->prefered_domains;
 326         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 327                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 328
 329         bo->flags = flags;
 330
 331         /* For architectures that don't support WC memory,
 332          * mask out the WC flag from the BO
 333          */
 334         if (!drm_arch_can_wc_memory())
 335                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 336
 337         amdgpu_fill_placement_to_bo(bo, placement);
 338         /* Kernel allocation are uninterruptible */
 339         r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
 340                         &bo->placement, page_align, !kernel, NULL,
 341                         acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 342         if (unlikely(r != 0)) {
 343                 return r;
 344         }
 345
 346         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 347             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 348                 struct fence *fence;
 349
 350                 if (adev->mman.buffer_funcs_ring == NULL ||
 351                    !adev->mman.buffer_funcs_ring->ready) {
 352                         r = -EBUSY;
 353                         goto fail_free;
 354                 }
 355
 356                 r = amdgpu_bo_reserve(bo, false);
 357                 if (unlikely(r != 0))
 358                         goto fail_free;
 359
 360                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 361                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 362                 if (unlikely(r != 0))
 363                         goto fail_unreserve;
 364
 365                 amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 366                 amdgpu_bo_fence(bo, fence, false);
 367                 amdgpu_bo_unreserve(bo);
 368                 fence_put(bo->tbo.moving);
 369                 bo->tbo.moving = fence_get(fence);
 370                 fence_put(fence);
 371         }
 372         *bo_ptr = bo;
 373
 374         trace_amdgpu_bo_create(bo);
 375
 376         return 0;
 377
 378 fail_unreserve:
 379         amdgpu_bo_unreserve(bo);
 380 fail_free:
 381         amdgpu_bo_unref(&bo);
 382         return r;
 383 }
 384
 385 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 386                                    unsigned long size, int byte_align,
 387                                    struct amdgpu_bo *bo)
 388 {
 389         struct ttm_placement placement = {0};
 390         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 391         int r;
 392
 393         if (bo->shadow)
 394                 return 0;
 395
 396         bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
 397         memset(&placements, 0,
 398                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 399
 400         amdgpu_ttm_placement_init(adev, &placement,
 401                                   placements, AMDGPU_GEM_DOMAIN_GTT,
 402                                   AMDGPU_GEM_CREATE_CPU_GTT_USWC);
 403
 404         r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
 405                                         AMDGPU_GEM_DOMAIN_GTT,
 406                                         AMDGPU_GEM_CREATE_CPU_GTT_USWC,
 407                                         NULL, &placement,
 408                                         bo->tbo.resv,
 409                                         &bo->shadow);
 410         if (!r)
 411                 bo->shadow->parent = amdgpu_bo_ref(bo);
 412
 413         return r;
 414 }
 415
 416 int amdgpu_bo_create(struct amdgpu_device *adev,
 417                      unsigned long size, int byte_align,
 418                      bool kernel, u32 domain, u64 flags,
 419                      struct sg_table *sg,
 420                      struct reservation_object *resv,
 421                      struct amdgpu_bo **bo_ptr)
 422 {
 423         struct ttm_placement placement = {0};
 424         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 425         int r;
 426
 427         memset(&placements, 0,
 428                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 429
 430         amdgpu_ttm_placement_init(adev, &placement,
 431                                   placements, domain, flags);
 432
 433         r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
 434                                         domain, flags, sg, &placement,
 435                                         resv, bo_ptr);
 436         if (r)
 437                 return r;
 438
 439         if (flags & AMDGPU_GEM_CREATE_SHADOW) {
 440                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 441                 if (r)
 442                         amdgpu_bo_unref(bo_ptr);
 443         }
 444
 445         return r;
 446 }
 447
 448 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 449 {
 450         bool is_iomem;
 451         long r;
 452
 453         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 454                 return -EPERM;
 455
 456         if (bo->kptr) {
 457                 if (ptr) {
 458                         *ptr = bo->kptr;
 459                 }
 460                 return 0;
 461         }
 462
 463         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 464                                                 MAX_SCHEDULE_TIMEOUT);
 465         if (r < 0)
 466                 return r;
 467
 468         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 469         if (r)
 470                 return r;
 471
 472         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 473         if (ptr)
 474                 *ptr = bo->kptr;
 475
 476         return 0;
 477 }
 478
 479 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 480 {
 481         if (bo->kptr == NULL)
 482                 return;
 483         bo->kptr = NULL;
 484         ttm_bo_kunmap(&bo->kmap);
 485 }
 486
 487 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 488 {
 489         if (bo == NULL)
 490                 return NULL;
 491
 492         ttm_bo_reference(&bo->tbo);
 493         return bo;
 494 }
 495
 496 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 497 {
 498         struct ttm_buffer_object *tbo;
 499
 500         if ((*bo) == NULL)
 501                 return;
 502
 503         tbo = &((*bo)->tbo);
 504         ttm_bo_unref(&tbo);
 505         if (tbo == NULL)
 506                 *bo = NULL;
 507 }
 508
 509 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 510                              u64 min_offset, u64 max_offset,
 511                              u64 *gpu_addr)
 512 {
 513         int r, i;
 514         unsigned fpfn, lpfn;
 515
 516         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 517                 return -EPERM;
 518
 519         if (WARN_ON_ONCE(min_offset > max_offset))
 520                 return -EINVAL;
 521
 522         if (bo->pin_count) {
 523                 bo->pin_count++;
 524                 if (gpu_addr)
 525                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 526
 527                 if (max_offset != 0) {
 528                         u64 domain_start;
 529                         if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 530                                 domain_start = bo->adev->mc.vram_start;
 531                         else
 532                                 domain_start = bo->adev->mc.gtt_start;
 533                         WARN_ON_ONCE(max_offset <
 534                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 535                 }
 536
 537                 return 0;
 538         }
 539         amdgpu_ttm_placement_from_domain(bo, domain);
 540         for (i = 0; i < bo->placement.num_placement; i++) {
 541                 /* force to pin into visible video ram */
 542                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 543                     !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 544                     (!max_offset || max_offset >
 545                      bo->adev->mc.visible_vram_size)) {
 546                         if (WARN_ON_ONCE(min_offset >
 547                                          bo->adev->mc.visible_vram_size))
 548                                 return -EINVAL;
 549                         fpfn = min_offset >> PAGE_SHIFT;
 550                         lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
 551                 } else {
 552                         fpfn = min_offset >> PAGE_SHIFT;
 553                         lpfn = max_offset >> PAGE_SHIFT;
 554                 }
 555                 if (fpfn > bo->placements[i].fpfn)
 556                         bo->placements[i].fpfn = fpfn;
 557                 if (!bo->placements[i].lpfn ||
 558                     (lpfn && lpfn < bo->placements[i].lpfn))
 559                         bo->placements[i].lpfn = lpfn;
 560                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 561         }
 562
 563         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 564         if (unlikely(r)) {
 565                 dev_err(bo->adev->dev, "%p pin failed\n", bo);
 566                 goto error;
 567         }
 568
 569         bo->pin_count = 1;
 570         if (gpu_addr != NULL)
 571                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 572         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 573                 bo->adev->vram_pin_size += amdgpu_bo_size(bo);
 574                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 575                         bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
 576         } else {
 577                 bo->adev->gart_pin_size += amdgpu_bo_size(bo);
 578         }
 579
 580 error:
 581         return r;
 582 }
 583
 584 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 585 {
 586         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 587 }
 588
 589 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 590 {
 591         int r, i;
 592
 593         if (!bo->pin_count) {
 594                 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
 595                 return 0;
 596         }
 597         bo->pin_count--;
 598         if (bo->pin_count)
 599                 return 0;
 600         for (i = 0; i < bo->placement.num_placement; i++) {
 601                 bo->placements[i].lpfn = 0;
 602                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 603         }
 604         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 605         if (unlikely(r)) {
 606                 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
 607                 goto error;
 608         }
 609
 610         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 611                 bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
 612                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 613                         bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
 614         } else {
 615                 bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
 616         }
 617
 618 error:
 619         return r;
 620 }
 621
 622 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 623 {
 624         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 625         if (0 && (adev->flags & AMD_IS_APU)) {
 626                 /* Useless to evict on IGP chips */
 627                 return 0;
 628         }
 629         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 630 }
 631
 632 static const char *amdgpu_vram_names[] = {
 633         "UNKNOWN",
 634         "GDDR1",
 635         "DDR2",
 636         "GDDR3",
 637         "GDDR4",
 638         "GDDR5",
 639         "HBM",
 640         "DDR3"
 641 };
 642
 643 int amdgpu_bo_init(struct amdgpu_device *adev)
 644 {
 645         /* Add an MTRR for the VRAM */
 646         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 647                                               adev->mc.aper_size);
 648         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 649                 adev->mc.mc_vram_size >> 20,
 650                 (unsigned long long)adev->mc.aper_size >> 20);
 651         DRM_INFO("RAM width %dbits %s\n",
 652                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 653         return amdgpu_ttm_init(adev);
 654 }
 655
 656 void amdgpu_bo_fini(struct amdgpu_device *adev)
 657 {
 658         amdgpu_ttm_fini(adev);
 659         arch_phys_wc_del(adev->mc.vram_mtrr);
 660 }
 661
 662 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 663                              struct vm_area_struct *vma)
 664 {
 665         return ttm_fbdev_mmap(vma, &bo->tbo);
 666 }
 667
 668 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 669 {
 670         if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 671                 return -EINVAL;
 672
 673         bo->tiling_flags = tiling_flags;
 674         return 0;
 675 }
 676
 677 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 678 {
 679         lockdep_assert_held(&bo->tbo.resv->lock.base);
 680
 681         if (tiling_flags)
 682                 *tiling_flags = bo->tiling_flags;
 683 }
 684
 685 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 686                             uint32_t metadata_size, uint64_t flags)
 687 {
 688         void *buffer;
 689
 690         if (!metadata_size) {
 691                 if (bo->metadata_size) {
 692                         kfree(bo->metadata);
 693                         bo->metadata = NULL;
 694                         bo->metadata_size = 0;
 695                 }
 696                 return 0;
 697         }
 698
 699         if (metadata == NULL)
 700                 return -EINVAL;
 701
 702         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 703         if (buffer == NULL)
 704                 return -ENOMEM;
 705
 706         kfree(bo->metadata);
 707         bo->metadata_flags = flags;
 708         bo->metadata = buffer;
 709         bo->metadata_size = metadata_size;
 710
 711         return 0;
 712 }
 713
 714 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 715                            size_t buffer_size, uint32_t *metadata_size,
 716                            uint64_t *flags)
 717 {
 718         if (!buffer && !metadata_size)
 719                 return -EINVAL;
 720
 721         if (buffer) {
 722                 if (buffer_size < bo->metadata_size)
 723                         return -EINVAL;
 724
 725                 if (bo->metadata_size)
 726                         memcpy(buffer, bo->metadata, bo->metadata_size);
 727         }
 728
 729         if (metadata_size)
 730                 *metadata_size = bo->metadata_size;
 731         if (flags)
 732                 *flags = bo->metadata_flags;
 733
 734         return 0;
 735 }
 736
 737 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 738                            struct ttm_mem_reg *new_mem)
 739 {
 740         struct amdgpu_bo *rbo;
 741         struct ttm_mem_reg *old_mem = &bo->mem;
 742
 743         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 744                 return;
 745
 746         rbo = container_of(bo, struct amdgpu_bo, tbo);
 747         amdgpu_vm_bo_invalidate(rbo->adev, rbo);
 748
 749         /* update statistics */
 750         if (!new_mem)
 751                 return;
 752
 753         /* move_notify is called before move happens */
 754         amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
 755
 756         trace_amdgpu_ttm_bo_move(rbo, new_mem->mem_type, old_mem->mem_type);
 757 }
 758
 759 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 760 {
 761         struct amdgpu_device *adev;
 762         struct amdgpu_bo *abo;
 763         unsigned long offset, size, lpfn;
 764         int i, r;
 765
 766         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 767                 return 0;
 768
 769         abo = container_of(bo, struct amdgpu_bo, tbo);
 770         adev = abo->adev;
 771         if (bo->mem.mem_type != TTM_PL_VRAM)
 772                 return 0;
 773
 774         size = bo->mem.num_pages << PAGE_SHIFT;
 775         offset = bo->mem.start << PAGE_SHIFT;
 776         if ((offset + size) <= adev->mc.visible_vram_size)
 777                 return 0;
 778
 779         /* Can't move a pinned BO to visible VRAM */
 780         if (abo->pin_count > 0)
 781                 return -EINVAL;
 782
 783         /* hurrah the memory is not visible ! */
 784         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
 785         lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
 786         for (i = 0; i < abo->placement.num_placement; i++) {
 787                 /* Force into visible VRAM */
 788                 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 789                     (!abo->placements[i].lpfn ||
 790                      abo->placements[i].lpfn > lpfn))
 791                         abo->placements[i].lpfn = lpfn;
 792         }
 793         r = ttm_bo_validate(bo, &abo->placement, false, false);
 794         if (unlikely(r == -ENOMEM)) {
 795                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 796                 return ttm_bo_validate(bo, &abo->placement, false, false);
 797         } else if (unlikely(r != 0)) {
 798                 return r;
 799         }
 800
 801         offset = bo->mem.start << PAGE_SHIFT;
 802         /* this should never happen */
 803         if ((offset + size) > adev->mc.visible_vram_size)
 804                 return -EINVAL;
 805
 806         return 0;
 807 }
 808
 809 /**
 810  * amdgpu_bo_fence - add fence to buffer object
 811  *
 812  * @bo: buffer object in question
 813  * @fence: fence to add
 814  * @shared: true if fence should be added shared
 815  *
 816  */
 817 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
 818                      bool shared)
 819 {
 820         struct reservation_object *resv = bo->tbo.resv;
 821
 822         if (shared)
 823                 reservation_object_add_shared_fence(resv, fence);
 824         else
 825                 reservation_object_add_excl_fence(resv, fence);
 826 }
 827
 828 /**
 829  * amdgpu_bo_gpu_offset - return GPU offset of bo
 830  * @bo: amdgpu object for which we query the offset
 831  *
 832  * Returns current GPU offset of the object.
 833  *
 834  * Note: object should either be pinned or reserved when calling this
 835  * function, it might be useful to add check for this for debugging.
 836  */
 837 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 838 {
 839         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
 840         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
 841                      !bo->pin_count);
 842
 843         return bo->tbo.offset;
 844 }