drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include "atom.h"
  26 #include "amdgpu.h"
  27 #include "amd_shared.h"
  28 #include <linux/module.h>
  29 #include <linux/moduleparam.h>
  30 #include "amdgpu_pm.h"
  31 #include <drm/amdgpu_drm.h>
  32 #include "amdgpu_powerplay.h"
  33 #include "cik_dpm.h"
  34 #include "vi_dpm.h"
  35
  36 static int amdgpu_powerplay_init(struct amdgpu_device *adev)
  37 {
  38         int ret = 0;
  39         struct amd_powerplay *amd_pp;
  40
  41         amd_pp = &(adev->powerplay);
  42
  43         if (adev->pp_enabled) {
  44 #ifdef CONFIG_DRM_AMD_POWERPLAY
  45                 struct amd_pp_init *pp_init;
  46
  47                 pp_init = kzalloc(sizeof(struct amd_pp_init), GFP_KERNEL);
  48
  49                 if (pp_init == NULL)
  50                         return -ENOMEM;
  51
  52                 pp_init->chip_family = adev->family;
  53                 pp_init->chip_id = adev->asic_type;
  54                 pp_init->device = amdgpu_cgs_create_device(adev);
  55                 pp_init->rev_id = adev->pdev->revision;
  56                 pp_init->sub_sys_id = adev->pdev->subsystem_device;
  57                 pp_init->sub_vendor_id = adev->pdev->subsystem_vendor;
  58
  59                 ret = amd_powerplay_init(pp_init, amd_pp);
  60                 kfree(pp_init);
  61 #endif
  62         } else {
  63                 amd_pp->pp_handle = (void *)adev;
  64
  65                 switch (adev->asic_type) {
  66 #ifdef CONFIG_DRM_AMDGPU_CIK
  67                 case CHIP_BONAIRE:
  68                 case CHIP_HAWAII:
  69                         amd_pp->ip_funcs = &ci_dpm_ip_funcs;
  70                         break;
  71                 case CHIP_KABINI:
  72                 case CHIP_MULLINS:
  73                 case CHIP_KAVERI:
  74                         amd_pp->ip_funcs = &kv_dpm_ip_funcs;
  75                         break;
  76 #endif
  77                 case CHIP_TOPAZ:
  78                         amd_pp->ip_funcs = &iceland_dpm_ip_funcs;
  79                         break;
  80                 case CHIP_TONGA:
  81                         amd_pp->ip_funcs = &tonga_dpm_ip_funcs;
  82                         break;
  83                 case CHIP_FIJI:
  84                         amd_pp->ip_funcs = &fiji_dpm_ip_funcs;
  85                         break;
  86                 case CHIP_CARRIZO:
  87                 case CHIP_STONEY:
  88                         amd_pp->ip_funcs = &cz_dpm_ip_funcs;
  89                         break;
  90                 default:
  91                         ret = -EINVAL;
  92                         break;
  93                 }
  94         }
  95         return ret;
  96 }
  97
  98 static int amdgpu_pp_early_init(void *handle)
  99 {
 100         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 101         int ret = 0;
 102
 103 #ifdef CONFIG_DRM_AMD_POWERPLAY
 104         switch (adev->asic_type) {
 105         case CHIP_POLARIS11:
 106         case CHIP_POLARIS10:
 107                 adev->pp_enabled = true;
 108                 break;
 109         case CHIP_TONGA:
 110         case CHIP_FIJI:
 111         case CHIP_TOPAZ:
 112                 adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true;
 113                 break;
 114         case CHIP_CARRIZO:
 115         case CHIP_STONEY:
 116                 adev->pp_enabled = (amdgpu_powerplay > 0) ? true : false;
 117                 break;
 118         /* These chips don't have powerplay implemenations */
 119         case CHIP_BONAIRE:
 120         case CHIP_HAWAII:
 121         case CHIP_KABINI:
 122         case CHIP_MULLINS:
 123         case CHIP_KAVERI:
 124         default:
 125                 adev->pp_enabled = false;
 126                 break;
 127         }
 128 #else
 129         adev->pp_enabled = false;
 130 #endif
 131
 132         ret = amdgpu_powerplay_init(adev);
 133         if (ret)
 134                 return ret;
 135
 136         if (adev->powerplay.ip_funcs->early_init)
 137                 ret = adev->powerplay.ip_funcs->early_init(
 138                                         adev->powerplay.pp_handle);
 139         return ret;
 140 }
 141
 142
 143 static int amdgpu_pp_late_init(void *handle)
 144 {
 145         int ret = 0;
 146         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 147
 148         if (adev->powerplay.ip_funcs->late_init)
 149                 ret = adev->powerplay.ip_funcs->late_init(
 150                                         adev->powerplay.pp_handle);
 151
 152 #ifdef CONFIG_DRM_AMD_POWERPLAY
 153         if (adev->pp_enabled && adev->pm.dpm_enabled) {
 154                 amdgpu_pm_sysfs_init(adev);
 155                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
 156         }
 157 #endif
 158         return ret;
 159 }
 160
 161 static int amdgpu_pp_sw_init(void *handle)
 162 {
 163         int ret = 0;
 164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 165
 166         if (adev->powerplay.ip_funcs->sw_init)
 167                 ret = adev->powerplay.ip_funcs->sw_init(
 168                                         adev->powerplay.pp_handle);
 169
 170 #ifdef CONFIG_DRM_AMD_POWERPLAY
 171         if (adev->pp_enabled)
 172                 adev->pm.dpm_enabled = true;
 173 #endif
 174
 175         return ret;
 176 }
 177
 178 static int amdgpu_pp_sw_fini(void *handle)
 179 {
 180         int ret = 0;
 181         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 182
 183         if (adev->powerplay.ip_funcs->sw_fini)
 184                 ret = adev->powerplay.ip_funcs->sw_fini(
 185                                         adev->powerplay.pp_handle);
 186         if (ret)
 187                 return ret;
 188
 189         return ret;
 190 }
 191
 192 static int amdgpu_pp_hw_init(void *handle)
 193 {
 194         int ret = 0;
 195         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 196
 197         if (adev->pp_enabled && adev->firmware.smu_load)
 198                 amdgpu_ucode_init_bo(adev);
 199
 200         if (adev->powerplay.ip_funcs->hw_init)
 201                 ret = adev->powerplay.ip_funcs->hw_init(
 202                                         adev->powerplay.pp_handle);
 203
 204         return ret;
 205 }
 206
 207 static int amdgpu_pp_hw_fini(void *handle)
 208 {
 209         int ret = 0;
 210         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 211
 212         if (adev->powerplay.ip_funcs->hw_fini)
 213                 ret = adev->powerplay.ip_funcs->hw_fini(
 214                                         adev->powerplay.pp_handle);
 215
 216         if (adev->pp_enabled && adev->firmware.smu_load)
 217                 amdgpu_ucode_fini_bo(adev);
 218
 219         return ret;
 220 }
 221
 222 static void amdgpu_pp_late_fini(void *handle)
 223 {
 224 #ifdef CONFIG_DRM_AMD_POWERPLAY
 225         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 226
 227         if (adev->pp_enabled) {
 228                 amdgpu_pm_sysfs_fini(adev);
 229                 amd_powerplay_fini(adev->powerplay.pp_handle);
 230         }
 231
 232         if (adev->powerplay.ip_funcs->late_fini)
 233                 adev->powerplay.ip_funcs->late_fini(
 234                           adev->powerplay.pp_handle);
 235 #endif
 236 }
 237
 238 static int amdgpu_pp_suspend(void *handle)
 239 {
 240         int ret = 0;
 241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 242
 243         if (adev->powerplay.ip_funcs->suspend)
 244                 ret = adev->powerplay.ip_funcs->suspend(
 245                                          adev->powerplay.pp_handle);
 246         return ret;
 247 }
 248
 249 static int amdgpu_pp_resume(void *handle)
 250 {
 251         int ret = 0;
 252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 253
 254         if (adev->powerplay.ip_funcs->resume)
 255                 ret = adev->powerplay.ip_funcs->resume(
 256                                         adev->powerplay.pp_handle);
 257         return ret;
 258 }
 259
 260 static int amdgpu_pp_set_clockgating_state(void *handle,
 261                                         enum amd_clockgating_state state)
 262 {
 263         int ret = 0;
 264         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 265
 266         if (adev->powerplay.ip_funcs->set_clockgating_state)
 267                 ret = adev->powerplay.ip_funcs->set_clockgating_state(
 268                                 adev->powerplay.pp_handle, state);
 269         return ret;
 270 }
 271
 272 static int amdgpu_pp_set_powergating_state(void *handle,
 273                                         enum amd_powergating_state state)
 274 {
 275         int ret = 0;
 276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 277
 278         if (adev->powerplay.ip_funcs->set_powergating_state)
 279                 ret = adev->powerplay.ip_funcs->set_powergating_state(
 280                                  adev->powerplay.pp_handle, state);
 281         return ret;
 282 }
 283
 284
 285 static bool amdgpu_pp_is_idle(void *handle)
 286 {
 287         bool ret = true;
 288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 289
 290         if (adev->powerplay.ip_funcs->is_idle)
 291                 ret = adev->powerplay.ip_funcs->is_idle(
 292                                         adev->powerplay.pp_handle);
 293         return ret;
 294 }
 295
 296 static int amdgpu_pp_wait_for_idle(void *handle)
 297 {
 298         int ret = 0;
 299         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 300
 301         if (adev->powerplay.ip_funcs->wait_for_idle)
 302                 ret = adev->powerplay.ip_funcs->wait_for_idle(
 303                                         adev->powerplay.pp_handle);
 304         return ret;
 305 }
 306
 307 static int amdgpu_pp_soft_reset(void *handle)
 308 {
 309         int ret = 0;
 310         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 311
 312         if (adev->powerplay.ip_funcs->soft_reset)
 313                 ret = adev->powerplay.ip_funcs->soft_reset(
 314                                         adev->powerplay.pp_handle);
 315         return ret;
 316 }
 317
 318 const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
 319         .name = "amdgpu_powerplay",
 320         .early_init = amdgpu_pp_early_init,
 321         .late_init = amdgpu_pp_late_init,
 322         .sw_init = amdgpu_pp_sw_init,
 323         .sw_fini = amdgpu_pp_sw_fini,
 324         .hw_init = amdgpu_pp_hw_init,
 325         .hw_fini = amdgpu_pp_hw_fini,
 326         .late_fini = amdgpu_pp_late_fini,
 327         .suspend = amdgpu_pp_suspend,
 328         .resume = amdgpu_pp_resume,
 329         .is_idle = amdgpu_pp_is_idle,
 330         .wait_for_idle = amdgpu_pp_wait_for_idle,
 331         .soft_reset = amdgpu_pp_soft_reset,
 332         .set_clockgating_state = amdgpu_pp_set_clockgating_state,
 333         .set_powergating_state = amdgpu_pp_set_powergating_state,
 334 };