2 * Copyright 2013 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vce.h"
38 /* 1 second timeout */
39 #define VCE_IDLE_TIMEOUT msecs_to_jiffies(1000)
42 #ifdef CONFIG_DRM_AMDGPU_CIK
43 #define FIRMWARE_BONAIRE "radeon/bonaire_vce.bin"
44 #define FIRMWARE_KABINI "radeon/kabini_vce.bin"
45 #define FIRMWARE_KAVERI "radeon/kaveri_vce.bin"
46 #define FIRMWARE_HAWAII "radeon/hawaii_vce.bin"
47 #define FIRMWARE_MULLINS "radeon/mullins_vce.bin"
49 #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin"
50 #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin"
51 #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin"
52 #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin"
53 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin"
54 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin"
56 #ifdef CONFIG_DRM_AMDGPU_CIK
57 MODULE_FIRMWARE(FIRMWARE_BONAIRE
);
58 MODULE_FIRMWARE(FIRMWARE_KABINI
);
59 MODULE_FIRMWARE(FIRMWARE_KAVERI
);
60 MODULE_FIRMWARE(FIRMWARE_HAWAII
);
61 MODULE_FIRMWARE(FIRMWARE_MULLINS
);
63 MODULE_FIRMWARE(FIRMWARE_TONGA
);
64 MODULE_FIRMWARE(FIRMWARE_CARRIZO
);
65 MODULE_FIRMWARE(FIRMWARE_FIJI
);
66 MODULE_FIRMWARE(FIRMWARE_STONEY
);
67 MODULE_FIRMWARE(FIRMWARE_POLARIS10
);
68 MODULE_FIRMWARE(FIRMWARE_POLARIS11
);
70 static void amdgpu_vce_idle_work_handler(struct work_struct
*work
);
73 * amdgpu_vce_init - allocate memory, load vce firmware
75 * @adev: amdgpu_device pointer
77 * First step to get VCE online, allocate memory and load the firmware
79 int amdgpu_vce_sw_init(struct amdgpu_device
*adev
, unsigned long size
)
81 struct amdgpu_ring
*ring
;
82 struct amd_sched_rq
*rq
;
84 const struct common_firmware_header
*hdr
;
85 unsigned ucode_version
, version_major
, version_minor
, binary_id
;
88 switch (adev
->asic_type
) {
89 #ifdef CONFIG_DRM_AMDGPU_CIK
91 fw_name
= FIRMWARE_BONAIRE
;
94 fw_name
= FIRMWARE_KAVERI
;
97 fw_name
= FIRMWARE_KABINI
;
100 fw_name
= FIRMWARE_HAWAII
;
103 fw_name
= FIRMWARE_MULLINS
;
107 fw_name
= FIRMWARE_TONGA
;
110 fw_name
= FIRMWARE_CARRIZO
;
113 fw_name
= FIRMWARE_FIJI
;
116 fw_name
= FIRMWARE_STONEY
;
119 fw_name
= FIRMWARE_POLARIS10
;
122 fw_name
= FIRMWARE_POLARIS11
;
129 r
= request_firmware(&adev
->vce
.fw
, fw_name
, adev
->dev
);
131 dev_err(adev
->dev
, "amdgpu_vce: Can't load firmware \"%s\"\n",
136 r
= amdgpu_ucode_validate(adev
->vce
.fw
);
138 dev_err(adev
->dev
, "amdgpu_vce: Can't validate firmware \"%s\"\n",
140 release_firmware(adev
->vce
.fw
);
145 hdr
= (const struct common_firmware_header
*)adev
->vce
.fw
->data
;
147 ucode_version
= le32_to_cpu(hdr
->ucode_version
);
148 version_major
= (ucode_version
>> 20) & 0xfff;
149 version_minor
= (ucode_version
>> 8) & 0xfff;
150 binary_id
= ucode_version
& 0xff;
151 DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n",
152 version_major
, version_minor
, binary_id
);
153 adev
->vce
.fw_version
= ((version_major
<< 24) | (version_minor
<< 16) |
156 /* allocate firmware, stack and heap BO */
158 r
= amdgpu_bo_create(adev
, size
, PAGE_SIZE
, true,
159 AMDGPU_GEM_DOMAIN_VRAM
,
160 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
161 NULL
, NULL
, &adev
->vce
.vcpu_bo
);
163 dev_err(adev
->dev
, "(%d) failed to allocate VCE bo\n", r
);
167 r
= amdgpu_bo_reserve(adev
->vce
.vcpu_bo
, false);
169 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
170 dev_err(adev
->dev
, "(%d) failed to reserve VCE bo\n", r
);
174 r
= amdgpu_bo_pin(adev
->vce
.vcpu_bo
, AMDGPU_GEM_DOMAIN_VRAM
,
175 &adev
->vce
.gpu_addr
);
176 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
178 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
179 dev_err(adev
->dev
, "(%d) VCE bo pin failed\n", r
);
184 ring
= &adev
->vce
.ring
[0];
185 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_NORMAL
];
186 r
= amd_sched_entity_init(&ring
->sched
, &adev
->vce
.entity
,
187 rq
, amdgpu_sched_jobs
);
189 DRM_ERROR("Failed setting up VCE run queue.\n");
193 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
194 atomic_set(&adev
->vce
.handles
[i
], 0);
195 adev
->vce
.filp
[i
] = NULL
;
198 INIT_DELAYED_WORK(&adev
->vce
.idle_work
, amdgpu_vce_idle_work_handler
);
199 mutex_init(&adev
->vce
.idle_mutex
);
205 * amdgpu_vce_fini - free memory
207 * @adev: amdgpu_device pointer
209 * Last step on VCE teardown, free firmware memory
211 int amdgpu_vce_sw_fini(struct amdgpu_device
*adev
)
213 if (adev
->vce
.vcpu_bo
== NULL
)
216 amd_sched_entity_fini(&adev
->vce
.ring
[0].sched
, &adev
->vce
.entity
);
218 amdgpu_bo_unref(&adev
->vce
.vcpu_bo
);
220 amdgpu_ring_fini(&adev
->vce
.ring
[0]);
221 amdgpu_ring_fini(&adev
->vce
.ring
[1]);
223 release_firmware(adev
->vce
.fw
);
224 mutex_destroy(&adev
->vce
.idle_mutex
);
230 * amdgpu_vce_suspend - unpin VCE fw memory
232 * @adev: amdgpu_device pointer
235 int amdgpu_vce_suspend(struct amdgpu_device
*adev
)
239 if (adev
->vce
.vcpu_bo
== NULL
)
242 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
243 if (atomic_read(&adev
->vce
.handles
[i
]))
246 if (i
== AMDGPU_MAX_VCE_HANDLES
)
249 cancel_delayed_work_sync(&adev
->vce
.idle_work
);
250 /* TODO: suspending running encoding sessions isn't supported */
255 * amdgpu_vce_resume - pin VCE fw memory
257 * @adev: amdgpu_device pointer
260 int amdgpu_vce_resume(struct amdgpu_device
*adev
)
263 const struct common_firmware_header
*hdr
;
267 if (adev
->vce
.vcpu_bo
== NULL
)
270 r
= amdgpu_bo_reserve(adev
->vce
.vcpu_bo
, false);
272 dev_err(adev
->dev
, "(%d) failed to reserve VCE bo\n", r
);
276 r
= amdgpu_bo_kmap(adev
->vce
.vcpu_bo
, &cpu_addr
);
278 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
279 dev_err(adev
->dev
, "(%d) VCE map failed\n", r
);
283 hdr
= (const struct common_firmware_header
*)adev
->vce
.fw
->data
;
284 offset
= le32_to_cpu(hdr
->ucode_array_offset_bytes
);
285 memcpy(cpu_addr
, (adev
->vce
.fw
->data
) + offset
,
286 (adev
->vce
.fw
->size
) - offset
);
288 amdgpu_bo_kunmap(adev
->vce
.vcpu_bo
);
290 amdgpu_bo_unreserve(adev
->vce
.vcpu_bo
);
296 * amdgpu_vce_idle_work_handler - power off VCE
298 * @work: pointer to work structure
300 * power of VCE when it's not used any more
302 static void amdgpu_vce_idle_work_handler(struct work_struct
*work
)
304 struct amdgpu_device
*adev
=
305 container_of(work
, struct amdgpu_device
, vce
.idle_work
.work
);
307 if ((amdgpu_fence_count_emitted(&adev
->vce
.ring
[0]) == 0) &&
308 (amdgpu_fence_count_emitted(&adev
->vce
.ring
[1]) == 0)) {
309 if (adev
->pm
.dpm_enabled
) {
310 amdgpu_dpm_enable_vce(adev
, false);
312 amdgpu_asic_set_vce_clocks(adev
, 0, 0);
315 schedule_delayed_work(&adev
->vce
.idle_work
, VCE_IDLE_TIMEOUT
);
320 * amdgpu_vce_ring_begin_use - power up VCE
324 * Make sure VCE is powerd up when we want to use it
326 void amdgpu_vce_ring_begin_use(struct amdgpu_ring
*ring
)
328 struct amdgpu_device
*adev
= ring
->adev
;
331 mutex_lock(&adev
->vce
.idle_mutex
);
332 set_clocks
= !cancel_delayed_work_sync(&adev
->vce
.idle_work
);
334 if (adev
->pm
.dpm_enabled
) {
335 amdgpu_dpm_enable_vce(adev
, true);
337 amdgpu_asic_set_vce_clocks(adev
, 53300, 40000);
340 mutex_unlock(&adev
->vce
.idle_mutex
);
344 * amdgpu_vce_ring_end_use - power VCE down
348 * Schedule work to power VCE down again
350 void amdgpu_vce_ring_end_use(struct amdgpu_ring
*ring
)
352 schedule_delayed_work(&ring
->adev
->vce
.idle_work
, VCE_IDLE_TIMEOUT
);
356 * amdgpu_vce_free_handles - free still open VCE handles
358 * @adev: amdgpu_device pointer
359 * @filp: drm file pointer
361 * Close all VCE handles still open by this file pointer
363 void amdgpu_vce_free_handles(struct amdgpu_device
*adev
, struct drm_file
*filp
)
365 struct amdgpu_ring
*ring
= &adev
->vce
.ring
[0];
367 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
368 uint32_t handle
= atomic_read(&adev
->vce
.handles
[i
]);
370 if (!handle
|| adev
->vce
.filp
[i
] != filp
)
373 r
= amdgpu_vce_get_destroy_msg(ring
, handle
, false, NULL
);
375 DRM_ERROR("Error destroying VCE handle (%d)!\n", r
);
377 adev
->vce
.filp
[i
] = NULL
;
378 atomic_set(&adev
->vce
.handles
[i
], 0);
383 * amdgpu_vce_get_create_msg - generate a VCE create msg
385 * @adev: amdgpu_device pointer
386 * @ring: ring we should submit the msg to
387 * @handle: VCE session handle to use
388 * @fence: optional fence to return
390 * Open up a stream for HW test
392 int amdgpu_vce_get_create_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
393 struct fence
**fence
)
395 const unsigned ib_size_dw
= 1024;
396 struct amdgpu_job
*job
;
397 struct amdgpu_ib
*ib
;
398 struct fence
*f
= NULL
;
402 r
= amdgpu_job_alloc_with_ib(ring
->adev
, ib_size_dw
* 4, &job
);
408 dummy
= ib
->gpu_addr
+ 1024;
410 /* stitch together an VCE create msg */
412 ib
->ptr
[ib
->length_dw
++] = 0x0000000c; /* len */
413 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* session cmd */
414 ib
->ptr
[ib
->length_dw
++] = handle
;
416 if ((ring
->adev
->vce
.fw_version
>> 24) >= 52)
417 ib
->ptr
[ib
->length_dw
++] = 0x00000040; /* len */
419 ib
->ptr
[ib
->length_dw
++] = 0x00000030; /* len */
420 ib
->ptr
[ib
->length_dw
++] = 0x01000001; /* create cmd */
421 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
422 ib
->ptr
[ib
->length_dw
++] = 0x00000042;
423 ib
->ptr
[ib
->length_dw
++] = 0x0000000a;
424 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
425 ib
->ptr
[ib
->length_dw
++] = 0x00000080;
426 ib
->ptr
[ib
->length_dw
++] = 0x00000060;
427 ib
->ptr
[ib
->length_dw
++] = 0x00000100;
428 ib
->ptr
[ib
->length_dw
++] = 0x00000100;
429 ib
->ptr
[ib
->length_dw
++] = 0x0000000c;
430 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
431 if ((ring
->adev
->vce
.fw_version
>> 24) >= 52) {
432 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
433 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
434 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
435 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
438 ib
->ptr
[ib
->length_dw
++] = 0x00000014; /* len */
439 ib
->ptr
[ib
->length_dw
++] = 0x05000005; /* feedback buffer */
440 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(dummy
);
441 ib
->ptr
[ib
->length_dw
++] = dummy
;
442 ib
->ptr
[ib
->length_dw
++] = 0x00000001;
444 for (i
= ib
->length_dw
; i
< ib_size_dw
; ++i
)
447 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, NULL
, &f
);
448 job
->fence
= fence_get(f
);
452 amdgpu_job_free(job
);
454 *fence
= fence_get(f
);
459 amdgpu_job_free(job
);
464 * amdgpu_vce_get_destroy_msg - generate a VCE destroy msg
466 * @adev: amdgpu_device pointer
467 * @ring: ring we should submit the msg to
468 * @handle: VCE session handle to use
469 * @fence: optional fence to return
471 * Close up a stream for HW test or if userspace failed to do so
473 int amdgpu_vce_get_destroy_msg(struct amdgpu_ring
*ring
, uint32_t handle
,
474 bool direct
, struct fence
**fence
)
476 const unsigned ib_size_dw
= 1024;
477 struct amdgpu_job
*job
;
478 struct amdgpu_ib
*ib
;
479 struct fence
*f
= NULL
;
482 r
= amdgpu_job_alloc_with_ib(ring
->adev
, ib_size_dw
* 4, &job
);
488 /* stitch together an VCE destroy msg */
490 ib
->ptr
[ib
->length_dw
++] = 0x0000000c; /* len */
491 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* session cmd */
492 ib
->ptr
[ib
->length_dw
++] = handle
;
494 ib
->ptr
[ib
->length_dw
++] = 0x00000020; /* len */
495 ib
->ptr
[ib
->length_dw
++] = 0x00000002; /* task info */
496 ib
->ptr
[ib
->length_dw
++] = 0xffffffff; /* next task info, set to 0xffffffff if no */
497 ib
->ptr
[ib
->length_dw
++] = 0x00000001; /* destroy session */
498 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
499 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
500 ib
->ptr
[ib
->length_dw
++] = 0xffffffff; /* feedback is not needed, set to 0xffffffff and firmware will not output feedback */
501 ib
->ptr
[ib
->length_dw
++] = 0x00000000;
503 ib
->ptr
[ib
->length_dw
++] = 0x00000008; /* len */
504 ib
->ptr
[ib
->length_dw
++] = 0x02000001; /* destroy cmd */
506 for (i
= ib
->length_dw
; i
< ib_size_dw
; ++i
)
510 r
= amdgpu_ib_schedule(ring
, 1, ib
, NULL
, NULL
, &f
);
511 job
->fence
= fence_get(f
);
515 amdgpu_job_free(job
);
517 r
= amdgpu_job_submit(job
, ring
, &ring
->adev
->vce
.entity
,
518 AMDGPU_FENCE_OWNER_UNDEFINED
, &f
);
524 *fence
= fence_get(f
);
529 amdgpu_job_free(job
);
534 * amdgpu_vce_cs_reloc - command submission relocation
537 * @lo: address of lower dword
538 * @hi: address of higher dword
539 * @size: minimum size
541 * Patch relocation inside command stream with real buffer address
543 static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
,
544 int lo
, int hi
, unsigned size
, uint32_t index
)
546 struct amdgpu_bo_va_mapping
*mapping
;
547 struct amdgpu_bo
*bo
;
550 if (index
== 0xffffffff)
553 addr
= ((uint64_t)amdgpu_get_ib_value(p
, ib_idx
, lo
)) |
554 ((uint64_t)amdgpu_get_ib_value(p
, ib_idx
, hi
)) << 32;
555 addr
+= ((uint64_t)size
) * ((uint64_t)index
);
557 mapping
= amdgpu_cs_find_mapping(p
, addr
, &bo
);
558 if (mapping
== NULL
) {
559 DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
560 addr
, lo
, hi
, size
, index
);
564 if ((addr
+ (uint64_t)size
) >
565 ((uint64_t)mapping
->it
.last
+ 1) * AMDGPU_GPU_PAGE_SIZE
) {
566 DRM_ERROR("BO to small for addr 0x%010Lx %d %d\n",
571 addr
-= ((uint64_t)mapping
->it
.start
) * AMDGPU_GPU_PAGE_SIZE
;
572 addr
+= amdgpu_bo_gpu_offset(bo
);
573 addr
-= ((uint64_t)size
) * ((uint64_t)index
);
575 amdgpu_set_ib_value(p
, ib_idx
, lo
, lower_32_bits(addr
));
576 amdgpu_set_ib_value(p
, ib_idx
, hi
, upper_32_bits(addr
));
582 * amdgpu_vce_validate_handle - validate stream handle
585 * @handle: handle to validate
586 * @allocated: allocated a new handle?
588 * Validates the handle and return the found session index or -EINVAL
589 * we we don't have another free session index.
591 static int amdgpu_vce_validate_handle(struct amdgpu_cs_parser
*p
,
592 uint32_t handle
, uint32_t *allocated
)
596 /* validate the handle */
597 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
598 if (atomic_read(&p
->adev
->vce
.handles
[i
]) == handle
) {
599 if (p
->adev
->vce
.filp
[i
] != p
->filp
) {
600 DRM_ERROR("VCE handle collision detected!\n");
607 /* handle not found try to alloc a new one */
608 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
) {
609 if (!atomic_cmpxchg(&p
->adev
->vce
.handles
[i
], 0, handle
)) {
610 p
->adev
->vce
.filp
[i
] = p
->filp
;
611 p
->adev
->vce
.img_size
[i
] = 0;
612 *allocated
|= 1 << i
;
617 DRM_ERROR("No more free VCE handles!\n");
622 * amdgpu_vce_cs_parse - parse and validate the command stream
627 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser
*p
, uint32_t ib_idx
)
629 struct amdgpu_ib
*ib
= &p
->job
->ibs
[ib_idx
];
630 unsigned fb_idx
= 0, bs_idx
= 0;
631 int session_idx
= -1;
632 uint32_t destroyed
= 0;
633 uint32_t created
= 0;
634 uint32_t allocated
= 0;
635 uint32_t tmp
, handle
= 0;
636 uint32_t *size
= &tmp
;
637 int i
, r
= 0, idx
= 0;
639 while (idx
< ib
->length_dw
) {
640 uint32_t len
= amdgpu_get_ib_value(p
, ib_idx
, idx
);
641 uint32_t cmd
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 1);
643 if ((len
< 8) || (len
& 3)) {
644 DRM_ERROR("invalid VCE command length (%d)!\n", len
);
650 case 0x00000001: /* session */
651 handle
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 2);
652 session_idx
= amdgpu_vce_validate_handle(p
, handle
,
654 if (session_idx
< 0) {
658 size
= &p
->adev
->vce
.img_size
[session_idx
];
661 case 0x00000002: /* task info */
662 fb_idx
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 6);
663 bs_idx
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 7);
666 case 0x01000001: /* create */
667 created
|= 1 << session_idx
;
668 if (destroyed
& (1 << session_idx
)) {
669 destroyed
&= ~(1 << session_idx
);
670 allocated
|= 1 << session_idx
;
672 } else if (!(allocated
& (1 << session_idx
))) {
673 DRM_ERROR("Handle already in use!\n");
678 *size
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 8) *
679 amdgpu_get_ib_value(p
, ib_idx
, idx
+ 10) *
683 case 0x04000001: /* config extension */
684 case 0x04000002: /* pic control */
685 case 0x04000005: /* rate control */
686 case 0x04000007: /* motion estimation */
687 case 0x04000008: /* rdo */
688 case 0x04000009: /* vui */
689 case 0x05000002: /* auxiliary buffer */
692 case 0x03000001: /* encode */
693 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 10, idx
+ 9,
698 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 12, idx
+ 11,
704 case 0x02000001: /* destroy */
705 destroyed
|= 1 << session_idx
;
708 case 0x05000001: /* context buffer */
709 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
715 case 0x05000004: /* video bitstream buffer */
716 tmp
= amdgpu_get_ib_value(p
, ib_idx
, idx
+ 4);
717 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
723 case 0x05000005: /* feedback buffer */
724 r
= amdgpu_vce_cs_reloc(p
, ib_idx
, idx
+ 3, idx
+ 2,
731 DRM_ERROR("invalid VCE command (0x%x)!\n", cmd
);
736 if (session_idx
== -1) {
737 DRM_ERROR("no session command at start of IB\n");
745 if (allocated
& ~created
) {
746 DRM_ERROR("New session without create command!\n");
752 /* No error, free all destroyed handle slots */
755 /* Error during parsing, free all allocated handle slots */
759 for (i
= 0; i
< AMDGPU_MAX_VCE_HANDLES
; ++i
)
761 atomic_set(&p
->adev
->vce
.handles
[i
], 0);
767 * amdgpu_vce_ring_emit_ib - execute indirect buffer
769 * @ring: engine to use
770 * @ib: the IB to execute
773 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring
*ring
, struct amdgpu_ib
*ib
,
774 unsigned vm_id
, bool ctx_switch
)
776 amdgpu_ring_write(ring
, VCE_CMD_IB
);
777 amdgpu_ring_write(ring
, lower_32_bits(ib
->gpu_addr
));
778 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
));
779 amdgpu_ring_write(ring
, ib
->length_dw
);
783 * amdgpu_vce_ring_emit_fence - add a fence command to the ring
785 * @ring: engine to use
789 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
792 WARN_ON(flags
& AMDGPU_FENCE_FLAG_64BIT
);
794 amdgpu_ring_write(ring
, VCE_CMD_FENCE
);
795 amdgpu_ring_write(ring
, addr
);
796 amdgpu_ring_write(ring
, upper_32_bits(addr
));
797 amdgpu_ring_write(ring
, seq
);
798 amdgpu_ring_write(ring
, VCE_CMD_TRAP
);
799 amdgpu_ring_write(ring
, VCE_CMD_END
);
803 * amdgpu_vce_ring_test_ring - test if VCE ring is working
805 * @ring: the engine to test on
808 int amdgpu_vce_ring_test_ring(struct amdgpu_ring
*ring
)
810 struct amdgpu_device
*adev
= ring
->adev
;
811 uint32_t rptr
= amdgpu_ring_get_rptr(ring
);
815 r
= amdgpu_ring_alloc(ring
, 16);
817 DRM_ERROR("amdgpu: vce failed to lock ring %d (%d).\n",
821 amdgpu_ring_write(ring
, VCE_CMD_END
);
822 amdgpu_ring_commit(ring
);
824 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
825 if (amdgpu_ring_get_rptr(ring
) != rptr
)
830 if (i
< adev
->usec_timeout
) {
831 DRM_INFO("ring test on %d succeeded in %d usecs\n",
834 DRM_ERROR("amdgpu: ring %d test failed\n",
843 * amdgpu_vce_ring_test_ib - test if VCE IBs are working
845 * @ring: the engine to test on
848 int amdgpu_vce_ring_test_ib(struct amdgpu_ring
*ring
, long timeout
)
850 struct fence
*fence
= NULL
;
853 /* skip vce ring1 ib test for now, since it's not reliable */
854 if (ring
== &ring
->adev
->vce
.ring
[1])
857 r
= amdgpu_vce_get_create_msg(ring
, 1, NULL
);
859 DRM_ERROR("amdgpu: failed to get create msg (%ld).\n", r
);
863 r
= amdgpu_vce_get_destroy_msg(ring
, 1, true, &fence
);
865 DRM_ERROR("amdgpu: failed to get destroy ib (%ld).\n", r
);
869 r
= fence_wait_timeout(fence
, false, timeout
);
871 DRM_ERROR("amdgpu: IB test timed out.\n");
874 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r
);
876 DRM_INFO("ib test on ring %d succeeded\n", ring
->idx
);