2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * amdgpu_vm_num_pde - return the number of page directory entries
56 * @adev: amdgpu_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
62 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
68 * @adev: amdgpu_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
80 * @vm: vm providing the BOs
81 * @head: head of validation list
83 * Add the page directory to the list of BOs to
84 * validate for command submission (cayman+).
86 struct amdgpu_bo_list_entry
*amdgpu_vm_get_bos(struct amdgpu_device
*adev
,
88 struct list_head
*head
)
90 struct amdgpu_bo_list_entry
*list
;
93 list
= drm_malloc_ab(vm
->max_pde_used
+ 2,
94 sizeof(struct amdgpu_bo_list_entry
));
99 /* add the vm page table to the list */
100 list
[0].robj
= vm
->page_directory
;
101 list
[0].prefered_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
102 list
[0].allowed_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
103 list
[0].priority
= 0;
104 list
[0].tv
.bo
= &vm
->page_directory
->tbo
;
105 list
[0].tv
.shared
= true;
106 list_add(&list
[0].tv
.head
, head
);
108 for (i
= 0, idx
= 1; i
<= vm
->max_pde_used
; i
++) {
109 if (!vm
->page_tables
[i
].bo
)
112 list
[idx
].robj
= vm
->page_tables
[i
].bo
;
113 list
[idx
].prefered_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
114 list
[idx
].allowed_domains
= AMDGPU_GEM_DOMAIN_VRAM
;
115 list
[idx
].priority
= 0;
116 list
[idx
].tv
.bo
= &list
[idx
].robj
->tbo
;
117 list
[idx
].tv
.shared
= true;
118 list_add(&list
[idx
++].tv
.head
, head
);
125 * amdgpu_vm_grab_id - allocate the next free VMID
127 * @vm: vm to allocate id for
128 * @ring: ring we want to submit job to
129 * @sync: sync object where we add dependencies
131 * Allocate an id for the vm, adding fences to the sync obj as necessary.
133 * Global mutex must be locked!
135 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
136 struct amdgpu_sync
*sync
)
138 struct fence
*best
[AMDGPU_MAX_RINGS
] = {};
139 struct amdgpu_vm_id
*vm_id
= &vm
->ids
[ring
->idx
];
140 struct amdgpu_device
*adev
= ring
->adev
;
142 unsigned choices
[2] = {};
145 /* check if the id is still valid */
147 unsigned id
= vm_id
->id
;
150 owner
= atomic_long_read(&adev
->vm_manager
.ids
[id
].owner
);
151 if (owner
== (long)vm
) {
152 trace_amdgpu_vm_grab_id(vm_id
->id
, ring
->idx
);
157 /* we definately need to flush */
158 vm_id
->pd_gpu_addr
= ~0ll;
160 /* skip over VMID 0, since it is the system VM */
161 for (i
= 1; i
< adev
->vm_manager
.nvm
; ++i
) {
162 struct fence
*fence
= adev
->vm_manager
.ids
[i
].active
;
163 struct amdgpu_ring
*fring
;
166 /* found a free one */
168 trace_amdgpu_vm_grab_id(i
, ring
->idx
);
172 fring
= amdgpu_ring_from_fence(fence
);
173 if (best
[fring
->idx
] == NULL
||
174 fence_is_later(best
[fring
->idx
], fence
)) {
175 best
[fring
->idx
] = fence
;
176 choices
[fring
== ring
? 0 : 1] = i
;
180 for (i
= 0; i
< 2; ++i
) {
184 fence
= adev
->vm_manager
.ids
[choices
[i
]].active
;
185 vm_id
->id
= choices
[i
];
187 trace_amdgpu_vm_grab_id(choices
[i
], ring
->idx
);
188 return amdgpu_sync_fence(ring
->adev
, sync
, fence
);
192 /* should never happen */
198 * amdgpu_vm_flush - hardware flush the vm
200 * @ring: ring to use for flush
201 * @vm: vm we want to flush
202 * @updates: last vm update that we waited for
204 * Flush the vm (cayman+).
206 * Global and local mutex must be locked!
208 void amdgpu_vm_flush(struct amdgpu_ring
*ring
,
209 struct amdgpu_vm
*vm
,
210 struct fence
*updates
)
212 uint64_t pd_addr
= amdgpu_bo_gpu_offset(vm
->page_directory
);
213 struct amdgpu_vm_id
*vm_id
= &vm
->ids
[ring
->idx
];
214 struct fence
*flushed_updates
= vm_id
->flushed_updates
;
217 if (!flushed_updates
)
222 is_later
= fence_is_later(updates
, flushed_updates
);
224 if (pd_addr
!= vm_id
->pd_gpu_addr
|| is_later
) {
225 trace_amdgpu_vm_flush(pd_addr
, ring
->idx
, vm_id
->id
);
227 vm_id
->flushed_updates
= fence_get(updates
);
228 fence_put(flushed_updates
);
230 vm_id
->pd_gpu_addr
= pd_addr
;
231 amdgpu_ring_emit_vm_flush(ring
, vm_id
->id
, vm_id
->pd_gpu_addr
);
236 * amdgpu_vm_fence - remember fence for vm
238 * @adev: amdgpu_device pointer
239 * @vm: vm we want to fence
240 * @fence: fence to remember
242 * Fence the vm (cayman+).
243 * Set the fence used to protect page table and id.
245 * Global and local mutex must be locked!
247 void amdgpu_vm_fence(struct amdgpu_device
*adev
,
248 struct amdgpu_vm
*vm
,
251 struct amdgpu_ring
*ring
= amdgpu_ring_from_fence(fence
);
252 unsigned vm_id
= vm
->ids
[ring
->idx
].id
;
254 fence_put(adev
->vm_manager
.ids
[vm_id
].active
);
255 adev
->vm_manager
.ids
[vm_id
].active
= fence_get(fence
);
256 atomic_long_set(&adev
->vm_manager
.ids
[vm_id
].owner
, (long)vm
);
260 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
263 * @bo: requested buffer object
265 * Find @bo inside the requested vm (cayman+).
266 * Search inside the @bos vm list for the requested vm
267 * Returns the found bo_va or NULL if none is found
269 * Object has to be reserved!
271 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
272 struct amdgpu_bo
*bo
)
274 struct amdgpu_bo_va
*bo_va
;
276 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
277 if (bo_va
->vm
== vm
) {
285 * amdgpu_vm_update_pages - helper to call the right asic function
287 * @adev: amdgpu_device pointer
288 * @ib: indirect buffer to fill with commands
289 * @pe: addr of the page entry
290 * @addr: dst addr to write into pe
291 * @count: number of page entries to update
292 * @incr: increase next addr by incr bytes
293 * @flags: hw access flags
294 * @gtt_flags: GTT hw access flags
296 * Traces the parameters and calls the right asic functions
297 * to setup the page table using the DMA.
299 static void amdgpu_vm_update_pages(struct amdgpu_device
*adev
,
300 struct amdgpu_ib
*ib
,
301 uint64_t pe
, uint64_t addr
,
302 unsigned count
, uint32_t incr
,
303 uint32_t flags
, uint32_t gtt_flags
)
305 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
307 if ((flags
& AMDGPU_PTE_SYSTEM
) && (flags
== gtt_flags
)) {
308 uint64_t src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
309 amdgpu_vm_copy_pte(adev
, ib
, pe
, src
, count
);
311 } else if ((flags
& AMDGPU_PTE_SYSTEM
) || (count
< 3)) {
312 amdgpu_vm_write_pte(adev
, ib
, pe
, addr
,
316 amdgpu_vm_set_pte_pde(adev
, ib
, pe
, addr
,
321 int amdgpu_vm_free_job(struct amdgpu_job
*job
)
324 for (i
= 0; i
< job
->num_ibs
; i
++)
325 amdgpu_ib_free(job
->adev
, &job
->ibs
[i
]);
331 * amdgpu_vm_clear_bo - initially clear the page dir/table
333 * @adev: amdgpu_device pointer
336 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
337 struct amdgpu_bo
*bo
)
339 struct amdgpu_ring
*ring
= adev
->vm_manager
.vm_pte_funcs_ring
;
340 struct fence
*fence
= NULL
;
341 struct amdgpu_ib
*ib
;
346 r
= amdgpu_bo_reserve(bo
, false);
350 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
354 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
356 goto error_unreserve
;
358 addr
= amdgpu_bo_gpu_offset(bo
);
359 entries
= amdgpu_bo_size(bo
) / 8;
361 ib
= kzalloc(sizeof(struct amdgpu_ib
), GFP_KERNEL
);
363 goto error_unreserve
;
365 r
= amdgpu_ib_get(ring
, NULL
, entries
* 2 + 64, ib
);
371 amdgpu_vm_update_pages(adev
, ib
, addr
, 0, entries
, 0, 0, 0);
372 amdgpu_vm_pad_ib(adev
, ib
);
373 WARN_ON(ib
->length_dw
> 64);
374 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, ib
, 1,
376 AMDGPU_FENCE_OWNER_VM
,
379 amdgpu_bo_fence(bo
, fence
, true);
381 if (amdgpu_enable_scheduler
) {
382 amdgpu_bo_unreserve(bo
);
386 amdgpu_ib_free(adev
, ib
);
390 amdgpu_bo_unreserve(bo
);
395 * amdgpu_vm_map_gart - get the physical address of a gart page
397 * @adev: amdgpu_device pointer
398 * @addr: the unmapped addr
400 * Look up the physical address of the page that the pte resolves
402 * Returns the physical address of the page.
404 uint64_t amdgpu_vm_map_gart(struct amdgpu_device
*adev
, uint64_t addr
)
408 /* page table offset */
409 result
= adev
->gart
.pages_addr
[addr
>> PAGE_SHIFT
];
411 /* in case cpu page size != gpu page size*/
412 result
|= addr
& (~PAGE_MASK
);
418 * amdgpu_vm_update_pdes - make sure that page directory is valid
420 * @adev: amdgpu_device pointer
422 * @start: start of GPU address range
423 * @end: end of GPU address range
425 * Allocates new page tables if necessary
426 * and updates the page directory (cayman+).
427 * Returns 0 for success, error for failure.
429 * Global and local mutex must be locked!
431 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
432 struct amdgpu_vm
*vm
)
434 struct amdgpu_ring
*ring
= adev
->vm_manager
.vm_pte_funcs_ring
;
435 struct amdgpu_bo
*pd
= vm
->page_directory
;
436 uint64_t pd_addr
= amdgpu_bo_gpu_offset(pd
);
437 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
438 uint64_t last_pde
= ~0, last_pt
= ~0;
439 unsigned count
= 0, pt_idx
, ndw
;
440 struct amdgpu_ib
*ib
;
441 struct fence
*fence
= NULL
;
448 /* assume the worst case */
449 ndw
+= vm
->max_pde_used
* 6;
451 /* update too big for an IB */
455 ib
= kzalloc(sizeof(struct amdgpu_ib
), GFP_KERNEL
);
459 r
= amdgpu_ib_get(ring
, NULL
, ndw
* 4, ib
);
466 /* walk over the address space and update the page directory */
467 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
468 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].bo
;
474 pt
= amdgpu_bo_gpu_offset(bo
);
475 if (vm
->page_tables
[pt_idx
].addr
== pt
)
477 vm
->page_tables
[pt_idx
].addr
= pt
;
479 pde
= pd_addr
+ pt_idx
* 8;
480 if (((last_pde
+ 8 * count
) != pde
) ||
481 ((last_pt
+ incr
* count
) != pt
)) {
484 amdgpu_vm_update_pages(adev
, ib
, last_pde
,
485 last_pt
, count
, incr
,
486 AMDGPU_PTE_VALID
, 0);
498 amdgpu_vm_update_pages(adev
, ib
, last_pde
, last_pt
, count
,
499 incr
, AMDGPU_PTE_VALID
, 0);
501 if (ib
->length_dw
!= 0) {
502 amdgpu_vm_pad_ib(adev
, ib
);
503 amdgpu_sync_resv(adev
, &ib
->sync
, pd
->tbo
.resv
, AMDGPU_FENCE_OWNER_VM
);
504 WARN_ON(ib
->length_dw
> ndw
);
505 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, ib
, 1,
507 AMDGPU_FENCE_OWNER_VM
,
512 amdgpu_bo_fence(pd
, fence
, true);
513 fence_put(vm
->page_directory_fence
);
514 vm
->page_directory_fence
= fence_get(fence
);
518 if (!amdgpu_enable_scheduler
|| ib
->length_dw
== 0) {
519 amdgpu_ib_free(adev
, ib
);
526 amdgpu_ib_free(adev
, ib
);
532 * amdgpu_vm_frag_ptes - add fragment information to PTEs
534 * @adev: amdgpu_device pointer
535 * @ib: IB for the update
536 * @pe_start: first PTE to handle
537 * @pe_end: last PTE to handle
538 * @addr: addr those PTEs should point to
539 * @flags: hw mapping flags
540 * @gtt_flags: GTT hw mapping flags
542 * Global and local mutex must be locked!
544 static void amdgpu_vm_frag_ptes(struct amdgpu_device
*adev
,
545 struct amdgpu_ib
*ib
,
546 uint64_t pe_start
, uint64_t pe_end
,
547 uint64_t addr
, uint32_t flags
,
551 * The MC L1 TLB supports variable sized pages, based on a fragment
552 * field in the PTE. When this field is set to a non-zero value, page
553 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
554 * flags are considered valid for all PTEs within the fragment range
555 * and corresponding mappings are assumed to be physically contiguous.
557 * The L1 TLB can store a single PTE for the whole fragment,
558 * significantly increasing the space available for translation
559 * caching. This leads to large improvements in throughput when the
560 * TLB is under pressure.
562 * The L2 TLB distributes small and large fragments into two
563 * asymmetric partitions. The large fragment cache is significantly
564 * larger. Thus, we try to use large fragments wherever possible.
565 * Userspace can support this by aligning virtual base address and
566 * allocation size to the fragment size.
569 /* SI and newer are optimized for 64KB */
570 uint64_t frag_flags
= AMDGPU_PTE_FRAG_64KB
;
571 uint64_t frag_align
= 0x80;
573 uint64_t frag_start
= ALIGN(pe_start
, frag_align
);
574 uint64_t frag_end
= pe_end
& ~(frag_align
- 1);
578 /* system pages are non continuously */
579 if ((flags
& AMDGPU_PTE_SYSTEM
) || !(flags
& AMDGPU_PTE_VALID
) ||
580 (frag_start
>= frag_end
)) {
582 count
= (pe_end
- pe_start
) / 8;
583 amdgpu_vm_update_pages(adev
, ib
, pe_start
, addr
, count
,
584 AMDGPU_GPU_PAGE_SIZE
, flags
, gtt_flags
);
588 /* handle the 4K area at the beginning */
589 if (pe_start
!= frag_start
) {
590 count
= (frag_start
- pe_start
) / 8;
591 amdgpu_vm_update_pages(adev
, ib
, pe_start
, addr
, count
,
592 AMDGPU_GPU_PAGE_SIZE
, flags
, gtt_flags
);
593 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
596 /* handle the area in the middle */
597 count
= (frag_end
- frag_start
) / 8;
598 amdgpu_vm_update_pages(adev
, ib
, frag_start
, addr
, count
,
599 AMDGPU_GPU_PAGE_SIZE
, flags
| frag_flags
,
602 /* handle the 4K area at the end */
603 if (frag_end
!= pe_end
) {
604 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
605 count
= (pe_end
- frag_end
) / 8;
606 amdgpu_vm_update_pages(adev
, ib
, frag_end
, addr
, count
,
607 AMDGPU_GPU_PAGE_SIZE
, flags
, gtt_flags
);
612 * amdgpu_vm_update_ptes - make sure that page tables are valid
614 * @adev: amdgpu_device pointer
616 * @start: start of GPU address range
617 * @end: end of GPU address range
618 * @dst: destination address to map to
619 * @flags: mapping flags
621 * Update the page tables in the range @start - @end (cayman+).
623 * Global and local mutex must be locked!
625 static int amdgpu_vm_update_ptes(struct amdgpu_device
*adev
,
626 struct amdgpu_vm
*vm
,
627 struct amdgpu_ib
*ib
,
628 uint64_t start
, uint64_t end
,
629 uint64_t dst
, uint32_t flags
,
632 uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
633 uint64_t last_pte
= ~0, last_dst
= ~0;
634 void *owner
= AMDGPU_FENCE_OWNER_VM
;
638 /* sync to everything on unmapping */
639 if (!(flags
& AMDGPU_PTE_VALID
))
640 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
642 /* walk over the address space and update the page tables */
643 for (addr
= start
; addr
< end
; ) {
644 uint64_t pt_idx
= addr
>> amdgpu_vm_block_size
;
645 struct amdgpu_bo
*pt
= vm
->page_tables
[pt_idx
].bo
;
650 amdgpu_sync_resv(adev
, &ib
->sync
, pt
->tbo
.resv
, owner
);
651 r
= reservation_object_reserve_shared(pt
->tbo
.resv
);
655 if ((addr
& ~mask
) == (end
& ~mask
))
658 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
660 pte
= amdgpu_bo_gpu_offset(pt
);
661 pte
+= (addr
& mask
) * 8;
663 if ((last_pte
+ 8 * count
) != pte
) {
666 amdgpu_vm_frag_ptes(adev
, ib
, last_pte
,
667 last_pte
+ 8 * count
,
680 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
684 amdgpu_vm_frag_ptes(adev
, ib
, last_pte
,
685 last_pte
+ 8 * count
,
686 last_dst
, flags
, gtt_flags
);
693 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
695 * @adev: amdgpu_device pointer
697 * @mapping: mapped range and flags to use for the update
698 * @addr: addr to set the area to
699 * @gtt_flags: flags as they are used for GTT
700 * @fence: optional resulting fence
702 * Fill in the page table entries for @mapping.
703 * Returns 0 for success, -EINVAL for failure.
705 * Object have to be reserved and mutex must be locked!
707 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
708 struct amdgpu_vm
*vm
,
709 struct amdgpu_bo_va_mapping
*mapping
,
710 uint64_t addr
, uint32_t gtt_flags
,
711 struct fence
**fence
)
713 struct amdgpu_ring
*ring
= adev
->vm_manager
.vm_pte_funcs_ring
;
714 unsigned nptes
, ncmds
, ndw
;
715 uint32_t flags
= gtt_flags
;
716 struct amdgpu_ib
*ib
;
717 struct fence
*f
= NULL
;
720 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
721 * but in case of something, we filter the flags in first place
723 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
724 flags
&= ~AMDGPU_PTE_READABLE
;
725 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
726 flags
&= ~AMDGPU_PTE_WRITEABLE
;
728 trace_amdgpu_vm_bo_update(mapping
);
730 nptes
= mapping
->it
.last
- mapping
->it
.start
+ 1;
733 * reserve space for one command every (1 << BLOCK_SIZE)
734 * entries or 2k dwords (whatever is smaller)
736 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
741 if ((flags
& AMDGPU_PTE_SYSTEM
) && (flags
== gtt_flags
)) {
742 /* only copy commands needed */
745 } else if (flags
& AMDGPU_PTE_SYSTEM
) {
746 /* header for write data commands */
749 /* body of write data command */
753 /* set page commands needed */
756 /* two extra commands for begin/end of fragment */
760 /* update too big for an IB */
764 ib
= kzalloc(sizeof(struct amdgpu_ib
), GFP_KERNEL
);
768 r
= amdgpu_ib_get(ring
, NULL
, ndw
* 4, ib
);
776 r
= amdgpu_vm_update_ptes(adev
, vm
, ib
, mapping
->it
.start
,
777 mapping
->it
.last
+ 1, addr
+ mapping
->offset
,
781 amdgpu_ib_free(adev
, ib
);
786 amdgpu_vm_pad_ib(adev
, ib
);
787 WARN_ON(ib
->length_dw
> ndw
);
788 r
= amdgpu_sched_ib_submit_kernel_helper(adev
, ring
, ib
, 1,
790 AMDGPU_FENCE_OWNER_VM
,
795 amdgpu_bo_fence(vm
->page_directory
, f
, true);
798 *fence
= fence_get(f
);
801 if (!amdgpu_enable_scheduler
) {
802 amdgpu_ib_free(adev
, ib
);
808 amdgpu_ib_free(adev
, ib
);
814 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
816 * @adev: amdgpu_device pointer
817 * @bo_va: requested BO and VM object
820 * Fill in the page table entries for @bo_va.
821 * Returns 0 for success, -EINVAL for failure.
823 * Object have to be reserved and mutex must be locked!
825 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
826 struct amdgpu_bo_va
*bo_va
,
827 struct ttm_mem_reg
*mem
)
829 struct amdgpu_vm
*vm
= bo_va
->vm
;
830 struct amdgpu_bo_va_mapping
*mapping
;
836 addr
= (u64
)mem
->start
<< PAGE_SHIFT
;
837 if (mem
->mem_type
!= TTM_PL_TT
)
838 addr
+= adev
->vm_manager
.vram_base_offset
;
843 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
845 spin_lock(&vm
->status_lock
);
846 if (!list_empty(&bo_va
->vm_status
))
847 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
848 spin_unlock(&vm
->status_lock
);
850 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
851 r
= amdgpu_vm_bo_update_mapping(adev
, vm
, mapping
, addr
,
852 flags
, &bo_va
->last_pt_update
);
857 if (trace_amdgpu_vm_bo_mapping_enabled()) {
858 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
859 trace_amdgpu_vm_bo_mapping(mapping
);
861 list_for_each_entry(mapping
, &bo_va
->invalids
, list
)
862 trace_amdgpu_vm_bo_mapping(mapping
);
865 spin_lock(&vm
->status_lock
);
866 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
867 list_del_init(&bo_va
->vm_status
);
869 list_add(&bo_va
->vm_status
, &vm
->cleared
);
870 spin_unlock(&vm
->status_lock
);
876 * amdgpu_vm_clear_freed - clear freed BOs in the PT
878 * @adev: amdgpu_device pointer
881 * Make sure all freed BOs are cleared in the PT.
882 * Returns 0 for success.
884 * PTs have to be reserved and mutex must be locked!
886 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
887 struct amdgpu_vm
*vm
)
889 struct amdgpu_bo_va_mapping
*mapping
;
892 while (!list_empty(&vm
->freed
)) {
893 mapping
= list_first_entry(&vm
->freed
,
894 struct amdgpu_bo_va_mapping
, list
);
895 list_del(&mapping
->list
);
897 r
= amdgpu_vm_bo_update_mapping(adev
, vm
, mapping
, 0, 0, NULL
);
908 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
910 * @adev: amdgpu_device pointer
913 * Make sure all invalidated BOs are cleared in the PT.
914 * Returns 0 for success.
916 * PTs have to be reserved and mutex must be locked!
918 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
919 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
921 struct amdgpu_bo_va
*bo_va
= NULL
;
924 spin_lock(&vm
->status_lock
);
925 while (!list_empty(&vm
->invalidated
)) {
926 bo_va
= list_first_entry(&vm
->invalidated
,
927 struct amdgpu_bo_va
, vm_status
);
928 spin_unlock(&vm
->status_lock
);
930 r
= amdgpu_vm_bo_update(adev
, bo_va
, NULL
);
934 spin_lock(&vm
->status_lock
);
936 spin_unlock(&vm
->status_lock
);
939 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
945 * amdgpu_vm_bo_add - add a bo to a specific vm
947 * @adev: amdgpu_device pointer
949 * @bo: amdgpu buffer object
951 * Add @bo into the requested vm (cayman+).
952 * Add @bo to the list of bos associated with the vm
953 * Returns newly added bo_va or NULL for failure
955 * Object has to be reserved!
957 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
958 struct amdgpu_vm
*vm
,
959 struct amdgpu_bo
*bo
)
961 struct amdgpu_bo_va
*bo_va
;
963 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
969 bo_va
->ref_count
= 1;
970 INIT_LIST_HEAD(&bo_va
->bo_list
);
971 INIT_LIST_HEAD(&bo_va
->valids
);
972 INIT_LIST_HEAD(&bo_va
->invalids
);
973 INIT_LIST_HEAD(&bo_va
->vm_status
);
975 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
981 * amdgpu_vm_bo_map - map bo inside a vm
983 * @adev: amdgpu_device pointer
984 * @bo_va: bo_va to store the address
985 * @saddr: where to map the BO
986 * @offset: requested offset in the BO
987 * @flags: attributes of pages (read/write/valid/etc.)
989 * Add a mapping of the BO at the specefied addr into the VM.
990 * Returns 0 for success, error for failure.
992 * Object has to be reserved and gets unreserved by this function!
994 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
995 struct amdgpu_bo_va
*bo_va
,
996 uint64_t saddr
, uint64_t offset
,
997 uint64_t size
, uint32_t flags
)
999 struct amdgpu_bo_va_mapping
*mapping
;
1000 struct amdgpu_vm
*vm
= bo_va
->vm
;
1001 struct interval_tree_node
*it
;
1002 unsigned last_pfn
, pt_idx
;
1006 /* validate the parameters */
1007 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1008 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
) {
1009 amdgpu_bo_unreserve(bo_va
->bo
);
1013 /* make sure object fit at this offset */
1014 eaddr
= saddr
+ size
;
1015 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
))) {
1016 amdgpu_bo_unreserve(bo_va
->bo
);
1020 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1021 if (last_pfn
> adev
->vm_manager
.max_pfn
) {
1022 dev_err(adev
->dev
, "va above limit (0x%08X > 0x%08X)\n",
1023 last_pfn
, adev
->vm_manager
.max_pfn
);
1024 amdgpu_bo_unreserve(bo_va
->bo
);
1028 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1029 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1031 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
- 1);
1033 struct amdgpu_bo_va_mapping
*tmp
;
1034 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1035 /* bo and tmp overlap, invalid addr */
1036 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1037 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1038 tmp
->it
.start
, tmp
->it
.last
+ 1);
1039 amdgpu_bo_unreserve(bo_va
->bo
);
1044 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1046 amdgpu_bo_unreserve(bo_va
->bo
);
1051 INIT_LIST_HEAD(&mapping
->list
);
1052 mapping
->it
.start
= saddr
;
1053 mapping
->it
.last
= eaddr
- 1;
1054 mapping
->offset
= offset
;
1055 mapping
->flags
= flags
;
1057 list_add(&mapping
->list
, &bo_va
->invalids
);
1058 interval_tree_insert(&mapping
->it
, &vm
->va
);
1059 trace_amdgpu_vm_bo_map(bo_va
, mapping
);
1061 /* Make sure the page tables are allocated */
1062 saddr
>>= amdgpu_vm_block_size
;
1063 eaddr
>>= amdgpu_vm_block_size
;
1065 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1067 if (eaddr
> vm
->max_pde_used
)
1068 vm
->max_pde_used
= eaddr
;
1070 amdgpu_bo_unreserve(bo_va
->bo
);
1072 /* walk over the address space and allocate the page tables */
1073 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1074 struct reservation_object
*resv
= vm
->page_directory
->tbo
.resv
;
1075 struct amdgpu_bo
*pt
;
1077 if (vm
->page_tables
[pt_idx
].bo
)
1080 ww_mutex_lock(&resv
->lock
, NULL
);
1081 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1082 AMDGPU_GPU_PAGE_SIZE
, true,
1083 AMDGPU_GEM_DOMAIN_VRAM
,
1084 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1086 ww_mutex_unlock(&resv
->lock
);
1090 r
= amdgpu_vm_clear_bo(adev
, pt
);
1092 amdgpu_bo_unref(&pt
);
1096 vm
->page_tables
[pt_idx
].addr
= 0;
1097 vm
->page_tables
[pt_idx
].bo
= pt
;
1103 list_del(&mapping
->list
);
1104 interval_tree_remove(&mapping
->it
, &vm
->va
);
1105 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1113 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1115 * @adev: amdgpu_device pointer
1116 * @bo_va: bo_va to remove the address from
1117 * @saddr: where to the BO is mapped
1119 * Remove a mapping of the BO at the specefied addr from the VM.
1120 * Returns 0 for success, error for failure.
1122 * Object has to be reserved and gets unreserved by this function!
1124 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1125 struct amdgpu_bo_va
*bo_va
,
1128 struct amdgpu_bo_va_mapping
*mapping
;
1129 struct amdgpu_vm
*vm
= bo_va
->vm
;
1132 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1134 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1135 if (mapping
->it
.start
== saddr
)
1139 if (&mapping
->list
== &bo_va
->valids
) {
1142 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1143 if (mapping
->it
.start
== saddr
)
1147 if (&mapping
->list
== &bo_va
->invalids
) {
1148 amdgpu_bo_unreserve(bo_va
->bo
);
1153 list_del(&mapping
->list
);
1154 interval_tree_remove(&mapping
->it
, &vm
->va
);
1155 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1158 list_add(&mapping
->list
, &vm
->freed
);
1161 amdgpu_bo_unreserve(bo_va
->bo
);
1167 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1169 * @adev: amdgpu_device pointer
1170 * @bo_va: requested bo_va
1172 * Remove @bo_va->bo from the requested vm (cayman+).
1174 * Object have to be reserved!
1176 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1177 struct amdgpu_bo_va
*bo_va
)
1179 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1180 struct amdgpu_vm
*vm
= bo_va
->vm
;
1182 list_del(&bo_va
->bo_list
);
1184 spin_lock(&vm
->status_lock
);
1185 list_del(&bo_va
->vm_status
);
1186 spin_unlock(&vm
->status_lock
);
1188 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1189 list_del(&mapping
->list
);
1190 interval_tree_remove(&mapping
->it
, &vm
->va
);
1191 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1192 list_add(&mapping
->list
, &vm
->freed
);
1194 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1195 list_del(&mapping
->list
);
1196 interval_tree_remove(&mapping
->it
, &vm
->va
);
1200 fence_put(bo_va
->last_pt_update
);
1205 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1207 * @adev: amdgpu_device pointer
1209 * @bo: amdgpu buffer object
1211 * Mark @bo as invalid (cayman+).
1213 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1214 struct amdgpu_bo
*bo
)
1216 struct amdgpu_bo_va
*bo_va
;
1218 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1219 spin_lock(&bo_va
->vm
->status_lock
);
1220 if (list_empty(&bo_va
->vm_status
))
1221 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1222 spin_unlock(&bo_va
->vm
->status_lock
);
1227 * amdgpu_vm_init - initialize a vm instance
1229 * @adev: amdgpu_device pointer
1232 * Init @vm fields (cayman+).
1234 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1236 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1237 AMDGPU_VM_PTE_COUNT
* 8);
1238 unsigned pd_size
, pd_entries
, pts_size
;
1241 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1243 vm
->ids
[i
].flushed_updates
= NULL
;
1245 mutex_init(&vm
->mutex
);
1247 spin_lock_init(&vm
->status_lock
);
1248 INIT_LIST_HEAD(&vm
->invalidated
);
1249 INIT_LIST_HEAD(&vm
->cleared
);
1250 INIT_LIST_HEAD(&vm
->freed
);
1252 pd_size
= amdgpu_vm_directory_size(adev
);
1253 pd_entries
= amdgpu_vm_num_pdes(adev
);
1255 /* allocate page table array */
1256 pts_size
= pd_entries
* sizeof(struct amdgpu_vm_pt
);
1257 vm
->page_tables
= kzalloc(pts_size
, GFP_KERNEL
);
1258 if (vm
->page_tables
== NULL
) {
1259 DRM_ERROR("Cannot allocate memory for page table array\n");
1263 vm
->page_directory_fence
= NULL
;
1265 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1266 AMDGPU_GEM_DOMAIN_VRAM
,
1267 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1268 NULL
, NULL
, &vm
->page_directory
);
1272 r
= amdgpu_vm_clear_bo(adev
, vm
->page_directory
);
1274 amdgpu_bo_unref(&vm
->page_directory
);
1275 vm
->page_directory
= NULL
;
1283 * amdgpu_vm_fini - tear down a vm instance
1285 * @adev: amdgpu_device pointer
1288 * Tear down @vm (cayman+).
1289 * Unbind the VM and remove all bos from the vm bo list
1291 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1293 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1296 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1297 dev_err(adev
->dev
, "still active bo inside vm\n");
1299 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1300 list_del(&mapping
->list
);
1301 interval_tree_remove(&mapping
->it
, &vm
->va
);
1304 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1305 list_del(&mapping
->list
);
1309 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++)
1310 amdgpu_bo_unref(&vm
->page_tables
[i
].bo
);
1311 kfree(vm
->page_tables
);
1313 amdgpu_bo_unref(&vm
->page_directory
);
1314 fence_put(vm
->page_directory_fence
);
1316 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
) {
1317 unsigned id
= vm
->ids
[i
].id
;
1319 atomic_long_cmpxchg(&adev
->vm_manager
.ids
[id
].owner
,
1321 fence_put(vm
->ids
[i
].flushed_updates
);
1324 mutex_destroy(&vm
->mutex
);
1328 * amdgpu_vm_manager_fini - cleanup VM manager
1330 * @adev: amdgpu_device pointer
1332 * Cleanup the VM manager and free resources.
1334 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
1338 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
)
1339 fence_put(adev
->vm_manager
.ids
[i
].active
);