2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Special value that no flush is necessary */
55 #define AMDGPU_VM_NO_FLUSH (~0ll)
57 /* Local structure. Encapsulate some VM table update parameters to reduce
58 * the number of function parameters
60 struct amdgpu_vm_update_params
{
61 /* address where to copy page table entries from */
63 /* DMA addresses to use for mapping */
64 dma_addr_t
*pages_addr
;
65 /* indirect buffer to fill with commands */
70 * amdgpu_vm_num_pde - return the number of page directory entries
72 * @adev: amdgpu_device pointer
74 * Calculate the number of page directory entries.
76 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
78 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
82 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
84 * @adev: amdgpu_device pointer
86 * Calculate the size of the page directory in bytes.
88 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
90 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
94 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
96 * @vm: vm providing the BOs
97 * @validated: head of validation list
98 * @entry: entry to add
100 * Add the page directory to the list of BOs to
101 * validate for command submission.
103 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
104 struct list_head
*validated
,
105 struct amdgpu_bo_list_entry
*entry
)
107 entry
->robj
= vm
->page_directory
;
109 entry
->tv
.bo
= &vm
->page_directory
->tbo
;
110 entry
->tv
.shared
= true;
111 entry
->user_pages
= NULL
;
112 list_add(&entry
->tv
.head
, validated
);
116 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
118 * @vm: vm providing the BOs
119 * @duplicates: head of duplicates list
121 * Add the page directory to the BO duplicates list
122 * for command submission.
124 void amdgpu_vm_get_pt_bos(struct amdgpu_vm
*vm
, struct list_head
*duplicates
)
128 /* add the vm page table to the list */
129 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
130 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
135 list_add(&entry
->tv
.head
, duplicates
);
141 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
143 * @adev: amdgpu device instance
144 * @vm: vm providing the BOs
146 * Move the PT BOs to the tail of the LRU.
148 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
149 struct amdgpu_vm
*vm
)
151 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
154 spin_lock(&glob
->lru_lock
);
155 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
156 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
161 ttm_bo_move_to_lru_tail(&entry
->robj
->tbo
);
163 spin_unlock(&glob
->lru_lock
);
167 * amdgpu_vm_grab_id - allocate the next free VMID
169 * @vm: vm to allocate id for
170 * @ring: ring we want to submit job to
171 * @sync: sync object where we add dependencies
172 * @fence: fence protecting ID from reuse
174 * Allocate an id for the vm, adding fences to the sync obj as necessary.
176 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
177 struct amdgpu_sync
*sync
, struct fence
*fence
,
178 unsigned *vm_id
, uint64_t *vm_pd_addr
)
180 uint64_t pd_addr
= amdgpu_bo_gpu_offset(vm
->page_directory
);
181 struct amdgpu_device
*adev
= ring
->adev
;
182 struct fence
*updates
= sync
->last_vm_update
;
183 struct amdgpu_vm_id
*id
, *idle
;
184 struct fence
**fences
;
188 fences
= kmalloc_array(sizeof(void *), adev
->vm_manager
.num_ids
,
193 mutex_lock(&adev
->vm_manager
.lock
);
195 /* Check if we have an idle VMID */
197 list_for_each_entry(idle
, &adev
->vm_manager
.ids_lru
, list
) {
198 fences
[i
] = amdgpu_sync_peek_fence(&idle
->active
, ring
);
204 /* If we can't find a idle VMID to use, wait till one becomes available */
205 if (&idle
->list
== &adev
->vm_manager
.ids_lru
) {
206 u64 fence_context
= adev
->vm_manager
.fence_context
+ ring
->idx
;
207 unsigned seqno
= ++adev
->vm_manager
.seqno
[ring
->idx
];
208 struct fence_array
*array
;
211 for (j
= 0; j
< i
; ++j
)
212 fence_get(fences
[j
]);
214 array
= fence_array_create(i
, fences
, fence_context
,
217 for (j
= 0; j
< i
; ++j
)
218 fence_put(fences
[j
]);
225 r
= amdgpu_sync_fence(ring
->adev
, sync
, &array
->base
);
226 fence_put(&array
->base
);
230 mutex_unlock(&adev
->vm_manager
.lock
);
236 /* Check if we can use a VMID already assigned to this VM */
239 struct fence
*flushed
;
242 if (i
== AMDGPU_MAX_RINGS
)
245 /* Check all the prerequisites to using this VMID */
249 if (atomic64_read(&id
->owner
) != vm
->client_id
)
252 if (pd_addr
!= id
->pd_gpu_addr
)
255 if (id
->last_user
!= ring
&&
256 (!id
->last_flush
|| !fence_is_signaled(id
->last_flush
)))
259 flushed
= id
->flushed_updates
;
261 (!flushed
|| fence_is_later(updates
, flushed
)))
264 /* Good we can use this VMID */
265 if (id
->last_user
== ring
) {
266 r
= amdgpu_sync_fence(ring
->adev
, sync
,
272 /* And remember this submission as user of the VMID */
273 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
277 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
278 vm
->ids
[ring
->idx
] = id
;
280 *vm_id
= id
- adev
->vm_manager
.ids
;
281 *vm_pd_addr
= AMDGPU_VM_NO_FLUSH
;
282 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, *vm_id
, *vm_pd_addr
);
284 mutex_unlock(&adev
->vm_manager
.lock
);
287 } while (i
!= ring
->idx
);
289 /* Still no ID to use? Then use the idle one found earlier */
292 /* Remember this submission as user of the VMID */
293 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
297 fence_put(id
->first
);
298 id
->first
= fence_get(fence
);
300 fence_put(id
->last_flush
);
301 id
->last_flush
= NULL
;
303 fence_put(id
->flushed_updates
);
304 id
->flushed_updates
= fence_get(updates
);
306 id
->pd_gpu_addr
= pd_addr
;
308 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
309 id
->last_user
= ring
;
310 atomic64_set(&id
->owner
, vm
->client_id
);
311 vm
->ids
[ring
->idx
] = id
;
313 *vm_id
= id
- adev
->vm_manager
.ids
;
314 *vm_pd_addr
= pd_addr
;
315 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, *vm_id
, *vm_pd_addr
);
318 mutex_unlock(&adev
->vm_manager
.lock
);
323 * amdgpu_vm_flush - hardware flush the vm
325 * @ring: ring to use for flush
326 * @vm_id: vmid number to use
327 * @pd_addr: address of the page directory
329 * Emit a VM flush when it is necessary.
331 int amdgpu_vm_flush(struct amdgpu_ring
*ring
,
332 unsigned vm_id
, uint64_t pd_addr
,
333 uint32_t gds_base
, uint32_t gds_size
,
334 uint32_t gws_base
, uint32_t gws_size
,
335 uint32_t oa_base
, uint32_t oa_size
)
337 struct amdgpu_device
*adev
= ring
->adev
;
338 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
339 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
340 id
->gds_base
!= gds_base
||
341 id
->gds_size
!= gds_size
||
342 id
->gws_base
!= gws_base
||
343 id
->gws_size
!= gws_size
||
344 id
->oa_base
!= oa_base
||
345 id
->oa_size
!= oa_size
);
348 if (ring
->funcs
->emit_pipeline_sync
&& (
349 pd_addr
!= AMDGPU_VM_NO_FLUSH
|| gds_switch_needed
||
350 ring
->type
== AMDGPU_RING_TYPE_COMPUTE
))
351 amdgpu_ring_emit_pipeline_sync(ring
);
353 if (ring
->funcs
->emit_vm_flush
&&
354 pd_addr
!= AMDGPU_VM_NO_FLUSH
) {
357 trace_amdgpu_vm_flush(pd_addr
, ring
->idx
, vm_id
);
358 amdgpu_ring_emit_vm_flush(ring
, vm_id
, pd_addr
);
360 mutex_lock(&adev
->vm_manager
.lock
);
361 if ((id
->pd_gpu_addr
== pd_addr
) && (id
->last_user
== ring
)) {
362 r
= amdgpu_fence_emit(ring
, &fence
);
364 mutex_unlock(&adev
->vm_manager
.lock
);
367 fence_put(id
->last_flush
);
368 id
->last_flush
= fence
;
370 mutex_unlock(&adev
->vm_manager
.lock
);
373 if (gds_switch_needed
) {
374 id
->gds_base
= gds_base
;
375 id
->gds_size
= gds_size
;
376 id
->gws_base
= gws_base
;
377 id
->gws_size
= gws_size
;
378 id
->oa_base
= oa_base
;
379 id
->oa_size
= oa_size
;
380 amdgpu_ring_emit_gds_switch(ring
, vm_id
,
390 * amdgpu_vm_reset_id - reset VMID to zero
392 * @adev: amdgpu device structure
393 * @vm_id: vmid number to use
395 * Reset saved GDW, GWS and OA to force switch on next flush.
397 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
)
399 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
410 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
413 * @bo: requested buffer object
415 * Find @bo inside the requested vm.
416 * Search inside the @bos vm list for the requested vm
417 * Returns the found bo_va or NULL if none is found
419 * Object has to be reserved!
421 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
422 struct amdgpu_bo
*bo
)
424 struct amdgpu_bo_va
*bo_va
;
426 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
427 if (bo_va
->vm
== vm
) {
435 * amdgpu_vm_update_pages - helper to call the right asic function
437 * @adev: amdgpu_device pointer
438 * @vm_update_params: see amdgpu_vm_update_params definition
439 * @pe: addr of the page entry
440 * @addr: dst addr to write into pe
441 * @count: number of page entries to update
442 * @incr: increase next addr by incr bytes
443 * @flags: hw access flags
445 * Traces the parameters and calls the right asic functions
446 * to setup the page table using the DMA.
448 static void amdgpu_vm_update_pages(struct amdgpu_device
*adev
,
449 struct amdgpu_vm_update_params
451 uint64_t pe
, uint64_t addr
,
452 unsigned count
, uint32_t incr
,
455 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
457 if (vm_update_params
->src
) {
458 amdgpu_vm_copy_pte(adev
, vm_update_params
->ib
,
459 pe
, (vm_update_params
->src
+ (addr
>> 12) * 8), count
);
461 } else if (vm_update_params
->pages_addr
) {
462 amdgpu_vm_write_pte(adev
, vm_update_params
->ib
,
463 vm_update_params
->pages_addr
,
464 pe
, addr
, count
, incr
, flags
);
466 } else if (count
< 3) {
467 amdgpu_vm_write_pte(adev
, vm_update_params
->ib
, NULL
, pe
, addr
,
471 amdgpu_vm_set_pte_pde(adev
, vm_update_params
->ib
, pe
, addr
,
477 * amdgpu_vm_clear_bo - initially clear the page dir/table
479 * @adev: amdgpu_device pointer
482 * need to reserve bo first before calling it.
484 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
485 struct amdgpu_vm
*vm
,
486 struct amdgpu_bo
*bo
)
488 struct amdgpu_ring
*ring
;
489 struct fence
*fence
= NULL
;
490 struct amdgpu_job
*job
;
491 struct amdgpu_vm_update_params vm_update_params
;
496 memset(&vm_update_params
, 0, sizeof(vm_update_params
));
497 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
499 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
503 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
507 addr
= amdgpu_bo_gpu_offset(bo
);
508 entries
= amdgpu_bo_size(bo
) / 8;
510 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
514 vm_update_params
.ib
= &job
->ibs
[0];
515 amdgpu_vm_update_pages(adev
, &vm_update_params
, addr
, 0, entries
,
517 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
519 WARN_ON(job
->ibs
[0].length_dw
> 64);
520 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
521 AMDGPU_FENCE_OWNER_VM
, &fence
);
525 amdgpu_bo_fence(bo
, fence
, true);
530 amdgpu_job_free(job
);
537 * amdgpu_vm_map_gart - Resolve gart mapping of addr
539 * @pages_addr: optional DMA address to use for lookup
540 * @addr: the unmapped addr
542 * Look up the physical address of the page that the pte resolves
543 * to and return the pointer for the page table entry.
545 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
550 /* page table offset */
551 result
= pages_addr
[addr
>> PAGE_SHIFT
];
553 /* in case cpu page size != gpu page size*/
554 result
|= addr
& (~PAGE_MASK
);
557 /* No mapping required */
561 result
&= 0xFFFFFFFFFFFFF000ULL
;
567 * amdgpu_vm_update_pdes - make sure that page directory is valid
569 * @adev: amdgpu_device pointer
571 * @start: start of GPU address range
572 * @end: end of GPU address range
574 * Allocates new page tables if necessary
575 * and updates the page directory.
576 * Returns 0 for success, error for failure.
578 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
579 struct amdgpu_vm
*vm
)
581 struct amdgpu_ring
*ring
;
582 struct amdgpu_bo
*pd
= vm
->page_directory
;
583 uint64_t pd_addr
= amdgpu_bo_gpu_offset(pd
);
584 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
585 uint64_t last_pde
= ~0, last_pt
= ~0;
586 unsigned count
= 0, pt_idx
, ndw
;
587 struct amdgpu_job
*job
;
588 struct amdgpu_vm_update_params vm_update_params
;
589 struct fence
*fence
= NULL
;
593 memset(&vm_update_params
, 0, sizeof(vm_update_params
));
594 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
599 /* assume the worst case */
600 ndw
+= vm
->max_pde_used
* 6;
602 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
606 vm_update_params
.ib
= &job
->ibs
[0];
608 /* walk over the address space and update the page directory */
609 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
610 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].entry
.robj
;
616 pt
= amdgpu_bo_gpu_offset(bo
);
617 if (vm
->page_tables
[pt_idx
].addr
== pt
)
619 vm
->page_tables
[pt_idx
].addr
= pt
;
621 pde
= pd_addr
+ pt_idx
* 8;
622 if (((last_pde
+ 8 * count
) != pde
) ||
623 ((last_pt
+ incr
* count
) != pt
)) {
626 amdgpu_vm_update_pages(adev
, &vm_update_params
,
641 amdgpu_vm_update_pages(adev
, &vm_update_params
,
643 count
, incr
, AMDGPU_PTE_VALID
);
645 if (vm_update_params
.ib
->length_dw
!= 0) {
646 amdgpu_ring_pad_ib(ring
, vm_update_params
.ib
);
647 amdgpu_sync_resv(adev
, &job
->sync
, pd
->tbo
.resv
,
648 AMDGPU_FENCE_OWNER_VM
);
649 WARN_ON(vm_update_params
.ib
->length_dw
> ndw
);
650 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
651 AMDGPU_FENCE_OWNER_VM
, &fence
);
655 amdgpu_bo_fence(pd
, fence
, true);
656 fence_put(vm
->page_directory_fence
);
657 vm
->page_directory_fence
= fence_get(fence
);
661 amdgpu_job_free(job
);
667 amdgpu_job_free(job
);
672 * amdgpu_vm_frag_ptes - add fragment information to PTEs
674 * @adev: amdgpu_device pointer
675 * @vm_update_params: see amdgpu_vm_update_params definition
676 * @pe_start: first PTE to handle
677 * @pe_end: last PTE to handle
678 * @addr: addr those PTEs should point to
679 * @flags: hw mapping flags
681 static void amdgpu_vm_frag_ptes(struct amdgpu_device
*adev
,
682 struct amdgpu_vm_update_params
684 uint64_t pe_start
, uint64_t pe_end
,
685 uint64_t addr
, uint32_t flags
)
688 * The MC L1 TLB supports variable sized pages, based on a fragment
689 * field in the PTE. When this field is set to a non-zero value, page
690 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
691 * flags are considered valid for all PTEs within the fragment range
692 * and corresponding mappings are assumed to be physically contiguous.
694 * The L1 TLB can store a single PTE for the whole fragment,
695 * significantly increasing the space available for translation
696 * caching. This leads to large improvements in throughput when the
697 * TLB is under pressure.
699 * The L2 TLB distributes small and large fragments into two
700 * asymmetric partitions. The large fragment cache is significantly
701 * larger. Thus, we try to use large fragments wherever possible.
702 * Userspace can support this by aligning virtual base address and
703 * allocation size to the fragment size.
706 /* SI and newer are optimized for 64KB */
707 uint64_t frag_flags
= AMDGPU_PTE_FRAG_64KB
;
708 uint64_t frag_align
= 0x80;
710 uint64_t frag_start
= ALIGN(pe_start
, frag_align
);
711 uint64_t frag_end
= pe_end
& ~(frag_align
- 1);
715 /* Abort early if there isn't anything to do */
716 if (pe_start
== pe_end
)
719 /* system pages are non continuously */
720 if (vm_update_params
->src
|| vm_update_params
->pages_addr
||
721 !(flags
& AMDGPU_PTE_VALID
) || (frag_start
>= frag_end
)) {
723 count
= (pe_end
- pe_start
) / 8;
724 amdgpu_vm_update_pages(adev
, vm_update_params
, pe_start
,
725 addr
, count
, AMDGPU_GPU_PAGE_SIZE
,
730 /* handle the 4K area at the beginning */
731 if (pe_start
!= frag_start
) {
732 count
= (frag_start
- pe_start
) / 8;
733 amdgpu_vm_update_pages(adev
, vm_update_params
, pe_start
, addr
,
734 count
, AMDGPU_GPU_PAGE_SIZE
, flags
);
735 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
738 /* handle the area in the middle */
739 count
= (frag_end
- frag_start
) / 8;
740 amdgpu_vm_update_pages(adev
, vm_update_params
, frag_start
, addr
, count
,
741 AMDGPU_GPU_PAGE_SIZE
, flags
| frag_flags
);
743 /* handle the 4K area at the end */
744 if (frag_end
!= pe_end
) {
745 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
746 count
= (pe_end
- frag_end
) / 8;
747 amdgpu_vm_update_pages(adev
, vm_update_params
, frag_end
, addr
,
748 count
, AMDGPU_GPU_PAGE_SIZE
, flags
);
753 * amdgpu_vm_update_ptes - make sure that page tables are valid
755 * @adev: amdgpu_device pointer
756 * @vm_update_params: see amdgpu_vm_update_params definition
758 * @start: start of GPU address range
759 * @end: end of GPU address range
760 * @dst: destination address to map to
761 * @flags: mapping flags
763 * Update the page tables in the range @start - @end.
765 static void amdgpu_vm_update_ptes(struct amdgpu_device
*adev
,
766 struct amdgpu_vm_update_params
768 struct amdgpu_vm
*vm
,
769 uint64_t start
, uint64_t end
,
770 uint64_t dst
, uint32_t flags
)
772 const uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
774 uint64_t last_pe_start
= ~0, last_pe_end
= ~0, last_dst
= ~0;
777 /* walk over the address space and update the page tables */
778 for (addr
= start
; addr
< end
; ) {
779 uint64_t pt_idx
= addr
>> amdgpu_vm_block_size
;
780 struct amdgpu_bo
*pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
784 if ((addr
& ~mask
) == (end
& ~mask
))
787 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
789 pe_start
= amdgpu_bo_gpu_offset(pt
);
790 pe_start
+= (addr
& mask
) * 8;
792 if (last_pe_end
!= pe_start
) {
794 amdgpu_vm_frag_ptes(adev
, vm_update_params
,
795 last_pe_start
, last_pe_end
,
798 last_pe_start
= pe_start
;
799 last_pe_end
= pe_start
+ 8 * nptes
;
802 last_pe_end
+= 8 * nptes
;
806 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
809 amdgpu_vm_frag_ptes(adev
, vm_update_params
, last_pe_start
,
810 last_pe_end
, last_dst
, flags
);
814 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
816 * @adev: amdgpu_device pointer
817 * @src: address where to copy page table entries from
818 * @pages_addr: DMA addresses to use for mapping
820 * @start: start of mapped range
821 * @last: last mapped entry
822 * @flags: flags for the entries
823 * @addr: addr to set the area to
824 * @fence: optional resulting fence
826 * Fill in the page table entries between @start and @last.
827 * Returns 0 for success, -EINVAL for failure.
829 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
831 dma_addr_t
*pages_addr
,
832 struct amdgpu_vm
*vm
,
833 uint64_t start
, uint64_t last
,
834 uint32_t flags
, uint64_t addr
,
835 struct fence
**fence
)
837 struct amdgpu_ring
*ring
;
838 void *owner
= AMDGPU_FENCE_OWNER_VM
;
839 unsigned nptes
, ncmds
, ndw
;
840 struct amdgpu_job
*job
;
841 struct amdgpu_vm_update_params vm_update_params
;
842 struct fence
*f
= NULL
;
845 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
846 memset(&vm_update_params
, 0, sizeof(vm_update_params
));
847 vm_update_params
.src
= src
;
848 vm_update_params
.pages_addr
= pages_addr
;
850 /* sync to everything on unmapping */
851 if (!(flags
& AMDGPU_PTE_VALID
))
852 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
854 nptes
= last
- start
+ 1;
857 * reserve space for one command every (1 << BLOCK_SIZE)
858 * entries or 2k dwords (whatever is smaller)
860 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
865 if (vm_update_params
.src
) {
866 /* only copy commands needed */
869 } else if (vm_update_params
.pages_addr
) {
870 /* header for write data commands */
873 /* body of write data command */
877 /* set page commands needed */
880 /* two extra commands for begin/end of fragment */
884 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
888 vm_update_params
.ib
= &job
->ibs
[0];
890 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->page_directory
->tbo
.resv
,
895 r
= reservation_object_reserve_shared(vm
->page_directory
->tbo
.resv
);
899 amdgpu_vm_update_ptes(adev
, &vm_update_params
, vm
, start
,
900 last
+ 1, addr
, flags
);
902 amdgpu_ring_pad_ib(ring
, vm_update_params
.ib
);
903 WARN_ON(vm_update_params
.ib
->length_dw
> ndw
);
904 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
905 AMDGPU_FENCE_OWNER_VM
, &f
);
909 amdgpu_bo_fence(vm
->page_directory
, f
, true);
912 *fence
= fence_get(f
);
918 amdgpu_job_free(job
);
923 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
925 * @adev: amdgpu_device pointer
926 * @gtt_flags: flags as they are used for GTT
927 * @pages_addr: DMA addresses to use for mapping
929 * @mapping: mapped range and flags to use for the update
930 * @addr: addr to set the area to
931 * @flags: HW flags for the mapping
932 * @fence: optional resulting fence
934 * Split the mapping into smaller chunks so that each update fits
936 * Returns 0 for success, -EINVAL for failure.
938 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
940 dma_addr_t
*pages_addr
,
941 struct amdgpu_vm
*vm
,
942 struct amdgpu_bo_va_mapping
*mapping
,
943 uint32_t flags
, uint64_t addr
,
944 struct fence
**fence
)
946 const uint64_t max_size
= 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE
;
948 uint64_t src
= 0, start
= mapping
->it
.start
;
951 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
952 * but in case of something, we filter the flags in first place
954 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
955 flags
&= ~AMDGPU_PTE_READABLE
;
956 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
957 flags
&= ~AMDGPU_PTE_WRITEABLE
;
959 trace_amdgpu_vm_bo_update(mapping
);
962 if (flags
== gtt_flags
)
963 src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
966 addr
+= mapping
->offset
;
968 if (!pages_addr
|| src
)
969 return amdgpu_vm_bo_update_mapping(adev
, src
, pages_addr
, vm
,
970 start
, mapping
->it
.last
,
973 while (start
!= mapping
->it
.last
+ 1) {
976 last
= min((uint64_t)mapping
->it
.last
, start
+ max_size
- 1);
977 r
= amdgpu_vm_bo_update_mapping(adev
, src
, pages_addr
, vm
,
978 start
, last
, flags
, addr
,
984 addr
+= max_size
* AMDGPU_GPU_PAGE_SIZE
;
991 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
993 * @adev: amdgpu_device pointer
994 * @bo_va: requested BO and VM object
997 * Fill in the page table entries for @bo_va.
998 * Returns 0 for success, -EINVAL for failure.
1000 * Object have to be reserved and mutex must be locked!
1002 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1003 struct amdgpu_bo_va
*bo_va
,
1004 struct ttm_mem_reg
*mem
)
1006 struct amdgpu_vm
*vm
= bo_va
->vm
;
1007 struct amdgpu_bo_va_mapping
*mapping
;
1008 dma_addr_t
*pages_addr
= NULL
;
1009 uint32_t gtt_flags
, flags
;
1014 struct ttm_dma_tt
*ttm
;
1016 addr
= (u64
)mem
->start
<< PAGE_SHIFT
;
1017 switch (mem
->mem_type
) {
1019 ttm
= container_of(bo_va
->bo
->tbo
.ttm
, struct
1021 pages_addr
= ttm
->dma_address
;
1025 addr
+= adev
->vm_manager
.vram_base_offset
;
1035 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
1036 gtt_flags
= (adev
== bo_va
->bo
->adev
) ? flags
: 0;
1038 spin_lock(&vm
->status_lock
);
1039 if (!list_empty(&bo_va
->vm_status
))
1040 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1041 spin_unlock(&vm
->status_lock
);
1043 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1044 r
= amdgpu_vm_bo_split_mapping(adev
, gtt_flags
, pages_addr
, vm
,
1045 mapping
, flags
, addr
,
1046 &bo_va
->last_pt_update
);
1051 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1052 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1053 trace_amdgpu_vm_bo_mapping(mapping
);
1055 list_for_each_entry(mapping
, &bo_va
->invalids
, list
)
1056 trace_amdgpu_vm_bo_mapping(mapping
);
1059 spin_lock(&vm
->status_lock
);
1060 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1061 list_del_init(&bo_va
->vm_status
);
1063 list_add(&bo_va
->vm_status
, &vm
->cleared
);
1064 spin_unlock(&vm
->status_lock
);
1070 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1072 * @adev: amdgpu_device pointer
1075 * Make sure all freed BOs are cleared in the PT.
1076 * Returns 0 for success.
1078 * PTs have to be reserved and mutex must be locked!
1080 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
1081 struct amdgpu_vm
*vm
)
1083 struct amdgpu_bo_va_mapping
*mapping
;
1086 while (!list_empty(&vm
->freed
)) {
1087 mapping
= list_first_entry(&vm
->freed
,
1088 struct amdgpu_bo_va_mapping
, list
);
1089 list_del(&mapping
->list
);
1091 r
= amdgpu_vm_bo_split_mapping(adev
, 0, NULL
, vm
, mapping
,
1103 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1105 * @adev: amdgpu_device pointer
1108 * Make sure all invalidated BOs are cleared in the PT.
1109 * Returns 0 for success.
1111 * PTs have to be reserved and mutex must be locked!
1113 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
1114 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
1116 struct amdgpu_bo_va
*bo_va
= NULL
;
1119 spin_lock(&vm
->status_lock
);
1120 while (!list_empty(&vm
->invalidated
)) {
1121 bo_va
= list_first_entry(&vm
->invalidated
,
1122 struct amdgpu_bo_va
, vm_status
);
1123 spin_unlock(&vm
->status_lock
);
1125 r
= amdgpu_vm_bo_update(adev
, bo_va
, NULL
);
1129 spin_lock(&vm
->status_lock
);
1131 spin_unlock(&vm
->status_lock
);
1134 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
1140 * amdgpu_vm_bo_add - add a bo to a specific vm
1142 * @adev: amdgpu_device pointer
1144 * @bo: amdgpu buffer object
1146 * Add @bo into the requested vm.
1147 * Add @bo to the list of bos associated with the vm
1148 * Returns newly added bo_va or NULL for failure
1150 * Object has to be reserved!
1152 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
1153 struct amdgpu_vm
*vm
,
1154 struct amdgpu_bo
*bo
)
1156 struct amdgpu_bo_va
*bo_va
;
1158 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
1159 if (bo_va
== NULL
) {
1164 bo_va
->ref_count
= 1;
1165 INIT_LIST_HEAD(&bo_va
->bo_list
);
1166 INIT_LIST_HEAD(&bo_va
->valids
);
1167 INIT_LIST_HEAD(&bo_va
->invalids
);
1168 INIT_LIST_HEAD(&bo_va
->vm_status
);
1170 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
1176 * amdgpu_vm_bo_map - map bo inside a vm
1178 * @adev: amdgpu_device pointer
1179 * @bo_va: bo_va to store the address
1180 * @saddr: where to map the BO
1181 * @offset: requested offset in the BO
1182 * @flags: attributes of pages (read/write/valid/etc.)
1184 * Add a mapping of the BO at the specefied addr into the VM.
1185 * Returns 0 for success, error for failure.
1187 * Object has to be reserved and unreserved outside!
1189 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1190 struct amdgpu_bo_va
*bo_va
,
1191 uint64_t saddr
, uint64_t offset
,
1192 uint64_t size
, uint32_t flags
)
1194 struct amdgpu_bo_va_mapping
*mapping
;
1195 struct amdgpu_vm
*vm
= bo_va
->vm
;
1196 struct interval_tree_node
*it
;
1197 unsigned last_pfn
, pt_idx
;
1201 /* validate the parameters */
1202 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1203 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
1206 /* make sure object fit at this offset */
1207 eaddr
= saddr
+ size
- 1;
1208 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
)))
1211 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1212 if (last_pfn
>= adev
->vm_manager
.max_pfn
) {
1213 dev_err(adev
->dev
, "va above limit (0x%08X >= 0x%08X)\n",
1214 last_pfn
, adev
->vm_manager
.max_pfn
);
1218 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1219 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1221 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
);
1223 struct amdgpu_bo_va_mapping
*tmp
;
1224 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1225 /* bo and tmp overlap, invalid addr */
1226 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1227 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1228 tmp
->it
.start
, tmp
->it
.last
+ 1);
1233 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1239 INIT_LIST_HEAD(&mapping
->list
);
1240 mapping
->it
.start
= saddr
;
1241 mapping
->it
.last
= eaddr
;
1242 mapping
->offset
= offset
;
1243 mapping
->flags
= flags
;
1245 list_add(&mapping
->list
, &bo_va
->invalids
);
1246 interval_tree_insert(&mapping
->it
, &vm
->va
);
1248 /* Make sure the page tables are allocated */
1249 saddr
>>= amdgpu_vm_block_size
;
1250 eaddr
>>= amdgpu_vm_block_size
;
1252 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1254 if (eaddr
> vm
->max_pde_used
)
1255 vm
->max_pde_used
= eaddr
;
1257 /* walk over the address space and allocate the page tables */
1258 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1259 struct reservation_object
*resv
= vm
->page_directory
->tbo
.resv
;
1260 struct amdgpu_bo_list_entry
*entry
;
1261 struct amdgpu_bo
*pt
;
1263 entry
= &vm
->page_tables
[pt_idx
].entry
;
1267 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1268 AMDGPU_GPU_PAGE_SIZE
, true,
1269 AMDGPU_GEM_DOMAIN_VRAM
,
1270 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1275 /* Keep a reference to the page table to avoid freeing
1276 * them up in the wrong order.
1278 pt
->parent
= amdgpu_bo_ref(vm
->page_directory
);
1280 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
);
1282 amdgpu_bo_unref(&pt
);
1287 entry
->priority
= 0;
1288 entry
->tv
.bo
= &entry
->robj
->tbo
;
1289 entry
->tv
.shared
= true;
1290 entry
->user_pages
= NULL
;
1291 vm
->page_tables
[pt_idx
].addr
= 0;
1297 list_del(&mapping
->list
);
1298 interval_tree_remove(&mapping
->it
, &vm
->va
);
1299 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1307 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1309 * @adev: amdgpu_device pointer
1310 * @bo_va: bo_va to remove the address from
1311 * @saddr: where to the BO is mapped
1313 * Remove a mapping of the BO at the specefied addr from the VM.
1314 * Returns 0 for success, error for failure.
1316 * Object has to be reserved and unreserved outside!
1318 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1319 struct amdgpu_bo_va
*bo_va
,
1322 struct amdgpu_bo_va_mapping
*mapping
;
1323 struct amdgpu_vm
*vm
= bo_va
->vm
;
1326 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1328 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1329 if (mapping
->it
.start
== saddr
)
1333 if (&mapping
->list
== &bo_va
->valids
) {
1336 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1337 if (mapping
->it
.start
== saddr
)
1341 if (&mapping
->list
== &bo_va
->invalids
)
1345 list_del(&mapping
->list
);
1346 interval_tree_remove(&mapping
->it
, &vm
->va
);
1347 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1350 list_add(&mapping
->list
, &vm
->freed
);
1358 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1360 * @adev: amdgpu_device pointer
1361 * @bo_va: requested bo_va
1363 * Remove @bo_va->bo from the requested vm.
1365 * Object have to be reserved!
1367 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1368 struct amdgpu_bo_va
*bo_va
)
1370 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1371 struct amdgpu_vm
*vm
= bo_va
->vm
;
1373 list_del(&bo_va
->bo_list
);
1375 spin_lock(&vm
->status_lock
);
1376 list_del(&bo_va
->vm_status
);
1377 spin_unlock(&vm
->status_lock
);
1379 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1380 list_del(&mapping
->list
);
1381 interval_tree_remove(&mapping
->it
, &vm
->va
);
1382 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1383 list_add(&mapping
->list
, &vm
->freed
);
1385 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1386 list_del(&mapping
->list
);
1387 interval_tree_remove(&mapping
->it
, &vm
->va
);
1391 fence_put(bo_va
->last_pt_update
);
1396 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1398 * @adev: amdgpu_device pointer
1400 * @bo: amdgpu buffer object
1402 * Mark @bo as invalid.
1404 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1405 struct amdgpu_bo
*bo
)
1407 struct amdgpu_bo_va
*bo_va
;
1409 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1410 spin_lock(&bo_va
->vm
->status_lock
);
1411 if (list_empty(&bo_va
->vm_status
))
1412 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1413 spin_unlock(&bo_va
->vm
->status_lock
);
1418 * amdgpu_vm_init - initialize a vm instance
1420 * @adev: amdgpu_device pointer
1425 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1427 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1428 AMDGPU_VM_PTE_COUNT
* 8);
1429 unsigned pd_size
, pd_entries
;
1430 unsigned ring_instance
;
1431 struct amdgpu_ring
*ring
;
1432 struct amd_sched_rq
*rq
;
1435 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1438 vm
->client_id
= atomic64_inc_return(&adev
->vm_manager
.client_counter
);
1439 spin_lock_init(&vm
->status_lock
);
1440 INIT_LIST_HEAD(&vm
->invalidated
);
1441 INIT_LIST_HEAD(&vm
->cleared
);
1442 INIT_LIST_HEAD(&vm
->freed
);
1444 pd_size
= amdgpu_vm_directory_size(adev
);
1445 pd_entries
= amdgpu_vm_num_pdes(adev
);
1447 /* allocate page table array */
1448 vm
->page_tables
= drm_calloc_large(pd_entries
, sizeof(struct amdgpu_vm_pt
));
1449 if (vm
->page_tables
== NULL
) {
1450 DRM_ERROR("Cannot allocate memory for page table array\n");
1454 /* create scheduler entity for page table updates */
1456 ring_instance
= atomic_inc_return(&adev
->vm_manager
.vm_pte_next_ring
);
1457 ring_instance
%= adev
->vm_manager
.vm_pte_num_rings
;
1458 ring
= adev
->vm_manager
.vm_pte_rings
[ring_instance
];
1459 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
1460 r
= amd_sched_entity_init(&ring
->sched
, &vm
->entity
,
1461 rq
, amdgpu_sched_jobs
);
1465 vm
->page_directory_fence
= NULL
;
1467 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1468 AMDGPU_GEM_DOMAIN_VRAM
,
1469 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1470 NULL
, NULL
, &vm
->page_directory
);
1472 goto error_free_sched_entity
;
1474 r
= amdgpu_bo_reserve(vm
->page_directory
, false);
1476 goto error_free_page_directory
;
1478 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->page_directory
);
1479 amdgpu_bo_unreserve(vm
->page_directory
);
1481 goto error_free_page_directory
;
1485 error_free_page_directory
:
1486 amdgpu_bo_unref(&vm
->page_directory
);
1487 vm
->page_directory
= NULL
;
1489 error_free_sched_entity
:
1490 amd_sched_entity_fini(&ring
->sched
, &vm
->entity
);
1496 * amdgpu_vm_fini - tear down a vm instance
1498 * @adev: amdgpu_device pointer
1502 * Unbind the VM and remove all bos from the vm bo list
1504 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1506 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1509 amd_sched_entity_fini(vm
->entity
.sched
, &vm
->entity
);
1511 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1512 dev_err(adev
->dev
, "still active bo inside vm\n");
1514 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1515 list_del(&mapping
->list
);
1516 interval_tree_remove(&mapping
->it
, &vm
->va
);
1519 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1520 list_del(&mapping
->list
);
1524 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++)
1525 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
);
1526 drm_free_large(vm
->page_tables
);
1528 amdgpu_bo_unref(&vm
->page_directory
);
1529 fence_put(vm
->page_directory_fence
);
1533 * amdgpu_vm_manager_init - init the VM manager
1535 * @adev: amdgpu_device pointer
1537 * Initialize the VM manager structures
1539 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
1543 INIT_LIST_HEAD(&adev
->vm_manager
.ids_lru
);
1545 /* skip over VMID 0, since it is the system VM */
1546 for (i
= 1; i
< adev
->vm_manager
.num_ids
; ++i
) {
1547 amdgpu_vm_reset_id(adev
, i
);
1548 amdgpu_sync_create(&adev
->vm_manager
.ids
[i
].active
);
1549 list_add_tail(&adev
->vm_manager
.ids
[i
].list
,
1550 &adev
->vm_manager
.ids_lru
);
1553 adev
->vm_manager
.fence_context
= fence_context_alloc(AMDGPU_MAX_RINGS
);
1554 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1555 adev
->vm_manager
.seqno
[i
] = 0;
1557 atomic_set(&adev
->vm_manager
.vm_pte_next_ring
, 0);
1558 atomic64_set(&adev
->vm_manager
.client_counter
, 0);
1562 * amdgpu_vm_manager_fini - cleanup VM manager
1564 * @adev: amdgpu_device pointer
1566 * Cleanup the VM manager and free resources.
1568 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
1572 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
) {
1573 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[i
];
1575 fence_put(adev
->vm_manager
.ids
[i
].first
);
1576 amdgpu_sync_free(&adev
->vm_manager
.ids
[i
].active
);
1577 fence_put(id
->flushed_updates
);