2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/fence-array.h>
30 #include <drm/amdgpu_drm.h>
32 #include "amdgpu_trace.h"
36 * GPUVM is similar to the legacy gart on older asics, however
37 * rather than there being a single global gart table
38 * for the entire GPU, there are multiple VM page tables active
39 * at any given time. The VM page tables can contain a mix
40 * vram pages and system memory pages and system memory pages
41 * can be mapped as snooped (cached system pages) or unsnooped
42 * (uncached system pages).
43 * Each VM has an ID associated with it and there is a page table
44 * associated with each VMID. When execting a command buffer,
45 * the kernel tells the the ring what VMID to use for that command
46 * buffer. VMIDs are allocated dynamically as commands are submitted.
47 * The userspace drivers maintain their own address space and the kernel
48 * sets up their pages tables accordingly when they submit their
49 * command buffers and a VMID is assigned.
50 * Cayman/Trinity support up to 8 active VMs at any given time;
54 /* Special value that no flush is necessary */
55 #define AMDGPU_VM_NO_FLUSH (~0ll)
57 /* Local structure. Encapsulate some VM table update parameters to reduce
58 * the number of function parameters
60 struct amdgpu_vm_update_params
{
61 /* address where to copy page table entries from */
63 /* DMA addresses to use for mapping */
64 dma_addr_t
*pages_addr
;
65 /* indirect buffer to fill with commands */
70 * amdgpu_vm_num_pde - return the number of page directory entries
72 * @adev: amdgpu_device pointer
74 * Calculate the number of page directory entries.
76 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device
*adev
)
78 return adev
->vm_manager
.max_pfn
>> amdgpu_vm_block_size
;
82 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
84 * @adev: amdgpu_device pointer
86 * Calculate the size of the page directory in bytes.
88 static unsigned amdgpu_vm_directory_size(struct amdgpu_device
*adev
)
90 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev
) * 8);
94 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
96 * @vm: vm providing the BOs
97 * @validated: head of validation list
98 * @entry: entry to add
100 * Add the page directory to the list of BOs to
101 * validate for command submission.
103 void amdgpu_vm_get_pd_bo(struct amdgpu_vm
*vm
,
104 struct list_head
*validated
,
105 struct amdgpu_bo_list_entry
*entry
)
107 entry
->robj
= vm
->page_directory
;
109 entry
->tv
.bo
= &vm
->page_directory
->tbo
;
110 entry
->tv
.shared
= true;
111 entry
->user_pages
= NULL
;
112 list_add(&entry
->tv
.head
, validated
);
116 * amdgpu_vm_get_bos - add the vm BOs to a duplicates list
118 * @vm: vm providing the BOs
119 * @duplicates: head of duplicates list
121 * Add the page directory to the BO duplicates list
122 * for command submission.
124 void amdgpu_vm_get_pt_bos(struct amdgpu_vm
*vm
, struct list_head
*duplicates
)
128 /* add the vm page table to the list */
129 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
130 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
135 list_add(&entry
->tv
.head
, duplicates
);
141 * amdgpu_vm_move_pt_bos_in_lru - move the PT BOs to the LRU tail
143 * @adev: amdgpu device instance
144 * @vm: vm providing the BOs
146 * Move the PT BOs to the tail of the LRU.
148 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device
*adev
,
149 struct amdgpu_vm
*vm
)
151 struct ttm_bo_global
*glob
= adev
->mman
.bdev
.glob
;
154 spin_lock(&glob
->lru_lock
);
155 for (i
= 0; i
<= vm
->max_pde_used
; ++i
) {
156 struct amdgpu_bo_list_entry
*entry
= &vm
->page_tables
[i
].entry
;
161 ttm_bo_move_to_lru_tail(&entry
->robj
->tbo
);
163 spin_unlock(&glob
->lru_lock
);
167 * amdgpu_vm_grab_id - allocate the next free VMID
169 * @vm: vm to allocate id for
170 * @ring: ring we want to submit job to
171 * @sync: sync object where we add dependencies
172 * @fence: fence protecting ID from reuse
174 * Allocate an id for the vm, adding fences to the sync obj as necessary.
176 int amdgpu_vm_grab_id(struct amdgpu_vm
*vm
, struct amdgpu_ring
*ring
,
177 struct amdgpu_sync
*sync
, struct fence
*fence
,
178 unsigned *vm_id
, uint64_t *vm_pd_addr
)
180 uint64_t pd_addr
= amdgpu_bo_gpu_offset(vm
->page_directory
);
181 struct amdgpu_device
*adev
= ring
->adev
;
182 struct fence
*updates
= sync
->last_vm_update
;
183 struct amdgpu_vm_id
*id
, *idle
;
184 struct fence
**fences
;
188 fences
= kmalloc_array(sizeof(void *), adev
->vm_manager
.num_ids
,
193 mutex_lock(&adev
->vm_manager
.lock
);
195 /* Check if we have an idle VMID */
197 list_for_each_entry(idle
, &adev
->vm_manager
.ids_lru
, list
) {
198 fences
[i
] = amdgpu_sync_peek_fence(&idle
->active
, ring
);
204 /* If we can't find a idle VMID to use, wait till one becomes available */
205 if (&idle
->list
== &adev
->vm_manager
.ids_lru
) {
206 u64 fence_context
= adev
->vm_manager
.fence_context
+ ring
->idx
;
207 unsigned seqno
= ++adev
->vm_manager
.seqno
[ring
->idx
];
208 struct fence_array
*array
;
211 for (j
= 0; j
< i
; ++j
)
212 fence_get(fences
[j
]);
214 array
= fence_array_create(i
, fences
, fence_context
,
217 for (j
= 0; j
< i
; ++j
)
218 fence_put(fences
[j
]);
225 r
= amdgpu_sync_fence(ring
->adev
, sync
, &array
->base
);
226 fence_put(&array
->base
);
230 mutex_unlock(&adev
->vm_manager
.lock
);
236 /* Check if we can use a VMID already assigned to this VM */
239 struct fence
*flushed
;
240 bool same_ring
= ring
->idx
== i
;
243 if (i
== AMDGPU_MAX_RINGS
)
246 /* Check all the prerequisites to using this VMID */
250 if (atomic64_read(&id
->owner
) != vm
->client_id
)
253 if (pd_addr
!= id
->pd_gpu_addr
)
257 (!id
->last_flush
|| !fence_is_signaled(id
->last_flush
)))
260 flushed
= id
->flushed_updates
;
262 (!flushed
|| fence_is_later(updates
, flushed
)))
265 /* Good we can use this VMID. Remember this submission as
268 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
272 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
273 vm
->ids
[ring
->idx
] = id
;
275 *vm_id
= id
- adev
->vm_manager
.ids
;
276 *vm_pd_addr
= AMDGPU_VM_NO_FLUSH
;
277 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, *vm_id
, *vm_pd_addr
);
279 mutex_unlock(&adev
->vm_manager
.lock
);
282 } while (i
!= ring
->idx
);
284 /* Still no ID to use? Then use the idle one found earlier */
287 /* Remember this submission as user of the VMID */
288 r
= amdgpu_sync_fence(ring
->adev
, &id
->active
, fence
);
292 fence_put(id
->first
);
293 id
->first
= fence_get(fence
);
295 fence_put(id
->last_flush
);
296 id
->last_flush
= NULL
;
298 fence_put(id
->flushed_updates
);
299 id
->flushed_updates
= fence_get(updates
);
301 id
->pd_gpu_addr
= pd_addr
;
303 list_move_tail(&id
->list
, &adev
->vm_manager
.ids_lru
);
304 atomic64_set(&id
->owner
, vm
->client_id
);
305 vm
->ids
[ring
->idx
] = id
;
307 *vm_id
= id
- adev
->vm_manager
.ids
;
308 *vm_pd_addr
= pd_addr
;
309 trace_amdgpu_vm_grab_id(vm
, ring
->idx
, *vm_id
, *vm_pd_addr
);
312 mutex_unlock(&adev
->vm_manager
.lock
);
317 * amdgpu_vm_flush - hardware flush the vm
319 * @ring: ring to use for flush
320 * @vm_id: vmid number to use
321 * @pd_addr: address of the page directory
323 * Emit a VM flush when it is necessary.
325 int amdgpu_vm_flush(struct amdgpu_ring
*ring
,
326 unsigned vm_id
, uint64_t pd_addr
,
327 uint32_t gds_base
, uint32_t gds_size
,
328 uint32_t gws_base
, uint32_t gws_size
,
329 uint32_t oa_base
, uint32_t oa_size
)
331 struct amdgpu_device
*adev
= ring
->adev
;
332 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
333 bool gds_switch_needed
= ring
->funcs
->emit_gds_switch
&& (
334 id
->gds_base
!= gds_base
||
335 id
->gds_size
!= gds_size
||
336 id
->gws_base
!= gws_base
||
337 id
->gws_size
!= gws_size
||
338 id
->oa_base
!= oa_base
||
339 id
->oa_size
!= oa_size
);
342 if (ring
->funcs
->emit_pipeline_sync
&& (
343 pd_addr
!= AMDGPU_VM_NO_FLUSH
|| gds_switch_needed
||
344 ring
->type
== AMDGPU_RING_TYPE_COMPUTE
))
345 amdgpu_ring_emit_pipeline_sync(ring
);
347 if (ring
->funcs
->emit_vm_flush
&&
348 pd_addr
!= AMDGPU_VM_NO_FLUSH
) {
351 trace_amdgpu_vm_flush(pd_addr
, ring
->idx
, vm_id
);
352 amdgpu_ring_emit_vm_flush(ring
, vm_id
, pd_addr
);
354 r
= amdgpu_fence_emit(ring
, &fence
);
358 mutex_lock(&adev
->vm_manager
.lock
);
359 fence_put(id
->last_flush
);
360 id
->last_flush
= fence
;
361 mutex_unlock(&adev
->vm_manager
.lock
);
364 if (gds_switch_needed
) {
365 id
->gds_base
= gds_base
;
366 id
->gds_size
= gds_size
;
367 id
->gws_base
= gws_base
;
368 id
->gws_size
= gws_size
;
369 id
->oa_base
= oa_base
;
370 id
->oa_size
= oa_size
;
371 amdgpu_ring_emit_gds_switch(ring
, vm_id
,
381 * amdgpu_vm_reset_id - reset VMID to zero
383 * @adev: amdgpu device structure
384 * @vm_id: vmid number to use
386 * Reset saved GDW, GWS and OA to force switch on next flush.
388 void amdgpu_vm_reset_id(struct amdgpu_device
*adev
, unsigned vm_id
)
390 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[vm_id
];
401 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
404 * @bo: requested buffer object
406 * Find @bo inside the requested vm.
407 * Search inside the @bos vm list for the requested vm
408 * Returns the found bo_va or NULL if none is found
410 * Object has to be reserved!
412 struct amdgpu_bo_va
*amdgpu_vm_bo_find(struct amdgpu_vm
*vm
,
413 struct amdgpu_bo
*bo
)
415 struct amdgpu_bo_va
*bo_va
;
417 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
418 if (bo_va
->vm
== vm
) {
426 * amdgpu_vm_update_pages - helper to call the right asic function
428 * @adev: amdgpu_device pointer
429 * @vm_update_params: see amdgpu_vm_update_params definition
430 * @pe: addr of the page entry
431 * @addr: dst addr to write into pe
432 * @count: number of page entries to update
433 * @incr: increase next addr by incr bytes
434 * @flags: hw access flags
436 * Traces the parameters and calls the right asic functions
437 * to setup the page table using the DMA.
439 static void amdgpu_vm_update_pages(struct amdgpu_device
*adev
,
440 struct amdgpu_vm_update_params
442 uint64_t pe
, uint64_t addr
,
443 unsigned count
, uint32_t incr
,
446 trace_amdgpu_vm_set_page(pe
, addr
, count
, incr
, flags
);
448 if (vm_update_params
->src
) {
449 amdgpu_vm_copy_pte(adev
, vm_update_params
->ib
,
450 pe
, (vm_update_params
->src
+ (addr
>> 12) * 8), count
);
452 } else if (vm_update_params
->pages_addr
) {
453 amdgpu_vm_write_pte(adev
, vm_update_params
->ib
,
454 vm_update_params
->pages_addr
,
455 pe
, addr
, count
, incr
, flags
);
457 } else if (count
< 3) {
458 amdgpu_vm_write_pte(adev
, vm_update_params
->ib
, NULL
, pe
, addr
,
462 amdgpu_vm_set_pte_pde(adev
, vm_update_params
->ib
, pe
, addr
,
468 * amdgpu_vm_clear_bo - initially clear the page dir/table
470 * @adev: amdgpu_device pointer
473 * need to reserve bo first before calling it.
475 static int amdgpu_vm_clear_bo(struct amdgpu_device
*adev
,
476 struct amdgpu_vm
*vm
,
477 struct amdgpu_bo
*bo
)
479 struct amdgpu_ring
*ring
;
480 struct fence
*fence
= NULL
;
481 struct amdgpu_job
*job
;
482 struct amdgpu_vm_update_params vm_update_params
;
487 memset(&vm_update_params
, 0, sizeof(vm_update_params
));
488 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
490 r
= reservation_object_reserve_shared(bo
->tbo
.resv
);
494 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
498 addr
= amdgpu_bo_gpu_offset(bo
);
499 entries
= amdgpu_bo_size(bo
) / 8;
501 r
= amdgpu_job_alloc_with_ib(adev
, 64, &job
);
505 vm_update_params
.ib
= &job
->ibs
[0];
506 amdgpu_vm_update_pages(adev
, &vm_update_params
, addr
, 0, entries
,
508 amdgpu_ring_pad_ib(ring
, &job
->ibs
[0]);
510 WARN_ON(job
->ibs
[0].length_dw
> 64);
511 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
512 AMDGPU_FENCE_OWNER_VM
, &fence
);
516 amdgpu_bo_fence(bo
, fence
, true);
521 amdgpu_job_free(job
);
528 * amdgpu_vm_map_gart - Resolve gart mapping of addr
530 * @pages_addr: optional DMA address to use for lookup
531 * @addr: the unmapped addr
533 * Look up the physical address of the page that the pte resolves
534 * to and return the pointer for the page table entry.
536 uint64_t amdgpu_vm_map_gart(const dma_addr_t
*pages_addr
, uint64_t addr
)
541 /* page table offset */
542 result
= pages_addr
[addr
>> PAGE_SHIFT
];
544 /* in case cpu page size != gpu page size*/
545 result
|= addr
& (~PAGE_MASK
);
548 /* No mapping required */
552 result
&= 0xFFFFFFFFFFFFF000ULL
;
558 * amdgpu_vm_update_pdes - make sure that page directory is valid
560 * @adev: amdgpu_device pointer
562 * @start: start of GPU address range
563 * @end: end of GPU address range
565 * Allocates new page tables if necessary
566 * and updates the page directory.
567 * Returns 0 for success, error for failure.
569 int amdgpu_vm_update_page_directory(struct amdgpu_device
*adev
,
570 struct amdgpu_vm
*vm
)
572 struct amdgpu_ring
*ring
;
573 struct amdgpu_bo
*pd
= vm
->page_directory
;
574 uint64_t pd_addr
= amdgpu_bo_gpu_offset(pd
);
575 uint32_t incr
= AMDGPU_VM_PTE_COUNT
* 8;
576 uint64_t last_pde
= ~0, last_pt
= ~0;
577 unsigned count
= 0, pt_idx
, ndw
;
578 struct amdgpu_job
*job
;
579 struct amdgpu_vm_update_params vm_update_params
;
580 struct fence
*fence
= NULL
;
584 memset(&vm_update_params
, 0, sizeof(vm_update_params
));
585 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
590 /* assume the worst case */
591 ndw
+= vm
->max_pde_used
* 6;
593 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
597 vm_update_params
.ib
= &job
->ibs
[0];
599 /* walk over the address space and update the page directory */
600 for (pt_idx
= 0; pt_idx
<= vm
->max_pde_used
; ++pt_idx
) {
601 struct amdgpu_bo
*bo
= vm
->page_tables
[pt_idx
].entry
.robj
;
607 pt
= amdgpu_bo_gpu_offset(bo
);
608 if (vm
->page_tables
[pt_idx
].addr
== pt
)
610 vm
->page_tables
[pt_idx
].addr
= pt
;
612 pde
= pd_addr
+ pt_idx
* 8;
613 if (((last_pde
+ 8 * count
) != pde
) ||
614 ((last_pt
+ incr
* count
) != pt
)) {
617 amdgpu_vm_update_pages(adev
, &vm_update_params
,
632 amdgpu_vm_update_pages(adev
, &vm_update_params
,
634 count
, incr
, AMDGPU_PTE_VALID
);
636 if (vm_update_params
.ib
->length_dw
!= 0) {
637 amdgpu_ring_pad_ib(ring
, vm_update_params
.ib
);
638 amdgpu_sync_resv(adev
, &job
->sync
, pd
->tbo
.resv
,
639 AMDGPU_FENCE_OWNER_VM
);
640 WARN_ON(vm_update_params
.ib
->length_dw
> ndw
);
641 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
642 AMDGPU_FENCE_OWNER_VM
, &fence
);
646 amdgpu_bo_fence(pd
, fence
, true);
647 fence_put(vm
->page_directory_fence
);
648 vm
->page_directory_fence
= fence_get(fence
);
652 amdgpu_job_free(job
);
658 amdgpu_job_free(job
);
663 * amdgpu_vm_frag_ptes - add fragment information to PTEs
665 * @adev: amdgpu_device pointer
666 * @vm_update_params: see amdgpu_vm_update_params definition
667 * @pe_start: first PTE to handle
668 * @pe_end: last PTE to handle
669 * @addr: addr those PTEs should point to
670 * @flags: hw mapping flags
672 static void amdgpu_vm_frag_ptes(struct amdgpu_device
*adev
,
673 struct amdgpu_vm_update_params
675 uint64_t pe_start
, uint64_t pe_end
,
676 uint64_t addr
, uint32_t flags
)
679 * The MC L1 TLB supports variable sized pages, based on a fragment
680 * field in the PTE. When this field is set to a non-zero value, page
681 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
682 * flags are considered valid for all PTEs within the fragment range
683 * and corresponding mappings are assumed to be physically contiguous.
685 * The L1 TLB can store a single PTE for the whole fragment,
686 * significantly increasing the space available for translation
687 * caching. This leads to large improvements in throughput when the
688 * TLB is under pressure.
690 * The L2 TLB distributes small and large fragments into two
691 * asymmetric partitions. The large fragment cache is significantly
692 * larger. Thus, we try to use large fragments wherever possible.
693 * Userspace can support this by aligning virtual base address and
694 * allocation size to the fragment size.
697 /* SI and newer are optimized for 64KB */
698 uint64_t frag_flags
= AMDGPU_PTE_FRAG_64KB
;
699 uint64_t frag_align
= 0x80;
701 uint64_t frag_start
= ALIGN(pe_start
, frag_align
);
702 uint64_t frag_end
= pe_end
& ~(frag_align
- 1);
706 /* Abort early if there isn't anything to do */
707 if (pe_start
== pe_end
)
710 /* system pages are non continuously */
711 if (vm_update_params
->src
|| vm_update_params
->pages_addr
||
712 !(flags
& AMDGPU_PTE_VALID
) || (frag_start
>= frag_end
)) {
714 count
= (pe_end
- pe_start
) / 8;
715 amdgpu_vm_update_pages(adev
, vm_update_params
, pe_start
,
716 addr
, count
, AMDGPU_GPU_PAGE_SIZE
,
721 /* handle the 4K area at the beginning */
722 if (pe_start
!= frag_start
) {
723 count
= (frag_start
- pe_start
) / 8;
724 amdgpu_vm_update_pages(adev
, vm_update_params
, pe_start
, addr
,
725 count
, AMDGPU_GPU_PAGE_SIZE
, flags
);
726 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
729 /* handle the area in the middle */
730 count
= (frag_end
- frag_start
) / 8;
731 amdgpu_vm_update_pages(adev
, vm_update_params
, frag_start
, addr
, count
,
732 AMDGPU_GPU_PAGE_SIZE
, flags
| frag_flags
);
734 /* handle the 4K area at the end */
735 if (frag_end
!= pe_end
) {
736 addr
+= AMDGPU_GPU_PAGE_SIZE
* count
;
737 count
= (pe_end
- frag_end
) / 8;
738 amdgpu_vm_update_pages(adev
, vm_update_params
, frag_end
, addr
,
739 count
, AMDGPU_GPU_PAGE_SIZE
, flags
);
744 * amdgpu_vm_update_ptes - make sure that page tables are valid
746 * @adev: amdgpu_device pointer
747 * @vm_update_params: see amdgpu_vm_update_params definition
749 * @start: start of GPU address range
750 * @end: end of GPU address range
751 * @dst: destination address to map to, the next dst inside the function
752 * @flags: mapping flags
754 * Update the page tables in the range @start - @end.
756 static void amdgpu_vm_update_ptes(struct amdgpu_device
*adev
,
757 struct amdgpu_vm_update_params
759 struct amdgpu_vm
*vm
,
760 uint64_t start
, uint64_t end
,
761 uint64_t dst
, uint32_t flags
)
763 const uint64_t mask
= AMDGPU_VM_PTE_COUNT
- 1;
765 uint64_t cur_pe_start
, cur_pe_end
, cur_dst
;
766 uint64_t addr
; /* next GPU address to be updated */
768 struct amdgpu_bo
*pt
;
769 unsigned nptes
; /* next number of ptes to be updated */
770 uint64_t next_pe_start
;
772 /* initialize the variables */
774 pt_idx
= addr
>> amdgpu_vm_block_size
;
775 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
777 if ((addr
& ~mask
) == (end
& ~mask
))
780 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
782 cur_pe_start
= amdgpu_bo_gpu_offset(pt
);
783 cur_pe_start
+= (addr
& mask
) * 8;
784 cur_pe_end
= cur_pe_start
+ 8 * nptes
;
789 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
791 /* walk over the address space and update the page tables */
793 pt_idx
= addr
>> amdgpu_vm_block_size
;
794 pt
= vm
->page_tables
[pt_idx
].entry
.robj
;
796 if ((addr
& ~mask
) == (end
& ~mask
))
799 nptes
= AMDGPU_VM_PTE_COUNT
- (addr
& mask
);
801 next_pe_start
= amdgpu_bo_gpu_offset(pt
);
802 next_pe_start
+= (addr
& mask
) * 8;
804 if (cur_pe_end
== next_pe_start
) {
805 /* The next ptb is consecutive to current ptb.
806 * Don't call amdgpu_vm_frag_ptes now.
807 * Will update two ptbs together in future.
809 cur_pe_end
+= 8 * nptes
;
811 amdgpu_vm_frag_ptes(adev
, vm_update_params
,
812 cur_pe_start
, cur_pe_end
,
815 cur_pe_start
= next_pe_start
;
816 cur_pe_end
= next_pe_start
+ 8 * nptes
;
822 dst
+= nptes
* AMDGPU_GPU_PAGE_SIZE
;
825 amdgpu_vm_frag_ptes(adev
, vm_update_params
, cur_pe_start
,
826 cur_pe_end
, cur_dst
, flags
);
830 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
832 * @adev: amdgpu_device pointer
833 * @src: address where to copy page table entries from
834 * @pages_addr: DMA addresses to use for mapping
836 * @start: start of mapped range
837 * @last: last mapped entry
838 * @flags: flags for the entries
839 * @addr: addr to set the area to
840 * @fence: optional resulting fence
842 * Fill in the page table entries between @start and @last.
843 * Returns 0 for success, -EINVAL for failure.
845 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device
*adev
,
847 dma_addr_t
*pages_addr
,
848 struct amdgpu_vm
*vm
,
849 uint64_t start
, uint64_t last
,
850 uint32_t flags
, uint64_t addr
,
851 struct fence
**fence
)
853 struct amdgpu_ring
*ring
;
854 void *owner
= AMDGPU_FENCE_OWNER_VM
;
855 unsigned nptes
, ncmds
, ndw
;
856 struct amdgpu_job
*job
;
857 struct amdgpu_vm_update_params vm_update_params
;
858 struct fence
*f
= NULL
;
861 ring
= container_of(vm
->entity
.sched
, struct amdgpu_ring
, sched
);
862 memset(&vm_update_params
, 0, sizeof(vm_update_params
));
863 vm_update_params
.src
= src
;
864 vm_update_params
.pages_addr
= pages_addr
;
866 /* sync to everything on unmapping */
867 if (!(flags
& AMDGPU_PTE_VALID
))
868 owner
= AMDGPU_FENCE_OWNER_UNDEFINED
;
870 nptes
= last
- start
+ 1;
873 * reserve space for one command every (1 << BLOCK_SIZE)
874 * entries or 2k dwords (whatever is smaller)
876 ncmds
= (nptes
>> min(amdgpu_vm_block_size
, 11)) + 1;
881 if (vm_update_params
.src
) {
882 /* only copy commands needed */
885 } else if (vm_update_params
.pages_addr
) {
886 /* header for write data commands */
889 /* body of write data command */
893 /* set page commands needed */
896 /* two extra commands for begin/end of fragment */
900 r
= amdgpu_job_alloc_with_ib(adev
, ndw
* 4, &job
);
904 vm_update_params
.ib
= &job
->ibs
[0];
906 r
= amdgpu_sync_resv(adev
, &job
->sync
, vm
->page_directory
->tbo
.resv
,
911 r
= reservation_object_reserve_shared(vm
->page_directory
->tbo
.resv
);
915 amdgpu_vm_update_ptes(adev
, &vm_update_params
, vm
, start
,
916 last
+ 1, addr
, flags
);
918 amdgpu_ring_pad_ib(ring
, vm_update_params
.ib
);
919 WARN_ON(vm_update_params
.ib
->length_dw
> ndw
);
920 r
= amdgpu_job_submit(job
, ring
, &vm
->entity
,
921 AMDGPU_FENCE_OWNER_VM
, &f
);
925 amdgpu_bo_fence(vm
->page_directory
, f
, true);
928 *fence
= fence_get(f
);
934 amdgpu_job_free(job
);
939 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
941 * @adev: amdgpu_device pointer
942 * @gtt_flags: flags as they are used for GTT
943 * @pages_addr: DMA addresses to use for mapping
945 * @mapping: mapped range and flags to use for the update
946 * @addr: addr to set the area to
947 * @flags: HW flags for the mapping
948 * @fence: optional resulting fence
950 * Split the mapping into smaller chunks so that each update fits
952 * Returns 0 for success, -EINVAL for failure.
954 static int amdgpu_vm_bo_split_mapping(struct amdgpu_device
*adev
,
956 dma_addr_t
*pages_addr
,
957 struct amdgpu_vm
*vm
,
958 struct amdgpu_bo_va_mapping
*mapping
,
959 uint32_t flags
, uint64_t addr
,
960 struct fence
**fence
)
962 const uint64_t max_size
= 64ULL * 1024ULL * 1024ULL / AMDGPU_GPU_PAGE_SIZE
;
964 uint64_t src
= 0, start
= mapping
->it
.start
;
967 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
968 * but in case of something, we filter the flags in first place
970 if (!(mapping
->flags
& AMDGPU_PTE_READABLE
))
971 flags
&= ~AMDGPU_PTE_READABLE
;
972 if (!(mapping
->flags
& AMDGPU_PTE_WRITEABLE
))
973 flags
&= ~AMDGPU_PTE_WRITEABLE
;
975 trace_amdgpu_vm_bo_update(mapping
);
978 if (flags
== gtt_flags
)
979 src
= adev
->gart
.table_addr
+ (addr
>> 12) * 8;
982 addr
+= mapping
->offset
;
984 if (!pages_addr
|| src
)
985 return amdgpu_vm_bo_update_mapping(adev
, src
, pages_addr
, vm
,
986 start
, mapping
->it
.last
,
989 while (start
!= mapping
->it
.last
+ 1) {
992 last
= min((uint64_t)mapping
->it
.last
, start
+ max_size
- 1);
993 r
= amdgpu_vm_bo_update_mapping(adev
, src
, pages_addr
, vm
,
994 start
, last
, flags
, addr
,
1000 addr
+= max_size
* AMDGPU_GPU_PAGE_SIZE
;
1007 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1009 * @adev: amdgpu_device pointer
1010 * @bo_va: requested BO and VM object
1013 * Fill in the page table entries for @bo_va.
1014 * Returns 0 for success, -EINVAL for failure.
1016 * Object have to be reserved and mutex must be locked!
1018 int amdgpu_vm_bo_update(struct amdgpu_device
*adev
,
1019 struct amdgpu_bo_va
*bo_va
,
1020 struct ttm_mem_reg
*mem
)
1022 struct amdgpu_vm
*vm
= bo_va
->vm
;
1023 struct amdgpu_bo_va_mapping
*mapping
;
1024 dma_addr_t
*pages_addr
= NULL
;
1025 uint32_t gtt_flags
, flags
;
1030 struct ttm_dma_tt
*ttm
;
1032 addr
= (u64
)mem
->start
<< PAGE_SHIFT
;
1033 switch (mem
->mem_type
) {
1035 ttm
= container_of(bo_va
->bo
->tbo
.ttm
, struct
1037 pages_addr
= ttm
->dma_address
;
1041 addr
+= adev
->vm_manager
.vram_base_offset
;
1051 flags
= amdgpu_ttm_tt_pte_flags(adev
, bo_va
->bo
->tbo
.ttm
, mem
);
1052 gtt_flags
= (adev
== bo_va
->bo
->adev
) ? flags
: 0;
1054 spin_lock(&vm
->status_lock
);
1055 if (!list_empty(&bo_va
->vm_status
))
1056 list_splice_init(&bo_va
->valids
, &bo_va
->invalids
);
1057 spin_unlock(&vm
->status_lock
);
1059 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1060 r
= amdgpu_vm_bo_split_mapping(adev
, gtt_flags
, pages_addr
, vm
,
1061 mapping
, flags
, addr
,
1062 &bo_va
->last_pt_update
);
1067 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1068 list_for_each_entry(mapping
, &bo_va
->valids
, list
)
1069 trace_amdgpu_vm_bo_mapping(mapping
);
1071 list_for_each_entry(mapping
, &bo_va
->invalids
, list
)
1072 trace_amdgpu_vm_bo_mapping(mapping
);
1075 spin_lock(&vm
->status_lock
);
1076 list_splice_init(&bo_va
->invalids
, &bo_va
->valids
);
1077 list_del_init(&bo_va
->vm_status
);
1079 list_add(&bo_va
->vm_status
, &vm
->cleared
);
1080 spin_unlock(&vm
->status_lock
);
1086 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1088 * @adev: amdgpu_device pointer
1091 * Make sure all freed BOs are cleared in the PT.
1092 * Returns 0 for success.
1094 * PTs have to be reserved and mutex must be locked!
1096 int amdgpu_vm_clear_freed(struct amdgpu_device
*adev
,
1097 struct amdgpu_vm
*vm
)
1099 struct amdgpu_bo_va_mapping
*mapping
;
1102 while (!list_empty(&vm
->freed
)) {
1103 mapping
= list_first_entry(&vm
->freed
,
1104 struct amdgpu_bo_va_mapping
, list
);
1105 list_del(&mapping
->list
);
1107 r
= amdgpu_vm_bo_split_mapping(adev
, 0, NULL
, vm
, mapping
,
1119 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1121 * @adev: amdgpu_device pointer
1124 * Make sure all invalidated BOs are cleared in the PT.
1125 * Returns 0 for success.
1127 * PTs have to be reserved and mutex must be locked!
1129 int amdgpu_vm_clear_invalids(struct amdgpu_device
*adev
,
1130 struct amdgpu_vm
*vm
, struct amdgpu_sync
*sync
)
1132 struct amdgpu_bo_va
*bo_va
= NULL
;
1135 spin_lock(&vm
->status_lock
);
1136 while (!list_empty(&vm
->invalidated
)) {
1137 bo_va
= list_first_entry(&vm
->invalidated
,
1138 struct amdgpu_bo_va
, vm_status
);
1139 spin_unlock(&vm
->status_lock
);
1141 r
= amdgpu_vm_bo_update(adev
, bo_va
, NULL
);
1145 spin_lock(&vm
->status_lock
);
1147 spin_unlock(&vm
->status_lock
);
1150 r
= amdgpu_sync_fence(adev
, sync
, bo_va
->last_pt_update
);
1156 * amdgpu_vm_bo_add - add a bo to a specific vm
1158 * @adev: amdgpu_device pointer
1160 * @bo: amdgpu buffer object
1162 * Add @bo into the requested vm.
1163 * Add @bo to the list of bos associated with the vm
1164 * Returns newly added bo_va or NULL for failure
1166 * Object has to be reserved!
1168 struct amdgpu_bo_va
*amdgpu_vm_bo_add(struct amdgpu_device
*adev
,
1169 struct amdgpu_vm
*vm
,
1170 struct amdgpu_bo
*bo
)
1172 struct amdgpu_bo_va
*bo_va
;
1174 bo_va
= kzalloc(sizeof(struct amdgpu_bo_va
), GFP_KERNEL
);
1175 if (bo_va
== NULL
) {
1180 bo_va
->ref_count
= 1;
1181 INIT_LIST_HEAD(&bo_va
->bo_list
);
1182 INIT_LIST_HEAD(&bo_va
->valids
);
1183 INIT_LIST_HEAD(&bo_va
->invalids
);
1184 INIT_LIST_HEAD(&bo_va
->vm_status
);
1186 list_add_tail(&bo_va
->bo_list
, &bo
->va
);
1192 * amdgpu_vm_bo_map - map bo inside a vm
1194 * @adev: amdgpu_device pointer
1195 * @bo_va: bo_va to store the address
1196 * @saddr: where to map the BO
1197 * @offset: requested offset in the BO
1198 * @flags: attributes of pages (read/write/valid/etc.)
1200 * Add a mapping of the BO at the specefied addr into the VM.
1201 * Returns 0 for success, error for failure.
1203 * Object has to be reserved and unreserved outside!
1205 int amdgpu_vm_bo_map(struct amdgpu_device
*adev
,
1206 struct amdgpu_bo_va
*bo_va
,
1207 uint64_t saddr
, uint64_t offset
,
1208 uint64_t size
, uint32_t flags
)
1210 struct amdgpu_bo_va_mapping
*mapping
;
1211 struct amdgpu_vm
*vm
= bo_va
->vm
;
1212 struct interval_tree_node
*it
;
1213 unsigned last_pfn
, pt_idx
;
1217 /* validate the parameters */
1218 if (saddr
& AMDGPU_GPU_PAGE_MASK
|| offset
& AMDGPU_GPU_PAGE_MASK
||
1219 size
== 0 || size
& AMDGPU_GPU_PAGE_MASK
)
1222 /* make sure object fit at this offset */
1223 eaddr
= saddr
+ size
- 1;
1224 if ((saddr
>= eaddr
) || (offset
+ size
> amdgpu_bo_size(bo_va
->bo
)))
1227 last_pfn
= eaddr
/ AMDGPU_GPU_PAGE_SIZE
;
1228 if (last_pfn
>= adev
->vm_manager
.max_pfn
) {
1229 dev_err(adev
->dev
, "va above limit (0x%08X >= 0x%08X)\n",
1230 last_pfn
, adev
->vm_manager
.max_pfn
);
1234 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1235 eaddr
/= AMDGPU_GPU_PAGE_SIZE
;
1237 it
= interval_tree_iter_first(&vm
->va
, saddr
, eaddr
);
1239 struct amdgpu_bo_va_mapping
*tmp
;
1240 tmp
= container_of(it
, struct amdgpu_bo_va_mapping
, it
);
1241 /* bo and tmp overlap, invalid addr */
1242 dev_err(adev
->dev
, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1243 "0x%010lx-0x%010lx\n", bo_va
->bo
, saddr
, eaddr
,
1244 tmp
->it
.start
, tmp
->it
.last
+ 1);
1249 mapping
= kmalloc(sizeof(*mapping
), GFP_KERNEL
);
1255 INIT_LIST_HEAD(&mapping
->list
);
1256 mapping
->it
.start
= saddr
;
1257 mapping
->it
.last
= eaddr
;
1258 mapping
->offset
= offset
;
1259 mapping
->flags
= flags
;
1261 list_add(&mapping
->list
, &bo_va
->invalids
);
1262 interval_tree_insert(&mapping
->it
, &vm
->va
);
1264 /* Make sure the page tables are allocated */
1265 saddr
>>= amdgpu_vm_block_size
;
1266 eaddr
>>= amdgpu_vm_block_size
;
1268 BUG_ON(eaddr
>= amdgpu_vm_num_pdes(adev
));
1270 if (eaddr
> vm
->max_pde_used
)
1271 vm
->max_pde_used
= eaddr
;
1273 /* walk over the address space and allocate the page tables */
1274 for (pt_idx
= saddr
; pt_idx
<= eaddr
; ++pt_idx
) {
1275 struct reservation_object
*resv
= vm
->page_directory
->tbo
.resv
;
1276 struct amdgpu_bo_list_entry
*entry
;
1277 struct amdgpu_bo
*pt
;
1279 entry
= &vm
->page_tables
[pt_idx
].entry
;
1283 r
= amdgpu_bo_create(adev
, AMDGPU_VM_PTE_COUNT
* 8,
1284 AMDGPU_GPU_PAGE_SIZE
, true,
1285 AMDGPU_GEM_DOMAIN_VRAM
,
1286 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1291 /* Keep a reference to the page table to avoid freeing
1292 * them up in the wrong order.
1294 pt
->parent
= amdgpu_bo_ref(vm
->page_directory
);
1296 r
= amdgpu_vm_clear_bo(adev
, vm
, pt
);
1298 amdgpu_bo_unref(&pt
);
1303 entry
->priority
= 0;
1304 entry
->tv
.bo
= &entry
->robj
->tbo
;
1305 entry
->tv
.shared
= true;
1306 entry
->user_pages
= NULL
;
1307 vm
->page_tables
[pt_idx
].addr
= 0;
1313 list_del(&mapping
->list
);
1314 interval_tree_remove(&mapping
->it
, &vm
->va
);
1315 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1323 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1325 * @adev: amdgpu_device pointer
1326 * @bo_va: bo_va to remove the address from
1327 * @saddr: where to the BO is mapped
1329 * Remove a mapping of the BO at the specefied addr from the VM.
1330 * Returns 0 for success, error for failure.
1332 * Object has to be reserved and unreserved outside!
1334 int amdgpu_vm_bo_unmap(struct amdgpu_device
*adev
,
1335 struct amdgpu_bo_va
*bo_va
,
1338 struct amdgpu_bo_va_mapping
*mapping
;
1339 struct amdgpu_vm
*vm
= bo_va
->vm
;
1342 saddr
/= AMDGPU_GPU_PAGE_SIZE
;
1344 list_for_each_entry(mapping
, &bo_va
->valids
, list
) {
1345 if (mapping
->it
.start
== saddr
)
1349 if (&mapping
->list
== &bo_va
->valids
) {
1352 list_for_each_entry(mapping
, &bo_va
->invalids
, list
) {
1353 if (mapping
->it
.start
== saddr
)
1357 if (&mapping
->list
== &bo_va
->invalids
)
1361 list_del(&mapping
->list
);
1362 interval_tree_remove(&mapping
->it
, &vm
->va
);
1363 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1366 list_add(&mapping
->list
, &vm
->freed
);
1374 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1376 * @adev: amdgpu_device pointer
1377 * @bo_va: requested bo_va
1379 * Remove @bo_va->bo from the requested vm.
1381 * Object have to be reserved!
1383 void amdgpu_vm_bo_rmv(struct amdgpu_device
*adev
,
1384 struct amdgpu_bo_va
*bo_va
)
1386 struct amdgpu_bo_va_mapping
*mapping
, *next
;
1387 struct amdgpu_vm
*vm
= bo_va
->vm
;
1389 list_del(&bo_va
->bo_list
);
1391 spin_lock(&vm
->status_lock
);
1392 list_del(&bo_va
->vm_status
);
1393 spin_unlock(&vm
->status_lock
);
1395 list_for_each_entry_safe(mapping
, next
, &bo_va
->valids
, list
) {
1396 list_del(&mapping
->list
);
1397 interval_tree_remove(&mapping
->it
, &vm
->va
);
1398 trace_amdgpu_vm_bo_unmap(bo_va
, mapping
);
1399 list_add(&mapping
->list
, &vm
->freed
);
1401 list_for_each_entry_safe(mapping
, next
, &bo_va
->invalids
, list
) {
1402 list_del(&mapping
->list
);
1403 interval_tree_remove(&mapping
->it
, &vm
->va
);
1407 fence_put(bo_va
->last_pt_update
);
1412 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1414 * @adev: amdgpu_device pointer
1416 * @bo: amdgpu buffer object
1418 * Mark @bo as invalid.
1420 void amdgpu_vm_bo_invalidate(struct amdgpu_device
*adev
,
1421 struct amdgpu_bo
*bo
)
1423 struct amdgpu_bo_va
*bo_va
;
1425 list_for_each_entry(bo_va
, &bo
->va
, bo_list
) {
1426 spin_lock(&bo_va
->vm
->status_lock
);
1427 if (list_empty(&bo_va
->vm_status
))
1428 list_add(&bo_va
->vm_status
, &bo_va
->vm
->invalidated
);
1429 spin_unlock(&bo_va
->vm
->status_lock
);
1434 * amdgpu_vm_init - initialize a vm instance
1436 * @adev: amdgpu_device pointer
1441 int amdgpu_vm_init(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1443 const unsigned align
= min(AMDGPU_VM_PTB_ALIGN_SIZE
,
1444 AMDGPU_VM_PTE_COUNT
* 8);
1445 unsigned pd_size
, pd_entries
;
1446 unsigned ring_instance
;
1447 struct amdgpu_ring
*ring
;
1448 struct amd_sched_rq
*rq
;
1451 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1454 vm
->client_id
= atomic64_inc_return(&adev
->vm_manager
.client_counter
);
1455 spin_lock_init(&vm
->status_lock
);
1456 INIT_LIST_HEAD(&vm
->invalidated
);
1457 INIT_LIST_HEAD(&vm
->cleared
);
1458 INIT_LIST_HEAD(&vm
->freed
);
1460 pd_size
= amdgpu_vm_directory_size(adev
);
1461 pd_entries
= amdgpu_vm_num_pdes(adev
);
1463 /* allocate page table array */
1464 vm
->page_tables
= drm_calloc_large(pd_entries
, sizeof(struct amdgpu_vm_pt
));
1465 if (vm
->page_tables
== NULL
) {
1466 DRM_ERROR("Cannot allocate memory for page table array\n");
1470 /* create scheduler entity for page table updates */
1472 ring_instance
= atomic_inc_return(&adev
->vm_manager
.vm_pte_next_ring
);
1473 ring_instance
%= adev
->vm_manager
.vm_pte_num_rings
;
1474 ring
= adev
->vm_manager
.vm_pte_rings
[ring_instance
];
1475 rq
= &ring
->sched
.sched_rq
[AMD_SCHED_PRIORITY_KERNEL
];
1476 r
= amd_sched_entity_init(&ring
->sched
, &vm
->entity
,
1477 rq
, amdgpu_sched_jobs
);
1481 vm
->page_directory_fence
= NULL
;
1483 r
= amdgpu_bo_create(adev
, pd_size
, align
, true,
1484 AMDGPU_GEM_DOMAIN_VRAM
,
1485 AMDGPU_GEM_CREATE_NO_CPU_ACCESS
,
1486 NULL
, NULL
, &vm
->page_directory
);
1488 goto error_free_sched_entity
;
1490 r
= amdgpu_bo_reserve(vm
->page_directory
, false);
1492 goto error_free_page_directory
;
1494 r
= amdgpu_vm_clear_bo(adev
, vm
, vm
->page_directory
);
1495 amdgpu_bo_unreserve(vm
->page_directory
);
1497 goto error_free_page_directory
;
1501 error_free_page_directory
:
1502 amdgpu_bo_unref(&vm
->page_directory
);
1503 vm
->page_directory
= NULL
;
1505 error_free_sched_entity
:
1506 amd_sched_entity_fini(&ring
->sched
, &vm
->entity
);
1512 * amdgpu_vm_fini - tear down a vm instance
1514 * @adev: amdgpu_device pointer
1518 * Unbind the VM and remove all bos from the vm bo list
1520 void amdgpu_vm_fini(struct amdgpu_device
*adev
, struct amdgpu_vm
*vm
)
1522 struct amdgpu_bo_va_mapping
*mapping
, *tmp
;
1525 amd_sched_entity_fini(vm
->entity
.sched
, &vm
->entity
);
1527 if (!RB_EMPTY_ROOT(&vm
->va
)) {
1528 dev_err(adev
->dev
, "still active bo inside vm\n");
1530 rbtree_postorder_for_each_entry_safe(mapping
, tmp
, &vm
->va
, it
.rb
) {
1531 list_del(&mapping
->list
);
1532 interval_tree_remove(&mapping
->it
, &vm
->va
);
1535 list_for_each_entry_safe(mapping
, tmp
, &vm
->freed
, list
) {
1536 list_del(&mapping
->list
);
1540 for (i
= 0; i
< amdgpu_vm_num_pdes(adev
); i
++)
1541 amdgpu_bo_unref(&vm
->page_tables
[i
].entry
.robj
);
1542 drm_free_large(vm
->page_tables
);
1544 amdgpu_bo_unref(&vm
->page_directory
);
1545 fence_put(vm
->page_directory_fence
);
1549 * amdgpu_vm_manager_init - init the VM manager
1551 * @adev: amdgpu_device pointer
1553 * Initialize the VM manager structures
1555 void amdgpu_vm_manager_init(struct amdgpu_device
*adev
)
1559 INIT_LIST_HEAD(&adev
->vm_manager
.ids_lru
);
1561 /* skip over VMID 0, since it is the system VM */
1562 for (i
= 1; i
< adev
->vm_manager
.num_ids
; ++i
) {
1563 amdgpu_vm_reset_id(adev
, i
);
1564 amdgpu_sync_create(&adev
->vm_manager
.ids
[i
].active
);
1565 list_add_tail(&adev
->vm_manager
.ids
[i
].list
,
1566 &adev
->vm_manager
.ids_lru
);
1569 adev
->vm_manager
.fence_context
= fence_context_alloc(AMDGPU_MAX_RINGS
);
1570 for (i
= 0; i
< AMDGPU_MAX_RINGS
; ++i
)
1571 adev
->vm_manager
.seqno
[i
] = 0;
1573 atomic_set(&adev
->vm_manager
.vm_pte_next_ring
, 0);
1574 atomic64_set(&adev
->vm_manager
.client_counter
, 0);
1578 * amdgpu_vm_manager_fini - cleanup VM manager
1580 * @adev: amdgpu_device pointer
1582 * Cleanup the VM manager and free resources.
1584 void amdgpu_vm_manager_fini(struct amdgpu_device
*adev
)
1588 for (i
= 0; i
< AMDGPU_NUM_VM
; ++i
) {
1589 struct amdgpu_vm_id
*id
= &adev
->vm_manager
.ids
[i
];
1591 fence_put(adev
->vm_manager
.ids
[i
].first
);
1592 amdgpu_sync_free(&adev
->vm_manager
.ids
[i
].active
);
1593 fence_put(id
->flushed_updates
);