2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_ih.h"
28 #include "bif/bif_4_1_d.h"
29 #include "bif/bif_4_1_sh_mask.h"
31 #include "oss/oss_2_0_d.h"
32 #include "oss/oss_2_0_sh_mask.h"
36 * Starting with r6xx, interrupts are handled via a ring buffer.
37 * Ring buffers are areas of GPU accessible memory that the GPU
38 * writes interrupt vectors into and the host reads vectors out of.
39 * There is a rptr (read pointer) that determines where the
40 * host is currently reading, and a wptr (write pointer)
41 * which determines where the GPU has written. When the
42 * pointers are equal, the ring is idle. When the GPU
43 * writes vectors to the ring buffer, it increments the
44 * wptr. When there is an interrupt, the host then starts
45 * fetching commands and processing them until the pointers are
46 * equal again at which point it updates the rptr.
49 static void cik_ih_set_interrupt_funcs(struct amdgpu_device
*adev
);
52 * cik_ih_enable_interrupts - Enable the interrupt ring buffer
54 * @adev: amdgpu_device pointer
56 * Enable the interrupt ring buffer (CIK).
58 static void cik_ih_enable_interrupts(struct amdgpu_device
*adev
)
60 u32 ih_cntl
= RREG32(mmIH_CNTL
);
61 u32 ih_rb_cntl
= RREG32(mmIH_RB_CNTL
);
63 ih_cntl
|= IH_CNTL__ENABLE_INTR_MASK
;
64 ih_rb_cntl
|= IH_RB_CNTL__RB_ENABLE_MASK
;
65 WREG32(mmIH_CNTL
, ih_cntl
);
66 WREG32(mmIH_RB_CNTL
, ih_rb_cntl
);
67 adev
->irq
.ih
.enabled
= true;
71 * cik_ih_disable_interrupts - Disable the interrupt ring buffer
73 * @adev: amdgpu_device pointer
75 * Disable the interrupt ring buffer (CIK).
77 static void cik_ih_disable_interrupts(struct amdgpu_device
*adev
)
79 u32 ih_rb_cntl
= RREG32(mmIH_RB_CNTL
);
80 u32 ih_cntl
= RREG32(mmIH_CNTL
);
82 ih_rb_cntl
&= ~IH_RB_CNTL__RB_ENABLE_MASK
;
83 ih_cntl
&= ~IH_CNTL__ENABLE_INTR_MASK
;
84 WREG32(mmIH_RB_CNTL
, ih_rb_cntl
);
85 WREG32(mmIH_CNTL
, ih_cntl
);
86 /* set rptr, wptr to 0 */
87 WREG32(mmIH_RB_RPTR
, 0);
88 WREG32(mmIH_RB_WPTR
, 0);
89 adev
->irq
.ih
.enabled
= false;
90 adev
->irq
.ih
.rptr
= 0;
94 * cik_ih_irq_init - init and enable the interrupt ring
96 * @adev: amdgpu_device pointer
98 * Allocate a ring buffer for the interrupt controller,
99 * enable the RLC, disable interrupts, enable the IH
100 * ring buffer and enable it (CIK).
101 * Called at device load and reume.
102 * Returns 0 for success, errors for failure.
104 static int cik_ih_irq_init(struct amdgpu_device
*adev
)
107 u32 interrupt_cntl
, ih_cntl
, ih_rb_cntl
;
111 cik_ih_disable_interrupts(adev
);
113 /* setup interrupt control */
114 WREG32(mmINTERRUPT_CNTL2
, adev
->dummy_page
.addr
>> 8);
115 interrupt_cntl
= RREG32(mmINTERRUPT_CNTL
);
116 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
117 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
119 interrupt_cntl
&= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK
;
120 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
121 interrupt_cntl
&= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK
;
122 WREG32(mmINTERRUPT_CNTL
, interrupt_cntl
);
124 WREG32(mmIH_RB_BASE
, adev
->irq
.ih
.gpu_addr
>> 8);
125 rb_bufsz
= order_base_2(adev
->irq
.ih
.ring_size
/ 4);
127 ih_rb_cntl
= (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK
|
128 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK
|
131 ih_rb_cntl
|= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK
;
133 /* set the writeback address whether it's enabled or not */
134 wptr_off
= adev
->wb
.gpu_addr
+ (adev
->irq
.ih
.wptr_offs
* 4);
135 WREG32(mmIH_RB_WPTR_ADDR_LO
, lower_32_bits(wptr_off
));
136 WREG32(mmIH_RB_WPTR_ADDR_HI
, upper_32_bits(wptr_off
) & 0xFF);
138 WREG32(mmIH_RB_CNTL
, ih_rb_cntl
);
140 /* set rptr, wptr to 0 */
141 WREG32(mmIH_RB_RPTR
, 0);
142 WREG32(mmIH_RB_WPTR
, 0);
144 /* Default settings for IH_CNTL (disabled at first) */
145 ih_cntl
= (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT
) |
146 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT
) |
147 (0 << IH_CNTL__MC_VMID__SHIFT
);
148 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */
149 if (adev
->irq
.msi_enabled
)
150 ih_cntl
|= IH_CNTL__RPTR_REARM_MASK
;
151 WREG32(mmIH_CNTL
, ih_cntl
);
153 pci_set_master(adev
->pdev
);
156 cik_ih_enable_interrupts(adev
);
162 * cik_ih_irq_disable - disable interrupts
164 * @adev: amdgpu_device pointer
166 * Disable interrupts on the hw (CIK).
168 static void cik_ih_irq_disable(struct amdgpu_device
*adev
)
170 cik_ih_disable_interrupts(adev
);
171 /* Wait and acknowledge irq */
176 * cik_ih_get_wptr - get the IH ring buffer wptr
178 * @adev: amdgpu_device pointer
180 * Get the IH ring buffer wptr from either the register
181 * or the writeback memory buffer (CIK). Also check for
182 * ring buffer overflow and deal with it.
183 * Used by cik_irq_process().
184 * Returns the value of the wptr.
186 static u32
cik_ih_get_wptr(struct amdgpu_device
*adev
)
190 wptr
= le32_to_cpu(adev
->wb
.wb
[adev
->irq
.ih
.wptr_offs
]);
192 if (wptr
& IH_RB_WPTR__RB_OVERFLOW_MASK
) {
193 wptr
&= ~IH_RB_WPTR__RB_OVERFLOW_MASK
;
194 /* When a ring buffer overflow happen start parsing interrupt
195 * from the last not overwritten vector (wptr + 16). Hopefully
196 * this should allow us to catchup.
198 dev_warn(adev
->dev
, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
199 wptr
, adev
->irq
.ih
.rptr
, (wptr
+ 16) & adev
->irq
.ih
.ptr_mask
);
200 adev
->irq
.ih
.rptr
= (wptr
+ 16) & adev
->irq
.ih
.ptr_mask
;
201 tmp
= RREG32(mmIH_RB_CNTL
);
202 tmp
|= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK
;
203 WREG32(mmIH_RB_CNTL
, tmp
);
205 return (wptr
& adev
->irq
.ih
.ptr_mask
);
209 * Each IV ring entry is 128 bits:
210 * [7:0] - interrupt source id
212 * [59:32] - interrupt source data
216 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
217 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
218 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
219 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
221 * - ME1&2 compute dispatcher (4 pipes each)
223 * INSTANCE_ID [1:0], QUEUE_ID[1:0]
224 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
225 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
228 * [127:96] - reserved
232 * cik_ih_decode_iv - decode an interrupt vector
234 * @adev: amdgpu_device pointer
236 * Decodes the interrupt vector at the current rptr
237 * position and also advance the position.
239 static void cik_ih_decode_iv(struct amdgpu_device
*adev
,
240 struct amdgpu_iv_entry
*entry
)
242 /* wptr/rptr are in bytes! */
243 u32 ring_index
= adev
->irq
.ih
.rptr
>> 2;
246 dw
[0] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 0]);
247 dw
[1] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 1]);
248 dw
[2] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 2]);
249 dw
[3] = le32_to_cpu(adev
->irq
.ih
.ring
[ring_index
+ 3]);
251 entry
->src_id
= dw
[0] & 0xff;
252 entry
->src_data
= dw
[1] & 0xfffffff;
253 entry
->ring_id
= dw
[2] & 0xff;
254 entry
->vm_id
= (dw
[2] >> 8) & 0xff;
255 entry
->pas_id
= (dw
[2] >> 16) & 0xffff;
257 /* wptr/rptr are in bytes! */
258 adev
->irq
.ih
.rptr
+= 16;
262 * cik_ih_set_rptr - set the IH ring buffer rptr
264 * @adev: amdgpu_device pointer
266 * Set the IH ring buffer rptr.
268 static void cik_ih_set_rptr(struct amdgpu_device
*adev
)
270 WREG32(mmIH_RB_RPTR
, adev
->irq
.ih
.rptr
);
273 static int cik_ih_early_init(void *handle
)
275 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
278 ret
= amdgpu_irq_add_domain(adev
);
282 cik_ih_set_interrupt_funcs(adev
);
287 static int cik_ih_sw_init(void *handle
)
290 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
292 r
= amdgpu_ih_ring_init(adev
, 64 * 1024, false);
296 r
= amdgpu_irq_init(adev
);
301 static int cik_ih_sw_fini(void *handle
)
303 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
305 amdgpu_irq_fini(adev
);
306 amdgpu_ih_ring_fini(adev
);
307 amdgpu_irq_remove_domain(adev
);
312 static int cik_ih_hw_init(void *handle
)
315 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
317 r
= cik_ih_irq_init(adev
);
324 static int cik_ih_hw_fini(void *handle
)
326 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
328 cik_ih_irq_disable(adev
);
333 static int cik_ih_suspend(void *handle
)
335 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
337 return cik_ih_hw_fini(adev
);
340 static int cik_ih_resume(void *handle
)
342 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
344 return cik_ih_hw_init(adev
);
347 static bool cik_ih_is_idle(void *handle
)
349 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
350 u32 tmp
= RREG32(mmSRBM_STATUS
);
352 if (tmp
& SRBM_STATUS__IH_BUSY_MASK
)
358 static int cik_ih_wait_for_idle(void *handle
)
362 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
364 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
366 tmp
= RREG32(mmSRBM_STATUS
) & SRBM_STATUS__IH_BUSY_MASK
;
374 static int cik_ih_soft_reset(void *handle
)
376 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
378 u32 srbm_soft_reset
= 0;
379 u32 tmp
= RREG32(mmSRBM_STATUS
);
381 if (tmp
& SRBM_STATUS__IH_BUSY_MASK
)
382 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK
;
384 if (srbm_soft_reset
) {
385 tmp
= RREG32(mmSRBM_SOFT_RESET
);
386 tmp
|= srbm_soft_reset
;
387 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
388 WREG32(mmSRBM_SOFT_RESET
, tmp
);
389 tmp
= RREG32(mmSRBM_SOFT_RESET
);
393 tmp
&= ~srbm_soft_reset
;
394 WREG32(mmSRBM_SOFT_RESET
, tmp
);
395 tmp
= RREG32(mmSRBM_SOFT_RESET
);
397 /* Wait a little for things to settle down */
404 static int cik_ih_set_clockgating_state(void *handle
,
405 enum amd_clockgating_state state
)
410 static int cik_ih_set_powergating_state(void *handle
,
411 enum amd_powergating_state state
)
416 const struct amd_ip_funcs cik_ih_ip_funcs
= {
418 .early_init
= cik_ih_early_init
,
420 .sw_init
= cik_ih_sw_init
,
421 .sw_fini
= cik_ih_sw_fini
,
422 .hw_init
= cik_ih_hw_init
,
423 .hw_fini
= cik_ih_hw_fini
,
424 .suspend
= cik_ih_suspend
,
425 .resume
= cik_ih_resume
,
426 .is_idle
= cik_ih_is_idle
,
427 .wait_for_idle
= cik_ih_wait_for_idle
,
428 .soft_reset
= cik_ih_soft_reset
,
429 .set_clockgating_state
= cik_ih_set_clockgating_state
,
430 .set_powergating_state
= cik_ih_set_powergating_state
,
433 static const struct amdgpu_ih_funcs cik_ih_funcs
= {
434 .get_wptr
= cik_ih_get_wptr
,
435 .decode_iv
= cik_ih_decode_iv
,
436 .set_rptr
= cik_ih_set_rptr
439 static void cik_ih_set_interrupt_funcs(struct amdgpu_device
*adev
)
441 if (adev
->irq
.ih_funcs
== NULL
)
442 adev
->irq
.ih_funcs
= &cik_ih_funcs
;