2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_trace.h"
32 #include "bif/bif_4_1_d.h"
33 #include "bif/bif_4_1_sh_mask.h"
35 #include "gca/gfx_7_2_d.h"
36 #include "gca/gfx_7_2_enum.h"
37 #include "gca/gfx_7_2_sh_mask.h"
39 #include "gmc/gmc_7_1_d.h"
40 #include "gmc/gmc_7_1_sh_mask.h"
42 #include "oss/oss_2_0_d.h"
43 #include "oss/oss_2_0_sh_mask.h"
45 static const u32 sdma_offsets
[SDMA_MAX_INSTANCE
] =
47 SDMA0_REGISTER_OFFSET
,
51 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
);
52 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
);
53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
);
54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
);
56 MODULE_FIRMWARE("radeon/bonaire_sdma.bin");
57 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin");
58 MODULE_FIRMWARE("radeon/hawaii_sdma.bin");
59 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin");
60 MODULE_FIRMWARE("radeon/kaveri_sdma.bin");
61 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin");
62 MODULE_FIRMWARE("radeon/kabini_sdma.bin");
63 MODULE_FIRMWARE("radeon/kabini_sdma1.bin");
64 MODULE_FIRMWARE("radeon/mullins_sdma.bin");
65 MODULE_FIRMWARE("radeon/mullins_sdma1.bin");
67 u32
amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device
*adev
);
71 * Starting with CIK, the GPU has new asynchronous
72 * DMA engines. These engines are used for compute
73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
75 * and 2 queues used for compute.
77 * The programming model is very similar to the CP
78 * (ring buffer, IBs, etc.), but sDMA has it's own
79 * packet format that is different from the PM4 format
80 * used by the CP. sDMA supports copying data, writing
81 * embedded data, solid fills, and a number of other
82 * things. It also has support for tiling/detiling of
87 * cik_sdma_init_microcode - load ucode images from disk
89 * @adev: amdgpu_device pointer
91 * Use the firmware interface to load the ucode images into
92 * the driver (not loaded into hw).
93 * Returns 0 on success, error on failure.
95 static int cik_sdma_init_microcode(struct amdgpu_device
*adev
)
97 const char *chip_name
;
103 switch (adev
->asic_type
) {
105 chip_name
= "bonaire";
108 chip_name
= "hawaii";
111 chip_name
= "kaveri";
114 chip_name
= "kabini";
117 chip_name
= "mullins";
122 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
124 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma.bin", chip_name
);
126 snprintf(fw_name
, sizeof(fw_name
), "radeon/%s_sdma1.bin", chip_name
);
127 err
= request_firmware(&adev
->sdma
[i
].fw
, fw_name
, adev
->dev
);
130 err
= amdgpu_ucode_validate(adev
->sdma
[i
].fw
);
135 "cik_sdma: Failed to load firmware \"%s\"\n",
137 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
138 release_firmware(adev
->sdma
[i
].fw
);
139 adev
->sdma
[i
].fw
= NULL
;
146 * cik_sdma_ring_get_rptr - get the current read pointer
148 * @ring: amdgpu ring pointer
150 * Get the current rptr from the hardware (CIK+).
152 static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring
*ring
)
156 rptr
= ring
->adev
->wb
.wb
[ring
->rptr_offs
];
158 return (rptr
& 0x3fffc) >> 2;
162 * cik_sdma_ring_get_wptr - get the current write pointer
164 * @ring: amdgpu ring pointer
166 * Get the current wptr from the hardware (CIK+).
168 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring
*ring
)
170 struct amdgpu_device
*adev
= ring
->adev
;
171 u32 me
= (ring
== &adev
->sdma
[0].ring
) ? 0 : 1;
173 return (RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
]) & 0x3fffc) >> 2;
177 * cik_sdma_ring_set_wptr - commit the write pointer
179 * @ring: amdgpu ring pointer
181 * Write the wptr back to the hardware (CIK+).
183 static void cik_sdma_ring_set_wptr(struct amdgpu_ring
*ring
)
185 struct amdgpu_device
*adev
= ring
->adev
;
186 u32 me
= (ring
== &adev
->sdma
[0].ring
) ? 0 : 1;
188 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[me
], (ring
->wptr
<< 2) & 0x3fffc);
192 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
194 * @ring: amdgpu ring pointer
195 * @ib: IB object to schedule
197 * Schedule an IB in the DMA ring (CIK).
199 static void cik_sdma_ring_emit_ib(struct amdgpu_ring
*ring
,
200 struct amdgpu_ib
*ib
)
202 u32 extra_bits
= (ib
->vm
? ib
->vm
->ids
[ring
->idx
].id
: 0) & 0xf;
203 u32 next_rptr
= ring
->wptr
+ 5;
205 while ((next_rptr
& 7) != 4)
209 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
210 amdgpu_ring_write(ring
, ring
->next_rptr_gpu_addr
& 0xfffffffc);
211 amdgpu_ring_write(ring
, upper_32_bits(ring
->next_rptr_gpu_addr
) & 0xffffffff);
212 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
213 amdgpu_ring_write(ring
, next_rptr
);
215 /* IB packet must end on a 8 DW boundary */
216 while ((ring
->wptr
& 7) != 4)
217 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0));
218 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER
, 0, extra_bits
));
219 amdgpu_ring_write(ring
, ib
->gpu_addr
& 0xffffffe0); /* base must be 32 byte aligned */
220 amdgpu_ring_write(ring
, upper_32_bits(ib
->gpu_addr
) & 0xffffffff);
221 amdgpu_ring_write(ring
, ib
->length_dw
);
226 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
228 * @ring: amdgpu ring pointer
230 * Emit an hdp flush packet on the requested DMA ring.
232 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring
*ring
)
234 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
235 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
238 if (ring
== &ring
->adev
->sdma
[0].ring
)
239 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA0_MASK
;
241 ref_and_mask
= GPU_HDP_FLUSH_DONE__SDMA1_MASK
;
243 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
244 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_DONE
<< 2);
245 amdgpu_ring_write(ring
, mmGPU_HDP_FLUSH_REQ
<< 2);
246 amdgpu_ring_write(ring
, ref_and_mask
); /* reference */
247 amdgpu_ring_write(ring
, ref_and_mask
); /* mask */
248 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
252 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
254 * @ring: amdgpu ring pointer
255 * @fence: amdgpu fence object
257 * Add a DMA fence packet to the ring to write
258 * the fence seq number and DMA trap packet to generate
259 * an interrupt if needed (CIK).
261 static void cik_sdma_ring_emit_fence(struct amdgpu_ring
*ring
, u64 addr
, u64 seq
,
264 bool write64bit
= flags
& AMDGPU_FENCE_FLAG_64BIT
;
265 /* write the fence */
266 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
267 amdgpu_ring_write(ring
, lower_32_bits(addr
));
268 amdgpu_ring_write(ring
, upper_32_bits(addr
));
269 amdgpu_ring_write(ring
, lower_32_bits(seq
));
271 /* optionally write high bits as well */
274 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_FENCE
, 0, 0));
275 amdgpu_ring_write(ring
, lower_32_bits(addr
));
276 amdgpu_ring_write(ring
, upper_32_bits(addr
));
277 amdgpu_ring_write(ring
, upper_32_bits(seq
));
280 /* generate an interrupt */
281 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_TRAP
, 0, 0));
285 * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring
287 * @ring: amdgpu_ring structure holding ring information
288 * @semaphore: amdgpu semaphore object
289 * @emit_wait: wait or signal semaphore
291 * Add a DMA semaphore packet to the ring wait on or signal
294 static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring
*ring
,
295 struct amdgpu_semaphore
*semaphore
,
298 u64 addr
= semaphore
->gpu_addr
;
299 u32 extra_bits
= emit_wait
? 0 : SDMA_SEMAPHORE_EXTRA_S
;
301 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE
, 0, extra_bits
));
302 amdgpu_ring_write(ring
, addr
& 0xfffffff8);
303 amdgpu_ring_write(ring
, upper_32_bits(addr
) & 0xffffffff);
309 * cik_sdma_gfx_stop - stop the gfx async dma engines
311 * @adev: amdgpu_device pointer
313 * Stop the gfx async dma ring buffers (CIK).
315 static void cik_sdma_gfx_stop(struct amdgpu_device
*adev
)
317 struct amdgpu_ring
*sdma0
= &adev
->sdma
[0].ring
;
318 struct amdgpu_ring
*sdma1
= &adev
->sdma
[1].ring
;
322 if ((adev
->mman
.buffer_funcs_ring
== sdma0
) ||
323 (adev
->mman
.buffer_funcs_ring
== sdma1
))
324 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.visible_vram_size
);
326 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
327 rb_cntl
= RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]);
328 rb_cntl
&= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
;
329 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
330 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], 0);
332 sdma0
->ready
= false;
333 sdma1
->ready
= false;
337 * cik_sdma_rlc_stop - stop the compute async dma engines
339 * @adev: amdgpu_device pointer
341 * Stop the compute async dma queues (CIK).
343 static void cik_sdma_rlc_stop(struct amdgpu_device
*adev
)
349 * cik_sdma_enable - stop the async dma engines
351 * @adev: amdgpu_device pointer
352 * @enable: enable/disable the DMA MEs.
354 * Halt or unhalt the async dma engines (CIK).
356 static void cik_sdma_enable(struct amdgpu_device
*adev
, bool enable
)
361 if (enable
== false) {
362 cik_sdma_gfx_stop(adev
);
363 cik_sdma_rlc_stop(adev
);
366 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
367 me_cntl
= RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]);
369 me_cntl
&= ~SDMA0_F32_CNTL__HALT_MASK
;
371 me_cntl
|= SDMA0_F32_CNTL__HALT_MASK
;
372 WREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
], me_cntl
);
377 * cik_sdma_gfx_resume - setup and start the async dma engines
379 * @adev: amdgpu_device pointer
381 * Set up the gfx DMA ring buffers and enable them (CIK).
382 * Returns 0 for success, error for failure.
384 static int cik_sdma_gfx_resume(struct amdgpu_device
*adev
)
386 struct amdgpu_ring
*ring
;
387 u32 rb_cntl
, ib_cntl
;
392 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
393 ring
= &adev
->sdma
[i
].ring
;
394 wb_offset
= (ring
->rptr_offs
* 4);
396 mutex_lock(&adev
->srbm_mutex
);
397 for (j
= 0; j
< 16; j
++) {
398 cik_srbm_select(adev
, 0, 0, 0, j
);
400 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
], 0);
401 WREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
], 0);
402 /* XXX SDMA RLC - todo */
404 cik_srbm_select(adev
, 0, 0, 0, 0);
405 mutex_unlock(&adev
->srbm_mutex
);
407 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
], 0);
408 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
], 0);
410 /* Set ring buffer size in dwords */
411 rb_bufsz
= order_base_2(ring
->ring_size
/ 4);
412 rb_cntl
= rb_bufsz
<< 1;
414 rb_cntl
|= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK
|
415 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK
;
417 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
], rb_cntl
);
419 /* Initialize the ring buffer's read and write pointers */
420 WREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
], 0);
421 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], 0);
423 /* set the wb address whether it's enabled or not */
424 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
],
425 upper_32_bits(adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFF);
426 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
],
427 ((adev
->wb
.gpu_addr
+ wb_offset
) & 0xFFFFFFFC));
429 rb_cntl
|= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK
;
431 WREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
], ring
->gpu_addr
>> 8);
432 WREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
], ring
->gpu_addr
>> 40);
435 WREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
], ring
->wptr
<< 2);
438 WREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
],
439 rb_cntl
| SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK
);
441 ib_cntl
= SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK
;
443 ib_cntl
|= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK
;
446 WREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
], ib_cntl
);
450 r
= amdgpu_ring_test_ring(ring
);
456 if (adev
->mman
.buffer_funcs_ring
== ring
)
457 amdgpu_ttm_set_active_vram_size(adev
, adev
->mc
.real_vram_size
);
464 * cik_sdma_rlc_resume - setup and start the async dma engines
466 * @adev: amdgpu_device pointer
468 * Set up the compute DMA queues and enable them (CIK).
469 * Returns 0 for success, error for failure.
471 static int cik_sdma_rlc_resume(struct amdgpu_device
*adev
)
478 * cik_sdma_load_microcode - load the sDMA ME ucode
480 * @adev: amdgpu_device pointer
482 * Loads the sDMA0/1 ucode.
483 * Returns 0 for success, -EINVAL if the ucode is not available.
485 static int cik_sdma_load_microcode(struct amdgpu_device
*adev
)
487 const struct sdma_firmware_header_v1_0
*hdr
;
488 const __le32
*fw_data
;
492 if (!adev
->sdma
[0].fw
|| !adev
->sdma
[1].fw
)
496 cik_sdma_enable(adev
, false);
498 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
499 hdr
= (const struct sdma_firmware_header_v1_0
*)adev
->sdma
[i
].fw
->data
;
500 amdgpu_ucode_print_sdma_hdr(&hdr
->header
);
501 fw_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
502 adev
->sdma
[i
].fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
503 fw_data
= (const __le32
*)
504 (adev
->sdma
[i
].fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
505 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], 0);
506 for (j
= 0; j
< fw_size
; j
++)
507 WREG32(mmSDMA0_UCODE_DATA
+ sdma_offsets
[i
], le32_to_cpup(fw_data
++));
508 WREG32(mmSDMA0_UCODE_ADDR
+ sdma_offsets
[i
], adev
->sdma
[i
].fw_version
);
515 * cik_sdma_start - setup and start the async dma engines
517 * @adev: amdgpu_device pointer
519 * Set up the DMA engines and enable them (CIK).
520 * Returns 0 for success, error for failure.
522 static int cik_sdma_start(struct amdgpu_device
*adev
)
526 r
= cik_sdma_load_microcode(adev
);
531 cik_sdma_enable(adev
, true);
533 /* start the gfx rings and rlc compute queues */
534 r
= cik_sdma_gfx_resume(adev
);
537 r
= cik_sdma_rlc_resume(adev
);
545 * cik_sdma_ring_test_ring - simple async dma engine test
547 * @ring: amdgpu_ring structure holding ring information
549 * Test the DMA engine by writing using it to write an
550 * value to memory. (CIK).
551 * Returns 0 for success, error for failure.
553 static int cik_sdma_ring_test_ring(struct amdgpu_ring
*ring
)
555 struct amdgpu_device
*adev
= ring
->adev
;
562 r
= amdgpu_wb_get(adev
, &index
);
564 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
568 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
570 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
572 r
= amdgpu_ring_lock(ring
, 5);
574 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring
->idx
, r
);
575 amdgpu_wb_free(adev
, index
);
578 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0));
579 amdgpu_ring_write(ring
, lower_32_bits(gpu_addr
));
580 amdgpu_ring_write(ring
, upper_32_bits(gpu_addr
));
581 amdgpu_ring_write(ring
, 1); /* number of DWs to follow */
582 amdgpu_ring_write(ring
, 0xDEADBEEF);
583 amdgpu_ring_unlock_commit(ring
);
585 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
586 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
587 if (tmp
== 0xDEADBEEF)
592 if (i
< adev
->usec_timeout
) {
593 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring
->idx
, i
);
595 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
599 amdgpu_wb_free(adev
, index
);
605 * cik_sdma_ring_test_ib - test an IB on the DMA engine
607 * @ring: amdgpu_ring structure holding ring information
609 * Test a simple IB in the DMA ring (CIK).
610 * Returns 0 on success, error on failure.
612 static int cik_sdma_ring_test_ib(struct amdgpu_ring
*ring
)
614 struct amdgpu_device
*adev
= ring
->adev
;
622 r
= amdgpu_wb_get(adev
, &index
);
624 dev_err(adev
->dev
, "(%d) failed to allocate wb slot\n", r
);
628 gpu_addr
= adev
->wb
.gpu_addr
+ (index
* 4);
630 adev
->wb
.wb
[index
] = cpu_to_le32(tmp
);
632 r
= amdgpu_ib_get(ring
, NULL
, 256, &ib
);
634 amdgpu_wb_free(adev
, index
);
635 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r
);
639 ib
.ptr
[0] = SDMA_PACKET(SDMA_OPCODE_WRITE
, SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
640 ib
.ptr
[1] = lower_32_bits(gpu_addr
);
641 ib
.ptr
[2] = upper_32_bits(gpu_addr
);
643 ib
.ptr
[4] = 0xDEADBEEF;
646 r
= amdgpu_ib_schedule(adev
, 1, &ib
, AMDGPU_FENCE_OWNER_UNDEFINED
);
648 amdgpu_ib_free(adev
, &ib
);
649 amdgpu_wb_free(adev
, index
);
650 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r
);
653 r
= amdgpu_fence_wait(ib
.fence
, false);
655 amdgpu_ib_free(adev
, &ib
);
656 amdgpu_wb_free(adev
, index
);
657 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r
);
660 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
661 tmp
= le32_to_cpu(adev
->wb
.wb
[index
]);
662 if (tmp
== 0xDEADBEEF)
666 if (i
< adev
->usec_timeout
) {
667 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
668 ib
.fence
->ring
->idx
, i
);
670 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp
);
673 amdgpu_ib_free(adev
, &ib
);
674 amdgpu_wb_free(adev
, index
);
679 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
681 * @ib: indirect buffer to fill with commands
682 * @pe: addr of the page entry
683 * @src: src addr to copy from
684 * @count: number of page entries to update
686 * Update PTEs by copying them from the GART using sDMA (CIK).
688 static void cik_sdma_vm_copy_pte(struct amdgpu_ib
*ib
,
689 uint64_t pe
, uint64_t src
,
693 unsigned bytes
= count
* 8;
694 if (bytes
> 0x1FFFF8)
697 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_COPY
,
698 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
699 ib
->ptr
[ib
->length_dw
++] = bytes
;
700 ib
->ptr
[ib
->length_dw
++] = 0; /* src/dst endian swap */
701 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(src
);
702 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(src
);
703 ib
->ptr
[ib
->length_dw
++] = lower_32_bits(pe
);
704 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
713 * cik_sdma_vm_write_pages - update PTEs by writing them manually
715 * @ib: indirect buffer to fill with commands
716 * @pe: addr of the page entry
717 * @addr: dst addr to write into pe
718 * @count: number of page entries to update
719 * @incr: increase next addr by incr bytes
720 * @flags: access flags
722 * Update PTEs by writing them manually using sDMA (CIK).
724 static void cik_sdma_vm_write_pte(struct amdgpu_ib
*ib
,
726 uint64_t addr
, unsigned count
,
727 uint32_t incr
, uint32_t flags
)
737 /* for non-physically contiguous pages (system) */
738 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_WRITE
,
739 SDMA_WRITE_SUB_OPCODE_LINEAR
, 0);
740 ib
->ptr
[ib
->length_dw
++] = pe
;
741 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
742 ib
->ptr
[ib
->length_dw
++] = ndw
;
743 for (; ndw
> 0; ndw
-= 2, --count
, pe
+= 8) {
744 if (flags
& AMDGPU_PTE_SYSTEM
) {
745 value
= amdgpu_vm_map_gart(ib
->ring
->adev
, addr
);
746 value
&= 0xFFFFFFFFFFFFF000ULL
;
747 } else if (flags
& AMDGPU_PTE_VALID
) {
754 ib
->ptr
[ib
->length_dw
++] = value
;
755 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
761 * cik_sdma_vm_set_pages - update the page tables using sDMA
763 * @ib: indirect buffer to fill with commands
764 * @pe: addr of the page entry
765 * @addr: dst addr to write into pe
766 * @count: number of page entries to update
767 * @incr: increase next addr by incr bytes
768 * @flags: access flags
770 * Update the page tables using sDMA (CIK).
772 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib
*ib
,
774 uint64_t addr
, unsigned count
,
775 uint32_t incr
, uint32_t flags
)
785 if (flags
& AMDGPU_PTE_VALID
)
790 /* for physically contiguous pages (vram) */
791 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE
, 0, 0);
792 ib
->ptr
[ib
->length_dw
++] = pe
; /* dst addr */
793 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(pe
);
794 ib
->ptr
[ib
->length_dw
++] = flags
; /* mask */
795 ib
->ptr
[ib
->length_dw
++] = 0;
796 ib
->ptr
[ib
->length_dw
++] = value
; /* value */
797 ib
->ptr
[ib
->length_dw
++] = upper_32_bits(value
);
798 ib
->ptr
[ib
->length_dw
++] = incr
; /* increment size */
799 ib
->ptr
[ib
->length_dw
++] = 0;
800 ib
->ptr
[ib
->length_dw
++] = ndw
; /* number of entries */
809 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
811 * @ib: indirect buffer to fill with padding
814 static void cik_sdma_vm_pad_ib(struct amdgpu_ib
*ib
)
816 while (ib
->length_dw
& 0x7)
817 ib
->ptr
[ib
->length_dw
++] = SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0);
821 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
823 * @ring: amdgpu_ring pointer
824 * @vm: amdgpu_vm pointer
826 * Update the page table base and flush the VM TLB
829 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring
*ring
,
830 unsigned vm_id
, uint64_t pd_addr
)
832 u32 extra_bits
= (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
833 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
835 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
837 amdgpu_ring_write(ring
, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ vm_id
));
839 amdgpu_ring_write(ring
, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ vm_id
- 8));
841 amdgpu_ring_write(ring
, pd_addr
>> 12);
844 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE
, 0, 0xf000));
845 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
);
846 amdgpu_ring_write(ring
, 1 << vm_id
);
848 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM
, 0, extra_bits
));
849 amdgpu_ring_write(ring
, mmVM_INVALIDATE_REQUEST
<< 2);
850 amdgpu_ring_write(ring
, 0);
851 amdgpu_ring_write(ring
, 0); /* reference */
852 amdgpu_ring_write(ring
, 0); /* mask */
853 amdgpu_ring_write(ring
, (0xfff << 16) | 10); /* retry count, poll interval */
856 static void cik_enable_sdma_mgcg(struct amdgpu_device
*adev
,
861 if (enable
&& (adev
->cg_flags
& AMDGPU_CG_SUPPORT_SDMA_MGCG
)) {
862 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, 0x00000100);
863 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, 0x00000100);
865 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
);
868 WREG32(mmSDMA0_CLK_CTRL
+ SDMA0_REGISTER_OFFSET
, data
);
870 orig
= data
= RREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
);
873 WREG32(mmSDMA0_CLK_CTRL
+ SDMA1_REGISTER_OFFSET
, data
);
877 static void cik_enable_sdma_mgls(struct amdgpu_device
*adev
,
882 if (enable
&& (adev
->cg_flags
& AMDGPU_CG_SUPPORT_SDMA_LS
)) {
883 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
886 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
888 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
891 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
893 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
);
896 WREG32(mmSDMA0_POWER_CNTL
+ SDMA0_REGISTER_OFFSET
, data
);
898 orig
= data
= RREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
);
901 WREG32(mmSDMA0_POWER_CNTL
+ SDMA1_REGISTER_OFFSET
, data
);
905 static int cik_sdma_early_init(void *handle
)
907 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
909 cik_sdma_set_ring_funcs(adev
);
910 cik_sdma_set_irq_funcs(adev
);
911 cik_sdma_set_buffer_funcs(adev
);
912 cik_sdma_set_vm_pte_funcs(adev
);
917 static int cik_sdma_sw_init(void *handle
)
919 struct amdgpu_ring
*ring
;
920 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
923 r
= cik_sdma_init_microcode(adev
);
925 DRM_ERROR("Failed to load sdma firmware!\n");
929 /* SDMA trap event */
930 r
= amdgpu_irq_add_id(adev
, 224, &adev
->sdma_trap_irq
);
934 /* SDMA Privileged inst */
935 r
= amdgpu_irq_add_id(adev
, 241, &adev
->sdma_illegal_inst_irq
);
939 /* SDMA Privileged inst */
940 r
= amdgpu_irq_add_id(adev
, 247, &adev
->sdma_illegal_inst_irq
);
944 ring
= &adev
->sdma
[0].ring
;
945 ring
->ring_obj
= NULL
;
947 ring
= &adev
->sdma
[1].ring
;
948 ring
->ring_obj
= NULL
;
950 ring
= &adev
->sdma
[0].ring
;
951 sprintf(ring
->name
, "sdma0");
952 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
953 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
954 &adev
->sdma_trap_irq
, AMDGPU_SDMA_IRQ_TRAP0
,
955 AMDGPU_RING_TYPE_SDMA
);
959 ring
= &adev
->sdma
[1].ring
;
960 sprintf(ring
->name
, "sdma1");
961 r
= amdgpu_ring_init(adev
, ring
, 256 * 1024,
962 SDMA_PACKET(SDMA_OPCODE_NOP
, 0, 0), 0xf,
963 &adev
->sdma_trap_irq
, AMDGPU_SDMA_IRQ_TRAP1
,
964 AMDGPU_RING_TYPE_SDMA
);
971 static int cik_sdma_sw_fini(void *handle
)
973 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
975 amdgpu_ring_fini(&adev
->sdma
[0].ring
);
976 amdgpu_ring_fini(&adev
->sdma
[1].ring
);
981 static int cik_sdma_hw_init(void *handle
)
984 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
986 r
= cik_sdma_start(adev
);
993 static int cik_sdma_hw_fini(void *handle
)
995 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
997 cik_sdma_enable(adev
, false);
1002 static int cik_sdma_suspend(void *handle
)
1004 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1006 return cik_sdma_hw_fini(adev
);
1009 static int cik_sdma_resume(void *handle
)
1011 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1013 return cik_sdma_hw_init(adev
);
1016 static bool cik_sdma_is_idle(void *handle
)
1018 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1019 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1021 if (tmp
& (SRBM_STATUS2__SDMA_BUSY_MASK
|
1022 SRBM_STATUS2__SDMA1_BUSY_MASK
))
1028 static int cik_sdma_wait_for_idle(void *handle
)
1032 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1034 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1035 tmp
= RREG32(mmSRBM_STATUS2
) & (SRBM_STATUS2__SDMA_BUSY_MASK
|
1036 SRBM_STATUS2__SDMA1_BUSY_MASK
);
1045 static void cik_sdma_print_status(void *handle
)
1048 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1050 dev_info(adev
->dev
, "CIK SDMA registers\n");
1051 dev_info(adev
->dev
, " SRBM_STATUS2=0x%08X\n",
1052 RREG32(mmSRBM_STATUS2
));
1053 for (i
= 0; i
< SDMA_MAX_INSTANCE
; i
++) {
1054 dev_info(adev
->dev
, " SDMA%d_STATUS_REG=0x%08X\n",
1055 i
, RREG32(mmSDMA0_STATUS_REG
+ sdma_offsets
[i
]));
1056 dev_info(adev
->dev
, " SDMA%d_ME_CNTL=0x%08X\n",
1057 i
, RREG32(mmSDMA0_F32_CNTL
+ sdma_offsets
[i
]));
1058 dev_info(adev
->dev
, " SDMA%d_CNTL=0x%08X\n",
1059 i
, RREG32(mmSDMA0_CNTL
+ sdma_offsets
[i
]));
1060 dev_info(adev
->dev
, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1061 i
, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL
+ sdma_offsets
[i
]));
1062 dev_info(adev
->dev
, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1063 i
, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL
+ sdma_offsets
[i
]));
1064 dev_info(adev
->dev
, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1065 i
, RREG32(mmSDMA0_GFX_IB_CNTL
+ sdma_offsets
[i
]));
1066 dev_info(adev
->dev
, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1067 i
, RREG32(mmSDMA0_GFX_RB_CNTL
+ sdma_offsets
[i
]));
1068 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1069 i
, RREG32(mmSDMA0_GFX_RB_RPTR
+ sdma_offsets
[i
]));
1070 dev_info(adev
->dev
, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1071 i
, RREG32(mmSDMA0_GFX_RB_WPTR
+ sdma_offsets
[i
]));
1072 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1073 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI
+ sdma_offsets
[i
]));
1074 dev_info(adev
->dev
, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1075 i
, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO
+ sdma_offsets
[i
]));
1076 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1077 i
, RREG32(mmSDMA0_GFX_RB_BASE
+ sdma_offsets
[i
]));
1078 dev_info(adev
->dev
, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1079 i
, RREG32(mmSDMA0_GFX_RB_BASE_HI
+ sdma_offsets
[i
]));
1080 mutex_lock(&adev
->srbm_mutex
);
1081 for (j
= 0; j
< 16; j
++) {
1082 cik_srbm_select(adev
, 0, 0, 0, j
);
1083 dev_info(adev
->dev
, " VM %d:\n", j
);
1084 dev_info(adev
->dev
, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1085 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR
+ sdma_offsets
[i
]));
1086 dev_info(adev
->dev
, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1087 RREG32(mmSDMA0_GFX_APE1_CNTL
+ sdma_offsets
[i
]));
1089 cik_srbm_select(adev
, 0, 0, 0, 0);
1090 mutex_unlock(&adev
->srbm_mutex
);
1094 static int cik_sdma_soft_reset(void *handle
)
1096 u32 srbm_soft_reset
= 0;
1097 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1098 u32 tmp
= RREG32(mmSRBM_STATUS2
);
1100 if (tmp
& SRBM_STATUS2__SDMA_BUSY_MASK
) {
1102 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
);
1103 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1104 WREG32(mmSDMA0_F32_CNTL
+ SDMA0_REGISTER_OFFSET
, tmp
);
1105 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK
;
1107 if (tmp
& SRBM_STATUS2__SDMA1_BUSY_MASK
) {
1109 tmp
= RREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
);
1110 tmp
|= SDMA0_F32_CNTL__HALT_MASK
;
1111 WREG32(mmSDMA0_F32_CNTL
+ SDMA1_REGISTER_OFFSET
, tmp
);
1112 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK
;
1115 if (srbm_soft_reset
) {
1116 cik_sdma_print_status((void *)adev
);
1118 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1119 tmp
|= srbm_soft_reset
;
1120 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1121 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1122 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1126 tmp
&= ~srbm_soft_reset
;
1127 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1128 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1130 /* Wait a little for things to settle down */
1133 cik_sdma_print_status((void *)adev
);
1139 static int cik_sdma_set_trap_irq_state(struct amdgpu_device
*adev
,
1140 struct amdgpu_irq_src
*src
,
1142 enum amdgpu_interrupt_state state
)
1147 case AMDGPU_SDMA_IRQ_TRAP0
:
1149 case AMDGPU_IRQ_STATE_DISABLE
:
1150 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1151 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1152 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1154 case AMDGPU_IRQ_STATE_ENABLE
:
1155 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
);
1156 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1157 WREG32(mmSDMA0_CNTL
+ SDMA0_REGISTER_OFFSET
, sdma_cntl
);
1163 case AMDGPU_SDMA_IRQ_TRAP1
:
1165 case AMDGPU_IRQ_STATE_DISABLE
:
1166 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1167 sdma_cntl
&= ~SDMA0_CNTL__TRAP_ENABLE_MASK
;
1168 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1170 case AMDGPU_IRQ_STATE_ENABLE
:
1171 sdma_cntl
= RREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
);
1172 sdma_cntl
|= SDMA0_CNTL__TRAP_ENABLE_MASK
;
1173 WREG32(mmSDMA0_CNTL
+ SDMA1_REGISTER_OFFSET
, sdma_cntl
);
1185 static int cik_sdma_process_trap_irq(struct amdgpu_device
*adev
,
1186 struct amdgpu_irq_src
*source
,
1187 struct amdgpu_iv_entry
*entry
)
1189 u8 instance_id
, queue_id
;
1191 instance_id
= (entry
->ring_id
& 0x3) >> 0;
1192 queue_id
= (entry
->ring_id
& 0xc) >> 2;
1193 DRM_DEBUG("IH: SDMA trap\n");
1194 switch (instance_id
) {
1198 amdgpu_fence_process(&adev
->sdma
[0].ring
);
1211 amdgpu_fence_process(&adev
->sdma
[1].ring
);
1226 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device
*adev
,
1227 struct amdgpu_irq_src
*source
,
1228 struct amdgpu_iv_entry
*entry
)
1230 DRM_ERROR("Illegal instruction in SDMA command stream\n");
1231 schedule_work(&adev
->reset_work
);
1235 static int cik_sdma_set_clockgating_state(void *handle
,
1236 enum amd_clockgating_state state
)
1239 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1241 if (state
== AMD_CG_STATE_GATE
)
1244 cik_enable_sdma_mgcg(adev
, gate
);
1245 cik_enable_sdma_mgls(adev
, gate
);
1250 static int cik_sdma_set_powergating_state(void *handle
,
1251 enum amd_powergating_state state
)
1256 const struct amd_ip_funcs cik_sdma_ip_funcs
= {
1257 .early_init
= cik_sdma_early_init
,
1259 .sw_init
= cik_sdma_sw_init
,
1260 .sw_fini
= cik_sdma_sw_fini
,
1261 .hw_init
= cik_sdma_hw_init
,
1262 .hw_fini
= cik_sdma_hw_fini
,
1263 .suspend
= cik_sdma_suspend
,
1264 .resume
= cik_sdma_resume
,
1265 .is_idle
= cik_sdma_is_idle
,
1266 .wait_for_idle
= cik_sdma_wait_for_idle
,
1267 .soft_reset
= cik_sdma_soft_reset
,
1268 .print_status
= cik_sdma_print_status
,
1269 .set_clockgating_state
= cik_sdma_set_clockgating_state
,
1270 .set_powergating_state
= cik_sdma_set_powergating_state
,
1274 * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
1276 * @ring: amdgpu_ring structure holding ring information
1278 * Check if the async DMA engine is locked up (CIK).
1279 * Returns true if the engine appears to be locked up, false if not.
1281 static bool cik_sdma_ring_is_lockup(struct amdgpu_ring
*ring
)
1284 if (cik_sdma_is_idle(ring
->adev
)) {
1285 amdgpu_ring_lockup_update(ring
);
1288 return amdgpu_ring_test_lockup(ring
);
1291 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs
= {
1292 .get_rptr
= cik_sdma_ring_get_rptr
,
1293 .get_wptr
= cik_sdma_ring_get_wptr
,
1294 .set_wptr
= cik_sdma_ring_set_wptr
,
1296 .emit_ib
= cik_sdma_ring_emit_ib
,
1297 .emit_fence
= cik_sdma_ring_emit_fence
,
1298 .emit_semaphore
= cik_sdma_ring_emit_semaphore
,
1299 .emit_vm_flush
= cik_sdma_ring_emit_vm_flush
,
1300 .emit_hdp_flush
= cik_sdma_ring_emit_hdp_flush
,
1301 .test_ring
= cik_sdma_ring_test_ring
,
1302 .test_ib
= cik_sdma_ring_test_ib
,
1303 .is_lockup
= cik_sdma_ring_is_lockup
,
1306 static void cik_sdma_set_ring_funcs(struct amdgpu_device
*adev
)
1308 adev
->sdma
[0].ring
.funcs
= &cik_sdma_ring_funcs
;
1309 adev
->sdma
[1].ring
.funcs
= &cik_sdma_ring_funcs
;
1312 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs
= {
1313 .set
= cik_sdma_set_trap_irq_state
,
1314 .process
= cik_sdma_process_trap_irq
,
1317 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs
= {
1318 .process
= cik_sdma_process_illegal_inst_irq
,
1321 static void cik_sdma_set_irq_funcs(struct amdgpu_device
*adev
)
1323 adev
->sdma_trap_irq
.num_types
= AMDGPU_SDMA_IRQ_LAST
;
1324 adev
->sdma_trap_irq
.funcs
= &cik_sdma_trap_irq_funcs
;
1325 adev
->sdma_illegal_inst_irq
.funcs
= &cik_sdma_illegal_inst_irq_funcs
;
1329 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1331 * @ring: amdgpu_ring structure holding ring information
1332 * @src_offset: src GPU address
1333 * @dst_offset: dst GPU address
1334 * @byte_count: number of bytes to xfer
1336 * Copy GPU buffers using the DMA engine (CIK).
1337 * Used by the amdgpu ttm implementation to move pages if
1338 * registered as the asic copy callback.
1340 static void cik_sdma_emit_copy_buffer(struct amdgpu_ring
*ring
,
1341 uint64_t src_offset
,
1342 uint64_t dst_offset
,
1343 uint32_t byte_count
)
1345 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_COPY
, SDMA_COPY_SUB_OPCODE_LINEAR
, 0));
1346 amdgpu_ring_write(ring
, byte_count
);
1347 amdgpu_ring_write(ring
, 0); /* src/dst endian swap */
1348 amdgpu_ring_write(ring
, lower_32_bits(src_offset
));
1349 amdgpu_ring_write(ring
, upper_32_bits(src_offset
));
1350 amdgpu_ring_write(ring
, lower_32_bits(dst_offset
));
1351 amdgpu_ring_write(ring
, upper_32_bits(dst_offset
));
1355 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1357 * @ring: amdgpu_ring structure holding ring information
1358 * @src_data: value to write to buffer
1359 * @dst_offset: dst GPU address
1360 * @byte_count: number of bytes to xfer
1362 * Fill GPU buffers using the DMA engine (CIK).
1364 static void cik_sdma_emit_fill_buffer(struct amdgpu_ring
*ring
,
1366 uint64_t dst_offset
,
1367 uint32_t byte_count
)
1369 amdgpu_ring_write(ring
, SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL
, 0, 0));
1370 amdgpu_ring_write(ring
, lower_32_bits(dst_offset
));
1371 amdgpu_ring_write(ring
, upper_32_bits(dst_offset
));
1372 amdgpu_ring_write(ring
, src_data
);
1373 amdgpu_ring_write(ring
, byte_count
);
1376 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs
= {
1377 .copy_max_bytes
= 0x1fffff,
1379 .emit_copy_buffer
= cik_sdma_emit_copy_buffer
,
1381 .fill_max_bytes
= 0x1fffff,
1383 .emit_fill_buffer
= cik_sdma_emit_fill_buffer
,
1386 static void cik_sdma_set_buffer_funcs(struct amdgpu_device
*adev
)
1388 if (adev
->mman
.buffer_funcs
== NULL
) {
1389 adev
->mman
.buffer_funcs
= &cik_sdma_buffer_funcs
;
1390 adev
->mman
.buffer_funcs_ring
= &adev
->sdma
[0].ring
;
1394 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs
= {
1395 .copy_pte
= cik_sdma_vm_copy_pte
,
1396 .write_pte
= cik_sdma_vm_write_pte
,
1397 .set_pte_pde
= cik_sdma_vm_set_pte_pde
,
1398 .pad_ib
= cik_sdma_vm_pad_ib
,
1401 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device
*adev
)
1403 if (adev
->vm_manager
.vm_pte_funcs
== NULL
) {
1404 adev
->vm_manager
.vm_pte_funcs
= &cik_sdma_vm_pte_funcs
;
1405 adev
->vm_manager
.vm_pte_funcs_ring
= &adev
->sdma
[0].ring
;