2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_10_0_d.h"
36 #include "dce/dce_10_0_sh_mask.h"
37 #include "dce/dce_10_0_enum.h"
38 #include "oss/oss_3_0_d.h"
39 #include "oss/oss_3_0_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
43 static void dce_v10_0_set_display_funcs(struct amdgpu_device
*adev
);
44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device
*adev
);
46 static const u32 crtc_offsets
[] =
48 CRTC0_REGISTER_OFFSET
,
49 CRTC1_REGISTER_OFFSET
,
50 CRTC2_REGISTER_OFFSET
,
51 CRTC3_REGISTER_OFFSET
,
52 CRTC4_REGISTER_OFFSET
,
53 CRTC5_REGISTER_OFFSET
,
57 static const u32 hpd_offsets
[] =
67 static const uint32_t dig_offsets
[] = {
83 } interrupt_status_offsets
[] = { {
84 .reg
= mmDISP_INTERRUPT_STATUS
,
85 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
86 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
87 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
89 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
90 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
91 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
92 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
94 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
95 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
96 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
97 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
99 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
100 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
101 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
102 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
104 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
105 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
106 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
107 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
109 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
110 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
111 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
112 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
115 static const u32 golden_settings_tonga_a11
[] =
117 mmDCI_CLK_CNTL
, 0x00000080, 0x00000000,
118 mmFBC_DEBUG_COMP
, 0x000000f0, 0x00000070,
119 mmFBC_MISC
, 0x1f311fff, 0x12300000,
120 mmHDMI_CONTROL
, 0x31000111, 0x00000011,
123 static void dce_v10_0_init_golden_registers(struct amdgpu_device
*adev
)
125 switch (adev
->asic_type
) {
127 amdgpu_program_register_sequence(adev
,
128 golden_settings_tonga_a11
,
129 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
136 static u32
dce_v10_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
137 u32 block_offset
, u32 reg
)
142 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
144 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
145 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
150 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
151 u32 block_offset
, u32 reg
, u32 v
)
155 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
156 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
157 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
158 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
161 static bool dce_v10_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
163 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
164 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
170 static bool dce_v10_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
174 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
175 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
184 * dce_v10_0_vblank_wait - vblank wait asic callback.
186 * @adev: amdgpu_device pointer
187 * @crtc: crtc to wait for vblank on
189 * Wait for vblank on the requested crtc (evergreen+).
191 static void dce_v10_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
195 if (crtc
>= adev
->mode_info
.num_crtc
)
198 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
201 /* depending on when we hit vblank, we may be close to active; if so,
202 * wait for another frame.
204 while (dce_v10_0_is_in_vblank(adev
, crtc
)) {
205 if (i
++ % 100 == 0) {
206 if (!dce_v10_0_is_counter_moving(adev
, crtc
))
211 while (!dce_v10_0_is_in_vblank(adev
, crtc
)) {
212 if (i
++ % 100 == 0) {
213 if (!dce_v10_0_is_counter_moving(adev
, crtc
))
219 static u32
dce_v10_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
221 if (crtc
>= adev
->mode_info
.num_crtc
)
224 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
228 * dce_v10_0_page_flip - pageflip callback.
230 * @adev: amdgpu_device pointer
231 * @crtc_id: crtc to cleanup pageflip on
232 * @crtc_base: new address of the crtc (GPU MC address)
234 * Does the actual pageflip (evergreen+).
235 * During vblank we take the crtc lock and wait for the update_pending
236 * bit to go high, when it does, we release the lock, and allow the
237 * double buffered update to take place.
238 * Returns the current update pending status.
240 static void dce_v10_0_page_flip(struct amdgpu_device
*adev
,
241 int crtc_id
, u64 crtc_base
)
243 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
244 u32 tmp
= RREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
);
247 /* Lock the graphics update lock */
248 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
249 WREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
, tmp
);
251 /* update the scanout addresses */
252 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
253 upper_32_bits(crtc_base
));
254 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
255 lower_32_bits(crtc_base
));
257 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
258 upper_32_bits(crtc_base
));
259 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
260 lower_32_bits(crtc_base
));
262 /* Wait for update_pending to go high. */
263 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
264 if (RREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
) &
265 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
)
269 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
271 /* Unlock the lock, so double-buffering can take place inside vblank */
272 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
273 WREG32(mmGRPH_UPDATE
+ amdgpu_crtc
->crtc_offset
, tmp
);
276 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
277 u32
*vbl
, u32
*position
)
279 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
282 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
283 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
289 * dce_v10_0_hpd_sense - hpd sense callback.
291 * @adev: amdgpu_device pointer
292 * @hpd: hpd (hotplug detect) pin
294 * Checks if a digital monitor is connected (evergreen+).
295 * Returns true if connected, false if not connected.
297 static bool dce_v10_0_hpd_sense(struct amdgpu_device
*adev
,
298 enum amdgpu_hpd_id hpd
)
301 bool connected
= false;
326 if (RREG32(mmDC_HPD_INT_STATUS
+ hpd_offsets
[idx
]) &
327 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK
)
334 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
336 * @adev: amdgpu_device pointer
337 * @hpd: hpd (hotplug detect) pin
339 * Set the polarity of the hpd pin (evergreen+).
341 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device
*adev
,
342 enum amdgpu_hpd_id hpd
)
345 bool connected
= dce_v10_0_hpd_sense(adev
, hpd
);
371 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
]);
373 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 0);
375 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_POLARITY
, 1);
376 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[idx
], tmp
);
380 * dce_v10_0_hpd_init - hpd setup callback.
382 * @adev: amdgpu_device pointer
384 * Setup the hpd pins used by the card (evergreen+).
385 * Enable the pin, set the polarity, and enable the hpd interrupts.
387 static void dce_v10_0_hpd_init(struct amdgpu_device
*adev
)
389 struct drm_device
*dev
= adev
->ddev
;
390 struct drm_connector
*connector
;
394 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
395 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
397 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
398 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
399 /* don't try to enable hpd on eDP or LVDS avoid breaking the
400 * aux dp channel on imac and help (but not completely fix)
401 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
402 * also avoid interrupt storms during dpms.
407 switch (amdgpu_connector
->hpd
.hpd
) {
430 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
431 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 1);
432 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
434 tmp
= RREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
]);
435 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
436 DC_HPD_CONNECT_INT_DELAY
,
437 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS
);
438 tmp
= REG_SET_FIELD(tmp
, DC_HPD_TOGGLE_FILT_CNTL
,
439 DC_HPD_DISCONNECT_INT_DELAY
,
440 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS
);
441 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL
+ hpd_offsets
[idx
], tmp
);
443 dce_v10_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
444 amdgpu_irq_get(adev
, &adev
->hpd_irq
,
445 amdgpu_connector
->hpd
.hpd
);
450 * dce_v10_0_hpd_fini - hpd tear down callback.
452 * @adev: amdgpu_device pointer
454 * Tear down the hpd pins used by the card (evergreen+).
455 * Disable the hpd interrupts.
457 static void dce_v10_0_hpd_fini(struct amdgpu_device
*adev
)
459 struct drm_device
*dev
= adev
->ddev
;
460 struct drm_connector
*connector
;
464 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
465 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
467 switch (amdgpu_connector
->hpd
.hpd
) {
490 tmp
= RREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
]);
491 tmp
= REG_SET_FIELD(tmp
, DC_HPD_CONTROL
, DC_HPD_EN
, 0);
492 WREG32(mmDC_HPD_CONTROL
+ hpd_offsets
[idx
], tmp
);
494 amdgpu_irq_put(adev
, &adev
->hpd_irq
,
495 amdgpu_connector
->hpd
.hpd
);
499 static u32
dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
501 return mmDC_GPIO_HPD_A
;
504 static bool dce_v10_0_is_display_hung(struct amdgpu_device
*adev
)
510 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
511 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
512 if (REG_GET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
)) {
513 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
514 crtc_hung
|= (1 << i
);
518 for (j
= 0; j
< 10; j
++) {
519 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
520 if (crtc_hung
& (1 << i
)) {
521 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
522 if (tmp
!= crtc_status
[i
])
523 crtc_hung
&= ~(1 << i
);
534 static void dce_v10_0_stop_mc_access(struct amdgpu_device
*adev
,
535 struct amdgpu_mode_mc_save
*save
)
537 u32 crtc_enabled
, tmp
;
540 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
541 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
543 /* disable VGA render */
544 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
545 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
546 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
548 /* blank the display controllers */
549 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
550 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
551 CRTC_CONTROL
, CRTC_MASTER_EN
);
557 save
->crtc_enabled
[i
] = true;
558 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
559 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
560 amdgpu_display_vblank_wait(adev
, i
);
561 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
562 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
563 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
564 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
566 /* wait for the next frame */
567 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
568 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
569 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
573 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
574 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
) == 0) {
575 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
576 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
578 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
579 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
) == 0) {
580 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 1);
581 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
584 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
585 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
586 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
587 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
588 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
589 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
590 save
->crtc_enabled
[i
] = false;
594 save
->crtc_enabled
[i
] = false;
599 static void dce_v10_0_resume_mc_access(struct amdgpu_device
*adev
,
600 struct amdgpu_mode_mc_save
*save
)
602 u32 tmp
, frame_count
;
605 /* update crtc base addresses */
606 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
607 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
608 upper_32_bits(adev
->mc
.vram_start
));
609 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
610 upper_32_bits(adev
->mc
.vram_start
));
611 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
612 (u32
)adev
->mc
.vram_start
);
613 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
614 (u32
)adev
->mc
.vram_start
);
616 if (save
->crtc_enabled
[i
]) {
617 tmp
= RREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
]);
618 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
) != 3) {
619 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
, 3);
620 WREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
], tmp
);
622 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
623 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
)) {
624 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
625 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
627 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
628 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
)) {
629 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 0);
630 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
632 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
633 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
634 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_SURFACE_UPDATE_PENDING
) == 0)
638 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
639 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
640 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
641 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
642 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
643 /* wait for the next frame */
644 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
645 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
646 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
653 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
654 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
656 /* Unlock vga access */
657 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
659 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
662 static void dce_v10_0_set_vga_render_state(struct amdgpu_device
*adev
,
667 /* Lockout access through VGA aperture*/
668 tmp
= RREG32(mmVGA_HDP_CONTROL
);
670 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
672 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
673 WREG32(mmVGA_HDP_CONTROL
, tmp
);
675 /* disable VGA render */
676 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
678 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
680 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
681 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
684 static void dce_v10_0_program_fmt(struct drm_encoder
*encoder
)
686 struct drm_device
*dev
= encoder
->dev
;
687 struct amdgpu_device
*adev
= dev
->dev_private
;
688 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
689 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
690 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
693 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
696 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
697 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
698 dither
= amdgpu_connector
->dither
;
701 /* LVDS/eDP FMT is set up by atom */
702 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
705 /* not needed for analog */
706 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
707 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
715 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
716 /* XXX sort out optimal dither settings */
717 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
718 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
719 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
720 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 0);
722 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
723 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 0);
727 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
728 /* XXX sort out optimal dither settings */
729 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
730 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
731 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
732 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
733 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 1);
735 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
736 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 1);
740 if (dither
== AMDGPU_FMT_DITHER_ENABLE
) {
741 /* XXX sort out optimal dither settings */
742 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_FRAME_RANDOM_ENABLE
, 1);
743 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_HIGHPASS_RANDOM_ENABLE
, 1);
744 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_RGB_RANDOM_ENABLE
, 1);
745 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_EN
, 1);
746 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_SPATIAL_DITHER_DEPTH
, 2);
748 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_EN
, 1);
749 tmp
= REG_SET_FIELD(tmp
, FMT_BIT_DEPTH_CONTROL
, FMT_TRUNCATE_DEPTH
, 2);
757 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
761 /* display watermark setup */
763 * dce_v10_0_line_buffer_adjust - Set up the line buffer
765 * @adev: amdgpu_device pointer
766 * @amdgpu_crtc: the selected display controller
767 * @mode: the current display mode on the selected display
770 * Setup up the line buffer allocation for
771 * the selected display controller (CIK).
772 * Returns the line buffer size in pixels.
774 static u32
dce_v10_0_line_buffer_adjust(struct amdgpu_device
*adev
,
775 struct amdgpu_crtc
*amdgpu_crtc
,
776 struct drm_display_mode
*mode
)
778 u32 tmp
, buffer_alloc
, i
, mem_cfg
;
779 u32 pipe_offset
= amdgpu_crtc
->crtc_id
;
782 * There are 6 line buffers, one for each display controllers.
783 * There are 3 partitions per LB. Select the number of partitions
784 * to enable based on the display width. For display widths larger
785 * than 4096, you need use to use 2 display controllers and combine
786 * them using the stereo blender.
788 if (amdgpu_crtc
->base
.enabled
&& mode
) {
789 if (mode
->crtc_hdisplay
< 1920) {
792 } else if (mode
->crtc_hdisplay
< 2560) {
795 } else if (mode
->crtc_hdisplay
< 4096) {
797 buffer_alloc
= (adev
->flags
& AMDGPU_IS_APU
) ? 2 : 4;
799 DRM_DEBUG_KMS("Mode too big for LB!\n");
801 buffer_alloc
= (adev
->flags
& AMDGPU_IS_APU
) ? 2 : 4;
808 tmp
= RREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
);
809 tmp
= REG_SET_FIELD(tmp
, LB_MEMORY_CTRL
, LB_MEMORY_CONFIG
, mem_cfg
);
810 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
, tmp
);
812 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
813 tmp
= REG_SET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATED
, buffer_alloc
);
814 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
, tmp
);
816 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
817 tmp
= RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
);
818 if (REG_GET_FIELD(tmp
, PIPE0_DMIF_BUFFER_CONTROL
, DMIF_BUFFERS_ALLOCATION_COMPLETED
))
823 if (amdgpu_crtc
->base
.enabled
&& mode
) {
835 /* controller not enabled, so no lb used */
840 * cik_get_number_of_dram_channels - get the number of dram channels
842 * @adev: amdgpu_device pointer
844 * Look up the number of video ram channels (CIK).
845 * Used for display watermark bandwidth calculations
846 * Returns the number of dram channels
848 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
850 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
852 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
875 struct dce10_wm_params
{
876 u32 dram_channels
; /* number of dram channels */
877 u32 yclk
; /* bandwidth per dram data pin in kHz */
878 u32 sclk
; /* engine clock in kHz */
879 u32 disp_clk
; /* display clock in kHz */
880 u32 src_width
; /* viewport width */
881 u32 active_time
; /* active display time in ns */
882 u32 blank_time
; /* blank time in ns */
883 bool interlaced
; /* mode is interlaced */
884 fixed20_12 vsc
; /* vertical scale ratio */
885 u32 num_heads
; /* number of active crtcs */
886 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
887 u32 lb_size
; /* line buffer allocated to pipe */
888 u32 vtaps
; /* vertical scaler taps */
892 * dce_v10_0_dram_bandwidth - get the dram bandwidth
894 * @wm: watermark calculation data
896 * Calculate the raw dram bandwidth (CIK).
897 * Used for display watermark bandwidth calculations
898 * Returns the dram bandwidth in MBytes/s
900 static u32
dce_v10_0_dram_bandwidth(struct dce10_wm_params
*wm
)
902 /* Calculate raw DRAM Bandwidth */
903 fixed20_12 dram_efficiency
; /* 0.7 */
904 fixed20_12 yclk
, dram_channels
, bandwidth
;
907 a
.full
= dfixed_const(1000);
908 yclk
.full
= dfixed_const(wm
->yclk
);
909 yclk
.full
= dfixed_div(yclk
, a
);
910 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
911 a
.full
= dfixed_const(10);
912 dram_efficiency
.full
= dfixed_const(7);
913 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
914 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
915 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
917 return dfixed_trunc(bandwidth
);
921 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
923 * @wm: watermark calculation data
925 * Calculate the dram bandwidth used for display (CIK).
926 * Used for display watermark bandwidth calculations
927 * Returns the dram bandwidth for display in MBytes/s
929 static u32
dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
931 /* Calculate DRAM Bandwidth and the part allocated to display. */
932 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
933 fixed20_12 yclk
, dram_channels
, bandwidth
;
936 a
.full
= dfixed_const(1000);
937 yclk
.full
= dfixed_const(wm
->yclk
);
938 yclk
.full
= dfixed_div(yclk
, a
);
939 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
940 a
.full
= dfixed_const(10);
941 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
942 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
943 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
944 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
946 return dfixed_trunc(bandwidth
);
950 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
952 * @wm: watermark calculation data
954 * Calculate the data return bandwidth used for display (CIK).
955 * Used for display watermark bandwidth calculations
956 * Returns the data return bandwidth in MBytes/s
958 static u32
dce_v10_0_data_return_bandwidth(struct dce10_wm_params
*wm
)
960 /* Calculate the display Data return Bandwidth */
961 fixed20_12 return_efficiency
; /* 0.8 */
962 fixed20_12 sclk
, bandwidth
;
965 a
.full
= dfixed_const(1000);
966 sclk
.full
= dfixed_const(wm
->sclk
);
967 sclk
.full
= dfixed_div(sclk
, a
);
968 a
.full
= dfixed_const(10);
969 return_efficiency
.full
= dfixed_const(8);
970 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
971 a
.full
= dfixed_const(32);
972 bandwidth
.full
= dfixed_mul(a
, sclk
);
973 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
975 return dfixed_trunc(bandwidth
);
979 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
981 * @wm: watermark calculation data
983 * Calculate the dmif bandwidth used for display (CIK).
984 * Used for display watermark bandwidth calculations
985 * Returns the dmif bandwidth in MBytes/s
987 static u32
dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params
*wm
)
989 /* Calculate the DMIF Request Bandwidth */
990 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
991 fixed20_12 disp_clk
, bandwidth
;
994 a
.full
= dfixed_const(1000);
995 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
996 disp_clk
.full
= dfixed_div(disp_clk
, a
);
997 a
.full
= dfixed_const(32);
998 b
.full
= dfixed_mul(a
, disp_clk
);
1000 a
.full
= dfixed_const(10);
1001 disp_clk_request_efficiency
.full
= dfixed_const(8);
1002 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
1004 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
1006 return dfixed_trunc(bandwidth
);
1010 * dce_v10_0_available_bandwidth - get the min available bandwidth
1012 * @wm: watermark calculation data
1014 * Calculate the min available bandwidth used for display (CIK).
1015 * Used for display watermark bandwidth calculations
1016 * Returns the min available bandwidth in MBytes/s
1018 static u32
dce_v10_0_available_bandwidth(struct dce10_wm_params
*wm
)
1020 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1021 u32 dram_bandwidth
= dce_v10_0_dram_bandwidth(wm
);
1022 u32 data_return_bandwidth
= dce_v10_0_data_return_bandwidth(wm
);
1023 u32 dmif_req_bandwidth
= dce_v10_0_dmif_request_bandwidth(wm
);
1025 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
1029 * dce_v10_0_average_bandwidth - get the average available bandwidth
1031 * @wm: watermark calculation data
1033 * Calculate the average available bandwidth used for display (CIK).
1034 * Used for display watermark bandwidth calculations
1035 * Returns the average available bandwidth in MBytes/s
1037 static u32
dce_v10_0_average_bandwidth(struct dce10_wm_params
*wm
)
1039 /* Calculate the display mode Average Bandwidth
1040 * DisplayMode should contain the source and destination dimensions,
1044 fixed20_12 line_time
;
1045 fixed20_12 src_width
;
1046 fixed20_12 bandwidth
;
1049 a
.full
= dfixed_const(1000);
1050 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1051 line_time
.full
= dfixed_div(line_time
, a
);
1052 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1053 src_width
.full
= dfixed_const(wm
->src_width
);
1054 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1055 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1056 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1058 return dfixed_trunc(bandwidth
);
1062 * dce_v10_0_latency_watermark - get the latency watermark
1064 * @wm: watermark calculation data
1066 * Calculate the latency watermark (CIK).
1067 * Used for display watermark bandwidth calculations
1068 * Returns the latency watermark in ns
1070 static u32
dce_v10_0_latency_watermark(struct dce10_wm_params
*wm
)
1072 /* First calculate the latency in ns */
1073 u32 mc_latency
= 2000; /* 2000 ns. */
1074 u32 available_bandwidth
= dce_v10_0_available_bandwidth(wm
);
1075 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1076 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1077 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1078 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1079 (wm
->num_heads
* cursor_line_pair_return_time
);
1080 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1081 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1082 u32 tmp
, dmif_size
= 12288;
1085 if (wm
->num_heads
== 0)
1088 a
.full
= dfixed_const(2);
1089 b
.full
= dfixed_const(1);
1090 if ((wm
->vsc
.full
> a
.full
) ||
1091 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1093 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1094 max_src_lines_per_dst_line
= 4;
1096 max_src_lines_per_dst_line
= 2;
1098 a
.full
= dfixed_const(available_bandwidth
);
1099 b
.full
= dfixed_const(wm
->num_heads
);
1100 a
.full
= dfixed_div(a
, b
);
1102 b
.full
= dfixed_const(mc_latency
+ 512);
1103 c
.full
= dfixed_const(wm
->disp_clk
);
1104 b
.full
= dfixed_div(b
, c
);
1106 c
.full
= dfixed_const(dmif_size
);
1107 b
.full
= dfixed_div(c
, b
);
1109 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1111 b
.full
= dfixed_const(1000);
1112 c
.full
= dfixed_const(wm
->disp_clk
);
1113 b
.full
= dfixed_div(c
, b
);
1114 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1115 b
.full
= dfixed_mul(b
, c
);
1117 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1119 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1120 b
.full
= dfixed_const(1000);
1121 c
.full
= dfixed_const(lb_fill_bw
);
1122 b
.full
= dfixed_div(c
, b
);
1123 a
.full
= dfixed_div(a
, b
);
1124 line_fill_time
= dfixed_trunc(a
);
1126 if (line_fill_time
< wm
->active_time
)
1129 return latency
+ (line_fill_time
- wm
->active_time
);
1134 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1135 * average and available dram bandwidth
1137 * @wm: watermark calculation data
1139 * Check if the display average bandwidth fits in the display
1140 * dram bandwidth (CIK).
1141 * Used for display watermark bandwidth calculations
1142 * Returns true if the display fits, false if not.
1144 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params
*wm
)
1146 if (dce_v10_0_average_bandwidth(wm
) <=
1147 (dce_v10_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1154 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
1155 * average and available bandwidth
1157 * @wm: watermark calculation data
1159 * Check if the display average bandwidth fits in the display
1160 * available bandwidth (CIK).
1161 * Used for display watermark bandwidth calculations
1162 * Returns true if the display fits, false if not.
1164 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params
*wm
)
1166 if (dce_v10_0_average_bandwidth(wm
) <=
1167 (dce_v10_0_available_bandwidth(wm
) / wm
->num_heads
))
1174 * dce_v10_0_check_latency_hiding - check latency hiding
1176 * @wm: watermark calculation data
1178 * Check latency hiding (CIK).
1179 * Used for display watermark bandwidth calculations
1180 * Returns true if the display fits, false if not.
1182 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params
*wm
)
1184 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1185 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1186 u32 latency_tolerant_lines
;
1190 a
.full
= dfixed_const(1);
1191 if (wm
->vsc
.full
> a
.full
)
1192 latency_tolerant_lines
= 1;
1194 if (lb_partitions
<= (wm
->vtaps
+ 1))
1195 latency_tolerant_lines
= 1;
1197 latency_tolerant_lines
= 2;
1200 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1202 if (dce_v10_0_latency_watermark(wm
) <= latency_hiding
)
1209 * dce_v10_0_program_watermarks - program display watermarks
1211 * @adev: amdgpu_device pointer
1212 * @amdgpu_crtc: the selected display controller
1213 * @lb_size: line buffer size
1214 * @num_heads: number of display controllers in use
1216 * Calculate and program the display watermarks for the
1217 * selected display controller (CIK).
1219 static void dce_v10_0_program_watermarks(struct amdgpu_device
*adev
,
1220 struct amdgpu_crtc
*amdgpu_crtc
,
1221 u32 lb_size
, u32 num_heads
)
1223 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1224 struct dce10_wm_params wm_low
, wm_high
;
1227 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1230 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1231 pixel_period
= 1000000 / (u32
)mode
->clock
;
1232 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1234 /* watermark for high clocks */
1235 if (adev
->pm
.dpm_enabled
) {
1237 amdgpu_dpm_get_mclk(adev
, false) * 10;
1239 amdgpu_dpm_get_sclk(adev
, false) * 10;
1241 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1242 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1245 wm_high
.disp_clk
= mode
->clock
;
1246 wm_high
.src_width
= mode
->crtc_hdisplay
;
1247 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1248 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1249 wm_high
.interlaced
= false;
1250 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1251 wm_high
.interlaced
= true;
1252 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1254 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1256 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1257 wm_high
.lb_size
= lb_size
;
1258 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1259 wm_high
.num_heads
= num_heads
;
1261 /* set for high clocks */
1262 latency_watermark_a
= min(dce_v10_0_latency_watermark(&wm_high
), (u32
)65535);
1264 /* possibly force display priority to high */
1265 /* should really do this at mode validation time... */
1266 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1267 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1268 !dce_v10_0_check_latency_hiding(&wm_high
) ||
1269 (adev
->mode_info
.disp_priority
== 2)) {
1270 DRM_DEBUG_KMS("force priority to high\n");
1273 /* watermark for low clocks */
1274 if (adev
->pm
.dpm_enabled
) {
1276 amdgpu_dpm_get_mclk(adev
, true) * 10;
1278 amdgpu_dpm_get_sclk(adev
, true) * 10;
1280 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1281 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1284 wm_low
.disp_clk
= mode
->clock
;
1285 wm_low
.src_width
= mode
->crtc_hdisplay
;
1286 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1287 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1288 wm_low
.interlaced
= false;
1289 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1290 wm_low
.interlaced
= true;
1291 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1293 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1295 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1296 wm_low
.lb_size
= lb_size
;
1297 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1298 wm_low
.num_heads
= num_heads
;
1300 /* set for low clocks */
1301 latency_watermark_b
= min(dce_v10_0_latency_watermark(&wm_low
), (u32
)65535);
1303 /* possibly force display priority to high */
1304 /* should really do this at mode validation time... */
1305 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1306 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1307 !dce_v10_0_check_latency_hiding(&wm_low
) ||
1308 (adev
->mode_info
.disp_priority
== 2)) {
1309 DRM_DEBUG_KMS("force priority to high\n");
1314 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1315 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 1);
1316 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1317 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1318 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1319 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1320 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1322 tmp
= REG_SET_FIELD(wm_mask
, DPG_WATERMARK_MASK_CONTROL
, URGENCY_WATERMARK_MASK
, 2);
1323 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1324 tmp
= RREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1325 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_LOW_WATERMARK
, latency_watermark_a
);
1326 tmp
= REG_SET_FIELD(tmp
, DPG_PIPE_URGENCY_CONTROL
, URGENCY_HIGH_WATERMARK
, line_time
);
1327 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1328 /* restore original selection */
1329 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1331 /* save values for DPM */
1332 amdgpu_crtc
->line_time
= line_time
;
1333 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1334 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1338 * dce_v10_0_bandwidth_update - program display watermarks
1340 * @adev: amdgpu_device pointer
1342 * Calculate and program the display watermarks and line
1343 * buffer allocation (CIK).
1345 static void dce_v10_0_bandwidth_update(struct amdgpu_device
*adev
)
1347 struct drm_display_mode
*mode
= NULL
;
1348 u32 num_heads
= 0, lb_size
;
1351 amdgpu_update_display_priority(adev
);
1353 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1354 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1357 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1358 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1359 lb_size
= dce_v10_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1360 dce_v10_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1361 lb_size
, num_heads
);
1365 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1370 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1371 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1372 tmp
= RREG32_AUDIO_ENDPT(offset
,
1373 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1375 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1376 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1377 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1379 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1383 static struct amdgpu_audio_pin
*dce_v10_0_audio_get_pin(struct amdgpu_device
*adev
)
1387 dce_v10_0_audio_get_connected_pins(adev
);
1389 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1390 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1391 return &adev
->mode_info
.audio
.pin
[i
];
1393 DRM_ERROR("No connected audio pins found!\n");
1397 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1399 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1400 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1401 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1404 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1407 tmp
= RREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
);
1408 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_SRC_CONTROL
, AFMT_AUDIO_SRC_SELECT
, dig
->afmt
->pin
->id
);
1409 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ dig
->afmt
->offset
, tmp
);
1412 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1413 struct drm_display_mode
*mode
)
1415 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1416 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1417 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1418 struct drm_connector
*connector
;
1419 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1423 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1426 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1427 if (connector
->encoder
== encoder
) {
1428 amdgpu_connector
= to_amdgpu_connector(connector
);
1433 if (!amdgpu_connector
) {
1434 DRM_ERROR("Couldn't find encoder's connector\n");
1438 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1440 if (connector
->latency_present
[interlace
]) {
1441 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1442 VIDEO_LIPSYNC
, connector
->video_latency
[interlace
]);
1443 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1444 AUDIO_LIPSYNC
, connector
->audio_latency
[interlace
]);
1446 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1448 tmp
= REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
,
1451 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1452 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1455 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1457 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1458 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1459 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1460 struct drm_connector
*connector
;
1461 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1466 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1469 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1470 if (connector
->encoder
== encoder
) {
1471 amdgpu_connector
= to_amdgpu_connector(connector
);
1476 if (!amdgpu_connector
) {
1477 DRM_ERROR("Couldn't find encoder's connector\n");
1481 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1482 if (sad_count
< 0) {
1483 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1487 /* program the speaker allocation */
1488 tmp
= RREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1489 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1490 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1493 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1494 HDMI_CONNECTION
, 1);
1496 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1497 SPEAKER_ALLOCATION
, sadb
[0]);
1499 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
,
1500 SPEAKER_ALLOCATION
, 5); /* stereo */
1501 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
,
1502 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1507 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1509 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1510 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1511 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1512 struct drm_connector
*connector
;
1513 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1514 struct cea_sad
*sads
;
1517 static const u16 eld_reg_to_type
[][2] = {
1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1520 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1521 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1522 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1523 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1524 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1525 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1526 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1527 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1528 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1529 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1532 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1535 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1536 if (connector
->encoder
== encoder
) {
1537 amdgpu_connector
= to_amdgpu_connector(connector
);
1542 if (!amdgpu_connector
) {
1543 DRM_ERROR("Couldn't find encoder's connector\n");
1547 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1548 if (sad_count
<= 0) {
1549 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1554 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1556 u8 stereo_freqs
= 0;
1557 int max_channels
= -1;
1560 for (j
= 0; j
< sad_count
; j
++) {
1561 struct cea_sad
*sad
= &sads
[j
];
1563 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1564 if (sad
->channels
> max_channels
) {
1565 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1566 MAX_CHANNELS
, sad
->channels
);
1567 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1568 DESCRIPTOR_BYTE_2
, sad
->byte2
);
1569 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1570 SUPPORTED_FREQUENCIES
, sad
->freq
);
1571 max_channels
= sad
->channels
;
1574 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1575 stereo_freqs
|= sad
->freq
;
1581 tmp
= REG_SET_FIELD(tmp
, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
,
1582 SUPPORTED_FREQUENCIES_STEREO
, stereo_freqs
);
1583 WREG32_AUDIO_ENDPT(dig
->afmt
->pin
->offset
, eld_reg_to_type
[i
][0], tmp
);
1589 static void dce_v10_0_audio_enable(struct amdgpu_device
*adev
,
1590 struct amdgpu_audio_pin
*pin
,
1596 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1597 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1600 static const u32 pin_offsets
[] =
1602 AUD0_REGISTER_OFFSET
,
1603 AUD1_REGISTER_OFFSET
,
1604 AUD2_REGISTER_OFFSET
,
1605 AUD3_REGISTER_OFFSET
,
1606 AUD4_REGISTER_OFFSET
,
1607 AUD5_REGISTER_OFFSET
,
1608 AUD6_REGISTER_OFFSET
,
1611 static int dce_v10_0_audio_init(struct amdgpu_device
*adev
)
1618 adev
->mode_info
.audio
.enabled
= true;
1620 adev
->mode_info
.audio
.num_pins
= 7;
1622 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1623 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1624 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1625 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1626 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1627 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1628 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1629 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1630 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1631 /* disable audio. it will be set up later */
1632 /* XXX remove once we switch to ip funcs */
1633 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1639 static void dce_v10_0_audio_fini(struct amdgpu_device
*adev
)
1643 if (!adev
->mode_info
.audio
.enabled
)
1646 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1647 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1649 adev
->mode_info
.audio
.enabled
= false;
1653 * update the N and CTS parameters for a given pixel clock rate
1655 static void dce_v10_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1657 struct drm_device
*dev
= encoder
->dev
;
1658 struct amdgpu_device
*adev
= dev
->dev_private
;
1659 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1660 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1661 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1664 tmp
= RREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
);
1665 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_0
, HDMI_ACR_CTS_32
, acr
.cts_32khz
);
1666 WREG32(mmHDMI_ACR_32_0
+ dig
->afmt
->offset
, tmp
);
1667 tmp
= RREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
);
1668 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_32_1
, HDMI_ACR_N_32
, acr
.n_32khz
);
1669 WREG32(mmHDMI_ACR_32_1
+ dig
->afmt
->offset
, tmp
);
1671 tmp
= RREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
);
1672 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_0
, HDMI_ACR_CTS_44
, acr
.cts_44_1khz
);
1673 WREG32(mmHDMI_ACR_44_0
+ dig
->afmt
->offset
, tmp
);
1674 tmp
= RREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
);
1675 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_44_1
, HDMI_ACR_N_44
, acr
.n_44_1khz
);
1676 WREG32(mmHDMI_ACR_44_1
+ dig
->afmt
->offset
, tmp
);
1678 tmp
= RREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
);
1679 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_0
, HDMI_ACR_CTS_48
, acr
.cts_48khz
);
1680 WREG32(mmHDMI_ACR_48_0
+ dig
->afmt
->offset
, tmp
);
1681 tmp
= RREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
);
1682 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_48_1
, HDMI_ACR_N_48
, acr
.n_48khz
);
1683 WREG32(mmHDMI_ACR_48_1
+ dig
->afmt
->offset
, tmp
);
1688 * build a HDMI Video Info Frame
1690 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1691 void *buffer
, size_t size
)
1693 struct drm_device
*dev
= encoder
->dev
;
1694 struct amdgpu_device
*adev
= dev
->dev_private
;
1695 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1696 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1697 uint8_t *frame
= buffer
+ 3;
1698 uint8_t *header
= buffer
;
1700 WREG32(mmAFMT_AVI_INFO0
+ dig
->afmt
->offset
,
1701 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1702 WREG32(mmAFMT_AVI_INFO1
+ dig
->afmt
->offset
,
1703 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1704 WREG32(mmAFMT_AVI_INFO2
+ dig
->afmt
->offset
,
1705 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1706 WREG32(mmAFMT_AVI_INFO3
+ dig
->afmt
->offset
,
1707 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1710 static void dce_v10_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1712 struct drm_device
*dev
= encoder
->dev
;
1713 struct amdgpu_device
*adev
= dev
->dev_private
;
1714 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1715 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1716 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1717 u32 dto_phase
= 24 * 1000;
1718 u32 dto_modulo
= clock
;
1721 if (!dig
|| !dig
->afmt
)
1724 /* XXX two dtos; generally use dto0 for hdmi */
1725 /* Express [24MHz / target pixel clock] as an exact rational
1726 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1727 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1729 tmp
= RREG32(mmDCCG_AUDIO_DTO_SOURCE
);
1730 tmp
= REG_SET_FIELD(tmp
, DCCG_AUDIO_DTO_SOURCE
, DCCG_AUDIO_DTO0_SOURCE_SEL
,
1731 amdgpu_crtc
->crtc_id
);
1732 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, tmp
);
1733 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1734 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1738 * update the info frames with the data from the current display mode
1740 static void dce_v10_0_afmt_setmode(struct drm_encoder
*encoder
,
1741 struct drm_display_mode
*mode
)
1743 struct drm_device
*dev
= encoder
->dev
;
1744 struct amdgpu_device
*adev
= dev
->dev_private
;
1745 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1746 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1747 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1748 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1749 struct hdmi_avi_infoframe frame
;
1754 if (!dig
|| !dig
->afmt
)
1757 /* Silent, r600_hdmi_enable will raise WARN for us */
1758 if (!dig
->afmt
->enabled
)
1761 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1762 if (encoder
->crtc
) {
1763 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1764 bpc
= amdgpu_crtc
->bpc
;
1767 /* disable audio prior to setting up hw */
1768 dig
->afmt
->pin
= dce_v10_0_audio_get_pin(adev
);
1769 dce_v10_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1771 dce_v10_0_audio_set_dto(encoder
, mode
->clock
);
1773 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1774 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1);
1775 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
); /* send null packets when required */
1777 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ dig
->afmt
->offset
, 0x1000);
1779 tmp
= RREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
);
1786 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 0);
1787 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 0);
1788 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1789 connector
->name
, bpc
);
1792 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1793 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 1);
1794 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1798 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_ENABLE
, 1);
1799 tmp
= REG_SET_FIELD(tmp
, HDMI_CONTROL
, HDMI_DEEP_COLOR_DEPTH
, 2);
1800 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1804 WREG32(mmHDMI_CONTROL
+ dig
->afmt
->offset
, tmp
);
1806 tmp
= RREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
);
1807 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_NULL_SEND
, 1); /* send null packets when required */
1808 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_SEND
, 1); /* send general control packets */
1809 tmp
= REG_SET_FIELD(tmp
, HDMI_VBI_PACKET_CONTROL
, HDMI_GC_CONT
, 1); /* send general control packets every frame */
1810 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1812 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1813 /* enable audio info frames (frames won't be set until audio is enabled) */
1814 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_SEND
, 1);
1815 /* required for audio info values to be updated */
1816 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AUDIO_INFO_CONT
, 1);
1817 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1819 tmp
= RREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1820 /* required for audio info values to be updated */
1821 tmp
= REG_SET_FIELD(tmp
, AFMT_INFOFRAME_CONTROL0
, AFMT_AUDIO_INFO_UPDATE
, 1);
1822 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1824 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1825 /* anything other than 0 */
1826 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AUDIO_INFO_LINE
, 2);
1827 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1829 WREG32(mmHDMI_GC
+ dig
->afmt
->offset
, 0); /* unset HDMI_GC_AVMUTE */
1831 tmp
= RREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1832 /* set the default audio delay */
1833 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_DELAY_EN
, 1);
1834 /* should be suffient for all audio modes and small enough for all hblanks */
1835 tmp
= REG_SET_FIELD(tmp
, HDMI_AUDIO_PACKET_CONTROL
, HDMI_AUDIO_PACKETS_PER_LINE
, 3);
1836 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1838 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1839 /* allow 60958 channel status fields to be updated */
1840 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_60958_CS_UPDATE
, 1);
1841 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1843 tmp
= RREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
);
1845 /* clear SW CTS value */
1846 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 0);
1848 /* select SW CTS value */
1849 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_SOURCE
, 1);
1850 /* allow hw to sent ACR packets when required */
1851 tmp
= REG_SET_FIELD(tmp
, HDMI_ACR_PACKET_CONTROL
, HDMI_ACR_AUTO_SEND
, 1);
1852 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1854 dce_v10_0_afmt_update_ACR(encoder
, mode
->clock
);
1856 tmp
= RREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
);
1857 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_0
, AFMT_60958_CS_CHANNEL_NUMBER_L
, 1);
1858 WREG32(mmAFMT_60958_0
+ dig
->afmt
->offset
, tmp
);
1860 tmp
= RREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
);
1861 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_1
, AFMT_60958_CS_CHANNEL_NUMBER_R
, 2);
1862 WREG32(mmAFMT_60958_1
+ dig
->afmt
->offset
, tmp
);
1864 tmp
= RREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
);
1865 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_2
, 3);
1866 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_3
, 4);
1867 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_4
, 5);
1868 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_5
, 6);
1869 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_6
, 7);
1870 tmp
= REG_SET_FIELD(tmp
, AFMT_60958_2
, AFMT_60958_CS_CHANNEL_NUMBER_7
, 8);
1871 WREG32(mmAFMT_60958_2
+ dig
->afmt
->offset
, tmp
);
1873 dce_v10_0_audio_write_speaker_allocation(encoder
);
1875 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ dig
->afmt
->offset
,
1876 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1878 dce_v10_0_afmt_audio_select_pin(encoder
);
1879 dce_v10_0_audio_write_sad_regs(encoder
);
1880 dce_v10_0_audio_write_latency_fields(encoder
, mode
);
1882 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1884 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1888 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1890 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1894 dce_v10_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1896 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
);
1897 /* enable AVI info frames */
1898 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_SEND
, 1);
1899 /* required for audio info values to be updated */
1900 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL0
, HDMI_AVI_INFO_CONT
, 1);
1901 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ dig
->afmt
->offset
, tmp
);
1903 tmp
= RREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
);
1904 tmp
= REG_SET_FIELD(tmp
, HDMI_INFOFRAME_CONTROL1
, HDMI_AVI_INFO_LINE
, 2);
1905 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ dig
->afmt
->offset
, tmp
);
1907 tmp
= RREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
);
1908 /* send audio packets */
1909 tmp
= REG_SET_FIELD(tmp
, AFMT_AUDIO_PACKET_CONTROL
, AFMT_AUDIO_SAMPLE_SEND
, 1);
1910 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ dig
->afmt
->offset
, tmp
);
1912 WREG32(mmAFMT_RAMP_CONTROL0
+ dig
->afmt
->offset
, 0x00FFFFFF);
1913 WREG32(mmAFMT_RAMP_CONTROL1
+ dig
->afmt
->offset
, 0x007FFFFF);
1914 WREG32(mmAFMT_RAMP_CONTROL2
+ dig
->afmt
->offset
, 0x00000001);
1915 WREG32(mmAFMT_RAMP_CONTROL3
+ dig
->afmt
->offset
, 0x00000001);
1917 /* enable audio after to setting up hw */
1918 dce_v10_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1921 static void dce_v10_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1923 struct drm_device
*dev
= encoder
->dev
;
1924 struct amdgpu_device
*adev
= dev
->dev_private
;
1925 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1926 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1928 if (!dig
|| !dig
->afmt
)
1931 /* Silent, r600_hdmi_enable will raise WARN for us */
1932 if (enable
&& dig
->afmt
->enabled
)
1934 if (!enable
&& !dig
->afmt
->enabled
)
1937 if (!enable
&& dig
->afmt
->pin
) {
1938 dce_v10_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1939 dig
->afmt
->pin
= NULL
;
1942 dig
->afmt
->enabled
= enable
;
1944 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1945 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1948 static void dce_v10_0_afmt_init(struct amdgpu_device
*adev
)
1952 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1953 adev
->mode_info
.afmt
[i
] = NULL
;
1955 /* DCE10 has audio blocks tied to DIG encoders */
1956 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1957 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1958 if (adev
->mode_info
.afmt
[i
]) {
1959 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1960 adev
->mode_info
.afmt
[i
]->id
= i
;
1965 static void dce_v10_0_afmt_fini(struct amdgpu_device
*adev
)
1969 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1970 kfree(adev
->mode_info
.afmt
[i
]);
1971 adev
->mode_info
.afmt
[i
] = NULL
;
1975 static const u32 vga_control_regs
[6] =
1985 static void dce_v10_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
1987 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1988 struct drm_device
*dev
= crtc
->dev
;
1989 struct amdgpu_device
*adev
= dev
->dev_private
;
1992 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
1994 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
1996 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
1999 static void dce_v10_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
2001 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2002 struct drm_device
*dev
= crtc
->dev
;
2003 struct amdgpu_device
*adev
= dev
->dev_private
;
2006 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
2008 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
2011 static int dce_v10_0_crtc_do_set_base(struct drm_crtc
*crtc
,
2012 struct drm_framebuffer
*fb
,
2013 int x
, int y
, int atomic
)
2015 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2016 struct drm_device
*dev
= crtc
->dev
;
2017 struct amdgpu_device
*adev
= dev
->dev_private
;
2018 struct amdgpu_framebuffer
*amdgpu_fb
;
2019 struct drm_framebuffer
*target_fb
;
2020 struct drm_gem_object
*obj
;
2021 struct amdgpu_bo
*rbo
;
2022 uint64_t fb_location
, tiling_flags
;
2023 uint32_t fb_format
, fb_pitch_pixels
;
2024 u32 fb_swap
= REG_SET_FIELD(0, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
, ENDIAN_NONE
);
2026 u32 tmp
, viewport_w
, viewport_h
;
2028 bool bypass_lut
= false;
2031 if (!atomic
&& !crtc
->primary
->fb
) {
2032 DRM_DEBUG_KMS("No FB bound\n");
2037 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2041 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2042 target_fb
= crtc
->primary
->fb
;
2045 /* If atomic, assume fb object is pinned & idle & fenced and
2046 * just update base pointers
2048 obj
= amdgpu_fb
->obj
;
2049 rbo
= gem_to_amdgpu_bo(obj
);
2050 r
= amdgpu_bo_reserve(rbo
, false);
2051 if (unlikely(r
!= 0))
2055 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2057 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2058 if (unlikely(r
!= 0)) {
2059 amdgpu_bo_unreserve(rbo
);
2064 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2065 amdgpu_bo_unreserve(rbo
);
2067 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2069 switch (target_fb
->pixel_format
) {
2071 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 0);
2072 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2074 case DRM_FORMAT_XRGB4444
:
2075 case DRM_FORMAT_ARGB4444
:
2076 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2077 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 2);
2079 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2083 case DRM_FORMAT_XRGB1555
:
2084 case DRM_FORMAT_ARGB1555
:
2085 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2086 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2088 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2092 case DRM_FORMAT_BGRX5551
:
2093 case DRM_FORMAT_BGRA5551
:
2094 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2095 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 5);
2097 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2101 case DRM_FORMAT_RGB565
:
2102 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 1);
2103 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2105 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2109 case DRM_FORMAT_XRGB8888
:
2110 case DRM_FORMAT_ARGB8888
:
2111 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2112 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 0);
2114 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2118 case DRM_FORMAT_XRGB2101010
:
2119 case DRM_FORMAT_ARGB2101010
:
2120 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2121 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 1);
2123 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2126 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2129 case DRM_FORMAT_BGRX1010102
:
2130 case DRM_FORMAT_BGRA1010102
:
2131 fb_format
= REG_SET_FIELD(0, GRPH_CONTROL
, GRPH_DEPTH
, 2);
2132 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_FORMAT
, 4);
2134 fb_swap
= REG_SET_FIELD(fb_swap
, GRPH_SWAP_CNTL
, GRPH_ENDIAN_SWAP
,
2137 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2141 DRM_ERROR("Unsupported screen format %s\n",
2142 drm_get_format_name(target_fb
->pixel_format
));
2146 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2147 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2149 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2150 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2151 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2152 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2153 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2155 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_NUM_BANKS
, num_banks
);
2156 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2157 ARRAY_2D_TILED_THIN1
);
2158 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_TILE_SPLIT
,
2160 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_WIDTH
, bankw
);
2161 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_BANK_HEIGHT
, bankh
);
2162 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MACRO_TILE_ASPECT
,
2164 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_MICRO_TILE_MODE
,
2165 ADDR_SURF_MICRO_TILING_DISPLAY
);
2166 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2167 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_ARRAY_MODE
,
2168 ARRAY_1D_TILED_THIN1
);
2171 fb_format
= REG_SET_FIELD(fb_format
, GRPH_CONTROL
, GRPH_PIPE_CONFIG
,
2174 dce_v10_0_vga_enable(crtc
, false);
2176 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2177 upper_32_bits(fb_location
));
2178 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2179 upper_32_bits(fb_location
));
2180 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2181 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2182 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2183 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2184 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2185 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2188 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2189 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2190 * retain the full precision throughout the pipeline.
2192 tmp
= RREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
);
2194 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 1);
2196 tmp
= REG_SET_FIELD(tmp
, GRPH_LUT_10BIT_BYPASS
, GRPH_LUT_10BIT_BYPASS_EN
, 0);
2197 WREG32(mmGRPH_LUT_10BIT_BYPASS
+ amdgpu_crtc
->crtc_offset
, tmp
);
2200 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2202 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2203 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2204 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2205 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2206 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2207 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2209 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2210 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2212 dce_v10_0_grph_enable(crtc
, true);
2214 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2219 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2221 viewport_w
= crtc
->mode
.hdisplay
;
2222 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2223 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2224 (viewport_w
<< 16) | viewport_h
);
2226 /* pageflip setup */
2227 /* make sure flip is at vb rather than hb */
2228 tmp
= RREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2229 tmp
= REG_SET_FIELD(tmp
, GRPH_FLIP_CONTROL
,
2230 GRPH_SURFACE_UPDATE_H_RETRACE_EN
, 0);
2231 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2233 /* set pageflip to happen only at start of vblank interval (front porch) */
2234 WREG32(mmMASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 3);
2236 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2237 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2238 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2239 r
= amdgpu_bo_reserve(rbo
, false);
2240 if (unlikely(r
!= 0))
2242 amdgpu_bo_unpin(rbo
);
2243 amdgpu_bo_unreserve(rbo
);
2246 /* Bytes per pixel may have changed */
2247 dce_v10_0_bandwidth_update(adev
);
2252 static void dce_v10_0_set_interleave(struct drm_crtc
*crtc
,
2253 struct drm_display_mode
*mode
)
2255 struct drm_device
*dev
= crtc
->dev
;
2256 struct amdgpu_device
*adev
= dev
->dev_private
;
2257 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2260 tmp
= RREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
);
2261 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2262 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 1);
2264 tmp
= REG_SET_FIELD(tmp
, LB_DATA_FORMAT
, INTERLEAVE_EN
, 0);
2265 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, tmp
);
2268 static void dce_v10_0_crtc_load_lut(struct drm_crtc
*crtc
)
2270 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2271 struct drm_device
*dev
= crtc
->dev
;
2272 struct amdgpu_device
*adev
= dev
->dev_private
;
2276 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2278 tmp
= RREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2279 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_GRPH_MODE
, 0);
2280 tmp
= REG_SET_FIELD(tmp
, INPUT_CSC_CONTROL
, INPUT_CSC_OVL_MODE
, 0);
2281 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2283 tmp
= RREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2284 tmp
= REG_SET_FIELD(tmp
, PRESCALE_GRPH_CONTROL
, GRPH_PRESCALE_BYPASS
, 1);
2285 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2287 tmp
= RREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2288 tmp
= REG_SET_FIELD(tmp
, PRESCALE_OVL_CONTROL
, OVL_PRESCALE_BYPASS
, 1);
2289 WREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2291 tmp
= RREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2292 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, GRPH_INPUT_GAMMA_MODE
, 0);
2293 tmp
= REG_SET_FIELD(tmp
, INPUT_GAMMA_CONTROL
, OVL_INPUT_GAMMA_MODE
, 0);
2294 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2296 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2298 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2299 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2300 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2302 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2303 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2304 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2306 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2307 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2309 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2310 for (i
= 0; i
< 256; i
++) {
2311 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2312 (amdgpu_crtc
->lut_r
[i
] << 20) |
2313 (amdgpu_crtc
->lut_g
[i
] << 10) |
2314 (amdgpu_crtc
->lut_b
[i
] << 0));
2317 tmp
= RREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2318 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, GRPH_DEGAMMA_MODE
, 0);
2319 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, OVL_DEGAMMA_MODE
, 0);
2320 tmp
= REG_SET_FIELD(tmp
, DEGAMMA_CONTROL
, CURSOR_DEGAMMA_MODE
, 0);
2321 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2323 tmp
= RREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2324 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, GRPH_GAMUT_REMAP_MODE
, 0);
2325 tmp
= REG_SET_FIELD(tmp
, GAMUT_REMAP_CONTROL
, OVL_GAMUT_REMAP_MODE
, 0);
2326 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2328 tmp
= RREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2329 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, GRPH_REGAMMA_MODE
, 0);
2330 tmp
= REG_SET_FIELD(tmp
, REGAMMA_CONTROL
, OVL_REGAMMA_MODE
, 0);
2331 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2333 tmp
= RREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2334 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_GRPH_MODE
, 0);
2335 tmp
= REG_SET_FIELD(tmp
, OUTPUT_CSC_CONTROL
, OUTPUT_CSC_OVL_MODE
, 0);
2336 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2338 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2339 WREG32(mmDENORM_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2340 /* XXX this only needs to be programmed once per crtc at startup,
2341 * not sure where the best place for it is
2343 tmp
= RREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2344 tmp
= REG_SET_FIELD(tmp
, ALPHA_CONTROL
, CURSOR_ALPHA_BLND_ENA
, 1);
2345 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2348 static int dce_v10_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2350 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2351 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2353 switch (amdgpu_encoder
->encoder_id
) {
2354 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2360 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2366 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2372 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2376 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2382 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2386 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2387 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2388 * monitors a dedicated PPLL must be used. If a particular board has
2389 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2390 * as there is no need to program the PLL itself. If we are not able to
2391 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2392 * avoid messing up an existing monitor.
2394 * Asic specific PLL information
2398 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2400 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2403 static u32
dce_v10_0_pick_pll(struct drm_crtc
*crtc
)
2405 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2406 struct drm_device
*dev
= crtc
->dev
;
2407 struct amdgpu_device
*adev
= dev
->dev_private
;
2411 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2412 if (adev
->clock
.dp_extclk
)
2413 /* skip PPLL programming if using ext clock */
2414 return ATOM_PPLL_INVALID
;
2416 /* use the same PPLL for all DP monitors */
2417 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2418 if (pll
!= ATOM_PPLL_INVALID
)
2422 /* use the same PPLL for all monitors with the same clock */
2423 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2424 if (pll
!= ATOM_PPLL_INVALID
)
2428 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2429 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2430 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2432 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2434 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2436 DRM_ERROR("unable to allocate a PPLL\n");
2437 return ATOM_PPLL_INVALID
;
2440 static void dce_v10_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2442 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2443 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2446 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2448 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 1);
2450 cur_lock
= REG_SET_FIELD(cur_lock
, CUR_UPDATE
, CURSOR_UPDATE_LOCK
, 0);
2451 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2454 static void dce_v10_0_hide_cursor(struct drm_crtc
*crtc
)
2456 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2457 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2460 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2461 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 0);
2462 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2465 static void dce_v10_0_show_cursor(struct drm_crtc
*crtc
)
2467 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2468 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2471 tmp
= RREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
);
2472 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_EN
, 1);
2473 tmp
= REG_SET_FIELD(tmp
, CUR_CONTROL
, CURSOR_MODE
, 2);
2474 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
2477 static void dce_v10_0_set_cursor(struct drm_crtc
*crtc
, struct drm_gem_object
*obj
,
2480 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2481 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2483 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2484 upper_32_bits(gpu_addr
));
2485 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2486 lower_32_bits(gpu_addr
));
2489 static int dce_v10_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2492 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2493 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2494 int xorigin
= 0, yorigin
= 0;
2496 /* avivo cursor are offset into the total surface */
2499 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2502 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2506 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2510 dce_v10_0_lock_cursor(crtc
, true);
2511 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2512 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2513 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2514 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2515 dce_v10_0_lock_cursor(crtc
, false);
2520 static int dce_v10_0_crtc_cursor_set(struct drm_crtc
*crtc
,
2521 struct drm_file
*file_priv
,
2526 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2527 struct drm_gem_object
*obj
;
2528 struct amdgpu_bo
*robj
;
2533 /* turn off cursor */
2534 dce_v10_0_hide_cursor(crtc
);
2539 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2540 (height
> amdgpu_crtc
->max_cursor_height
)) {
2541 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2545 obj
= drm_gem_object_lookup(crtc
->dev
, file_priv
, handle
);
2547 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2551 robj
= gem_to_amdgpu_bo(obj
);
2552 ret
= amdgpu_bo_reserve(robj
, false);
2553 if (unlikely(ret
!= 0))
2555 ret
= amdgpu_bo_pin_restricted(robj
, AMDGPU_GEM_DOMAIN_VRAM
,
2557 amdgpu_bo_unreserve(robj
);
2561 amdgpu_crtc
->cursor_width
= width
;
2562 amdgpu_crtc
->cursor_height
= height
;
2564 dce_v10_0_lock_cursor(crtc
, true);
2565 dce_v10_0_set_cursor(crtc
, obj
, gpu_addr
);
2566 dce_v10_0_show_cursor(crtc
);
2567 dce_v10_0_lock_cursor(crtc
, false);
2570 if (amdgpu_crtc
->cursor_bo
) {
2571 robj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2572 ret
= amdgpu_bo_reserve(robj
, false);
2573 if (likely(ret
== 0)) {
2574 amdgpu_bo_unpin(robj
);
2575 amdgpu_bo_unreserve(robj
);
2577 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2580 amdgpu_crtc
->cursor_bo
= obj
;
2583 drm_gem_object_unreference_unlocked(obj
);
2588 static void dce_v10_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2589 u16
*blue
, uint32_t start
, uint32_t size
)
2591 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2592 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
2594 /* userspace palettes are always correct as is */
2595 for (i
= start
; i
< end
; i
++) {
2596 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2597 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2598 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2600 dce_v10_0_crtc_load_lut(crtc
);
2603 static void dce_v10_0_crtc_destroy(struct drm_crtc
*crtc
)
2605 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2607 drm_crtc_cleanup(crtc
);
2608 destroy_workqueue(amdgpu_crtc
->pflip_queue
);
2612 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs
= {
2613 .cursor_set
= dce_v10_0_crtc_cursor_set
,
2614 .cursor_move
= dce_v10_0_crtc_cursor_move
,
2615 .gamma_set
= dce_v10_0_crtc_gamma_set
,
2616 .set_config
= amdgpu_crtc_set_config
,
2617 .destroy
= dce_v10_0_crtc_destroy
,
2618 .page_flip
= amdgpu_crtc_page_flip
,
2621 static void dce_v10_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2623 struct drm_device
*dev
= crtc
->dev
;
2624 struct amdgpu_device
*adev
= dev
->dev_private
;
2625 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2628 case DRM_MODE_DPMS_ON
:
2629 amdgpu_crtc
->enabled
= true;
2630 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2631 dce_v10_0_vga_enable(crtc
, true);
2632 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2633 dce_v10_0_vga_enable(crtc
, false);
2634 drm_vblank_post_modeset(dev
, amdgpu_crtc
->crtc_id
);
2635 dce_v10_0_crtc_load_lut(crtc
);
2637 case DRM_MODE_DPMS_STANDBY
:
2638 case DRM_MODE_DPMS_SUSPEND
:
2639 case DRM_MODE_DPMS_OFF
:
2640 drm_vblank_pre_modeset(dev
, amdgpu_crtc
->crtc_id
);
2641 if (amdgpu_crtc
->enabled
) {
2642 dce_v10_0_vga_enable(crtc
, true);
2643 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2644 dce_v10_0_vga_enable(crtc
, false);
2646 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2647 amdgpu_crtc
->enabled
= false;
2650 /* adjust pm to dpms */
2651 amdgpu_pm_compute_clocks(adev
);
2654 static void dce_v10_0_crtc_prepare(struct drm_crtc
*crtc
)
2656 /* disable crtc pair power gating before programming */
2657 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2658 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2659 dce_v10_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2662 static void dce_v10_0_crtc_commit(struct drm_crtc
*crtc
)
2664 dce_v10_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2665 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2668 static void dce_v10_0_crtc_disable(struct drm_crtc
*crtc
)
2670 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2671 struct drm_device
*dev
= crtc
->dev
;
2672 struct amdgpu_device
*adev
= dev
->dev_private
;
2673 struct amdgpu_atom_ss ss
;
2676 dce_v10_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2677 if (crtc
->primary
->fb
) {
2679 struct amdgpu_framebuffer
*amdgpu_fb
;
2680 struct amdgpu_bo
*rbo
;
2682 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2683 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2684 r
= amdgpu_bo_reserve(rbo
, false);
2686 DRM_ERROR("failed to reserve rbo before unpin\n");
2688 amdgpu_bo_unpin(rbo
);
2689 amdgpu_bo_unreserve(rbo
);
2692 /* disable the GRPH */
2693 dce_v10_0_grph_enable(crtc
, false);
2695 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2697 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2698 if (adev
->mode_info
.crtcs
[i
] &&
2699 adev
->mode_info
.crtcs
[i
]->enabled
&&
2700 i
!= amdgpu_crtc
->crtc_id
&&
2701 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2702 /* one other crtc is using this pll don't turn
2709 switch (amdgpu_crtc
->pll_id
) {
2713 /* disable the ppll */
2714 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2715 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2721 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2722 amdgpu_crtc
->adjusted_clock
= 0;
2723 amdgpu_crtc
->encoder
= NULL
;
2724 amdgpu_crtc
->connector
= NULL
;
2727 static int dce_v10_0_crtc_mode_set(struct drm_crtc
*crtc
,
2728 struct drm_display_mode
*mode
,
2729 struct drm_display_mode
*adjusted_mode
,
2730 int x
, int y
, struct drm_framebuffer
*old_fb
)
2732 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2734 if (!amdgpu_crtc
->adjusted_clock
)
2737 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2738 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2739 dce_v10_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2740 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2741 amdgpu_atombios_crtc_scaler_setup(crtc
);
2742 /* update the hw version fpr dpm */
2743 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2748 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2749 const struct drm_display_mode
*mode
,
2750 struct drm_display_mode
*adjusted_mode
)
2752 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2753 struct drm_device
*dev
= crtc
->dev
;
2754 struct drm_encoder
*encoder
;
2756 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2757 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2758 if (encoder
->crtc
== crtc
) {
2759 amdgpu_crtc
->encoder
= encoder
;
2760 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2764 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2765 amdgpu_crtc
->encoder
= NULL
;
2766 amdgpu_crtc
->connector
= NULL
;
2769 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2771 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2774 amdgpu_crtc
->pll_id
= dce_v10_0_pick_pll(crtc
);
2775 /* if we can't get a PPLL for a non-DP encoder, fail */
2776 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2777 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2783 static int dce_v10_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2784 struct drm_framebuffer
*old_fb
)
2786 return dce_v10_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2789 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2790 struct drm_framebuffer
*fb
,
2791 int x
, int y
, enum mode_set_atomic state
)
2793 return dce_v10_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2796 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs
= {
2797 .dpms
= dce_v10_0_crtc_dpms
,
2798 .mode_fixup
= dce_v10_0_crtc_mode_fixup
,
2799 .mode_set
= dce_v10_0_crtc_mode_set
,
2800 .mode_set_base
= dce_v10_0_crtc_set_base
,
2801 .mode_set_base_atomic
= dce_v10_0_crtc_set_base_atomic
,
2802 .prepare
= dce_v10_0_crtc_prepare
,
2803 .commit
= dce_v10_0_crtc_commit
,
2804 .load_lut
= dce_v10_0_crtc_load_lut
,
2805 .disable
= dce_v10_0_crtc_disable
,
2808 static int dce_v10_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2810 struct amdgpu_crtc
*amdgpu_crtc
;
2813 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2814 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2815 if (amdgpu_crtc
== NULL
)
2818 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v10_0_crtc_funcs
);
2820 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2821 amdgpu_crtc
->crtc_id
= index
;
2822 amdgpu_crtc
->pflip_queue
= create_singlethread_workqueue("amdgpu-pageflip-queue");
2823 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2825 amdgpu_crtc
->max_cursor_width
= 128;
2826 amdgpu_crtc
->max_cursor_height
= 128;
2827 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2828 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2830 for (i
= 0; i
< 256; i
++) {
2831 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
2832 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
2833 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
2836 switch (amdgpu_crtc
->crtc_id
) {
2839 amdgpu_crtc
->crtc_offset
= CRTC0_REGISTER_OFFSET
;
2842 amdgpu_crtc
->crtc_offset
= CRTC1_REGISTER_OFFSET
;
2845 amdgpu_crtc
->crtc_offset
= CRTC2_REGISTER_OFFSET
;
2848 amdgpu_crtc
->crtc_offset
= CRTC3_REGISTER_OFFSET
;
2851 amdgpu_crtc
->crtc_offset
= CRTC4_REGISTER_OFFSET
;
2854 amdgpu_crtc
->crtc_offset
= CRTC5_REGISTER_OFFSET
;
2858 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2859 amdgpu_crtc
->adjusted_clock
= 0;
2860 amdgpu_crtc
->encoder
= NULL
;
2861 amdgpu_crtc
->connector
= NULL
;
2862 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v10_0_crtc_helper_funcs
);
2867 static int dce_v10_0_early_init(void *handle
)
2869 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2871 adev
->audio_endpt_rreg
= &dce_v10_0_audio_endpt_rreg
;
2872 adev
->audio_endpt_wreg
= &dce_v10_0_audio_endpt_wreg
;
2874 dce_v10_0_set_display_funcs(adev
);
2875 dce_v10_0_set_irq_funcs(adev
);
2877 switch (adev
->asic_type
) {
2879 adev
->mode_info
.num_crtc
= 6; /* XXX 7??? */
2880 adev
->mode_info
.num_hpd
= 6;
2881 adev
->mode_info
.num_dig
= 7;
2884 /* FIXME: not supported yet */
2891 static int dce_v10_0_sw_init(void *handle
)
2894 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2896 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2897 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
2902 for (i
= 8; i
< 20; i
+= 2) {
2903 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
2909 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
2913 adev
->mode_info
.mode_config_initialized
= true;
2915 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2917 adev
->ddev
->mode_config
.max_width
= 16384;
2918 adev
->ddev
->mode_config
.max_height
= 16384;
2920 adev
->ddev
->mode_config
.preferred_depth
= 24;
2921 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2923 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
2925 r
= amdgpu_modeset_create_props(adev
);
2929 adev
->ddev
->mode_config
.max_width
= 16384;
2930 adev
->ddev
->mode_config
.max_height
= 16384;
2932 /* allocate crtcs */
2933 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2934 r
= dce_v10_0_crtc_init(adev
, i
);
2939 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2940 amdgpu_print_display_setup(adev
->ddev
);
2945 dce_v10_0_afmt_init(adev
);
2947 r
= dce_v10_0_audio_init(adev
);
2951 drm_kms_helper_poll_init(adev
->ddev
);
2956 static int dce_v10_0_sw_fini(void *handle
)
2958 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2960 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2962 drm_kms_helper_poll_fini(adev
->ddev
);
2964 dce_v10_0_audio_fini(adev
);
2966 dce_v10_0_afmt_fini(adev
);
2968 drm_mode_config_cleanup(adev
->ddev
);
2969 adev
->mode_info
.mode_config_initialized
= false;
2974 static int dce_v10_0_hw_init(void *handle
)
2977 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2979 dce_v10_0_init_golden_registers(adev
);
2981 /* init dig PHYs, disp eng pll */
2982 amdgpu_atombios_encoder_init_dig(adev
);
2983 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
2985 /* initialize hpd */
2986 dce_v10_0_hpd_init(adev
);
2988 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2989 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2995 static int dce_v10_0_hw_fini(void *handle
)
2998 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3000 dce_v10_0_hpd_fini(adev
);
3002 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
3003 dce_v10_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3009 static int dce_v10_0_suspend(void *handle
)
3011 struct drm_connector
*connector
;
3012 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3014 drm_kms_helper_poll_disable(adev
->ddev
);
3016 /* turn off display hw */
3017 list_for_each_entry(connector
, &adev
->ddev
->mode_config
.connector_list
, head
) {
3018 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_OFF
);
3021 amdgpu_atombios_scratch_regs_save(adev
);
3023 dce_v10_0_hpd_fini(adev
);
3028 static int dce_v10_0_resume(void *handle
)
3030 struct drm_connector
*connector
;
3031 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3033 dce_v10_0_init_golden_registers(adev
);
3035 amdgpu_atombios_scratch_regs_restore(adev
);
3037 /* init dig PHYs, disp eng pll */
3038 amdgpu_atombios_encoder_init_dig(adev
);
3039 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
3040 /* turn on the BL */
3041 if (adev
->mode_info
.bl_encoder
) {
3042 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3043 adev
->mode_info
.bl_encoder
);
3044 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3048 /* initialize hpd */
3049 dce_v10_0_hpd_init(adev
);
3051 /* blat the mode back in */
3052 drm_helper_resume_force_mode(adev
->ddev
);
3053 /* turn on display hw */
3054 list_for_each_entry(connector
, &adev
->ddev
->mode_config
.connector_list
, head
) {
3055 drm_helper_connector_dpms(connector
, DRM_MODE_DPMS_ON
);
3058 drm_kms_helper_poll_enable(adev
->ddev
);
3063 static bool dce_v10_0_is_idle(void *handle
)
3068 static int dce_v10_0_wait_for_idle(void *handle
)
3073 static void dce_v10_0_print_status(void *handle
)
3075 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3077 dev_info(adev
->dev
, "DCE 10.x registers\n");
3081 static int dce_v10_0_soft_reset(void *handle
)
3083 u32 srbm_soft_reset
= 0, tmp
;
3084 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3086 if (dce_v10_0_is_display_hung(adev
))
3087 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3089 if (srbm_soft_reset
) {
3090 dce_v10_0_print_status((void *)adev
);
3092 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3093 tmp
|= srbm_soft_reset
;
3094 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3095 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3096 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3100 tmp
&= ~srbm_soft_reset
;
3101 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3102 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3104 /* Wait a little for things to settle down */
3106 dce_v10_0_print_status((void *)adev
);
3111 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3113 enum amdgpu_interrupt_state state
)
3115 u32 lb_interrupt_mask
;
3117 if (crtc
>= adev
->mode_info
.num_crtc
) {
3118 DRM_DEBUG("invalid crtc %d\n", crtc
);
3123 case AMDGPU_IRQ_STATE_DISABLE
:
3124 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3125 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3126 VBLANK_INTERRUPT_MASK
, 0);
3127 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3129 case AMDGPU_IRQ_STATE_ENABLE
:
3130 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3131 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3132 VBLANK_INTERRUPT_MASK
, 1);
3133 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3140 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3142 enum amdgpu_interrupt_state state
)
3144 u32 lb_interrupt_mask
;
3146 if (crtc
>= adev
->mode_info
.num_crtc
) {
3147 DRM_DEBUG("invalid crtc %d\n", crtc
);
3152 case AMDGPU_IRQ_STATE_DISABLE
:
3153 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3154 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3155 VLINE_INTERRUPT_MASK
, 0);
3156 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3158 case AMDGPU_IRQ_STATE_ENABLE
:
3159 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
]);
3160 lb_interrupt_mask
= REG_SET_FIELD(lb_interrupt_mask
, LB_INTERRUPT_MASK
,
3161 VLINE_INTERRUPT_MASK
, 1);
3162 WREG32(mmLB_INTERRUPT_MASK
+ crtc_offsets
[crtc
], lb_interrupt_mask
);
3169 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device
*adev
,
3170 struct amdgpu_irq_src
*source
,
3172 enum amdgpu_interrupt_state state
)
3176 if (hpd
>= adev
->mode_info
.num_hpd
) {
3177 DRM_DEBUG("invalid hdp %d\n", hpd
);
3182 case AMDGPU_IRQ_STATE_DISABLE
:
3183 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3184 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 0);
3185 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3187 case AMDGPU_IRQ_STATE_ENABLE
:
3188 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3189 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_EN
, 1);
3190 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3199 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device
*adev
,
3200 struct amdgpu_irq_src
*source
,
3202 enum amdgpu_interrupt_state state
)
3205 case AMDGPU_CRTC_IRQ_VBLANK1
:
3206 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3208 case AMDGPU_CRTC_IRQ_VBLANK2
:
3209 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3211 case AMDGPU_CRTC_IRQ_VBLANK3
:
3212 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3214 case AMDGPU_CRTC_IRQ_VBLANK4
:
3215 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3217 case AMDGPU_CRTC_IRQ_VBLANK5
:
3218 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3220 case AMDGPU_CRTC_IRQ_VBLANK6
:
3221 dce_v10_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3223 case AMDGPU_CRTC_IRQ_VLINE1
:
3224 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3226 case AMDGPU_CRTC_IRQ_VLINE2
:
3227 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3229 case AMDGPU_CRTC_IRQ_VLINE3
:
3230 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3232 case AMDGPU_CRTC_IRQ_VLINE4
:
3233 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3235 case AMDGPU_CRTC_IRQ_VLINE5
:
3236 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3238 case AMDGPU_CRTC_IRQ_VLINE6
:
3239 dce_v10_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3247 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device
*adev
,
3248 struct amdgpu_irq_src
*src
,
3250 enum amdgpu_interrupt_state state
)
3253 /* now deal with page flip IRQ */
3255 case AMDGPU_PAGEFLIP_IRQ_D1
:
3256 reg_block
= CRTC0_REGISTER_OFFSET
;
3258 case AMDGPU_PAGEFLIP_IRQ_D2
:
3259 reg_block
= CRTC1_REGISTER_OFFSET
;
3261 case AMDGPU_PAGEFLIP_IRQ_D3
:
3262 reg_block
= CRTC2_REGISTER_OFFSET
;
3264 case AMDGPU_PAGEFLIP_IRQ_D4
:
3265 reg_block
= CRTC3_REGISTER_OFFSET
;
3267 case AMDGPU_PAGEFLIP_IRQ_D5
:
3268 reg_block
= CRTC4_REGISTER_OFFSET
;
3270 case AMDGPU_PAGEFLIP_IRQ_D6
:
3271 reg_block
= CRTC5_REGISTER_OFFSET
;
3274 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3278 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ reg_block
);
3279 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3280 WREG32(mmGRPH_INTERRUPT_CONTROL
+ reg_block
, reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3282 WREG32(mmGRPH_INTERRUPT_CONTROL
+ reg_block
, reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3287 static int dce_v10_0_pageflip_irq(struct amdgpu_device
*adev
,
3288 struct amdgpu_irq_src
*source
,
3289 struct amdgpu_iv_entry
*entry
)
3292 unsigned long flags
;
3294 struct amdgpu_crtc
*amdgpu_crtc
;
3295 struct amdgpu_flip_work
*works
;
3297 crtc_id
= (entry
->src_id
- 8) >> 1;
3298 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3300 /* ack the interrupt */
3302 case AMDGPU_PAGEFLIP_IRQ_D1
:
3303 reg_block
= CRTC0_REGISTER_OFFSET
;
3305 case AMDGPU_PAGEFLIP_IRQ_D2
:
3306 reg_block
= CRTC1_REGISTER_OFFSET
;
3308 case AMDGPU_PAGEFLIP_IRQ_D3
:
3309 reg_block
= CRTC2_REGISTER_OFFSET
;
3311 case AMDGPU_PAGEFLIP_IRQ_D4
:
3312 reg_block
= CRTC3_REGISTER_OFFSET
;
3314 case AMDGPU_PAGEFLIP_IRQ_D5
:
3315 reg_block
= CRTC4_REGISTER_OFFSET
;
3317 case AMDGPU_PAGEFLIP_IRQ_D6
:
3318 reg_block
= CRTC5_REGISTER_OFFSET
;
3321 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3325 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ reg_block
) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3326 WREG32(mmGRPH_INTERRUPT_STATUS
+ reg_block
, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3328 /* IRQ could occur when in initial stage */
3329 if (amdgpu_crtc
== NULL
)
3332 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3333 works
= amdgpu_crtc
->pflip_works
;
3334 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
) {
3335 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3336 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3337 amdgpu_crtc
->pflip_status
,
3338 AMDGPU_FLIP_SUBMITTED
);
3339 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3343 /* page flip completed. clean up */
3344 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3345 amdgpu_crtc
->pflip_works
= NULL
;
3347 /* wakeup usersapce */
3349 drm_send_vblank_event(adev
->ddev
, crtc_id
, works
->event
);
3351 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3353 drm_vblank_put(adev
->ddev
, amdgpu_crtc
->crtc_id
);
3354 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, crtc_id
);
3355 queue_work(amdgpu_crtc
->pflip_queue
, &works
->unpin_work
);
3360 static void dce_v10_0_hpd_int_ack(struct amdgpu_device
*adev
,
3365 if (hpd
>= adev
->mode_info
.num_hpd
) {
3366 DRM_DEBUG("invalid hdp %d\n", hpd
);
3370 tmp
= RREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
]);
3371 tmp
= REG_SET_FIELD(tmp
, DC_HPD_INT_CONTROL
, DC_HPD_INT_ACK
, 1);
3372 WREG32(mmDC_HPD_INT_CONTROL
+ hpd_offsets
[hpd
], tmp
);
3375 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device
*adev
,
3380 if (crtc
>= adev
->mode_info
.num_crtc
) {
3381 DRM_DEBUG("invalid crtc %d\n", crtc
);
3385 tmp
= RREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
]);
3386 tmp
= REG_SET_FIELD(tmp
, LB_VBLANK_STATUS
, VBLANK_ACK
, 1);
3387 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], tmp
);
3390 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device
*adev
,
3395 if (crtc
>= adev
->mode_info
.num_crtc
) {
3396 DRM_DEBUG("invalid crtc %d\n", crtc
);
3400 tmp
= RREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
]);
3401 tmp
= REG_SET_FIELD(tmp
, LB_VLINE_STATUS
, VLINE_ACK
, 1);
3402 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], tmp
);
3405 static int dce_v10_0_crtc_irq(struct amdgpu_device
*adev
,
3406 struct amdgpu_irq_src
*source
,
3407 struct amdgpu_iv_entry
*entry
)
3409 unsigned crtc
= entry
->src_id
- 1;
3410 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3411 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3413 switch (entry
->src_data
) {
3414 case 0: /* vblank */
3415 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
) {
3416 dce_v10_0_crtc_vblank_int_ack(adev
, crtc
);
3417 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3418 drm_handle_vblank(adev
->ddev
, crtc
);
3420 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3424 if (disp_int
& interrupt_status_offsets
[crtc
].vline
) {
3425 dce_v10_0_crtc_vline_int_ack(adev
, crtc
);
3426 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3430 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3437 static int dce_v10_0_hpd_irq(struct amdgpu_device
*adev
,
3438 struct amdgpu_irq_src
*source
,
3439 struct amdgpu_iv_entry
*entry
)
3441 uint32_t disp_int
, mask
;
3444 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3445 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3449 hpd
= entry
->src_data
;
3450 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3451 mask
= interrupt_status_offsets
[hpd
].hpd
;
3453 if (disp_int
& mask
) {
3454 dce_v10_0_hpd_int_ack(adev
, hpd
);
3455 schedule_work(&adev
->hotplug_work
);
3456 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3462 static int dce_v10_0_set_clockgating_state(void *handle
,
3463 enum amd_clockgating_state state
)
3468 static int dce_v10_0_set_powergating_state(void *handle
,
3469 enum amd_powergating_state state
)
3474 const struct amd_ip_funcs dce_v10_0_ip_funcs
= {
3475 .early_init
= dce_v10_0_early_init
,
3477 .sw_init
= dce_v10_0_sw_init
,
3478 .sw_fini
= dce_v10_0_sw_fini
,
3479 .hw_init
= dce_v10_0_hw_init
,
3480 .hw_fini
= dce_v10_0_hw_fini
,
3481 .suspend
= dce_v10_0_suspend
,
3482 .resume
= dce_v10_0_resume
,
3483 .is_idle
= dce_v10_0_is_idle
,
3484 .wait_for_idle
= dce_v10_0_wait_for_idle
,
3485 .soft_reset
= dce_v10_0_soft_reset
,
3486 .print_status
= dce_v10_0_print_status
,
3487 .set_clockgating_state
= dce_v10_0_set_clockgating_state
,
3488 .set_powergating_state
= dce_v10_0_set_powergating_state
,
3492 dce_v10_0_encoder_mode_set(struct drm_encoder
*encoder
,
3493 struct drm_display_mode
*mode
,
3494 struct drm_display_mode
*adjusted_mode
)
3496 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3498 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3500 /* need to call this here rather than in prepare() since we need some crtc info */
3501 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3503 /* set scaler clears this on some chips */
3504 dce_v10_0_set_interleave(encoder
->crtc
, mode
);
3506 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3507 dce_v10_0_afmt_enable(encoder
, true);
3508 dce_v10_0_afmt_setmode(encoder
, adjusted_mode
);
3512 static void dce_v10_0_encoder_prepare(struct drm_encoder
*encoder
)
3514 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3515 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3516 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3518 if ((amdgpu_encoder
->active_device
&
3519 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3520 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3521 ENCODER_OBJECT_ID_NONE
)) {
3522 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3524 dig
->dig_encoder
= dce_v10_0_pick_dig_encoder(encoder
);
3525 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3526 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3530 amdgpu_atombios_scratch_regs_lock(adev
, true);
3533 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3535 /* select the clock/data port if it uses a router */
3536 if (amdgpu_connector
->router
.cd_valid
)
3537 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3539 /* turn eDP panel on for mode set */
3540 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3541 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3542 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3545 /* this is needed for the pll/ss setup to work correctly in some cases */
3546 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3547 /* set up the FMT blocks */
3548 dce_v10_0_program_fmt(encoder
);
3551 static void dce_v10_0_encoder_commit(struct drm_encoder
*encoder
)
3553 struct drm_device
*dev
= encoder
->dev
;
3554 struct amdgpu_device
*adev
= dev
->dev_private
;
3556 /* need to call this here as we need the crtc set up */
3557 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3558 amdgpu_atombios_scratch_regs_lock(adev
, false);
3561 static void dce_v10_0_encoder_disable(struct drm_encoder
*encoder
)
3563 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3564 struct amdgpu_encoder_atom_dig
*dig
;
3566 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3568 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3569 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3570 dce_v10_0_afmt_enable(encoder
, false);
3571 dig
= amdgpu_encoder
->enc_priv
;
3572 dig
->dig_encoder
= -1;
3574 amdgpu_encoder
->active_device
= 0;
3577 /* these are handled by the primary encoders */
3578 static void dce_v10_0_ext_prepare(struct drm_encoder
*encoder
)
3583 static void dce_v10_0_ext_commit(struct drm_encoder
*encoder
)
3589 dce_v10_0_ext_mode_set(struct drm_encoder
*encoder
,
3590 struct drm_display_mode
*mode
,
3591 struct drm_display_mode
*adjusted_mode
)
3596 static void dce_v10_0_ext_disable(struct drm_encoder
*encoder
)
3602 dce_v10_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3607 static bool dce_v10_0_ext_mode_fixup(struct drm_encoder
*encoder
,
3608 const struct drm_display_mode
*mode
,
3609 struct drm_display_mode
*adjusted_mode
)
3614 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs
= {
3615 .dpms
= dce_v10_0_ext_dpms
,
3616 .mode_fixup
= dce_v10_0_ext_mode_fixup
,
3617 .prepare
= dce_v10_0_ext_prepare
,
3618 .mode_set
= dce_v10_0_ext_mode_set
,
3619 .commit
= dce_v10_0_ext_commit
,
3620 .disable
= dce_v10_0_ext_disable
,
3621 /* no detect for TMDS/LVDS yet */
3624 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs
= {
3625 .dpms
= amdgpu_atombios_encoder_dpms
,
3626 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3627 .prepare
= dce_v10_0_encoder_prepare
,
3628 .mode_set
= dce_v10_0_encoder_mode_set
,
3629 .commit
= dce_v10_0_encoder_commit
,
3630 .disable
= dce_v10_0_encoder_disable
,
3631 .detect
= amdgpu_atombios_encoder_dig_detect
,
3634 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs
= {
3635 .dpms
= amdgpu_atombios_encoder_dpms
,
3636 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3637 .prepare
= dce_v10_0_encoder_prepare
,
3638 .mode_set
= dce_v10_0_encoder_mode_set
,
3639 .commit
= dce_v10_0_encoder_commit
,
3640 .detect
= amdgpu_atombios_encoder_dac_detect
,
3643 static void dce_v10_0_encoder_destroy(struct drm_encoder
*encoder
)
3645 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3646 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3647 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3648 kfree(amdgpu_encoder
->enc_priv
);
3649 drm_encoder_cleanup(encoder
);
3650 kfree(amdgpu_encoder
);
3653 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs
= {
3654 .destroy
= dce_v10_0_encoder_destroy
,
3657 static void dce_v10_0_encoder_add(struct amdgpu_device
*adev
,
3658 uint32_t encoder_enum
,
3659 uint32_t supported_device
,
3662 struct drm_device
*dev
= adev
->ddev
;
3663 struct drm_encoder
*encoder
;
3664 struct amdgpu_encoder
*amdgpu_encoder
;
3666 /* see if we already added it */
3667 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3668 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3669 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3670 amdgpu_encoder
->devices
|= supported_device
;
3677 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3678 if (!amdgpu_encoder
)
3681 encoder
= &amdgpu_encoder
->base
;
3682 switch (adev
->mode_info
.num_crtc
) {
3684 encoder
->possible_crtcs
= 0x1;
3688 encoder
->possible_crtcs
= 0x3;
3691 encoder
->possible_crtcs
= 0xf;
3694 encoder
->possible_crtcs
= 0x3f;
3698 amdgpu_encoder
->enc_priv
= NULL
;
3700 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3701 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3702 amdgpu_encoder
->devices
= supported_device
;
3703 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3704 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3705 amdgpu_encoder
->is_ext_encoder
= false;
3706 amdgpu_encoder
->caps
= caps
;
3708 switch (amdgpu_encoder
->encoder_id
) {
3709 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3710 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3711 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3712 DRM_MODE_ENCODER_DAC
);
3713 drm_encoder_helper_add(encoder
, &dce_v10_0_dac_helper_funcs
);
3715 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3716 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3717 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3718 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3719 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3720 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3721 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3722 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3723 DRM_MODE_ENCODER_LVDS
);
3724 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3725 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3726 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3727 DRM_MODE_ENCODER_DAC
);
3728 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3730 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3731 DRM_MODE_ENCODER_TMDS
);
3732 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3734 drm_encoder_helper_add(encoder
, &dce_v10_0_dig_helper_funcs
);
3736 case ENCODER_OBJECT_ID_SI170B
:
3737 case ENCODER_OBJECT_ID_CH7303
:
3738 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3739 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3740 case ENCODER_OBJECT_ID_TITFP513
:
3741 case ENCODER_OBJECT_ID_VT1623
:
3742 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3743 case ENCODER_OBJECT_ID_TRAVIS
:
3744 case ENCODER_OBJECT_ID_NUTMEG
:
3745 /* these are handled by the primary encoders */
3746 amdgpu_encoder
->is_ext_encoder
= true;
3747 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3748 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3749 DRM_MODE_ENCODER_LVDS
);
3750 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3751 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3752 DRM_MODE_ENCODER_DAC
);
3754 drm_encoder_init(dev
, encoder
, &dce_v10_0_encoder_funcs
,
3755 DRM_MODE_ENCODER_TMDS
);
3756 drm_encoder_helper_add(encoder
, &dce_v10_0_ext_helper_funcs
);
3761 static const struct amdgpu_display_funcs dce_v10_0_display_funcs
= {
3762 .set_vga_render_state
= &dce_v10_0_set_vga_render_state
,
3763 .bandwidth_update
= &dce_v10_0_bandwidth_update
,
3764 .vblank_get_counter
= &dce_v10_0_vblank_get_counter
,
3765 .vblank_wait
= &dce_v10_0_vblank_wait
,
3766 .is_display_hung
= &dce_v10_0_is_display_hung
,
3767 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3768 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3769 .hpd_sense
= &dce_v10_0_hpd_sense
,
3770 .hpd_set_polarity
= &dce_v10_0_hpd_set_polarity
,
3771 .hpd_get_gpio_reg
= &dce_v10_0_hpd_get_gpio_reg
,
3772 .page_flip
= &dce_v10_0_page_flip
,
3773 .page_flip_get_scanoutpos
= &dce_v10_0_crtc_get_scanoutpos
,
3774 .add_encoder
= &dce_v10_0_encoder_add
,
3775 .add_connector
= &amdgpu_connector_add
,
3776 .stop_mc_access
= &dce_v10_0_stop_mc_access
,
3777 .resume_mc_access
= &dce_v10_0_resume_mc_access
,
3780 static void dce_v10_0_set_display_funcs(struct amdgpu_device
*adev
)
3782 if (adev
->mode_info
.funcs
== NULL
)
3783 adev
->mode_info
.funcs
= &dce_v10_0_display_funcs
;
3786 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs
= {
3787 .set
= dce_v10_0_set_crtc_irq_state
,
3788 .process
= dce_v10_0_crtc_irq
,
3791 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs
= {
3792 .set
= dce_v10_0_set_pageflip_irq_state
,
3793 .process
= dce_v10_0_pageflip_irq
,
3796 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs
= {
3797 .set
= dce_v10_0_set_hpd_irq_state
,
3798 .process
= dce_v10_0_hpd_irq
,
3801 static void dce_v10_0_set_irq_funcs(struct amdgpu_device
*adev
)
3803 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3804 adev
->crtc_irq
.funcs
= &dce_v10_0_crtc_irq_funcs
;
3806 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3807 adev
->pageflip_irq
.funcs
= &dce_v10_0_pageflip_irq_funcs
;
3809 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3810 adev
->hpd_irq
.funcs
= &dce_v10_0_hpd_irq_funcs
;