2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include "amdgpu_pm.h"
26 #include "amdgpu_i2c.h"
29 #include "amdgpu_atombios.h"
30 #include "atombios_crtc.h"
31 #include "atombios_encoders.h"
32 #include "amdgpu_pll.h"
33 #include "amdgpu_connectors.h"
35 #include "dce/dce_8_0_d.h"
36 #include "dce/dce_8_0_sh_mask.h"
38 #include "gca/gfx_7_2_enum.h"
40 #include "gmc/gmc_7_1_d.h"
41 #include "gmc/gmc_7_1_sh_mask.h"
43 #include "oss/oss_2_0_d.h"
44 #include "oss/oss_2_0_sh_mask.h"
46 static void dce_v8_0_set_display_funcs(struct amdgpu_device
*adev
);
47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device
*adev
);
49 static const u32 crtc_offsets
[6] =
51 CRTC0_REGISTER_OFFSET
,
52 CRTC1_REGISTER_OFFSET
,
53 CRTC2_REGISTER_OFFSET
,
54 CRTC3_REGISTER_OFFSET
,
55 CRTC4_REGISTER_OFFSET
,
59 static const uint32_t dig_offsets
[] = {
60 CRTC0_REGISTER_OFFSET
,
61 CRTC1_REGISTER_OFFSET
,
62 CRTC2_REGISTER_OFFSET
,
63 CRTC3_REGISTER_OFFSET
,
64 CRTC4_REGISTER_OFFSET
,
65 CRTC5_REGISTER_OFFSET
,
66 (0x13830 - 0x7030) >> 2,
75 } interrupt_status_offsets
[6] = { {
76 .reg
= mmDISP_INTERRUPT_STATUS
,
77 .vblank
= DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK
,
78 .vline
= DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK
,
79 .hpd
= DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
81 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE
,
82 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK
,
83 .vline
= DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK
,
84 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
86 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE2
,
87 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK
,
88 .vline
= DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK
,
89 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
91 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE3
,
92 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK
,
93 .vline
= DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK
,
94 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
96 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE4
,
97 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK
,
98 .vline
= DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK
,
99 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
101 .reg
= mmDISP_INTERRUPT_STATUS_CONTINUE5
,
102 .vblank
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK
,
103 .vline
= DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK
,
104 .hpd
= DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
107 static const uint32_t hpd_int_control_offsets
[6] = {
108 mmDC_HPD1_INT_CONTROL
,
109 mmDC_HPD2_INT_CONTROL
,
110 mmDC_HPD3_INT_CONTROL
,
111 mmDC_HPD4_INT_CONTROL
,
112 mmDC_HPD5_INT_CONTROL
,
113 mmDC_HPD6_INT_CONTROL
,
116 static u32
dce_v8_0_audio_endpt_rreg(struct amdgpu_device
*adev
,
117 u32 block_offset
, u32 reg
)
122 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
124 r
= RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
);
125 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device
*adev
,
131 u32 block_offset
, u32 reg
, u32 v
)
135 spin_lock_irqsave(&adev
->audio_endpt_idx_lock
, flags
);
136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX
+ block_offset
, reg
);
137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA
+ block_offset
, v
);
138 spin_unlock_irqrestore(&adev
->audio_endpt_idx_lock
, flags
);
141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device
*adev
, int crtc
)
143 if (RREG32(mmCRTC_STATUS
+ crtc_offsets
[crtc
]) &
144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK
)
150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device
*adev
, int crtc
)
154 pos1
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
155 pos2
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
164 * dce_v8_0_vblank_wait - vblank wait asic callback.
166 * @adev: amdgpu_device pointer
167 * @crtc: crtc to wait for vblank on
169 * Wait for vblank on the requested crtc (evergreen+).
171 static void dce_v8_0_vblank_wait(struct amdgpu_device
*adev
, int crtc
)
175 if (crtc
>= adev
->mode_info
.num_crtc
)
178 if (!(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[crtc
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
))
181 /* depending on when we hit vblank, we may be close to active; if so,
182 * wait for another frame.
184 while (dce_v8_0_is_in_vblank(adev
, crtc
)) {
185 if (i
++ % 100 == 0) {
186 if (!dce_v8_0_is_counter_moving(adev
, crtc
))
191 while (!dce_v8_0_is_in_vblank(adev
, crtc
)) {
192 if (i
++ % 100 == 0) {
193 if (!dce_v8_0_is_counter_moving(adev
, crtc
))
199 static u32
dce_v8_0_vblank_get_counter(struct amdgpu_device
*adev
, int crtc
)
201 if (crtc
>= adev
->mode_info
.num_crtc
)
204 return RREG32(mmCRTC_STATUS_FRAME_COUNT
+ crtc_offsets
[crtc
]);
207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device
*adev
)
211 /* Enable pflip interrupts */
212 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
213 amdgpu_irq_get(adev
, &adev
->pageflip_irq
, i
);
216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device
*adev
)
220 /* Disable pflip interrupts */
221 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++)
222 amdgpu_irq_put(adev
, &adev
->pageflip_irq
, i
);
226 * dce_v8_0_page_flip - pageflip callback.
228 * @adev: amdgpu_device pointer
229 * @crtc_id: crtc to cleanup pageflip on
230 * @crtc_base: new address of the crtc (GPU MC address)
232 * Triggers the actual pageflip by updating the primary
233 * surface base address.
235 static void dce_v8_0_page_flip(struct amdgpu_device
*adev
,
236 int crtc_id
, u64 crtc_base
, bool async
)
238 struct amdgpu_crtc
*amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
240 /* flip at hsync for async, default is vsync */
241 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, async
?
242 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK
: 0);
243 /* update the primary scanout addresses */
244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
245 upper_32_bits(crtc_base
));
246 /* writing to the low address triggers the update */
247 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
248 lower_32_bits(crtc_base
));
250 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
);
253 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device
*adev
, int crtc
,
254 u32
*vbl
, u32
*position
)
256 if ((crtc
< 0) || (crtc
>= adev
->mode_info
.num_crtc
))
259 *vbl
= RREG32(mmCRTC_V_BLANK_START_END
+ crtc_offsets
[crtc
]);
260 *position
= RREG32(mmCRTC_STATUS_POSITION
+ crtc_offsets
[crtc
]);
266 * dce_v8_0_hpd_sense - hpd sense callback.
268 * @adev: amdgpu_device pointer
269 * @hpd: hpd (hotplug detect) pin
271 * Checks if a digital monitor is connected (evergreen+).
272 * Returns true if connected, false if not connected.
274 static bool dce_v8_0_hpd_sense(struct amdgpu_device
*adev
,
275 enum amdgpu_hpd_id hpd
)
277 bool connected
= false;
281 if (RREG32(mmDC_HPD1_INT_STATUS
) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK
)
285 if (RREG32(mmDC_HPD2_INT_STATUS
) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK
)
289 if (RREG32(mmDC_HPD3_INT_STATUS
) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK
)
293 if (RREG32(mmDC_HPD4_INT_STATUS
) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK
)
297 if (RREG32(mmDC_HPD5_INT_STATUS
) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK
)
301 if (RREG32(mmDC_HPD6_INT_STATUS
) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK
)
312 * dce_v8_0_hpd_set_polarity - hpd set polarity callback.
314 * @adev: amdgpu_device pointer
315 * @hpd: hpd (hotplug detect) pin
317 * Set the polarity of the hpd pin (evergreen+).
319 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device
*adev
,
320 enum amdgpu_hpd_id hpd
)
323 bool connected
= dce_v8_0_hpd_sense(adev
, hpd
);
327 tmp
= RREG32(mmDC_HPD1_INT_CONTROL
);
329 tmp
&= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
;
331 tmp
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK
;
332 WREG32(mmDC_HPD1_INT_CONTROL
, tmp
);
335 tmp
= RREG32(mmDC_HPD2_INT_CONTROL
);
337 tmp
&= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
;
339 tmp
|= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK
;
340 WREG32(mmDC_HPD2_INT_CONTROL
, tmp
);
343 tmp
= RREG32(mmDC_HPD3_INT_CONTROL
);
345 tmp
&= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
;
347 tmp
|= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK
;
348 WREG32(mmDC_HPD3_INT_CONTROL
, tmp
);
351 tmp
= RREG32(mmDC_HPD4_INT_CONTROL
);
353 tmp
&= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
;
355 tmp
|= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK
;
356 WREG32(mmDC_HPD4_INT_CONTROL
, tmp
);
359 tmp
= RREG32(mmDC_HPD5_INT_CONTROL
);
361 tmp
&= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
;
363 tmp
|= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK
;
364 WREG32(mmDC_HPD5_INT_CONTROL
, tmp
);
367 tmp
= RREG32(mmDC_HPD6_INT_CONTROL
);
369 tmp
&= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
;
371 tmp
|= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK
;
372 WREG32(mmDC_HPD6_INT_CONTROL
, tmp
);
380 * dce_v8_0_hpd_init - hpd setup callback.
382 * @adev: amdgpu_device pointer
384 * Setup the hpd pins used by the card (evergreen+).
385 * Enable the pin, set the polarity, and enable the hpd interrupts.
387 static void dce_v8_0_hpd_init(struct amdgpu_device
*adev
)
389 struct drm_device
*dev
= adev
->ddev
;
390 struct drm_connector
*connector
;
391 u32 tmp
= (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT
) |
392 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT
) |
393 DC_HPD1_CONTROL__DC_HPD1_EN_MASK
;
395 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
396 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
398 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
||
399 connector
->connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
400 /* don't try to enable hpd on eDP or LVDS avoid breaking the
401 * aux dp channel on imac and help (but not completely fix)
402 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
403 * also avoid interrupt storms during dpms.
407 switch (amdgpu_connector
->hpd
.hpd
) {
409 WREG32(mmDC_HPD1_CONTROL
, tmp
);
412 WREG32(mmDC_HPD2_CONTROL
, tmp
);
415 WREG32(mmDC_HPD3_CONTROL
, tmp
);
418 WREG32(mmDC_HPD4_CONTROL
, tmp
);
421 WREG32(mmDC_HPD5_CONTROL
, tmp
);
424 WREG32(mmDC_HPD6_CONTROL
, tmp
);
429 dce_v8_0_hpd_set_polarity(adev
, amdgpu_connector
->hpd
.hpd
);
430 amdgpu_irq_get(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
435 * dce_v8_0_hpd_fini - hpd tear down callback.
437 * @adev: amdgpu_device pointer
439 * Tear down the hpd pins used by the card (evergreen+).
440 * Disable the hpd interrupts.
442 static void dce_v8_0_hpd_fini(struct amdgpu_device
*adev
)
444 struct drm_device
*dev
= adev
->ddev
;
445 struct drm_connector
*connector
;
447 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
448 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
450 switch (amdgpu_connector
->hpd
.hpd
) {
452 WREG32(mmDC_HPD1_CONTROL
, 0);
455 WREG32(mmDC_HPD2_CONTROL
, 0);
458 WREG32(mmDC_HPD3_CONTROL
, 0);
461 WREG32(mmDC_HPD4_CONTROL
, 0);
464 WREG32(mmDC_HPD5_CONTROL
, 0);
467 WREG32(mmDC_HPD6_CONTROL
, 0);
472 amdgpu_irq_put(adev
, &adev
->hpd_irq
, amdgpu_connector
->hpd
.hpd
);
476 static u32
dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device
*adev
)
478 return mmDC_GPIO_HPD_A
;
481 static bool dce_v8_0_is_display_hung(struct amdgpu_device
*adev
)
487 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
488 if (RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK
) {
489 crtc_status
[i
] = RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
490 crtc_hung
|= (1 << i
);
494 for (j
= 0; j
< 10; j
++) {
495 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
496 if (crtc_hung
& (1 << i
)) {
497 tmp
= RREG32(mmCRTC_STATUS_HV_COUNT
+ crtc_offsets
[i
]);
498 if (tmp
!= crtc_status
[i
])
499 crtc_hung
&= ~(1 << i
);
510 static void dce_v8_0_stop_mc_access(struct amdgpu_device
*adev
,
511 struct amdgpu_mode_mc_save
*save
)
513 u32 crtc_enabled
, tmp
;
516 save
->vga_render_control
= RREG32(mmVGA_RENDER_CONTROL
);
517 save
->vga_hdp_control
= RREG32(mmVGA_HDP_CONTROL
);
519 /* disable VGA render */
520 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
521 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
522 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
524 /* blank the display controllers */
525 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
526 crtc_enabled
= REG_GET_FIELD(RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]),
527 CRTC_CONTROL
, CRTC_MASTER_EN
);
533 save
->crtc_enabled
[i
] = true;
534 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
535 if (REG_GET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
) == 0) {
536 amdgpu_display_vblank_wait(adev
, i
);
537 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
538 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 1);
539 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
540 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
542 /* wait for the next frame */
543 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
544 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
545 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
549 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
550 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
) == 0) {
551 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 1);
552 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
554 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
555 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
) == 0) {
556 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 1);
557 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
560 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
561 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
562 tmp
= RREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
]);
563 tmp
= REG_SET_FIELD(tmp
, CRTC_CONTROL
, CRTC_MASTER_EN
, 0);
564 WREG32(mmCRTC_CONTROL
+ crtc_offsets
[i
], tmp
);
565 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
566 save
->crtc_enabled
[i
] = false;
570 save
->crtc_enabled
[i
] = false;
575 static void dce_v8_0_resume_mc_access(struct amdgpu_device
*adev
,
576 struct amdgpu_mode_mc_save
*save
)
578 u32 tmp
, frame_count
;
581 /* update crtc base addresses */
582 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
583 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
584 upper_32_bits(adev
->mc
.vram_start
));
585 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ crtc_offsets
[i
],
586 upper_32_bits(adev
->mc
.vram_start
));
587 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
588 (u32
)adev
->mc
.vram_start
);
589 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ crtc_offsets
[i
],
590 (u32
)adev
->mc
.vram_start
);
592 if (save
->crtc_enabled
[i
]) {
593 tmp
= RREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
]);
594 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
) != 3) {
595 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_MODE
, MASTER_UPDATE_MODE
, 3);
596 WREG32(mmMASTER_UPDATE_MODE
+ crtc_offsets
[i
], tmp
);
598 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
599 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
)) {
600 tmp
= REG_SET_FIELD(tmp
, GRPH_UPDATE
, GRPH_UPDATE_LOCK
, 0);
601 WREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
], tmp
);
603 tmp
= RREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
]);
604 if (REG_GET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
)) {
605 tmp
= REG_SET_FIELD(tmp
, MASTER_UPDATE_LOCK
, MASTER_UPDATE_LOCK
, 0);
606 WREG32(mmMASTER_UPDATE_LOCK
+ crtc_offsets
[i
], tmp
);
608 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
609 tmp
= RREG32(mmGRPH_UPDATE
+ crtc_offsets
[i
]);
610 if (REG_GET_FIELD(tmp
, GRPH_UPDATE
, GRPH_SURFACE_UPDATE_PENDING
) == 0)
614 tmp
= RREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
]);
615 tmp
= REG_SET_FIELD(tmp
, CRTC_BLANK_CONTROL
, CRTC_BLANK_DATA_EN
, 0);
616 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 1);
617 WREG32(mmCRTC_BLANK_CONTROL
+ crtc_offsets
[i
], tmp
);
618 WREG32(mmCRTC_UPDATE_LOCK
+ crtc_offsets
[i
], 0);
619 /* wait for the next frame */
620 frame_count
= amdgpu_display_vblank_get_counter(adev
, i
);
621 for (j
= 0; j
< adev
->usec_timeout
; j
++) {
622 if (amdgpu_display_vblank_get_counter(adev
, i
) != frame_count
)
629 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH
, upper_32_bits(adev
->mc
.vram_start
));
630 WREG32(mmVGA_MEMORY_BASE_ADDRESS
, lower_32_bits(adev
->mc
.vram_start
));
632 /* Unlock vga access */
633 WREG32(mmVGA_HDP_CONTROL
, save
->vga_hdp_control
);
635 WREG32(mmVGA_RENDER_CONTROL
, save
->vga_render_control
);
638 static void dce_v8_0_set_vga_render_state(struct amdgpu_device
*adev
,
643 /* Lockout access through VGA aperture*/
644 tmp
= RREG32(mmVGA_HDP_CONTROL
);
646 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 0);
648 tmp
= REG_SET_FIELD(tmp
, VGA_HDP_CONTROL
, VGA_MEMORY_DISABLE
, 1);
649 WREG32(mmVGA_HDP_CONTROL
, tmp
);
651 /* disable VGA render */
652 tmp
= RREG32(mmVGA_RENDER_CONTROL
);
654 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 1);
656 tmp
= REG_SET_FIELD(tmp
, VGA_RENDER_CONTROL
, VGA_VSTATUS_CNTL
, 0);
657 WREG32(mmVGA_RENDER_CONTROL
, tmp
);
660 static void dce_v8_0_program_fmt(struct drm_encoder
*encoder
)
662 struct drm_device
*dev
= encoder
->dev
;
663 struct amdgpu_device
*adev
= dev
->dev_private
;
664 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
665 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
666 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
669 enum amdgpu_connector_dither dither
= AMDGPU_FMT_DITHER_DISABLE
;
672 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
673 bpc
= amdgpu_connector_get_monitor_bpc(connector
);
674 dither
= amdgpu_connector
->dither
;
677 /* LVDS/eDP FMT is set up by atom */
678 if (amdgpu_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
681 /* not needed for analog */
682 if ((amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
) ||
683 (amdgpu_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
))
691 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
692 /* XXX sort out optimal dither settings */
693 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
694 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
695 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
696 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
698 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
699 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
702 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
703 /* XXX sort out optimal dither settings */
704 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
705 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
706 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK
|
707 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
708 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
710 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
711 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
714 if (dither
== AMDGPU_FMT_DITHER_ENABLE
)
715 /* XXX sort out optimal dither settings */
716 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK
|
717 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK
|
718 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK
|
719 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK
|
720 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT
));
722 tmp
|= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK
|
723 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT
));
730 WREG32(mmFMT_BIT_DEPTH_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
734 /* display watermark setup */
736 * dce_v8_0_line_buffer_adjust - Set up the line buffer
738 * @adev: amdgpu_device pointer
739 * @amdgpu_crtc: the selected display controller
740 * @mode: the current display mode on the selected display
743 * Setup up the line buffer allocation for
744 * the selected display controller (CIK).
745 * Returns the line buffer size in pixels.
747 static u32
dce_v8_0_line_buffer_adjust(struct amdgpu_device
*adev
,
748 struct amdgpu_crtc
*amdgpu_crtc
,
749 struct drm_display_mode
*mode
)
751 u32 tmp
, buffer_alloc
, i
;
752 u32 pipe_offset
= amdgpu_crtc
->crtc_id
* 0x8;
755 * There are 6 line buffers, one for each display controllers.
756 * There are 3 partitions per LB. Select the number of partitions
757 * to enable based on the display width. For display widths larger
758 * than 4096, you need use to use 2 display controllers and combine
759 * them using the stereo blender.
761 if (amdgpu_crtc
->base
.enabled
&& mode
) {
762 if (mode
->crtc_hdisplay
< 1920) {
765 } else if (mode
->crtc_hdisplay
< 2560) {
768 } else if (mode
->crtc_hdisplay
< 4096) {
770 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
772 DRM_DEBUG_KMS("Mode too big for LB!\n");
774 buffer_alloc
= (adev
->flags
& AMD_IS_APU
) ? 2 : 4;
781 WREG32(mmLB_MEMORY_CTRL
+ amdgpu_crtc
->crtc_offset
,
782 (tmp
<< LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT
) |
783 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT
));
785 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
,
786 (buffer_alloc
<< PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT
));
787 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
788 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL
+ pipe_offset
) &
789 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK
)
794 if (amdgpu_crtc
->base
.enabled
&& mode
) {
806 /* controller not enabled, so no lb used */
811 * cik_get_number_of_dram_channels - get the number of dram channels
813 * @adev: amdgpu_device pointer
815 * Look up the number of video ram channels (CIK).
816 * Used for display watermark bandwidth calculations
817 * Returns the number of dram channels
819 static u32
cik_get_number_of_dram_channels(struct amdgpu_device
*adev
)
821 u32 tmp
= RREG32(mmMC_SHARED_CHMAP
);
823 switch ((tmp
& MC_SHARED_CHMAP__NOOFCHAN_MASK
) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT
) {
846 struct dce8_wm_params
{
847 u32 dram_channels
; /* number of dram channels */
848 u32 yclk
; /* bandwidth per dram data pin in kHz */
849 u32 sclk
; /* engine clock in kHz */
850 u32 disp_clk
; /* display clock in kHz */
851 u32 src_width
; /* viewport width */
852 u32 active_time
; /* active display time in ns */
853 u32 blank_time
; /* blank time in ns */
854 bool interlaced
; /* mode is interlaced */
855 fixed20_12 vsc
; /* vertical scale ratio */
856 u32 num_heads
; /* number of active crtcs */
857 u32 bytes_per_pixel
; /* bytes per pixel display + overlay */
858 u32 lb_size
; /* line buffer allocated to pipe */
859 u32 vtaps
; /* vertical scaler taps */
863 * dce_v8_0_dram_bandwidth - get the dram bandwidth
865 * @wm: watermark calculation data
867 * Calculate the raw dram bandwidth (CIK).
868 * Used for display watermark bandwidth calculations
869 * Returns the dram bandwidth in MBytes/s
871 static u32
dce_v8_0_dram_bandwidth(struct dce8_wm_params
*wm
)
873 /* Calculate raw DRAM Bandwidth */
874 fixed20_12 dram_efficiency
; /* 0.7 */
875 fixed20_12 yclk
, dram_channels
, bandwidth
;
878 a
.full
= dfixed_const(1000);
879 yclk
.full
= dfixed_const(wm
->yclk
);
880 yclk
.full
= dfixed_div(yclk
, a
);
881 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
882 a
.full
= dfixed_const(10);
883 dram_efficiency
.full
= dfixed_const(7);
884 dram_efficiency
.full
= dfixed_div(dram_efficiency
, a
);
885 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
886 bandwidth
.full
= dfixed_mul(bandwidth
, dram_efficiency
);
888 return dfixed_trunc(bandwidth
);
892 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display
894 * @wm: watermark calculation data
896 * Calculate the dram bandwidth used for display (CIK).
897 * Used for display watermark bandwidth calculations
898 * Returns the dram bandwidth for display in MBytes/s
900 static u32
dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params
*wm
)
902 /* Calculate DRAM Bandwidth and the part allocated to display. */
903 fixed20_12 disp_dram_allocation
; /* 0.3 to 0.7 */
904 fixed20_12 yclk
, dram_channels
, bandwidth
;
907 a
.full
= dfixed_const(1000);
908 yclk
.full
= dfixed_const(wm
->yclk
);
909 yclk
.full
= dfixed_div(yclk
, a
);
910 dram_channels
.full
= dfixed_const(wm
->dram_channels
* 4);
911 a
.full
= dfixed_const(10);
912 disp_dram_allocation
.full
= dfixed_const(3); /* XXX worse case value 0.3 */
913 disp_dram_allocation
.full
= dfixed_div(disp_dram_allocation
, a
);
914 bandwidth
.full
= dfixed_mul(dram_channels
, yclk
);
915 bandwidth
.full
= dfixed_mul(bandwidth
, disp_dram_allocation
);
917 return dfixed_trunc(bandwidth
);
921 * dce_v8_0_data_return_bandwidth - get the data return bandwidth
923 * @wm: watermark calculation data
925 * Calculate the data return bandwidth used for display (CIK).
926 * Used for display watermark bandwidth calculations
927 * Returns the data return bandwidth in MBytes/s
929 static u32
dce_v8_0_data_return_bandwidth(struct dce8_wm_params
*wm
)
931 /* Calculate the display Data return Bandwidth */
932 fixed20_12 return_efficiency
; /* 0.8 */
933 fixed20_12 sclk
, bandwidth
;
936 a
.full
= dfixed_const(1000);
937 sclk
.full
= dfixed_const(wm
->sclk
);
938 sclk
.full
= dfixed_div(sclk
, a
);
939 a
.full
= dfixed_const(10);
940 return_efficiency
.full
= dfixed_const(8);
941 return_efficiency
.full
= dfixed_div(return_efficiency
, a
);
942 a
.full
= dfixed_const(32);
943 bandwidth
.full
= dfixed_mul(a
, sclk
);
944 bandwidth
.full
= dfixed_mul(bandwidth
, return_efficiency
);
946 return dfixed_trunc(bandwidth
);
950 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth
952 * @wm: watermark calculation data
954 * Calculate the dmif bandwidth used for display (CIK).
955 * Used for display watermark bandwidth calculations
956 * Returns the dmif bandwidth in MBytes/s
958 static u32
dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params
*wm
)
960 /* Calculate the DMIF Request Bandwidth */
961 fixed20_12 disp_clk_request_efficiency
; /* 0.8 */
962 fixed20_12 disp_clk
, bandwidth
;
965 a
.full
= dfixed_const(1000);
966 disp_clk
.full
= dfixed_const(wm
->disp_clk
);
967 disp_clk
.full
= dfixed_div(disp_clk
, a
);
968 a
.full
= dfixed_const(32);
969 b
.full
= dfixed_mul(a
, disp_clk
);
971 a
.full
= dfixed_const(10);
972 disp_clk_request_efficiency
.full
= dfixed_const(8);
973 disp_clk_request_efficiency
.full
= dfixed_div(disp_clk_request_efficiency
, a
);
975 bandwidth
.full
= dfixed_mul(b
, disp_clk_request_efficiency
);
977 return dfixed_trunc(bandwidth
);
981 * dce_v8_0_available_bandwidth - get the min available bandwidth
983 * @wm: watermark calculation data
985 * Calculate the min available bandwidth used for display (CIK).
986 * Used for display watermark bandwidth calculations
987 * Returns the min available bandwidth in MBytes/s
989 static u32
dce_v8_0_available_bandwidth(struct dce8_wm_params
*wm
)
991 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
992 u32 dram_bandwidth
= dce_v8_0_dram_bandwidth(wm
);
993 u32 data_return_bandwidth
= dce_v8_0_data_return_bandwidth(wm
);
994 u32 dmif_req_bandwidth
= dce_v8_0_dmif_request_bandwidth(wm
);
996 return min(dram_bandwidth
, min(data_return_bandwidth
, dmif_req_bandwidth
));
1000 * dce_v8_0_average_bandwidth - get the average available bandwidth
1002 * @wm: watermark calculation data
1004 * Calculate the average available bandwidth used for display (CIK).
1005 * Used for display watermark bandwidth calculations
1006 * Returns the average available bandwidth in MBytes/s
1008 static u32
dce_v8_0_average_bandwidth(struct dce8_wm_params
*wm
)
1010 /* Calculate the display mode Average Bandwidth
1011 * DisplayMode should contain the source and destination dimensions,
1015 fixed20_12 line_time
;
1016 fixed20_12 src_width
;
1017 fixed20_12 bandwidth
;
1020 a
.full
= dfixed_const(1000);
1021 line_time
.full
= dfixed_const(wm
->active_time
+ wm
->blank_time
);
1022 line_time
.full
= dfixed_div(line_time
, a
);
1023 bpp
.full
= dfixed_const(wm
->bytes_per_pixel
);
1024 src_width
.full
= dfixed_const(wm
->src_width
);
1025 bandwidth
.full
= dfixed_mul(src_width
, bpp
);
1026 bandwidth
.full
= dfixed_mul(bandwidth
, wm
->vsc
);
1027 bandwidth
.full
= dfixed_div(bandwidth
, line_time
);
1029 return dfixed_trunc(bandwidth
);
1033 * dce_v8_0_latency_watermark - get the latency watermark
1035 * @wm: watermark calculation data
1037 * Calculate the latency watermark (CIK).
1038 * Used for display watermark bandwidth calculations
1039 * Returns the latency watermark in ns
1041 static u32
dce_v8_0_latency_watermark(struct dce8_wm_params
*wm
)
1043 /* First calculate the latency in ns */
1044 u32 mc_latency
= 2000; /* 2000 ns. */
1045 u32 available_bandwidth
= dce_v8_0_available_bandwidth(wm
);
1046 u32 worst_chunk_return_time
= (512 * 8 * 1000) / available_bandwidth
;
1047 u32 cursor_line_pair_return_time
= (128 * 4 * 1000) / available_bandwidth
;
1048 u32 dc_latency
= 40000000 / wm
->disp_clk
; /* dc pipe latency */
1049 u32 other_heads_data_return_time
= ((wm
->num_heads
+ 1) * worst_chunk_return_time
) +
1050 (wm
->num_heads
* cursor_line_pair_return_time
);
1051 u32 latency
= mc_latency
+ other_heads_data_return_time
+ dc_latency
;
1052 u32 max_src_lines_per_dst_line
, lb_fill_bw
, line_fill_time
;
1053 u32 tmp
, dmif_size
= 12288;
1056 if (wm
->num_heads
== 0)
1059 a
.full
= dfixed_const(2);
1060 b
.full
= dfixed_const(1);
1061 if ((wm
->vsc
.full
> a
.full
) ||
1062 ((wm
->vsc
.full
> b
.full
) && (wm
->vtaps
>= 3)) ||
1064 ((wm
->vsc
.full
>= a
.full
) && wm
->interlaced
))
1065 max_src_lines_per_dst_line
= 4;
1067 max_src_lines_per_dst_line
= 2;
1069 a
.full
= dfixed_const(available_bandwidth
);
1070 b
.full
= dfixed_const(wm
->num_heads
);
1071 a
.full
= dfixed_div(a
, b
);
1073 b
.full
= dfixed_const(mc_latency
+ 512);
1074 c
.full
= dfixed_const(wm
->disp_clk
);
1075 b
.full
= dfixed_div(b
, c
);
1077 c
.full
= dfixed_const(dmif_size
);
1078 b
.full
= dfixed_div(c
, b
);
1080 tmp
= min(dfixed_trunc(a
), dfixed_trunc(b
));
1082 b
.full
= dfixed_const(1000);
1083 c
.full
= dfixed_const(wm
->disp_clk
);
1084 b
.full
= dfixed_div(c
, b
);
1085 c
.full
= dfixed_const(wm
->bytes_per_pixel
);
1086 b
.full
= dfixed_mul(b
, c
);
1088 lb_fill_bw
= min(tmp
, dfixed_trunc(b
));
1090 a
.full
= dfixed_const(max_src_lines_per_dst_line
* wm
->src_width
* wm
->bytes_per_pixel
);
1091 b
.full
= dfixed_const(1000);
1092 c
.full
= dfixed_const(lb_fill_bw
);
1093 b
.full
= dfixed_div(c
, b
);
1094 a
.full
= dfixed_div(a
, b
);
1095 line_fill_time
= dfixed_trunc(a
);
1097 if (line_fill_time
< wm
->active_time
)
1100 return latency
+ (line_fill_time
- wm
->active_time
);
1105 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check
1106 * average and available dram bandwidth
1108 * @wm: watermark calculation data
1110 * Check if the display average bandwidth fits in the display
1111 * dram bandwidth (CIK).
1112 * Used for display watermark bandwidth calculations
1113 * Returns true if the display fits, false if not.
1115 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params
*wm
)
1117 if (dce_v8_0_average_bandwidth(wm
) <=
1118 (dce_v8_0_dram_bandwidth_for_display(wm
) / wm
->num_heads
))
1125 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check
1126 * average and available bandwidth
1128 * @wm: watermark calculation data
1130 * Check if the display average bandwidth fits in the display
1131 * available bandwidth (CIK).
1132 * Used for display watermark bandwidth calculations
1133 * Returns true if the display fits, false if not.
1135 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params
*wm
)
1137 if (dce_v8_0_average_bandwidth(wm
) <=
1138 (dce_v8_0_available_bandwidth(wm
) / wm
->num_heads
))
1145 * dce_v8_0_check_latency_hiding - check latency hiding
1147 * @wm: watermark calculation data
1149 * Check latency hiding (CIK).
1150 * Used for display watermark bandwidth calculations
1151 * Returns true if the display fits, false if not.
1153 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params
*wm
)
1155 u32 lb_partitions
= wm
->lb_size
/ wm
->src_width
;
1156 u32 line_time
= wm
->active_time
+ wm
->blank_time
;
1157 u32 latency_tolerant_lines
;
1161 a
.full
= dfixed_const(1);
1162 if (wm
->vsc
.full
> a
.full
)
1163 latency_tolerant_lines
= 1;
1165 if (lb_partitions
<= (wm
->vtaps
+ 1))
1166 latency_tolerant_lines
= 1;
1168 latency_tolerant_lines
= 2;
1171 latency_hiding
= (latency_tolerant_lines
* line_time
+ wm
->blank_time
);
1173 if (dce_v8_0_latency_watermark(wm
) <= latency_hiding
)
1180 * dce_v8_0_program_watermarks - program display watermarks
1182 * @adev: amdgpu_device pointer
1183 * @amdgpu_crtc: the selected display controller
1184 * @lb_size: line buffer size
1185 * @num_heads: number of display controllers in use
1187 * Calculate and program the display watermarks for the
1188 * selected display controller (CIK).
1190 static void dce_v8_0_program_watermarks(struct amdgpu_device
*adev
,
1191 struct amdgpu_crtc
*amdgpu_crtc
,
1192 u32 lb_size
, u32 num_heads
)
1194 struct drm_display_mode
*mode
= &amdgpu_crtc
->base
.mode
;
1195 struct dce8_wm_params wm_low
, wm_high
;
1198 u32 latency_watermark_a
= 0, latency_watermark_b
= 0;
1199 u32 tmp
, wm_mask
, lb_vblank_lead_lines
= 0;
1201 if (amdgpu_crtc
->base
.enabled
&& num_heads
&& mode
) {
1202 pixel_period
= 1000000 / (u32
)mode
->clock
;
1203 line_time
= min((u32
)mode
->crtc_htotal
* pixel_period
, (u32
)65535);
1205 /* watermark for high clocks */
1206 if (adev
->pm
.dpm_enabled
) {
1208 amdgpu_dpm_get_mclk(adev
, false) * 10;
1210 amdgpu_dpm_get_sclk(adev
, false) * 10;
1212 wm_high
.yclk
= adev
->pm
.current_mclk
* 10;
1213 wm_high
.sclk
= adev
->pm
.current_sclk
* 10;
1216 wm_high
.disp_clk
= mode
->clock
;
1217 wm_high
.src_width
= mode
->crtc_hdisplay
;
1218 wm_high
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1219 wm_high
.blank_time
= line_time
- wm_high
.active_time
;
1220 wm_high
.interlaced
= false;
1221 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1222 wm_high
.interlaced
= true;
1223 wm_high
.vsc
= amdgpu_crtc
->vsc
;
1225 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1227 wm_high
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1228 wm_high
.lb_size
= lb_size
;
1229 wm_high
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1230 wm_high
.num_heads
= num_heads
;
1232 /* set for high clocks */
1233 latency_watermark_a
= min(dce_v8_0_latency_watermark(&wm_high
), (u32
)65535);
1235 /* possibly force display priority to high */
1236 /* should really do this at mode validation time... */
1237 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high
) ||
1238 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high
) ||
1239 !dce_v8_0_check_latency_hiding(&wm_high
) ||
1240 (adev
->mode_info
.disp_priority
== 2)) {
1241 DRM_DEBUG_KMS("force priority to high\n");
1244 /* watermark for low clocks */
1245 if (adev
->pm
.dpm_enabled
) {
1247 amdgpu_dpm_get_mclk(adev
, true) * 10;
1249 amdgpu_dpm_get_sclk(adev
, true) * 10;
1251 wm_low
.yclk
= adev
->pm
.current_mclk
* 10;
1252 wm_low
.sclk
= adev
->pm
.current_sclk
* 10;
1255 wm_low
.disp_clk
= mode
->clock
;
1256 wm_low
.src_width
= mode
->crtc_hdisplay
;
1257 wm_low
.active_time
= mode
->crtc_hdisplay
* pixel_period
;
1258 wm_low
.blank_time
= line_time
- wm_low
.active_time
;
1259 wm_low
.interlaced
= false;
1260 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1261 wm_low
.interlaced
= true;
1262 wm_low
.vsc
= amdgpu_crtc
->vsc
;
1264 if (amdgpu_crtc
->rmx_type
!= RMX_OFF
)
1266 wm_low
.bytes_per_pixel
= 4; /* XXX: get this from fb config */
1267 wm_low
.lb_size
= lb_size
;
1268 wm_low
.dram_channels
= cik_get_number_of_dram_channels(adev
);
1269 wm_low
.num_heads
= num_heads
;
1271 /* set for low clocks */
1272 latency_watermark_b
= min(dce_v8_0_latency_watermark(&wm_low
), (u32
)65535);
1274 /* possibly force display priority to high */
1275 /* should really do this at mode validation time... */
1276 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low
) ||
1277 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low
) ||
1278 !dce_v8_0_check_latency_hiding(&wm_low
) ||
1279 (adev
->mode_info
.disp_priority
== 2)) {
1280 DRM_DEBUG_KMS("force priority to high\n");
1282 lb_vblank_lead_lines
= DIV_ROUND_UP(lb_size
, mode
->crtc_hdisplay
);
1286 wm_mask
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1288 tmp
&= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1289 tmp
|= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1290 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1291 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
,
1292 ((latency_watermark_a
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
) |
1293 (line_time
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
)));
1295 tmp
= RREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
);
1296 tmp
&= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1297 tmp
|= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT
);
1298 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, tmp
);
1299 WREG32(mmDPG_PIPE_URGENCY_CONTROL
+ amdgpu_crtc
->crtc_offset
,
1300 ((latency_watermark_b
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT
) |
1301 (line_time
<< DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT
)));
1302 /* restore original selection */
1303 WREG32(mmDPG_WATERMARK_MASK_CONTROL
+ amdgpu_crtc
->crtc_offset
, wm_mask
);
1305 /* save values for DPM */
1306 amdgpu_crtc
->line_time
= line_time
;
1307 amdgpu_crtc
->wm_high
= latency_watermark_a
;
1308 amdgpu_crtc
->wm_low
= latency_watermark_b
;
1309 /* Save number of lines the linebuffer leads before the scanout */
1310 amdgpu_crtc
->lb_vblank_lead_lines
= lb_vblank_lead_lines
;
1314 * dce_v8_0_bandwidth_update - program display watermarks
1316 * @adev: amdgpu_device pointer
1318 * Calculate and program the display watermarks and line
1319 * buffer allocation (CIK).
1321 static void dce_v8_0_bandwidth_update(struct amdgpu_device
*adev
)
1323 struct drm_display_mode
*mode
= NULL
;
1324 u32 num_heads
= 0, lb_size
;
1327 amdgpu_update_display_priority(adev
);
1329 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1330 if (adev
->mode_info
.crtcs
[i
]->base
.enabled
)
1333 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
1334 mode
= &adev
->mode_info
.crtcs
[i
]->base
.mode
;
1335 lb_size
= dce_v8_0_line_buffer_adjust(adev
, adev
->mode_info
.crtcs
[i
], mode
);
1336 dce_v8_0_program_watermarks(adev
, adev
->mode_info
.crtcs
[i
],
1337 lb_size
, num_heads
);
1341 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device
*adev
)
1346 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1347 offset
= adev
->mode_info
.audio
.pin
[i
].offset
;
1348 tmp
= RREG32_AUDIO_ENDPT(offset
,
1349 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
);
1351 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK
) >>
1352 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT
) == 1)
1353 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1355 adev
->mode_info
.audio
.pin
[i
].connected
= true;
1359 static struct amdgpu_audio_pin
*dce_v8_0_audio_get_pin(struct amdgpu_device
*adev
)
1363 dce_v8_0_audio_get_connected_pins(adev
);
1365 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1366 if (adev
->mode_info
.audio
.pin
[i
].connected
)
1367 return &adev
->mode_info
.audio
.pin
[i
];
1369 DRM_ERROR("No connected audio pins found!\n");
1373 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder
*encoder
)
1375 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1376 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1377 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1380 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1383 offset
= dig
->afmt
->offset
;
1385 WREG32(mmAFMT_AUDIO_SRC_CONTROL
+ offset
,
1386 (dig
->afmt
->pin
->id
<< AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT
));
1389 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder
*encoder
,
1390 struct drm_display_mode
*mode
)
1392 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1393 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1394 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1395 struct drm_connector
*connector
;
1396 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1397 u32 tmp
= 0, offset
;
1399 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1402 offset
= dig
->afmt
->pin
->offset
;
1404 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1405 if (connector
->encoder
== encoder
) {
1406 amdgpu_connector
= to_amdgpu_connector(connector
);
1411 if (!amdgpu_connector
) {
1412 DRM_ERROR("Couldn't find encoder's connector\n");
1416 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
1417 if (connector
->latency_present
[1])
1419 (connector
->video_latency
[1] <<
1420 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1421 (connector
->audio_latency
[1] <<
1422 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1426 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1428 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1430 if (connector
->latency_present
[0])
1432 (connector
->video_latency
[0] <<
1433 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1434 (connector
->audio_latency
[0] <<
1435 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1439 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT
) |
1441 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT
);
1444 WREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC
, tmp
);
1447 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder
*encoder
)
1449 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1450 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1451 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1452 struct drm_connector
*connector
;
1453 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1458 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1461 offset
= dig
->afmt
->pin
->offset
;
1463 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1464 if (connector
->encoder
== encoder
) {
1465 amdgpu_connector
= to_amdgpu_connector(connector
);
1470 if (!amdgpu_connector
) {
1471 DRM_ERROR("Couldn't find encoder's connector\n");
1475 sad_count
= drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector
), &sadb
);
1476 if (sad_count
< 0) {
1477 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count
);
1481 /* program the speaker allocation */
1482 tmp
= RREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
);
1483 tmp
&= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK
|
1484 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK
);
1486 tmp
|= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK
;
1488 tmp
|= (sadb
[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
);
1490 tmp
|= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT
); /* stereo */
1491 WREG32_AUDIO_ENDPT(offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER
, tmp
);
1496 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder
*encoder
)
1498 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
1499 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1500 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1502 struct drm_connector
*connector
;
1503 struct amdgpu_connector
*amdgpu_connector
= NULL
;
1504 struct cea_sad
*sads
;
1507 static const u16 eld_reg_to_type
[][2] = {
1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0
, HDMI_AUDIO_CODING_TYPE_PCM
},
1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1
, HDMI_AUDIO_CODING_TYPE_AC3
},
1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2
, HDMI_AUDIO_CODING_TYPE_MPEG1
},
1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3
, HDMI_AUDIO_CODING_TYPE_MP3
},
1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4
, HDMI_AUDIO_CODING_TYPE_MPEG2
},
1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5
, HDMI_AUDIO_CODING_TYPE_AAC_LC
},
1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6
, HDMI_AUDIO_CODING_TYPE_DTS
},
1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7
, HDMI_AUDIO_CODING_TYPE_ATRAC
},
1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9
, HDMI_AUDIO_CODING_TYPE_EAC3
},
1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10
, HDMI_AUDIO_CODING_TYPE_DTS_HD
},
1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11
, HDMI_AUDIO_CODING_TYPE_MLP
},
1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13
, HDMI_AUDIO_CODING_TYPE_WMA_PRO
},
1522 if (!dig
|| !dig
->afmt
|| !dig
->afmt
->pin
)
1525 offset
= dig
->afmt
->pin
->offset
;
1527 list_for_each_entry(connector
, &encoder
->dev
->mode_config
.connector_list
, head
) {
1528 if (connector
->encoder
== encoder
) {
1529 amdgpu_connector
= to_amdgpu_connector(connector
);
1534 if (!amdgpu_connector
) {
1535 DRM_ERROR("Couldn't find encoder's connector\n");
1539 sad_count
= drm_edid_to_sad(amdgpu_connector_edid(connector
), &sads
);
1540 if (sad_count
<= 0) {
1541 DRM_ERROR("Couldn't read SADs: %d\n", sad_count
);
1546 for (i
= 0; i
< ARRAY_SIZE(eld_reg_to_type
); i
++) {
1548 u8 stereo_freqs
= 0;
1549 int max_channels
= -1;
1552 for (j
= 0; j
< sad_count
; j
++) {
1553 struct cea_sad
*sad
= &sads
[j
];
1555 if (sad
->format
== eld_reg_to_type
[i
][1]) {
1556 if (sad
->channels
> max_channels
) {
1557 value
= (sad
->channels
<<
1558 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT
) |
1560 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT
) |
1562 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT
);
1563 max_channels
= sad
->channels
;
1566 if (sad
->format
== HDMI_AUDIO_CODING_TYPE_PCM
)
1567 stereo_freqs
|= sad
->freq
;
1573 value
|= (stereo_freqs
<<
1574 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT
);
1576 WREG32_AUDIO_ENDPT(offset
, eld_reg_to_type
[i
][0], value
);
1582 static void dce_v8_0_audio_enable(struct amdgpu_device
*adev
,
1583 struct amdgpu_audio_pin
*pin
,
1589 WREG32_AUDIO_ENDPT(pin
->offset
, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL
,
1590 enable
? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK
: 0);
1593 static const u32 pin_offsets
[7] =
1604 static int dce_v8_0_audio_init(struct amdgpu_device
*adev
)
1611 adev
->mode_info
.audio
.enabled
= true;
1613 if (adev
->asic_type
== CHIP_KAVERI
) /* KV: 4 streams, 7 endpoints */
1614 adev
->mode_info
.audio
.num_pins
= 7;
1615 else if ((adev
->asic_type
== CHIP_KABINI
) ||
1616 (adev
->asic_type
== CHIP_MULLINS
)) /* KB/ML: 2 streams, 3 endpoints */
1617 adev
->mode_info
.audio
.num_pins
= 3;
1618 else if ((adev
->asic_type
== CHIP_BONAIRE
) ||
1619 (adev
->asic_type
== CHIP_HAWAII
))/* BN/HW: 6 streams, 7 endpoints */
1620 adev
->mode_info
.audio
.num_pins
= 7;
1622 adev
->mode_info
.audio
.num_pins
= 3;
1624 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
1625 adev
->mode_info
.audio
.pin
[i
].channels
= -1;
1626 adev
->mode_info
.audio
.pin
[i
].rate
= -1;
1627 adev
->mode_info
.audio
.pin
[i
].bits_per_sample
= -1;
1628 adev
->mode_info
.audio
.pin
[i
].status_bits
= 0;
1629 adev
->mode_info
.audio
.pin
[i
].category_code
= 0;
1630 adev
->mode_info
.audio
.pin
[i
].connected
= false;
1631 adev
->mode_info
.audio
.pin
[i
].offset
= pin_offsets
[i
];
1632 adev
->mode_info
.audio
.pin
[i
].id
= i
;
1633 /* disable audio. it will be set up later */
1634 /* XXX remove once we switch to ip funcs */
1635 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1641 static void dce_v8_0_audio_fini(struct amdgpu_device
*adev
)
1648 if (!adev
->mode_info
.audio
.enabled
)
1651 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++)
1652 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
1654 adev
->mode_info
.audio
.enabled
= false;
1658 * update the N and CTS parameters for a given pixel clock rate
1660 static void dce_v8_0_afmt_update_ACR(struct drm_encoder
*encoder
, uint32_t clock
)
1662 struct drm_device
*dev
= encoder
->dev
;
1663 struct amdgpu_device
*adev
= dev
->dev_private
;
1664 struct amdgpu_afmt_acr acr
= amdgpu_afmt_acr(clock
);
1665 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1666 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1667 uint32_t offset
= dig
->afmt
->offset
;
1669 WREG32(mmHDMI_ACR_32_0
+ offset
, (acr
.cts_32khz
<< HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
));
1670 WREG32(mmHDMI_ACR_32_1
+ offset
, acr
.n_32khz
);
1672 WREG32(mmHDMI_ACR_44_0
+ offset
, (acr
.cts_44_1khz
<< HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT
));
1673 WREG32(mmHDMI_ACR_44_1
+ offset
, acr
.n_44_1khz
);
1675 WREG32(mmHDMI_ACR_48_0
+ offset
, (acr
.cts_48khz
<< HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT
));
1676 WREG32(mmHDMI_ACR_48_1
+ offset
, acr
.n_48khz
);
1680 * build a HDMI Video Info Frame
1682 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder
*encoder
,
1683 void *buffer
, size_t size
)
1685 struct drm_device
*dev
= encoder
->dev
;
1686 struct amdgpu_device
*adev
= dev
->dev_private
;
1687 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1688 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1689 uint32_t offset
= dig
->afmt
->offset
;
1690 uint8_t *frame
= buffer
+ 3;
1691 uint8_t *header
= buffer
;
1693 WREG32(mmAFMT_AVI_INFO0
+ offset
,
1694 frame
[0x0] | (frame
[0x1] << 8) | (frame
[0x2] << 16) | (frame
[0x3] << 24));
1695 WREG32(mmAFMT_AVI_INFO1
+ offset
,
1696 frame
[0x4] | (frame
[0x5] << 8) | (frame
[0x6] << 16) | (frame
[0x7] << 24));
1697 WREG32(mmAFMT_AVI_INFO2
+ offset
,
1698 frame
[0x8] | (frame
[0x9] << 8) | (frame
[0xA] << 16) | (frame
[0xB] << 24));
1699 WREG32(mmAFMT_AVI_INFO3
+ offset
,
1700 frame
[0xC] | (frame
[0xD] << 8) | (header
[1] << 24));
1703 static void dce_v8_0_audio_set_dto(struct drm_encoder
*encoder
, u32 clock
)
1705 struct drm_device
*dev
= encoder
->dev
;
1706 struct amdgpu_device
*adev
= dev
->dev_private
;
1707 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1708 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1709 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1710 u32 dto_phase
= 24 * 1000;
1711 u32 dto_modulo
= clock
;
1713 if (!dig
|| !dig
->afmt
)
1716 /* XXX two dtos; generally use dto0 for hdmi */
1717 /* Express [24MHz / target pixel clock] as an exact rational
1718 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1719 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1721 WREG32(mmDCCG_AUDIO_DTO_SOURCE
, (amdgpu_crtc
->crtc_id
<< DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT
));
1722 WREG32(mmDCCG_AUDIO_DTO0_PHASE
, dto_phase
);
1723 WREG32(mmDCCG_AUDIO_DTO0_MODULE
, dto_modulo
);
1727 * update the info frames with the data from the current display mode
1729 static void dce_v8_0_afmt_setmode(struct drm_encoder
*encoder
,
1730 struct drm_display_mode
*mode
)
1732 struct drm_device
*dev
= encoder
->dev
;
1733 struct amdgpu_device
*adev
= dev
->dev_private
;
1734 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1735 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1736 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
1737 u8 buffer
[HDMI_INFOFRAME_HEADER_SIZE
+ HDMI_AVI_INFOFRAME_SIZE
];
1738 struct hdmi_avi_infoframe frame
;
1739 uint32_t offset
, val
;
1743 if (!dig
|| !dig
->afmt
)
1746 /* Silent, r600_hdmi_enable will raise WARN for us */
1747 if (!dig
->afmt
->enabled
)
1749 offset
= dig
->afmt
->offset
;
1751 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1752 if (encoder
->crtc
) {
1753 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(encoder
->crtc
);
1754 bpc
= amdgpu_crtc
->bpc
;
1757 /* disable audio prior to setting up hw */
1758 dig
->afmt
->pin
= dce_v8_0_audio_get_pin(adev
);
1759 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1761 dce_v8_0_audio_set_dto(encoder
, mode
->clock
);
1763 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ offset
,
1764 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
); /* send null packets when required */
1766 WREG32(mmAFMT_AUDIO_CRC_CONTROL
+ offset
, 0x1000);
1768 val
= RREG32(mmHDMI_CONTROL
+ offset
);
1769 val
&= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1770 val
&= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK
;
1778 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1779 connector
->name
, bpc
);
1782 val
|= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1783 val
|= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
;
1784 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1788 val
|= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK
;
1789 val
|= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT
;
1790 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1795 WREG32(mmHDMI_CONTROL
+ offset
, val
);
1797 WREG32(mmHDMI_VBI_PACKET_CONTROL
+ offset
,
1798 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK
| /* send null packets when required */
1799 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK
| /* send general control packets */
1800 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK
); /* send general control packets every frame */
1802 WREG32(mmHDMI_INFOFRAME_CONTROL0
+ offset
,
1803 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK
| /* enable audio info frames (frames won't be set until audio is enabled) */
1804 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK
); /* required for audio info values to be updated */
1806 WREG32(mmAFMT_INFOFRAME_CONTROL0
+ offset
,
1807 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK
); /* required for audio info values to be updated */
1809 WREG32(mmHDMI_INFOFRAME_CONTROL1
+ offset
,
1810 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT
)); /* anything other than 0 */
1812 WREG32(mmHDMI_GC
+ offset
, 0); /* unset HDMI_GC_AVMUTE */
1814 WREG32(mmHDMI_AUDIO_PACKET_CONTROL
+ offset
,
1815 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT
) | /* set the default audio delay */
1816 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT
)); /* should be suffient for all audio modes and small enough for all hblanks */
1818 WREG32(mmAFMT_AUDIO_PACKET_CONTROL
+ offset
,
1819 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK
); /* allow 60958 channel status fields to be updated */
1821 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
1824 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ offset
,
1825 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
); /* allow hw to sent ACR packets when required */
1827 WREG32(mmHDMI_ACR_PACKET_CONTROL
+ offset
,
1828 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK
| /* select SW CTS value */
1829 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK
); /* allow hw to sent ACR packets when required */
1831 dce_v8_0_afmt_update_ACR(encoder
, mode
->clock
);
1833 WREG32(mmAFMT_60958_0
+ offset
,
1834 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT
));
1836 WREG32(mmAFMT_60958_1
+ offset
,
1837 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT
));
1839 WREG32(mmAFMT_60958_2
+ offset
,
1840 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT
) |
1841 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT
) |
1842 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT
) |
1843 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT
) |
1844 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT
) |
1845 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT
));
1847 dce_v8_0_audio_write_speaker_allocation(encoder
);
1850 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2
+ offset
,
1851 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT
));
1853 dce_v8_0_afmt_audio_select_pin(encoder
);
1854 dce_v8_0_audio_write_sad_regs(encoder
);
1855 dce_v8_0_audio_write_latency_fields(encoder
, mode
);
1857 err
= drm_hdmi_avi_infoframe_from_display_mode(&frame
, mode
);
1859 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err
);
1863 err
= hdmi_avi_infoframe_pack(&frame
, buffer
, sizeof(buffer
));
1865 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err
);
1869 dce_v8_0_afmt_update_avi_infoframe(encoder
, buffer
, sizeof(buffer
));
1871 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0
+ offset
,
1872 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
| /* enable AVI info frames */
1873 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK
); /* required for audio info values to be updated */
1875 WREG32_P(mmHDMI_INFOFRAME_CONTROL1
+ offset
,
1876 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT
), /* anything other than 0 */
1877 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK
);
1879 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL
+ offset
,
1880 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK
); /* send audio packets */
1882 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
1883 WREG32(mmAFMT_RAMP_CONTROL0
+ offset
, 0x00FFFFFF);
1884 WREG32(mmAFMT_RAMP_CONTROL1
+ offset
, 0x007FFFFF);
1885 WREG32(mmAFMT_RAMP_CONTROL2
+ offset
, 0x00000001);
1886 WREG32(mmAFMT_RAMP_CONTROL3
+ offset
, 0x00000001);
1888 /* enable audio after to setting up hw */
1889 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, true);
1892 static void dce_v8_0_afmt_enable(struct drm_encoder
*encoder
, bool enable
)
1894 struct drm_device
*dev
= encoder
->dev
;
1895 struct amdgpu_device
*adev
= dev
->dev_private
;
1896 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
1897 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
1899 if (!dig
|| !dig
->afmt
)
1902 /* Silent, r600_hdmi_enable will raise WARN for us */
1903 if (enable
&& dig
->afmt
->enabled
)
1905 if (!enable
&& !dig
->afmt
->enabled
)
1908 if (!enable
&& dig
->afmt
->pin
) {
1909 dce_v8_0_audio_enable(adev
, dig
->afmt
->pin
, false);
1910 dig
->afmt
->pin
= NULL
;
1913 dig
->afmt
->enabled
= enable
;
1915 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1916 enable
? "En" : "Dis", dig
->afmt
->offset
, amdgpu_encoder
->encoder_id
);
1919 static int dce_v8_0_afmt_init(struct amdgpu_device
*adev
)
1923 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++)
1924 adev
->mode_info
.afmt
[i
] = NULL
;
1926 /* DCE8 has audio blocks tied to DIG encoders */
1927 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1928 adev
->mode_info
.afmt
[i
] = kzalloc(sizeof(struct amdgpu_afmt
), GFP_KERNEL
);
1929 if (adev
->mode_info
.afmt
[i
]) {
1930 adev
->mode_info
.afmt
[i
]->offset
= dig_offsets
[i
];
1931 adev
->mode_info
.afmt
[i
]->id
= i
;
1934 for (j
= 0; j
< i
; j
++) {
1935 kfree(adev
->mode_info
.afmt
[j
]);
1936 adev
->mode_info
.afmt
[j
] = NULL
;
1944 static void dce_v8_0_afmt_fini(struct amdgpu_device
*adev
)
1948 for (i
= 0; i
< adev
->mode_info
.num_dig
; i
++) {
1949 kfree(adev
->mode_info
.afmt
[i
]);
1950 adev
->mode_info
.afmt
[i
] = NULL
;
1954 static const u32 vga_control_regs
[6] =
1964 static void dce_v8_0_vga_enable(struct drm_crtc
*crtc
, bool enable
)
1966 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1967 struct drm_device
*dev
= crtc
->dev
;
1968 struct amdgpu_device
*adev
= dev
->dev_private
;
1971 vga_control
= RREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
]) & ~1;
1973 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
| 1);
1975 WREG32(vga_control_regs
[amdgpu_crtc
->crtc_id
], vga_control
);
1978 static void dce_v8_0_grph_enable(struct drm_crtc
*crtc
, bool enable
)
1980 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1981 struct drm_device
*dev
= crtc
->dev
;
1982 struct amdgpu_device
*adev
= dev
->dev_private
;
1985 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 1);
1987 WREG32(mmGRPH_ENABLE
+ amdgpu_crtc
->crtc_offset
, 0);
1990 static int dce_v8_0_crtc_do_set_base(struct drm_crtc
*crtc
,
1991 struct drm_framebuffer
*fb
,
1992 int x
, int y
, int atomic
)
1994 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
1995 struct drm_device
*dev
= crtc
->dev
;
1996 struct amdgpu_device
*adev
= dev
->dev_private
;
1997 struct amdgpu_framebuffer
*amdgpu_fb
;
1998 struct drm_framebuffer
*target_fb
;
1999 struct drm_gem_object
*obj
;
2000 struct amdgpu_bo
*rbo
;
2001 uint64_t fb_location
, tiling_flags
;
2002 uint32_t fb_format
, fb_pitch_pixels
;
2003 u32 fb_swap
= (GRPH_ENDIAN_NONE
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2005 u32 viewport_w
, viewport_h
;
2007 bool bypass_lut
= false;
2010 if (!atomic
&& !crtc
->primary
->fb
) {
2011 DRM_DEBUG_KMS("No FB bound\n");
2016 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2019 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2020 target_fb
= crtc
->primary
->fb
;
2023 /* If atomic, assume fb object is pinned & idle & fenced and
2024 * just update base pointers
2026 obj
= amdgpu_fb
->obj
;
2027 rbo
= gem_to_amdgpu_bo(obj
);
2028 r
= amdgpu_bo_reserve(rbo
, false);
2029 if (unlikely(r
!= 0))
2033 fb_location
= amdgpu_bo_gpu_offset(rbo
);
2035 r
= amdgpu_bo_pin(rbo
, AMDGPU_GEM_DOMAIN_VRAM
, &fb_location
);
2036 if (unlikely(r
!= 0)) {
2037 amdgpu_bo_unreserve(rbo
);
2042 amdgpu_bo_get_tiling_flags(rbo
, &tiling_flags
);
2043 amdgpu_bo_unreserve(rbo
);
2045 pipe_config
= AMDGPU_TILING_GET(tiling_flags
, PIPE_CONFIG
);
2047 switch (target_fb
->pixel_format
) {
2049 fb_format
= ((GRPH_DEPTH_8BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2050 (GRPH_FORMAT_INDEXED
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2052 case DRM_FORMAT_XRGB4444
:
2053 case DRM_FORMAT_ARGB4444
:
2054 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2055 (GRPH_FORMAT_ARGB1555
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2057 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2060 case DRM_FORMAT_XRGB1555
:
2061 case DRM_FORMAT_ARGB1555
:
2062 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2063 (GRPH_FORMAT_ARGB1555
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2065 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2068 case DRM_FORMAT_BGRX5551
:
2069 case DRM_FORMAT_BGRA5551
:
2070 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2071 (GRPH_FORMAT_BGRA5551
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2073 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2076 case DRM_FORMAT_RGB565
:
2077 fb_format
= ((GRPH_DEPTH_16BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2078 (GRPH_FORMAT_ARGB565
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2080 fb_swap
= (GRPH_ENDIAN_8IN16
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2083 case DRM_FORMAT_XRGB8888
:
2084 case DRM_FORMAT_ARGB8888
:
2085 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2086 (GRPH_FORMAT_ARGB8888
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2088 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2091 case DRM_FORMAT_XRGB2101010
:
2092 case DRM_FORMAT_ARGB2101010
:
2093 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2094 (GRPH_FORMAT_ARGB2101010
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2096 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2098 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2101 case DRM_FORMAT_BGRX1010102
:
2102 case DRM_FORMAT_BGRA1010102
:
2103 fb_format
= ((GRPH_DEPTH_32BPP
<< GRPH_CONTROL__GRPH_DEPTH__SHIFT
) |
2104 (GRPH_FORMAT_BGRA1010102
<< GRPH_CONTROL__GRPH_FORMAT__SHIFT
));
2106 fb_swap
= (GRPH_ENDIAN_8IN32
<< GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
);
2108 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2112 DRM_ERROR("Unsupported screen format %s\n",
2113 drm_get_format_name(target_fb
->pixel_format
));
2117 if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_2D_TILED_THIN1
) {
2118 unsigned bankw
, bankh
, mtaspect
, tile_split
, num_banks
;
2120 bankw
= AMDGPU_TILING_GET(tiling_flags
, BANK_WIDTH
);
2121 bankh
= AMDGPU_TILING_GET(tiling_flags
, BANK_HEIGHT
);
2122 mtaspect
= AMDGPU_TILING_GET(tiling_flags
, MACRO_TILE_ASPECT
);
2123 tile_split
= AMDGPU_TILING_GET(tiling_flags
, TILE_SPLIT
);
2124 num_banks
= AMDGPU_TILING_GET(tiling_flags
, NUM_BANKS
);
2126 fb_format
|= (num_banks
<< GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
);
2127 fb_format
|= (GRPH_ARRAY_2D_TILED_THIN1
<< GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
);
2128 fb_format
|= (tile_split
<< GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT
);
2129 fb_format
|= (bankw
<< GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT
);
2130 fb_format
|= (bankh
<< GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT
);
2131 fb_format
|= (mtaspect
<< GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT
);
2132 fb_format
|= (DISPLAY_MICRO_TILING
<< GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT
);
2133 } else if (AMDGPU_TILING_GET(tiling_flags
, ARRAY_MODE
) == ARRAY_1D_TILED_THIN1
) {
2134 fb_format
|= (GRPH_ARRAY_1D_TILED_THIN1
<< GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
);
2137 fb_format
|= (pipe_config
<< GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
);
2139 dce_v8_0_vga_enable(crtc
, false);
2141 /* Make sure surface address is updated at vertical blank rather than
2144 WREG32(mmGRPH_FLIP_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2146 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2147 upper_32_bits(fb_location
));
2148 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2149 upper_32_bits(fb_location
));
2150 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2151 (u32
)fb_location
& GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK
);
2152 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2153 (u32
) fb_location
& GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK
);
2154 WREG32(mmGRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
, fb_format
);
2155 WREG32(mmGRPH_SWAP_CNTL
+ amdgpu_crtc
->crtc_offset
, fb_swap
);
2158 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2159 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2160 * retain the full precision throughout the pipeline.
2162 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2163 (bypass_lut
? LUT_10BIT_BYPASS_EN
: 0),
2164 ~LUT_10BIT_BYPASS_EN
);
2167 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2169 WREG32(mmGRPH_SURFACE_OFFSET_X
+ amdgpu_crtc
->crtc_offset
, 0);
2170 WREG32(mmGRPH_SURFACE_OFFSET_Y
+ amdgpu_crtc
->crtc_offset
, 0);
2171 WREG32(mmGRPH_X_START
+ amdgpu_crtc
->crtc_offset
, 0);
2172 WREG32(mmGRPH_Y_START
+ amdgpu_crtc
->crtc_offset
, 0);
2173 WREG32(mmGRPH_X_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->width
);
2174 WREG32(mmGRPH_Y_END
+ amdgpu_crtc
->crtc_offset
, target_fb
->height
);
2176 fb_pitch_pixels
= target_fb
->pitches
[0] / (target_fb
->bits_per_pixel
/ 8);
2177 WREG32(mmGRPH_PITCH
+ amdgpu_crtc
->crtc_offset
, fb_pitch_pixels
);
2179 dce_v8_0_grph_enable(crtc
, true);
2181 WREG32(mmLB_DESKTOP_HEIGHT
+ amdgpu_crtc
->crtc_offset
,
2186 WREG32(mmVIEWPORT_START
+ amdgpu_crtc
->crtc_offset
,
2188 viewport_w
= crtc
->mode
.hdisplay
;
2189 viewport_h
= (crtc
->mode
.vdisplay
+ 1) & ~1;
2190 WREG32(mmVIEWPORT_SIZE
+ amdgpu_crtc
->crtc_offset
,
2191 (viewport_w
<< 16) | viewport_h
);
2193 /* set pageflip to happen only at start of vblank interval (front porch) */
2194 WREG32(mmMASTER_UPDATE_MODE
+ amdgpu_crtc
->crtc_offset
, 3);
2196 if (!atomic
&& fb
&& fb
!= crtc
->primary
->fb
) {
2197 amdgpu_fb
= to_amdgpu_framebuffer(fb
);
2198 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2199 r
= amdgpu_bo_reserve(rbo
, false);
2200 if (unlikely(r
!= 0))
2202 amdgpu_bo_unpin(rbo
);
2203 amdgpu_bo_unreserve(rbo
);
2206 /* Bytes per pixel may have changed */
2207 dce_v8_0_bandwidth_update(adev
);
2212 static void dce_v8_0_set_interleave(struct drm_crtc
*crtc
,
2213 struct drm_display_mode
*mode
)
2215 struct drm_device
*dev
= crtc
->dev
;
2216 struct amdgpu_device
*adev
= dev
->dev_private
;
2217 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2219 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
2220 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
,
2221 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT
);
2223 WREG32(mmLB_DATA_FORMAT
+ amdgpu_crtc
->crtc_offset
, 0);
2226 static void dce_v8_0_crtc_load_lut(struct drm_crtc
*crtc
)
2228 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2229 struct drm_device
*dev
= crtc
->dev
;
2230 struct amdgpu_device
*adev
= dev
->dev_private
;
2233 DRM_DEBUG_KMS("%d\n", amdgpu_crtc
->crtc_id
);
2235 WREG32(mmINPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2236 ((INPUT_CSC_BYPASS
<< INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT
) |
2237 (INPUT_CSC_BYPASS
<< INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT
)));
2238 WREG32(mmPRESCALE_GRPH_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2239 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK
);
2240 WREG32(mmPRESCALE_OVL_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2241 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK
);
2242 WREG32(mmINPUT_GAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2243 ((INPUT_GAMMA_USE_LUT
<< INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT
) |
2244 (INPUT_GAMMA_USE_LUT
<< INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT
)));
2246 WREG32(mmDC_LUT_CONTROL
+ amdgpu_crtc
->crtc_offset
, 0);
2248 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0);
2249 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0);
2250 WREG32(mmDC_LUT_BLACK_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0);
2252 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2253 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2254 WREG32(mmDC_LUT_WHITE_OFFSET_RED
+ amdgpu_crtc
->crtc_offset
, 0xffff);
2256 WREG32(mmDC_LUT_RW_MODE
+ amdgpu_crtc
->crtc_offset
, 0);
2257 WREG32(mmDC_LUT_WRITE_EN_MASK
+ amdgpu_crtc
->crtc_offset
, 0x00000007);
2259 WREG32(mmDC_LUT_RW_INDEX
+ amdgpu_crtc
->crtc_offset
, 0);
2260 for (i
= 0; i
< 256; i
++) {
2261 WREG32(mmDC_LUT_30_COLOR
+ amdgpu_crtc
->crtc_offset
,
2262 (amdgpu_crtc
->lut_r
[i
] << 20) |
2263 (amdgpu_crtc
->lut_g
[i
] << 10) |
2264 (amdgpu_crtc
->lut_b
[i
] << 0));
2267 WREG32(mmDEGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2268 ((DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT
) |
2269 (DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT
) |
2270 (DEGAMMA_BYPASS
<< DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT
)));
2271 WREG32(mmGAMUT_REMAP_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2272 ((GAMUT_REMAP_BYPASS
<< GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT
) |
2273 (GAMUT_REMAP_BYPASS
<< GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT
)));
2274 WREG32(mmREGAMMA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2275 ((REGAMMA_BYPASS
<< REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
) |
2276 (REGAMMA_BYPASS
<< REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT
)));
2277 WREG32(mmOUTPUT_CSC_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2278 ((OUTPUT_CSC_BYPASS
<< OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT
) |
2279 (OUTPUT_CSC_BYPASS
<< OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT
)));
2280 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2281 WREG32(0x1a50 + amdgpu_crtc
->crtc_offset
, 0);
2282 /* XXX this only needs to be programmed once per crtc at startup,
2283 * not sure where the best place for it is
2285 WREG32(mmALPHA_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2286 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK
);
2289 static int dce_v8_0_pick_dig_encoder(struct drm_encoder
*encoder
)
2291 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
2292 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
2294 switch (amdgpu_encoder
->encoder_id
) {
2295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2307 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2313 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
2317 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder
->encoder_id
);
2323 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc.
2327 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2328 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2329 * monitors a dedicated PPLL must be used. If a particular board has
2330 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2331 * as there is no need to program the PLL itself. If we are not able to
2332 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2333 * avoid messing up an existing monitor.
2335 * Asic specific PLL information
2339 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2341 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2344 static u32
dce_v8_0_pick_pll(struct drm_crtc
*crtc
)
2346 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2347 struct drm_device
*dev
= crtc
->dev
;
2348 struct amdgpu_device
*adev
= dev
->dev_private
;
2352 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
))) {
2353 if (adev
->clock
.dp_extclk
)
2354 /* skip PPLL programming if using ext clock */
2355 return ATOM_PPLL_INVALID
;
2357 /* use the same PPLL for all DP monitors */
2358 pll
= amdgpu_pll_get_shared_dp_ppll(crtc
);
2359 if (pll
!= ATOM_PPLL_INVALID
)
2363 /* use the same PPLL for all monitors with the same clock */
2364 pll
= amdgpu_pll_get_shared_nondp_ppll(crtc
);
2365 if (pll
!= ATOM_PPLL_INVALID
)
2368 /* otherwise, pick one of the plls */
2369 if ((adev
->asic_type
== CHIP_KABINI
) ||
2370 (adev
->asic_type
== CHIP_MULLINS
)) {
2371 /* KB/ML has PPLL1 and PPLL2 */
2372 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2373 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2375 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2377 DRM_ERROR("unable to allocate a PPLL\n");
2378 return ATOM_PPLL_INVALID
;
2380 /* CI/KV has PPLL0, PPLL1, and PPLL2 */
2381 pll_in_use
= amdgpu_pll_get_use_mask(crtc
);
2382 if (!(pll_in_use
& (1 << ATOM_PPLL2
)))
2384 if (!(pll_in_use
& (1 << ATOM_PPLL1
)))
2386 if (!(pll_in_use
& (1 << ATOM_PPLL0
)))
2388 DRM_ERROR("unable to allocate a PPLL\n");
2389 return ATOM_PPLL_INVALID
;
2391 return ATOM_PPLL_INVALID
;
2394 static void dce_v8_0_lock_cursor(struct drm_crtc
*crtc
, bool lock
)
2396 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2397 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2400 cur_lock
= RREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
);
2402 cur_lock
|= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
;
2404 cur_lock
&= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK
;
2405 WREG32(mmCUR_UPDATE
+ amdgpu_crtc
->crtc_offset
, cur_lock
);
2408 static void dce_v8_0_hide_cursor(struct drm_crtc
*crtc
)
2410 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2411 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2413 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2414 (CURSOR_24_8_PRE_MULT
<< CUR_CONTROL__CURSOR_MODE__SHIFT
) |
2415 (CURSOR_URGENT_1_2
<< CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
));
2418 static void dce_v8_0_show_cursor(struct drm_crtc
*crtc
)
2420 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2421 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2423 WREG32(mmCUR_SURFACE_ADDRESS_HIGH
+ amdgpu_crtc
->crtc_offset
,
2424 upper_32_bits(amdgpu_crtc
->cursor_addr
));
2425 WREG32(mmCUR_SURFACE_ADDRESS
+ amdgpu_crtc
->crtc_offset
,
2426 lower_32_bits(amdgpu_crtc
->cursor_addr
));
2428 WREG32_IDX(mmCUR_CONTROL
+ amdgpu_crtc
->crtc_offset
,
2429 CUR_CONTROL__CURSOR_EN_MASK
|
2430 (CURSOR_24_8_PRE_MULT
<< CUR_CONTROL__CURSOR_MODE__SHIFT
) |
2431 (CURSOR_URGENT_1_2
<< CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT
));
2434 static int dce_v8_0_cursor_move_locked(struct drm_crtc
*crtc
,
2437 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2438 struct amdgpu_device
*adev
= crtc
->dev
->dev_private
;
2439 int xorigin
= 0, yorigin
= 0;
2441 /* avivo cursor are offset into the total surface */
2444 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x
, y
, crtc
->x
, crtc
->y
);
2447 xorigin
= min(-x
, amdgpu_crtc
->max_cursor_width
- 1);
2451 yorigin
= min(-y
, amdgpu_crtc
->max_cursor_height
- 1);
2455 WREG32(mmCUR_POSITION
+ amdgpu_crtc
->crtc_offset
, (x
<< 16) | y
);
2456 WREG32(mmCUR_HOT_SPOT
+ amdgpu_crtc
->crtc_offset
, (xorigin
<< 16) | yorigin
);
2457 WREG32(mmCUR_SIZE
+ amdgpu_crtc
->crtc_offset
,
2458 ((amdgpu_crtc
->cursor_width
- 1) << 16) | (amdgpu_crtc
->cursor_height
- 1));
2460 amdgpu_crtc
->cursor_x
= x
;
2461 amdgpu_crtc
->cursor_y
= y
;
2466 static int dce_v8_0_crtc_cursor_move(struct drm_crtc
*crtc
,
2471 dce_v8_0_lock_cursor(crtc
, true);
2472 ret
= dce_v8_0_cursor_move_locked(crtc
, x
, y
);
2473 dce_v8_0_lock_cursor(crtc
, false);
2478 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc
*crtc
,
2479 struct drm_file
*file_priv
,
2486 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2487 struct drm_gem_object
*obj
;
2488 struct amdgpu_bo
*aobj
;
2492 /* turn off cursor */
2493 dce_v8_0_hide_cursor(crtc
);
2498 if ((width
> amdgpu_crtc
->max_cursor_width
) ||
2499 (height
> amdgpu_crtc
->max_cursor_height
)) {
2500 DRM_ERROR("bad cursor width or height %d x %d\n", width
, height
);
2504 obj
= drm_gem_object_lookup(file_priv
, handle
);
2506 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc
->crtc_id
);
2510 aobj
= gem_to_amdgpu_bo(obj
);
2511 ret
= amdgpu_bo_reserve(aobj
, false);
2513 drm_gem_object_unreference_unlocked(obj
);
2517 ret
= amdgpu_bo_pin(aobj
, AMDGPU_GEM_DOMAIN_VRAM
, &amdgpu_crtc
->cursor_addr
);
2518 amdgpu_bo_unreserve(aobj
);
2520 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret
);
2521 drm_gem_object_unreference_unlocked(obj
);
2525 amdgpu_crtc
->cursor_width
= width
;
2526 amdgpu_crtc
->cursor_height
= height
;
2528 dce_v8_0_lock_cursor(crtc
, true);
2530 if (hot_x
!= amdgpu_crtc
->cursor_hot_x
||
2531 hot_y
!= amdgpu_crtc
->cursor_hot_y
) {
2534 x
= amdgpu_crtc
->cursor_x
+ amdgpu_crtc
->cursor_hot_x
- hot_x
;
2535 y
= amdgpu_crtc
->cursor_y
+ amdgpu_crtc
->cursor_hot_y
- hot_y
;
2537 dce_v8_0_cursor_move_locked(crtc
, x
, y
);
2539 amdgpu_crtc
->cursor_hot_x
= hot_x
;
2540 amdgpu_crtc
->cursor_hot_y
= hot_y
;
2543 dce_v8_0_show_cursor(crtc
);
2544 dce_v8_0_lock_cursor(crtc
, false);
2547 if (amdgpu_crtc
->cursor_bo
) {
2548 struct amdgpu_bo
*aobj
= gem_to_amdgpu_bo(amdgpu_crtc
->cursor_bo
);
2549 ret
= amdgpu_bo_reserve(aobj
, false);
2550 if (likely(ret
== 0)) {
2551 amdgpu_bo_unpin(aobj
);
2552 amdgpu_bo_unreserve(aobj
);
2554 drm_gem_object_unreference_unlocked(amdgpu_crtc
->cursor_bo
);
2557 amdgpu_crtc
->cursor_bo
= obj
;
2561 static void dce_v8_0_cursor_reset(struct drm_crtc
*crtc
)
2563 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2565 if (amdgpu_crtc
->cursor_bo
) {
2566 dce_v8_0_lock_cursor(crtc
, true);
2568 dce_v8_0_cursor_move_locked(crtc
, amdgpu_crtc
->cursor_x
,
2569 amdgpu_crtc
->cursor_y
);
2571 dce_v8_0_show_cursor(crtc
);
2573 dce_v8_0_lock_cursor(crtc
, false);
2577 static void dce_v8_0_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2578 u16
*blue
, uint32_t start
, uint32_t size
)
2580 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2581 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
2583 /* userspace palettes are always correct as is */
2584 for (i
= start
; i
< end
; i
++) {
2585 amdgpu_crtc
->lut_r
[i
] = red
[i
] >> 6;
2586 amdgpu_crtc
->lut_g
[i
] = green
[i
] >> 6;
2587 amdgpu_crtc
->lut_b
[i
] = blue
[i
] >> 6;
2589 dce_v8_0_crtc_load_lut(crtc
);
2592 static void dce_v8_0_crtc_destroy(struct drm_crtc
*crtc
)
2594 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2596 drm_crtc_cleanup(crtc
);
2600 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs
= {
2601 .cursor_set2
= dce_v8_0_crtc_cursor_set2
,
2602 .cursor_move
= dce_v8_0_crtc_cursor_move
,
2603 .gamma_set
= dce_v8_0_crtc_gamma_set
,
2604 .set_config
= amdgpu_crtc_set_config
,
2605 .destroy
= dce_v8_0_crtc_destroy
,
2606 .page_flip
= amdgpu_crtc_page_flip
,
2609 static void dce_v8_0_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2611 struct drm_device
*dev
= crtc
->dev
;
2612 struct amdgpu_device
*adev
= dev
->dev_private
;
2613 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2617 case DRM_MODE_DPMS_ON
:
2618 amdgpu_crtc
->enabled
= true;
2619 amdgpu_atombios_crtc_enable(crtc
, ATOM_ENABLE
);
2620 dce_v8_0_vga_enable(crtc
, true);
2621 amdgpu_atombios_crtc_blank(crtc
, ATOM_DISABLE
);
2622 dce_v8_0_vga_enable(crtc
, false);
2623 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2624 type
= amdgpu_crtc_idx_to_irq_type(adev
, amdgpu_crtc
->crtc_id
);
2625 amdgpu_irq_update(adev
, &adev
->crtc_irq
, type
);
2626 amdgpu_irq_update(adev
, &adev
->pageflip_irq
, type
);
2627 drm_vblank_on(dev
, amdgpu_crtc
->crtc_id
);
2628 dce_v8_0_crtc_load_lut(crtc
);
2630 case DRM_MODE_DPMS_STANDBY
:
2631 case DRM_MODE_DPMS_SUSPEND
:
2632 case DRM_MODE_DPMS_OFF
:
2633 drm_vblank_off(dev
, amdgpu_crtc
->crtc_id
);
2634 if (amdgpu_crtc
->enabled
) {
2635 dce_v8_0_vga_enable(crtc
, true);
2636 amdgpu_atombios_crtc_blank(crtc
, ATOM_ENABLE
);
2637 dce_v8_0_vga_enable(crtc
, false);
2639 amdgpu_atombios_crtc_enable(crtc
, ATOM_DISABLE
);
2640 amdgpu_crtc
->enabled
= false;
2643 /* adjust pm to dpms */
2644 amdgpu_pm_compute_clocks(adev
);
2647 static void dce_v8_0_crtc_prepare(struct drm_crtc
*crtc
)
2649 /* disable crtc pair power gating before programming */
2650 amdgpu_atombios_crtc_powergate(crtc
, ATOM_DISABLE
);
2651 amdgpu_atombios_crtc_lock(crtc
, ATOM_ENABLE
);
2652 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2655 static void dce_v8_0_crtc_commit(struct drm_crtc
*crtc
)
2657 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_ON
);
2658 amdgpu_atombios_crtc_lock(crtc
, ATOM_DISABLE
);
2661 static void dce_v8_0_crtc_disable(struct drm_crtc
*crtc
)
2663 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2664 struct drm_device
*dev
= crtc
->dev
;
2665 struct amdgpu_device
*adev
= dev
->dev_private
;
2666 struct amdgpu_atom_ss ss
;
2669 dce_v8_0_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
2670 if (crtc
->primary
->fb
) {
2672 struct amdgpu_framebuffer
*amdgpu_fb
;
2673 struct amdgpu_bo
*rbo
;
2675 amdgpu_fb
= to_amdgpu_framebuffer(crtc
->primary
->fb
);
2676 rbo
= gem_to_amdgpu_bo(amdgpu_fb
->obj
);
2677 r
= amdgpu_bo_reserve(rbo
, false);
2679 DRM_ERROR("failed to reserve rbo before unpin\n");
2681 amdgpu_bo_unpin(rbo
);
2682 amdgpu_bo_unreserve(rbo
);
2685 /* disable the GRPH */
2686 dce_v8_0_grph_enable(crtc
, false);
2688 amdgpu_atombios_crtc_powergate(crtc
, ATOM_ENABLE
);
2690 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2691 if (adev
->mode_info
.crtcs
[i
] &&
2692 adev
->mode_info
.crtcs
[i
]->enabled
&&
2693 i
!= amdgpu_crtc
->crtc_id
&&
2694 amdgpu_crtc
->pll_id
== adev
->mode_info
.crtcs
[i
]->pll_id
) {
2695 /* one other crtc is using this pll don't turn
2702 switch (amdgpu_crtc
->pll_id
) {
2705 /* disable the ppll */
2706 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2707 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2710 /* disable the ppll */
2711 if ((adev
->asic_type
== CHIP_KAVERI
) ||
2712 (adev
->asic_type
== CHIP_BONAIRE
) ||
2713 (adev
->asic_type
== CHIP_HAWAII
))
2714 amdgpu_atombios_crtc_program_pll(crtc
, amdgpu_crtc
->crtc_id
, amdgpu_crtc
->pll_id
,
2715 0, 0, ATOM_DISABLE
, 0, 0, 0, 0, 0, false, &ss
);
2721 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2722 amdgpu_crtc
->adjusted_clock
= 0;
2723 amdgpu_crtc
->encoder
= NULL
;
2724 amdgpu_crtc
->connector
= NULL
;
2727 static int dce_v8_0_crtc_mode_set(struct drm_crtc
*crtc
,
2728 struct drm_display_mode
*mode
,
2729 struct drm_display_mode
*adjusted_mode
,
2730 int x
, int y
, struct drm_framebuffer
*old_fb
)
2732 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2734 if (!amdgpu_crtc
->adjusted_clock
)
2737 amdgpu_atombios_crtc_set_pll(crtc
, adjusted_mode
);
2738 amdgpu_atombios_crtc_set_dtd_timing(crtc
, adjusted_mode
);
2739 dce_v8_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2740 amdgpu_atombios_crtc_overscan_setup(crtc
, mode
, adjusted_mode
);
2741 amdgpu_atombios_crtc_scaler_setup(crtc
);
2742 dce_v8_0_cursor_reset(crtc
);
2743 /* update the hw version fpr dpm */
2744 amdgpu_crtc
->hw_mode
= *adjusted_mode
;
2749 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc
*crtc
,
2750 const struct drm_display_mode
*mode
,
2751 struct drm_display_mode
*adjusted_mode
)
2753 struct amdgpu_crtc
*amdgpu_crtc
= to_amdgpu_crtc(crtc
);
2754 struct drm_device
*dev
= crtc
->dev
;
2755 struct drm_encoder
*encoder
;
2757 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2758 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2759 if (encoder
->crtc
== crtc
) {
2760 amdgpu_crtc
->encoder
= encoder
;
2761 amdgpu_crtc
->connector
= amdgpu_get_connector_for_encoder(encoder
);
2765 if ((amdgpu_crtc
->encoder
== NULL
) || (amdgpu_crtc
->connector
== NULL
)) {
2766 amdgpu_crtc
->encoder
= NULL
;
2767 amdgpu_crtc
->connector
= NULL
;
2770 if (!amdgpu_crtc_scaling_mode_fixup(crtc
, mode
, adjusted_mode
))
2772 if (amdgpu_atombios_crtc_prepare_pll(crtc
, adjusted_mode
))
2775 amdgpu_crtc
->pll_id
= dce_v8_0_pick_pll(crtc
);
2776 /* if we can't get a PPLL for a non-DP encoder, fail */
2777 if ((amdgpu_crtc
->pll_id
== ATOM_PPLL_INVALID
) &&
2778 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder
)))
2784 static int dce_v8_0_crtc_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2785 struct drm_framebuffer
*old_fb
)
2787 return dce_v8_0_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
2790 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc
*crtc
,
2791 struct drm_framebuffer
*fb
,
2792 int x
, int y
, enum mode_set_atomic state
)
2794 return dce_v8_0_crtc_do_set_base(crtc
, fb
, x
, y
, 1);
2797 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs
= {
2798 .dpms
= dce_v8_0_crtc_dpms
,
2799 .mode_fixup
= dce_v8_0_crtc_mode_fixup
,
2800 .mode_set
= dce_v8_0_crtc_mode_set
,
2801 .mode_set_base
= dce_v8_0_crtc_set_base
,
2802 .mode_set_base_atomic
= dce_v8_0_crtc_set_base_atomic
,
2803 .prepare
= dce_v8_0_crtc_prepare
,
2804 .commit
= dce_v8_0_crtc_commit
,
2805 .load_lut
= dce_v8_0_crtc_load_lut
,
2806 .disable
= dce_v8_0_crtc_disable
,
2809 static int dce_v8_0_crtc_init(struct amdgpu_device
*adev
, int index
)
2811 struct amdgpu_crtc
*amdgpu_crtc
;
2814 amdgpu_crtc
= kzalloc(sizeof(struct amdgpu_crtc
) +
2815 (AMDGPUFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
2816 if (amdgpu_crtc
== NULL
)
2819 drm_crtc_init(adev
->ddev
, &amdgpu_crtc
->base
, &dce_v8_0_crtc_funcs
);
2821 drm_mode_crtc_set_gamma_size(&amdgpu_crtc
->base
, 256);
2822 amdgpu_crtc
->crtc_id
= index
;
2823 adev
->mode_info
.crtcs
[index
] = amdgpu_crtc
;
2825 amdgpu_crtc
->max_cursor_width
= CIK_CURSOR_WIDTH
;
2826 amdgpu_crtc
->max_cursor_height
= CIK_CURSOR_HEIGHT
;
2827 adev
->ddev
->mode_config
.cursor_width
= amdgpu_crtc
->max_cursor_width
;
2828 adev
->ddev
->mode_config
.cursor_height
= amdgpu_crtc
->max_cursor_height
;
2830 for (i
= 0; i
< 256; i
++) {
2831 amdgpu_crtc
->lut_r
[i
] = i
<< 2;
2832 amdgpu_crtc
->lut_g
[i
] = i
<< 2;
2833 amdgpu_crtc
->lut_b
[i
] = i
<< 2;
2836 amdgpu_crtc
->crtc_offset
= crtc_offsets
[amdgpu_crtc
->crtc_id
];
2838 amdgpu_crtc
->pll_id
= ATOM_PPLL_INVALID
;
2839 amdgpu_crtc
->adjusted_clock
= 0;
2840 amdgpu_crtc
->encoder
= NULL
;
2841 amdgpu_crtc
->connector
= NULL
;
2842 drm_crtc_helper_add(&amdgpu_crtc
->base
, &dce_v8_0_crtc_helper_funcs
);
2847 static int dce_v8_0_early_init(void *handle
)
2849 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2851 adev
->audio_endpt_rreg
= &dce_v8_0_audio_endpt_rreg
;
2852 adev
->audio_endpt_wreg
= &dce_v8_0_audio_endpt_wreg
;
2854 dce_v8_0_set_display_funcs(adev
);
2855 dce_v8_0_set_irq_funcs(adev
);
2857 switch (adev
->asic_type
) {
2860 adev
->mode_info
.num_crtc
= 6;
2861 adev
->mode_info
.num_hpd
= 6;
2862 adev
->mode_info
.num_dig
= 6;
2865 adev
->mode_info
.num_crtc
= 4;
2866 adev
->mode_info
.num_hpd
= 6;
2867 adev
->mode_info
.num_dig
= 7;
2871 adev
->mode_info
.num_crtc
= 2;
2872 adev
->mode_info
.num_hpd
= 6;
2873 adev
->mode_info
.num_dig
= 6; /* ? */
2876 /* FIXME: not supported yet */
2883 static int dce_v8_0_sw_init(void *handle
)
2886 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2888 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2889 r
= amdgpu_irq_add_id(adev
, i
+ 1, &adev
->crtc_irq
);
2894 for (i
= 8; i
< 20; i
+= 2) {
2895 r
= amdgpu_irq_add_id(adev
, i
, &adev
->pageflip_irq
);
2901 r
= amdgpu_irq_add_id(adev
, 42, &adev
->hpd_irq
);
2905 adev
->ddev
->mode_config
.funcs
= &amdgpu_mode_funcs
;
2907 adev
->ddev
->mode_config
.async_page_flip
= true;
2909 adev
->ddev
->mode_config
.max_width
= 16384;
2910 adev
->ddev
->mode_config
.max_height
= 16384;
2912 adev
->ddev
->mode_config
.preferred_depth
= 24;
2913 adev
->ddev
->mode_config
.prefer_shadow
= 1;
2915 adev
->ddev
->mode_config
.fb_base
= adev
->mc
.aper_base
;
2917 r
= amdgpu_modeset_create_props(adev
);
2921 adev
->ddev
->mode_config
.max_width
= 16384;
2922 adev
->ddev
->mode_config
.max_height
= 16384;
2924 /* allocate crtcs */
2925 for (i
= 0; i
< adev
->mode_info
.num_crtc
; i
++) {
2926 r
= dce_v8_0_crtc_init(adev
, i
);
2931 if (amdgpu_atombios_get_connector_info_from_object_table(adev
))
2932 amdgpu_print_display_setup(adev
->ddev
);
2937 r
= dce_v8_0_afmt_init(adev
);
2941 r
= dce_v8_0_audio_init(adev
);
2945 drm_kms_helper_poll_init(adev
->ddev
);
2947 adev
->mode_info
.mode_config_initialized
= true;
2951 static int dce_v8_0_sw_fini(void *handle
)
2953 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2955 kfree(adev
->mode_info
.bios_hardcoded_edid
);
2957 drm_kms_helper_poll_fini(adev
->ddev
);
2959 dce_v8_0_audio_fini(adev
);
2961 dce_v8_0_afmt_fini(adev
);
2963 drm_mode_config_cleanup(adev
->ddev
);
2964 adev
->mode_info
.mode_config_initialized
= false;
2969 static int dce_v8_0_hw_init(void *handle
)
2972 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2974 /* init dig PHYs, disp eng pll */
2975 amdgpu_atombios_encoder_init_dig(adev
);
2976 amdgpu_atombios_crtc_set_disp_eng_pll(adev
, adev
->clock
.default_dispclk
);
2978 /* initialize hpd */
2979 dce_v8_0_hpd_init(adev
);
2981 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2982 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
2985 dce_v8_0_pageflip_interrupt_init(adev
);
2990 static int dce_v8_0_hw_fini(void *handle
)
2993 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
2995 dce_v8_0_hpd_fini(adev
);
2997 for (i
= 0; i
< adev
->mode_info
.audio
.num_pins
; i
++) {
2998 dce_v8_0_audio_enable(adev
, &adev
->mode_info
.audio
.pin
[i
], false);
3001 dce_v8_0_pageflip_interrupt_fini(adev
);
3006 static int dce_v8_0_suspend(void *handle
)
3008 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3010 amdgpu_atombios_scratch_regs_save(adev
);
3012 return dce_v8_0_hw_fini(handle
);
3015 static int dce_v8_0_resume(void *handle
)
3017 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3020 ret
= dce_v8_0_hw_init(handle
);
3022 amdgpu_atombios_scratch_regs_restore(adev
);
3024 /* turn on the BL */
3025 if (adev
->mode_info
.bl_encoder
) {
3026 u8 bl_level
= amdgpu_display_backlight_get_level(adev
,
3027 adev
->mode_info
.bl_encoder
);
3028 amdgpu_display_backlight_set_level(adev
, adev
->mode_info
.bl_encoder
,
3035 static bool dce_v8_0_is_idle(void *handle
)
3040 static int dce_v8_0_wait_for_idle(void *handle
)
3045 static int dce_v8_0_soft_reset(void *handle
)
3047 u32 srbm_soft_reset
= 0, tmp
;
3048 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
3050 if (dce_v8_0_is_display_hung(adev
))
3051 srbm_soft_reset
|= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK
;
3053 if (srbm_soft_reset
) {
3054 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3055 tmp
|= srbm_soft_reset
;
3056 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
3057 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3058 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3062 tmp
&= ~srbm_soft_reset
;
3063 WREG32(mmSRBM_SOFT_RESET
, tmp
);
3064 tmp
= RREG32(mmSRBM_SOFT_RESET
);
3066 /* Wait a little for things to settle down */
3072 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device
*adev
,
3074 enum amdgpu_interrupt_state state
)
3076 u32 reg_block
, lb_interrupt_mask
;
3078 if (crtc
>= adev
->mode_info
.num_crtc
) {
3079 DRM_DEBUG("invalid crtc %d\n", crtc
);
3085 reg_block
= CRTC0_REGISTER_OFFSET
;
3088 reg_block
= CRTC1_REGISTER_OFFSET
;
3091 reg_block
= CRTC2_REGISTER_OFFSET
;
3094 reg_block
= CRTC3_REGISTER_OFFSET
;
3097 reg_block
= CRTC4_REGISTER_OFFSET
;
3100 reg_block
= CRTC5_REGISTER_OFFSET
;
3103 DRM_DEBUG("invalid crtc %d\n", crtc
);
3108 case AMDGPU_IRQ_STATE_DISABLE
:
3109 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3110 lb_interrupt_mask
&= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK
;
3111 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3113 case AMDGPU_IRQ_STATE_ENABLE
:
3114 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3115 lb_interrupt_mask
|= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK
;
3116 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3123 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device
*adev
,
3125 enum amdgpu_interrupt_state state
)
3127 u32 reg_block
, lb_interrupt_mask
;
3129 if (crtc
>= adev
->mode_info
.num_crtc
) {
3130 DRM_DEBUG("invalid crtc %d\n", crtc
);
3136 reg_block
= CRTC0_REGISTER_OFFSET
;
3139 reg_block
= CRTC1_REGISTER_OFFSET
;
3142 reg_block
= CRTC2_REGISTER_OFFSET
;
3145 reg_block
= CRTC3_REGISTER_OFFSET
;
3148 reg_block
= CRTC4_REGISTER_OFFSET
;
3151 reg_block
= CRTC5_REGISTER_OFFSET
;
3154 DRM_DEBUG("invalid crtc %d\n", crtc
);
3159 case AMDGPU_IRQ_STATE_DISABLE
:
3160 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3161 lb_interrupt_mask
&= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
;
3162 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3164 case AMDGPU_IRQ_STATE_ENABLE
:
3165 lb_interrupt_mask
= RREG32(mmLB_INTERRUPT_MASK
+ reg_block
);
3166 lb_interrupt_mask
|= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
;
3167 WREG32(mmLB_INTERRUPT_MASK
+ reg_block
, lb_interrupt_mask
);
3174 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device
*adev
,
3175 struct amdgpu_irq_src
*src
,
3177 enum amdgpu_interrupt_state state
)
3179 u32 dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
;
3183 dc_hpd_int_cntl_reg
= mmDC_HPD1_INT_CONTROL
;
3186 dc_hpd_int_cntl_reg
= mmDC_HPD2_INT_CONTROL
;
3189 dc_hpd_int_cntl_reg
= mmDC_HPD3_INT_CONTROL
;
3192 dc_hpd_int_cntl_reg
= mmDC_HPD4_INT_CONTROL
;
3195 dc_hpd_int_cntl_reg
= mmDC_HPD5_INT_CONTROL
;
3198 dc_hpd_int_cntl_reg
= mmDC_HPD6_INT_CONTROL
;
3201 DRM_DEBUG("invalid hdp %d\n", type
);
3206 case AMDGPU_IRQ_STATE_DISABLE
:
3207 dc_hpd_int_cntl
= RREG32(dc_hpd_int_cntl_reg
);
3208 dc_hpd_int_cntl
&= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
;
3209 WREG32(dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
);
3211 case AMDGPU_IRQ_STATE_ENABLE
:
3212 dc_hpd_int_cntl
= RREG32(dc_hpd_int_cntl_reg
);
3213 dc_hpd_int_cntl
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK
;
3214 WREG32(dc_hpd_int_cntl_reg
, dc_hpd_int_cntl
);
3223 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device
*adev
,
3224 struct amdgpu_irq_src
*src
,
3226 enum amdgpu_interrupt_state state
)
3229 case AMDGPU_CRTC_IRQ_VBLANK1
:
3230 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 0, state
);
3232 case AMDGPU_CRTC_IRQ_VBLANK2
:
3233 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 1, state
);
3235 case AMDGPU_CRTC_IRQ_VBLANK3
:
3236 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 2, state
);
3238 case AMDGPU_CRTC_IRQ_VBLANK4
:
3239 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 3, state
);
3241 case AMDGPU_CRTC_IRQ_VBLANK5
:
3242 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 4, state
);
3244 case AMDGPU_CRTC_IRQ_VBLANK6
:
3245 dce_v8_0_set_crtc_vblank_interrupt_state(adev
, 5, state
);
3247 case AMDGPU_CRTC_IRQ_VLINE1
:
3248 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 0, state
);
3250 case AMDGPU_CRTC_IRQ_VLINE2
:
3251 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 1, state
);
3253 case AMDGPU_CRTC_IRQ_VLINE3
:
3254 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 2, state
);
3256 case AMDGPU_CRTC_IRQ_VLINE4
:
3257 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 3, state
);
3259 case AMDGPU_CRTC_IRQ_VLINE5
:
3260 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 4, state
);
3262 case AMDGPU_CRTC_IRQ_VLINE6
:
3263 dce_v8_0_set_crtc_vline_interrupt_state(adev
, 5, state
);
3271 static int dce_v8_0_crtc_irq(struct amdgpu_device
*adev
,
3272 struct amdgpu_irq_src
*source
,
3273 struct amdgpu_iv_entry
*entry
)
3275 unsigned crtc
= entry
->src_id
- 1;
3276 uint32_t disp_int
= RREG32(interrupt_status_offsets
[crtc
].reg
);
3277 unsigned irq_type
= amdgpu_crtc_idx_to_irq_type(adev
, crtc
);
3279 switch (entry
->src_data
) {
3280 case 0: /* vblank */
3281 if (disp_int
& interrupt_status_offsets
[crtc
].vblank
)
3282 WREG32(mmLB_VBLANK_STATUS
+ crtc_offsets
[crtc
], LB_VBLANK_STATUS__VBLANK_ACK_MASK
);
3284 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3286 if (amdgpu_irq_enabled(adev
, source
, irq_type
)) {
3287 drm_handle_vblank(adev
->ddev
, crtc
);
3289 DRM_DEBUG("IH: D%d vblank\n", crtc
+ 1);
3293 if (disp_int
& interrupt_status_offsets
[crtc
].vline
)
3294 WREG32(mmLB_VLINE_STATUS
+ crtc_offsets
[crtc
], LB_VLINE_STATUS__VLINE_ACK_MASK
);
3296 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3298 DRM_DEBUG("IH: D%d vline\n", crtc
+ 1);
3302 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3309 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device
*adev
,
3310 struct amdgpu_irq_src
*src
,
3312 enum amdgpu_interrupt_state state
)
3316 if (type
>= adev
->mode_info
.num_crtc
) {
3317 DRM_ERROR("invalid pageflip crtc %d\n", type
);
3321 reg
= RREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
]);
3322 if (state
== AMDGPU_IRQ_STATE_DISABLE
)
3323 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3324 reg
& ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3326 WREG32(mmGRPH_INTERRUPT_CONTROL
+ crtc_offsets
[type
],
3327 reg
| GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
);
3332 static int dce_v8_0_pageflip_irq(struct amdgpu_device
*adev
,
3333 struct amdgpu_irq_src
*source
,
3334 struct amdgpu_iv_entry
*entry
)
3336 unsigned long flags
;
3338 struct amdgpu_crtc
*amdgpu_crtc
;
3339 struct amdgpu_flip_work
*works
;
3341 crtc_id
= (entry
->src_id
- 8) >> 1;
3342 amdgpu_crtc
= adev
->mode_info
.crtcs
[crtc_id
];
3344 if (crtc_id
>= adev
->mode_info
.num_crtc
) {
3345 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id
);
3349 if (RREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
]) &
3350 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
)
3351 WREG32(mmGRPH_INTERRUPT_STATUS
+ crtc_offsets
[crtc_id
],
3352 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
);
3354 /* IRQ could occur when in initial stage */
3355 if (amdgpu_crtc
== NULL
)
3358 spin_lock_irqsave(&adev
->ddev
->event_lock
, flags
);
3359 works
= amdgpu_crtc
->pflip_works
;
3360 if (amdgpu_crtc
->pflip_status
!= AMDGPU_FLIP_SUBMITTED
){
3361 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3362 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3363 amdgpu_crtc
->pflip_status
,
3364 AMDGPU_FLIP_SUBMITTED
);
3365 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3369 /* page flip completed. clean up */
3370 amdgpu_crtc
->pflip_status
= AMDGPU_FLIP_NONE
;
3371 amdgpu_crtc
->pflip_works
= NULL
;
3373 /* wakeup usersapce */
3375 drm_crtc_send_vblank_event(&amdgpu_crtc
->base
, works
->event
);
3377 spin_unlock_irqrestore(&adev
->ddev
->event_lock
, flags
);
3379 drm_vblank_put(adev
->ddev
, amdgpu_crtc
->crtc_id
);
3380 schedule_work(&works
->unpin_work
);
3385 static int dce_v8_0_hpd_irq(struct amdgpu_device
*adev
,
3386 struct amdgpu_irq_src
*source
,
3387 struct amdgpu_iv_entry
*entry
)
3389 uint32_t disp_int
, mask
, int_control
, tmp
;
3392 if (entry
->src_data
>= adev
->mode_info
.num_hpd
) {
3393 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry
->src_id
, entry
->src_data
);
3397 hpd
= entry
->src_data
;
3398 disp_int
= RREG32(interrupt_status_offsets
[hpd
].reg
);
3399 mask
= interrupt_status_offsets
[hpd
].hpd
;
3400 int_control
= hpd_int_control_offsets
[hpd
];
3402 if (disp_int
& mask
) {
3403 tmp
= RREG32(int_control
);
3404 tmp
|= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK
;
3405 WREG32(int_control
, tmp
);
3406 schedule_work(&adev
->hotplug_work
);
3407 DRM_DEBUG("IH: HPD%d\n", hpd
+ 1);
3414 static int dce_v8_0_set_clockgating_state(void *handle
,
3415 enum amd_clockgating_state state
)
3420 static int dce_v8_0_set_powergating_state(void *handle
,
3421 enum amd_powergating_state state
)
3426 const struct amd_ip_funcs dce_v8_0_ip_funcs
= {
3428 .early_init
= dce_v8_0_early_init
,
3430 .sw_init
= dce_v8_0_sw_init
,
3431 .sw_fini
= dce_v8_0_sw_fini
,
3432 .hw_init
= dce_v8_0_hw_init
,
3433 .hw_fini
= dce_v8_0_hw_fini
,
3434 .suspend
= dce_v8_0_suspend
,
3435 .resume
= dce_v8_0_resume
,
3436 .is_idle
= dce_v8_0_is_idle
,
3437 .wait_for_idle
= dce_v8_0_wait_for_idle
,
3438 .soft_reset
= dce_v8_0_soft_reset
,
3439 .set_clockgating_state
= dce_v8_0_set_clockgating_state
,
3440 .set_powergating_state
= dce_v8_0_set_powergating_state
,
3444 dce_v8_0_encoder_mode_set(struct drm_encoder
*encoder
,
3445 struct drm_display_mode
*mode
,
3446 struct drm_display_mode
*adjusted_mode
)
3448 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3450 amdgpu_encoder
->pixel_clock
= adjusted_mode
->clock
;
3452 /* need to call this here rather than in prepare() since we need some crtc info */
3453 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3455 /* set scaler clears this on some chips */
3456 dce_v8_0_set_interleave(encoder
->crtc
, mode
);
3458 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
3459 dce_v8_0_afmt_enable(encoder
, true);
3460 dce_v8_0_afmt_setmode(encoder
, adjusted_mode
);
3464 static void dce_v8_0_encoder_prepare(struct drm_encoder
*encoder
)
3466 struct amdgpu_device
*adev
= encoder
->dev
->dev_private
;
3467 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3468 struct drm_connector
*connector
= amdgpu_get_connector_for_encoder(encoder
);
3470 if ((amdgpu_encoder
->active_device
&
3471 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) ||
3472 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder
) !=
3473 ENCODER_OBJECT_ID_NONE
)) {
3474 struct amdgpu_encoder_atom_dig
*dig
= amdgpu_encoder
->enc_priv
;
3476 dig
->dig_encoder
= dce_v8_0_pick_dig_encoder(encoder
);
3477 if (amdgpu_encoder
->active_device
& ATOM_DEVICE_DFP_SUPPORT
)
3478 dig
->afmt
= adev
->mode_info
.afmt
[dig
->dig_encoder
];
3482 amdgpu_atombios_scratch_regs_lock(adev
, true);
3485 struct amdgpu_connector
*amdgpu_connector
= to_amdgpu_connector(connector
);
3487 /* select the clock/data port if it uses a router */
3488 if (amdgpu_connector
->router
.cd_valid
)
3489 amdgpu_i2c_router_select_cd_port(amdgpu_connector
);
3491 /* turn eDP panel on for mode set */
3492 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
3493 amdgpu_atombios_encoder_set_edp_panel_power(connector
,
3494 ATOM_TRANSMITTER_ACTION_POWER_ON
);
3497 /* this is needed for the pll/ss setup to work correctly in some cases */
3498 amdgpu_atombios_encoder_set_crtc_source(encoder
);
3499 /* set up the FMT blocks */
3500 dce_v8_0_program_fmt(encoder
);
3503 static void dce_v8_0_encoder_commit(struct drm_encoder
*encoder
)
3505 struct drm_device
*dev
= encoder
->dev
;
3506 struct amdgpu_device
*adev
= dev
->dev_private
;
3508 /* need to call this here as we need the crtc set up */
3509 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
3510 amdgpu_atombios_scratch_regs_lock(adev
, false);
3513 static void dce_v8_0_encoder_disable(struct drm_encoder
*encoder
)
3515 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3516 struct amdgpu_encoder_atom_dig
*dig
;
3518 amdgpu_atombios_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
3520 if (amdgpu_atombios_encoder_is_digital(encoder
)) {
3521 if (amdgpu_atombios_encoder_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
3522 dce_v8_0_afmt_enable(encoder
, false);
3523 dig
= amdgpu_encoder
->enc_priv
;
3524 dig
->dig_encoder
= -1;
3526 amdgpu_encoder
->active_device
= 0;
3529 /* these are handled by the primary encoders */
3530 static void dce_v8_0_ext_prepare(struct drm_encoder
*encoder
)
3535 static void dce_v8_0_ext_commit(struct drm_encoder
*encoder
)
3541 dce_v8_0_ext_mode_set(struct drm_encoder
*encoder
,
3542 struct drm_display_mode
*mode
,
3543 struct drm_display_mode
*adjusted_mode
)
3548 static void dce_v8_0_ext_disable(struct drm_encoder
*encoder
)
3554 dce_v8_0_ext_dpms(struct drm_encoder
*encoder
, int mode
)
3559 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs
= {
3560 .dpms
= dce_v8_0_ext_dpms
,
3561 .prepare
= dce_v8_0_ext_prepare
,
3562 .mode_set
= dce_v8_0_ext_mode_set
,
3563 .commit
= dce_v8_0_ext_commit
,
3564 .disable
= dce_v8_0_ext_disable
,
3565 /* no detect for TMDS/LVDS yet */
3568 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs
= {
3569 .dpms
= amdgpu_atombios_encoder_dpms
,
3570 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3571 .prepare
= dce_v8_0_encoder_prepare
,
3572 .mode_set
= dce_v8_0_encoder_mode_set
,
3573 .commit
= dce_v8_0_encoder_commit
,
3574 .disable
= dce_v8_0_encoder_disable
,
3575 .detect
= amdgpu_atombios_encoder_dig_detect
,
3578 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs
= {
3579 .dpms
= amdgpu_atombios_encoder_dpms
,
3580 .mode_fixup
= amdgpu_atombios_encoder_mode_fixup
,
3581 .prepare
= dce_v8_0_encoder_prepare
,
3582 .mode_set
= dce_v8_0_encoder_mode_set
,
3583 .commit
= dce_v8_0_encoder_commit
,
3584 .detect
= amdgpu_atombios_encoder_dac_detect
,
3587 static void dce_v8_0_encoder_destroy(struct drm_encoder
*encoder
)
3589 struct amdgpu_encoder
*amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3590 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3591 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder
);
3592 kfree(amdgpu_encoder
->enc_priv
);
3593 drm_encoder_cleanup(encoder
);
3594 kfree(amdgpu_encoder
);
3597 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs
= {
3598 .destroy
= dce_v8_0_encoder_destroy
,
3601 static void dce_v8_0_encoder_add(struct amdgpu_device
*adev
,
3602 uint32_t encoder_enum
,
3603 uint32_t supported_device
,
3606 struct drm_device
*dev
= adev
->ddev
;
3607 struct drm_encoder
*encoder
;
3608 struct amdgpu_encoder
*amdgpu_encoder
;
3610 /* see if we already added it */
3611 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3612 amdgpu_encoder
= to_amdgpu_encoder(encoder
);
3613 if (amdgpu_encoder
->encoder_enum
== encoder_enum
) {
3614 amdgpu_encoder
->devices
|= supported_device
;
3621 amdgpu_encoder
= kzalloc(sizeof(struct amdgpu_encoder
), GFP_KERNEL
);
3622 if (!amdgpu_encoder
)
3625 encoder
= &amdgpu_encoder
->base
;
3626 switch (adev
->mode_info
.num_crtc
) {
3628 encoder
->possible_crtcs
= 0x1;
3632 encoder
->possible_crtcs
= 0x3;
3635 encoder
->possible_crtcs
= 0xf;
3638 encoder
->possible_crtcs
= 0x3f;
3642 amdgpu_encoder
->enc_priv
= NULL
;
3644 amdgpu_encoder
->encoder_enum
= encoder_enum
;
3645 amdgpu_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
3646 amdgpu_encoder
->devices
= supported_device
;
3647 amdgpu_encoder
->rmx_type
= RMX_OFF
;
3648 amdgpu_encoder
->underscan_type
= UNDERSCAN_OFF
;
3649 amdgpu_encoder
->is_ext_encoder
= false;
3650 amdgpu_encoder
->caps
= caps
;
3652 switch (amdgpu_encoder
->encoder_id
) {
3653 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
3654 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
3655 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3656 DRM_MODE_ENCODER_DAC
, NULL
);
3657 drm_encoder_helper_add(encoder
, &dce_v8_0_dac_helper_funcs
);
3659 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
3660 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
3661 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
3662 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
3663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3
:
3664 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
3665 amdgpu_encoder
->rmx_type
= RMX_FULL
;
3666 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3667 DRM_MODE_ENCODER_LVDS
, NULL
);
3668 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder
);
3669 } else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
3670 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3671 DRM_MODE_ENCODER_DAC
, NULL
);
3672 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3674 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3675 DRM_MODE_ENCODER_TMDS
, NULL
);
3676 amdgpu_encoder
->enc_priv
= amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder
);
3678 drm_encoder_helper_add(encoder
, &dce_v8_0_dig_helper_funcs
);
3680 case ENCODER_OBJECT_ID_SI170B
:
3681 case ENCODER_OBJECT_ID_CH7303
:
3682 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
3683 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
3684 case ENCODER_OBJECT_ID_TITFP513
:
3685 case ENCODER_OBJECT_ID_VT1623
:
3686 case ENCODER_OBJECT_ID_HDMI_SI1930
:
3687 case ENCODER_OBJECT_ID_TRAVIS
:
3688 case ENCODER_OBJECT_ID_NUTMEG
:
3689 /* these are handled by the primary encoders */
3690 amdgpu_encoder
->is_ext_encoder
= true;
3691 if (amdgpu_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
3692 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3693 DRM_MODE_ENCODER_LVDS
, NULL
);
3694 else if (amdgpu_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
3695 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3696 DRM_MODE_ENCODER_DAC
, NULL
);
3698 drm_encoder_init(dev
, encoder
, &dce_v8_0_encoder_funcs
,
3699 DRM_MODE_ENCODER_TMDS
, NULL
);
3700 drm_encoder_helper_add(encoder
, &dce_v8_0_ext_helper_funcs
);
3705 static const struct amdgpu_display_funcs dce_v8_0_display_funcs
= {
3706 .set_vga_render_state
= &dce_v8_0_set_vga_render_state
,
3707 .bandwidth_update
= &dce_v8_0_bandwidth_update
,
3708 .vblank_get_counter
= &dce_v8_0_vblank_get_counter
,
3709 .vblank_wait
= &dce_v8_0_vblank_wait
,
3710 .is_display_hung
= &dce_v8_0_is_display_hung
,
3711 .backlight_set_level
= &amdgpu_atombios_encoder_set_backlight_level
,
3712 .backlight_get_level
= &amdgpu_atombios_encoder_get_backlight_level
,
3713 .hpd_sense
= &dce_v8_0_hpd_sense
,
3714 .hpd_set_polarity
= &dce_v8_0_hpd_set_polarity
,
3715 .hpd_get_gpio_reg
= &dce_v8_0_hpd_get_gpio_reg
,
3716 .page_flip
= &dce_v8_0_page_flip
,
3717 .page_flip_get_scanoutpos
= &dce_v8_0_crtc_get_scanoutpos
,
3718 .add_encoder
= &dce_v8_0_encoder_add
,
3719 .add_connector
= &amdgpu_connector_add
,
3720 .stop_mc_access
= &dce_v8_0_stop_mc_access
,
3721 .resume_mc_access
= &dce_v8_0_resume_mc_access
,
3724 static void dce_v8_0_set_display_funcs(struct amdgpu_device
*adev
)
3726 if (adev
->mode_info
.funcs
== NULL
)
3727 adev
->mode_info
.funcs
= &dce_v8_0_display_funcs
;
3730 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs
= {
3731 .set
= dce_v8_0_set_crtc_interrupt_state
,
3732 .process
= dce_v8_0_crtc_irq
,
3735 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs
= {
3736 .set
= dce_v8_0_set_pageflip_interrupt_state
,
3737 .process
= dce_v8_0_pageflip_irq
,
3740 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs
= {
3741 .set
= dce_v8_0_set_hpd_interrupt_state
,
3742 .process
= dce_v8_0_hpd_irq
,
3745 static void dce_v8_0_set_irq_funcs(struct amdgpu_device
*adev
)
3747 adev
->crtc_irq
.num_types
= AMDGPU_CRTC_IRQ_LAST
;
3748 adev
->crtc_irq
.funcs
= &dce_v8_0_crtc_irq_funcs
;
3750 adev
->pageflip_irq
.num_types
= AMDGPU_PAGEFLIP_IRQ_LAST
;
3751 adev
->pageflip_irq
.funcs
= &dce_v8_0_pageflip_irq_funcs
;
3753 adev
->hpd_irq
.num_types
= AMDGPU_HPD_LAST
;
3754 adev
->hpd_irq
.funcs
= &dce_v8_0_hpd_irq_funcs
;