2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
27 #include "amdgpu_ucode.h"
29 #include "gmc/gmc_8_1_d.h"
30 #include "gmc/gmc_8_1_sh_mask.h"
32 #include "bif/bif_5_0_d.h"
33 #include "bif/bif_5_0_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device
*adev
);
43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device
*adev
);
44 static int gmc_v8_0_wait_for_idle(void *handle
);
46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
50 static const u32 golden_settings_tonga_a11
[] =
52 mmMC_ARB_WTM_GRPWT_RD
, 0x00000003, 0x00000000,
53 mmMC_HUB_RDREQ_DMIF_LIMIT
, 0x0000007f, 0x00000028,
54 mmMC_HUB_WDP_UMC
, 0x00007fb6, 0x00000991,
55 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
56 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
57 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
58 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
61 static const u32 tonga_mgcg_cgcg_init
[] =
63 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
66 static const u32 golden_settings_fiji_a10
[] =
68 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
69 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
70 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
71 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
74 static const u32 fiji_mgcg_cgcg_init
[] =
76 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
79 static const u32 golden_settings_polaris11_a11
[] =
81 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
82 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff
87 static const u32 golden_settings_polaris10_a11
[] =
89 mmMC_ARB_WTM_GRPWT_RD
, 0x00000003, 0x00000000,
90 mmVM_PRT_APERTURE0_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
91 mmVM_PRT_APERTURE1_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
92 mmVM_PRT_APERTURE2_LOW_ADDR
, 0x0fffffff, 0x0fffffff,
93 mmVM_PRT_APERTURE3_LOW_ADDR
, 0x0fffffff, 0x0fffffff
96 static const u32 cz_mgcg_cgcg_init
[] =
98 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
101 static const u32 stoney_mgcg_cgcg_init
[] =
103 mmMC_MEM_POWER_LS
, 0xffffffff, 0x00000104
106 static const u32 golden_settings_stoney_common
[] =
108 mmMC_HUB_RDREQ_UVD
, MC_HUB_RDREQ_UVD__PRESCALE_MASK
, 0x00000004,
109 mmMC_RD_GRP_OTH
, MC_RD_GRP_OTH__UVD_MASK
, 0x00600000
112 static void gmc_v8_0_init_golden_registers(struct amdgpu_device
*adev
)
114 switch (adev
->asic_type
) {
116 amdgpu_program_register_sequence(adev
,
118 (const u32
)ARRAY_SIZE(fiji_mgcg_cgcg_init
));
119 amdgpu_program_register_sequence(adev
,
120 golden_settings_fiji_a10
,
121 (const u32
)ARRAY_SIZE(golden_settings_fiji_a10
));
124 amdgpu_program_register_sequence(adev
,
125 tonga_mgcg_cgcg_init
,
126 (const u32
)ARRAY_SIZE(tonga_mgcg_cgcg_init
));
127 amdgpu_program_register_sequence(adev
,
128 golden_settings_tonga_a11
,
129 (const u32
)ARRAY_SIZE(golden_settings_tonga_a11
));
132 amdgpu_program_register_sequence(adev
,
133 golden_settings_polaris11_a11
,
134 (const u32
)ARRAY_SIZE(golden_settings_polaris11_a11
));
137 amdgpu_program_register_sequence(adev
,
138 golden_settings_polaris10_a11
,
139 (const u32
)ARRAY_SIZE(golden_settings_polaris10_a11
));
142 amdgpu_program_register_sequence(adev
,
144 (const u32
)ARRAY_SIZE(cz_mgcg_cgcg_init
));
147 amdgpu_program_register_sequence(adev
,
148 stoney_mgcg_cgcg_init
,
149 (const u32
)ARRAY_SIZE(stoney_mgcg_cgcg_init
));
150 amdgpu_program_register_sequence(adev
,
151 golden_settings_stoney_common
,
152 (const u32
)ARRAY_SIZE(golden_settings_stoney_common
));
159 static void gmc_v8_0_mc_stop(struct amdgpu_device
*adev
,
160 struct amdgpu_mode_mc_save
*save
)
164 if (adev
->mode_info
.num_crtc
)
165 amdgpu_display_stop_mc_access(adev
, save
);
167 gmc_v8_0_wait_for_idle(adev
);
169 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
170 if (REG_GET_FIELD(blackout
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
) != 1) {
171 /* Block CPU access */
172 WREG32(mmBIF_FB_EN
, 0);
173 /* blackout the MC */
174 blackout
= REG_SET_FIELD(blackout
,
175 MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 1);
176 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
);
178 /* wait for the MC to settle */
182 static void gmc_v8_0_mc_resume(struct amdgpu_device
*adev
,
183 struct amdgpu_mode_mc_save
*save
)
187 /* unblackout the MC */
188 tmp
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
189 tmp
= REG_SET_FIELD(tmp
, MC_SHARED_BLACKOUT_CNTL
, BLACKOUT_MODE
, 0);
190 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, tmp
);
191 /* allow CPU access */
192 tmp
= REG_SET_FIELD(0, BIF_FB_EN
, FB_READ_EN
, 1);
193 tmp
= REG_SET_FIELD(tmp
, BIF_FB_EN
, FB_WRITE_EN
, 1);
194 WREG32(mmBIF_FB_EN
, tmp
);
196 if (adev
->mode_info
.num_crtc
)
197 amdgpu_display_resume_mc_access(adev
, save
);
201 * gmc_v8_0_init_microcode - load ucode images from disk
203 * @adev: amdgpu_device pointer
205 * Use the firmware interface to load the ucode images into
206 * the driver (not loaded into hw).
207 * Returns 0 on success, error on failure.
209 static int gmc_v8_0_init_microcode(struct amdgpu_device
*adev
)
211 const char *chip_name
;
217 switch (adev
->asic_type
) {
222 chip_name
= "polaris11";
225 chip_name
= "polaris10";
234 snprintf(fw_name
, sizeof(fw_name
), "amdgpu/%s_mc.bin", chip_name
);
235 err
= request_firmware(&adev
->mc
.fw
, fw_name
, adev
->dev
);
238 err
= amdgpu_ucode_validate(adev
->mc
.fw
);
243 "mc: Failed to load firmware \"%s\"\n",
245 release_firmware(adev
->mc
.fw
);
252 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw
254 * @adev: amdgpu_device pointer
256 * Load the GDDR MC ucode into the hw (CIK).
257 * Returns 0 on success, error on failure.
259 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device
*adev
)
261 const struct mc_firmware_header_v1_0
*hdr
;
262 const __le32
*fw_data
= NULL
;
263 const __le32
*io_mc_regs
= NULL
;
264 u32 running
, blackout
= 0;
265 int i
, ucode_size
, regs_size
;
270 /* Skip MC ucode loading on SR-IOV capable boards.
271 * vbios does this for us in asic_init in that case.
273 if (adev
->virtualization
.supports_sr_iov
)
276 hdr
= (const struct mc_firmware_header_v1_0
*)adev
->mc
.fw
->data
;
277 amdgpu_ucode_print_mc_hdr(&hdr
->header
);
279 adev
->mc
.fw_version
= le32_to_cpu(hdr
->header
.ucode_version
);
280 regs_size
= le32_to_cpu(hdr
->io_debug_size_bytes
) / (4 * 2);
281 io_mc_regs
= (const __le32
*)
282 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->io_debug_array_offset_bytes
));
283 ucode_size
= le32_to_cpu(hdr
->header
.ucode_size_bytes
) / 4;
284 fw_data
= (const __le32
*)
285 (adev
->mc
.fw
->data
+ le32_to_cpu(hdr
->header
.ucode_array_offset_bytes
));
287 running
= REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL
), MC_SEQ_SUP_CNTL
, RUN
);
291 blackout
= RREG32(mmMC_SHARED_BLACKOUT_CNTL
);
292 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
| 1);
295 /* reset the engine and set to writable */
296 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
297 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000010);
299 /* load mc io regs */
300 for (i
= 0; i
< regs_size
; i
++) {
301 WREG32(mmMC_SEQ_IO_DEBUG_INDEX
, le32_to_cpup(io_mc_regs
++));
302 WREG32(mmMC_SEQ_IO_DEBUG_DATA
, le32_to_cpup(io_mc_regs
++));
304 /* load the MC ucode */
305 for (i
= 0; i
< ucode_size
; i
++)
306 WREG32(mmMC_SEQ_SUP_PGM
, le32_to_cpup(fw_data
++));
308 /* put the engine back into the active state */
309 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000008);
310 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000004);
311 WREG32(mmMC_SEQ_SUP_CNTL
, 0x00000001);
313 /* wait for training to complete */
314 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
315 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
),
316 MC_SEQ_TRAIN_WAKEUP_CNTL
, TRAIN_DONE_D0
))
320 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
321 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL
),
322 MC_SEQ_TRAIN_WAKEUP_CNTL
, TRAIN_DONE_D1
))
328 WREG32(mmMC_SHARED_BLACKOUT_CNTL
, blackout
);
334 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device
*adev
,
335 struct amdgpu_mc
*mc
)
337 if (mc
->mc_vram_size
> 0xFFC0000000ULL
) {
338 /* leave room for at least 1024M GTT */
339 dev_warn(adev
->dev
, "limiting VRAM\n");
340 mc
->real_vram_size
= 0xFFC0000000ULL
;
341 mc
->mc_vram_size
= 0xFFC0000000ULL
;
343 amdgpu_vram_location(adev
, &adev
->mc
, 0);
344 adev
->mc
.gtt_base_align
= 0;
345 amdgpu_gtt_location(adev
, mc
);
349 * gmc_v8_0_mc_program - program the GPU memory controller
351 * @adev: amdgpu_device pointer
353 * Set the location of vram, gart, and AGP in the GPU's
354 * physical address space (CIK).
356 static void gmc_v8_0_mc_program(struct amdgpu_device
*adev
)
358 struct amdgpu_mode_mc_save save
;
363 for (i
= 0, j
= 0; i
< 32; i
++, j
+= 0x6) {
364 WREG32((0xb05 + j
), 0x00000000);
365 WREG32((0xb06 + j
), 0x00000000);
366 WREG32((0xb07 + j
), 0x00000000);
367 WREG32((0xb08 + j
), 0x00000000);
368 WREG32((0xb09 + j
), 0x00000000);
370 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL
, 0);
372 if (adev
->mode_info
.num_crtc
)
373 amdgpu_display_set_vga_render_state(adev
, false);
375 gmc_v8_0_mc_stop(adev
, &save
);
376 if (gmc_v8_0_wait_for_idle((void *)adev
)) {
377 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
379 /* Update configuration */
380 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR
,
381 adev
->mc
.vram_start
>> 12);
382 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR
,
383 adev
->mc
.vram_end
>> 12);
384 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
,
385 adev
->vram_scratch
.gpu_addr
>> 12);
386 tmp
= ((adev
->mc
.vram_end
>> 24) & 0xFFFF) << 16;
387 tmp
|= ((adev
->mc
.vram_start
>> 24) & 0xFFFF);
388 WREG32(mmMC_VM_FB_LOCATION
, tmp
);
389 /* XXX double check these! */
390 WREG32(mmHDP_NONSURFACE_BASE
, (adev
->mc
.vram_start
>> 8));
391 WREG32(mmHDP_NONSURFACE_INFO
, (2 << 7) | (1 << 30));
392 WREG32(mmHDP_NONSURFACE_SIZE
, 0x3FFFFFFF);
393 WREG32(mmMC_VM_AGP_BASE
, 0);
394 WREG32(mmMC_VM_AGP_TOP
, 0x0FFFFFFF);
395 WREG32(mmMC_VM_AGP_BOT
, 0x0FFFFFFF);
396 if (gmc_v8_0_wait_for_idle((void *)adev
)) {
397 dev_warn(adev
->dev
, "Wait for MC idle timedout !\n");
399 gmc_v8_0_mc_resume(adev
, &save
);
401 WREG32(mmBIF_FB_EN
, BIF_FB_EN__FB_READ_EN_MASK
| BIF_FB_EN__FB_WRITE_EN_MASK
);
403 tmp
= RREG32(mmHDP_MISC_CNTL
);
404 tmp
= REG_SET_FIELD(tmp
, HDP_MISC_CNTL
, FLUSH_INVALIDATE_CACHE
, 0);
405 WREG32(mmHDP_MISC_CNTL
, tmp
);
407 tmp
= RREG32(mmHDP_HOST_PATH_CNTL
);
408 WREG32(mmHDP_HOST_PATH_CNTL
, tmp
);
412 * gmc_v8_0_mc_init - initialize the memory controller driver params
414 * @adev: amdgpu_device pointer
416 * Look up the amount of vram, vram width, and decide how to place
417 * vram and gart within the GPU's physical address space (CIK).
418 * Returns 0 for success.
420 static int gmc_v8_0_mc_init(struct amdgpu_device
*adev
)
423 int chansize
, numchan
;
425 /* Get VRAM informations */
426 tmp
= RREG32(mmMC_ARB_RAMCFG
);
427 if (REG_GET_FIELD(tmp
, MC_ARB_RAMCFG
, CHANSIZE
)) {
432 tmp
= RREG32(mmMC_SHARED_CHMAP
);
433 switch (REG_GET_FIELD(tmp
, MC_SHARED_CHMAP
, NOOFCHAN
)) {
463 adev
->mc
.vram_width
= numchan
* chansize
;
464 /* Could aper size report 0 ? */
465 adev
->mc
.aper_base
= pci_resource_start(adev
->pdev
, 0);
466 adev
->mc
.aper_size
= pci_resource_len(adev
->pdev
, 0);
467 /* size in MB on si */
468 adev
->mc
.mc_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
469 adev
->mc
.real_vram_size
= RREG32(mmCONFIG_MEMSIZE
) * 1024ULL * 1024ULL;
470 adev
->mc
.visible_vram_size
= adev
->mc
.aper_size
;
472 /* In case the PCI BAR is larger than the actual amount of vram */
473 if (adev
->mc
.visible_vram_size
> adev
->mc
.real_vram_size
)
474 adev
->mc
.visible_vram_size
= adev
->mc
.real_vram_size
;
476 /* unless the user had overridden it, set the gart
477 * size equal to the 1024 or vram, whichever is larger.
479 if (amdgpu_gart_size
== -1)
480 adev
->mc
.gtt_size
= max((1024ULL << 20), adev
->mc
.mc_vram_size
);
482 adev
->mc
.gtt_size
= (uint64_t)amdgpu_gart_size
<< 20;
484 gmc_v8_0_vram_gtt_location(adev
, &adev
->mc
);
491 * VMID 0 is the physical GPU addresses as used by the kernel.
492 * VMIDs 1-15 are used for userspace clients and are handled
493 * by the amdgpu vm/hsa code.
497 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback
499 * @adev: amdgpu_device pointer
500 * @vmid: vm instance to flush
502 * Flush the TLB for the requested page table (CIK).
504 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device
*adev
,
507 /* flush hdp cache */
508 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL
, 0);
510 /* bits 0-15 are the VM contexts0-15 */
511 WREG32(mmVM_INVALIDATE_REQUEST
, 1 << vmid
);
515 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO
517 * @adev: amdgpu_device pointer
518 * @cpu_pt_addr: cpu address of the page table
519 * @gpu_page_idx: entry in the page table to update
520 * @addr: dst addr to write into pte/pde
521 * @flags: access flags
523 * Update the page tables using the CPU.
525 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device
*adev
,
527 uint32_t gpu_page_idx
,
531 void __iomem
*ptr
= (void *)cpu_pt_addr
;
537 * 39:12 4k physical page base address
548 * 63:59 block fragment size
550 * 39:1 physical base address of PTE
551 * bits 5:1 must be 0.
554 value
= addr
& 0x000000FFFFFFF000ULL
;
556 writeq(value
, ptr
+ (gpu_page_idx
* 8));
562 * gmc_v8_0_set_fault_enable_default - update VM fault handling
564 * @adev: amdgpu_device pointer
565 * @value: true redirects VM faults to the default page
567 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device
*adev
,
572 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
573 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
574 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
575 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
576 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
577 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
578 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
579 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
580 VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
581 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
582 READ_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
583 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
584 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
585 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
,
586 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
, value
);
587 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
591 * gmc_v8_0_gart_enable - gart enable
593 * @adev: amdgpu_device pointer
595 * This sets up the TLBs, programs the page tables for VMID0,
596 * sets up the hw for VMIDs 1-15 which are allocated on
597 * demand, and sets up the global locations for the LDS, GDS,
598 * and GPUVM for FSA64 clients (CIK).
599 * Returns 0 for success, errors for failure.
601 static int gmc_v8_0_gart_enable(struct amdgpu_device
*adev
)
606 if (adev
->gart
.robj
== NULL
) {
607 dev_err(adev
->dev
, "No VRAM object for PCIE GART.\n");
610 r
= amdgpu_gart_table_vram_pin(adev
);
613 /* Setup TLB control */
614 tmp
= RREG32(mmMC_VM_MX_L1_TLB_CNTL
);
615 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_TLB
, 1);
616 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
, 1);
617 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, SYSTEM_ACCESS_MODE
, 3);
618 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_ADVANCED_DRIVER_MODEL
, 1);
619 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, SYSTEM_APERTURE_UNMAPPED_ACCESS
, 0);
620 WREG32(mmMC_VM_MX_L1_TLB_CNTL
, tmp
);
622 tmp
= RREG32(mmVM_L2_CNTL
);
623 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_CACHE
, 1);
624 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_FRAGMENT_PROCESSING
, 1);
625 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE
, 1);
626 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE
, 1);
627 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, EFFECTIVE_L2_QUEUE_SIZE
, 7);
628 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, CONTEXT1_IDENTITY_ACCESS_MODE
, 1);
629 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY
, 1);
630 WREG32(mmVM_L2_CNTL
, tmp
);
631 tmp
= RREG32(mmVM_L2_CNTL2
);
632 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL2
, INVALIDATE_ALL_L1_TLBS
, 1);
633 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL2
, INVALIDATE_L2_CACHE
, 1);
634 WREG32(mmVM_L2_CNTL2
, tmp
);
635 tmp
= RREG32(mmVM_L2_CNTL3
);
636 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, L2_CACHE_BIGK_ASSOCIATIVITY
, 1);
637 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, BANK_SELECT
, 4);
638 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL3
, L2_CACHE_BIGK_FRAGMENT_SIZE
, 4);
639 WREG32(mmVM_L2_CNTL3
, tmp
);
640 /* XXX: set to enable PTE/PDE in system memory */
641 tmp
= RREG32(mmVM_L2_CNTL4
);
642 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL
, 0);
643 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED
, 0);
644 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP
, 0);
645 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL
, 0);
646 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED
, 0);
647 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP
, 0);
648 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL
, 0);
649 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED
, 0);
650 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP
, 0);
651 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL
, 0);
652 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED
, 0);
653 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL4
, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP
, 0);
654 WREG32(mmVM_L2_CNTL4
, tmp
);
656 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR
, adev
->mc
.gtt_start
>> 12);
657 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR
, adev
->mc
.gtt_end
>> 12);
658 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
, adev
->gart
.table_addr
>> 12);
659 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
,
660 (u32
)(adev
->dummy_page
.addr
>> 12));
661 WREG32(mmVM_CONTEXT0_CNTL2
, 0);
662 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
663 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, ENABLE_CONTEXT
, 1);
664 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, PAGE_TABLE_DEPTH
, 0);
665 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT0_CNTL
, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
666 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
668 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR
, 0);
669 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR
, 0);
670 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET
, 0);
672 /* empty context1-15 */
673 /* FIXME start with 4G, once using 2 level pt switch to full
676 /* set vm size, must be a multiple of 4 */
677 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR
, 0);
678 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR
, adev
->vm_manager
.max_pfn
- 1);
679 for (i
= 1; i
< 16; i
++) {
681 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR
+ i
,
682 adev
->gart
.table_addr
>> 12);
684 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR
+ i
- 8,
685 adev
->gart
.table_addr
>> 12);
688 /* enable context1-15 */
689 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
,
690 (u32
)(adev
->dummy_page
.addr
>> 12));
691 WREG32(mmVM_CONTEXT1_CNTL2
, 4);
692 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
693 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, ENABLE_CONTEXT
, 1);
694 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PAGE_TABLE_DEPTH
, 1);
695 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
696 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
697 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
698 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, VALID_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
699 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, READ_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
700 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
701 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT
, 1);
702 tmp
= REG_SET_FIELD(tmp
, VM_CONTEXT1_CNTL
, PAGE_TABLE_BLOCK_SIZE
,
703 amdgpu_vm_block_size
- 9);
704 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
705 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_ALWAYS
)
706 gmc_v8_0_set_fault_enable_default(adev
, false);
708 gmc_v8_0_set_fault_enable_default(adev
, true);
710 gmc_v8_0_gart_flush_gpu_tlb(adev
, 0);
711 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
712 (unsigned)(adev
->mc
.gtt_size
>> 20),
713 (unsigned long long)adev
->gart
.table_addr
);
714 adev
->gart
.ready
= true;
718 static int gmc_v8_0_gart_init(struct amdgpu_device
*adev
)
722 if (adev
->gart
.robj
) {
723 WARN(1, "R600 PCIE GART already initialized\n");
726 /* Initialize common gart structure */
727 r
= amdgpu_gart_init(adev
);
730 adev
->gart
.table_size
= adev
->gart
.num_gpu_pages
* 8;
731 return amdgpu_gart_table_vram_alloc(adev
);
735 * gmc_v8_0_gart_disable - gart disable
737 * @adev: amdgpu_device pointer
739 * This disables all VM page table (CIK).
741 static void gmc_v8_0_gart_disable(struct amdgpu_device
*adev
)
745 /* Disable all tables */
746 WREG32(mmVM_CONTEXT0_CNTL
, 0);
747 WREG32(mmVM_CONTEXT1_CNTL
, 0);
748 /* Setup TLB control */
749 tmp
= RREG32(mmMC_VM_MX_L1_TLB_CNTL
);
750 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_TLB
, 0);
751 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_L1_FRAGMENT_PROCESSING
, 0);
752 tmp
= REG_SET_FIELD(tmp
, MC_VM_MX_L1_TLB_CNTL
, ENABLE_ADVANCED_DRIVER_MODEL
, 0);
753 WREG32(mmMC_VM_MX_L1_TLB_CNTL
, tmp
);
755 tmp
= RREG32(mmVM_L2_CNTL
);
756 tmp
= REG_SET_FIELD(tmp
, VM_L2_CNTL
, ENABLE_L2_CACHE
, 0);
757 WREG32(mmVM_L2_CNTL
, tmp
);
758 WREG32(mmVM_L2_CNTL2
, 0);
759 amdgpu_gart_table_vram_unpin(adev
);
763 * gmc_v8_0_gart_fini - vm fini callback
765 * @adev: amdgpu_device pointer
767 * Tears down the driver GART/VM setup (CIK).
769 static void gmc_v8_0_gart_fini(struct amdgpu_device
*adev
)
771 amdgpu_gart_table_vram_free(adev
);
772 amdgpu_gart_fini(adev
);
777 * VMID 0 is the physical GPU addresses as used by the kernel.
778 * VMIDs 1-15 are used for userspace clients and are handled
779 * by the amdgpu vm/hsa code.
782 * gmc_v8_0_vm_init - cik vm init callback
784 * @adev: amdgpu_device pointer
786 * Inits cik specific vm parameters (number of VMs, base of vram for
788 * Returns 0 for success.
790 static int gmc_v8_0_vm_init(struct amdgpu_device
*adev
)
794 * VMID 0 is reserved for System
795 * amdgpu graphics/compute will use VMIDs 1-7
796 * amdkfd will use VMIDs 8-15
798 adev
->vm_manager
.num_ids
= AMDGPU_NUM_OF_VMIDS
;
799 amdgpu_vm_manager_init(adev
);
801 /* base offset of vram pages */
802 if (adev
->flags
& AMD_IS_APU
) {
803 u64 tmp
= RREG32(mmMC_VM_FB_OFFSET
);
805 adev
->vm_manager
.vram_base_offset
= tmp
;
807 adev
->vm_manager
.vram_base_offset
= 0;
813 * gmc_v8_0_vm_fini - cik vm fini callback
815 * @adev: amdgpu_device pointer
817 * Tear down any asic specific VM setup (CIK).
819 static void gmc_v8_0_vm_fini(struct amdgpu_device
*adev
)
824 * gmc_v8_0_vm_decode_fault - print human readable fault info
826 * @adev: amdgpu_device pointer
827 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
828 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
830 * Print human readable fault information (CIK).
832 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device
*adev
,
833 u32 status
, u32 addr
, u32 mc_client
)
836 u32 vmid
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
, VMID
);
837 u32 protections
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
839 char block
[5] = { mc_client
>> 24, (mc_client
>> 16) & 0xff,
840 (mc_client
>> 8) & 0xff, mc_client
& 0xff, 0 };
842 mc_id
= REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
845 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
846 protections
, vmid
, addr
,
847 REG_GET_FIELD(status
, VM_CONTEXT1_PROTECTION_FAULT_STATUS
,
849 "write" : "read", block
, mc_client
, mc_id
);
852 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type
)
854 switch (mc_seq_vram_type
) {
855 case MC_SEQ_MISC0__MT__GDDR1
:
856 return AMDGPU_VRAM_TYPE_GDDR1
;
857 case MC_SEQ_MISC0__MT__DDR2
:
858 return AMDGPU_VRAM_TYPE_DDR2
;
859 case MC_SEQ_MISC0__MT__GDDR3
:
860 return AMDGPU_VRAM_TYPE_GDDR3
;
861 case MC_SEQ_MISC0__MT__GDDR4
:
862 return AMDGPU_VRAM_TYPE_GDDR4
;
863 case MC_SEQ_MISC0__MT__GDDR5
:
864 return AMDGPU_VRAM_TYPE_GDDR5
;
865 case MC_SEQ_MISC0__MT__HBM
:
866 return AMDGPU_VRAM_TYPE_HBM
;
867 case MC_SEQ_MISC0__MT__DDR3
:
868 return AMDGPU_VRAM_TYPE_DDR3
;
870 return AMDGPU_VRAM_TYPE_UNKNOWN
;
874 static int gmc_v8_0_early_init(void *handle
)
876 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
878 gmc_v8_0_set_gart_funcs(adev
);
879 gmc_v8_0_set_irq_funcs(adev
);
884 static int gmc_v8_0_late_init(void *handle
)
886 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
888 if (amdgpu_vm_fault_stop
!= AMDGPU_VM_FAULT_STOP_ALWAYS
)
889 return amdgpu_irq_get(adev
, &adev
->mc
.vm_fault
, 0);
894 #define mmMC_SEQ_MISC0_FIJI 0xA71
896 static int gmc_v8_0_sw_init(void *handle
)
900 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
902 if (adev
->flags
& AMD_IS_APU
) {
903 adev
->mc
.vram_type
= AMDGPU_VRAM_TYPE_UNKNOWN
;
907 if (adev
->asic_type
== CHIP_FIJI
)
908 tmp
= RREG32(mmMC_SEQ_MISC0_FIJI
);
910 tmp
= RREG32(mmMC_SEQ_MISC0
);
911 tmp
&= MC_SEQ_MISC0__MT__MASK
;
912 adev
->mc
.vram_type
= gmc_v8_0_convert_vram_type(tmp
);
915 r
= amdgpu_irq_add_id(adev
, 146, &adev
->mc
.vm_fault
);
919 r
= amdgpu_irq_add_id(adev
, 147, &adev
->mc
.vm_fault
);
923 /* Adjust VM size here.
924 * Currently set to 4GB ((1 << 20) 4k pages).
925 * Max GPUVM size for cayman and SI is 40 bits.
927 adev
->vm_manager
.max_pfn
= amdgpu_vm_size
<< 18;
929 /* Set the internal MC address mask
930 * This is the max address of the GPU's
931 * internal address space.
933 adev
->mc
.mc_mask
= 0xffffffffffULL
; /* 40 bit MC */
935 /* set DMA mask + need_dma32 flags.
936 * PCIE - can handle 40-bits.
937 * IGP - can handle 40-bits
938 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
940 adev
->need_dma32
= false;
941 dma_bits
= adev
->need_dma32
? 32 : 40;
942 r
= pci_set_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
944 adev
->need_dma32
= true;
946 printk(KERN_WARNING
"amdgpu: No suitable DMA available.\n");
948 r
= pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(dma_bits
));
950 pci_set_consistent_dma_mask(adev
->pdev
, DMA_BIT_MASK(32));
951 printk(KERN_WARNING
"amdgpu: No coherent DMA available.\n");
954 r
= gmc_v8_0_init_microcode(adev
);
956 DRM_ERROR("Failed to load mc firmware!\n");
960 r
= gmc_v8_0_mc_init(adev
);
965 r
= amdgpu_bo_init(adev
);
969 r
= gmc_v8_0_gart_init(adev
);
973 if (!adev
->vm_manager
.enabled
) {
974 r
= gmc_v8_0_vm_init(adev
);
976 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
979 adev
->vm_manager
.enabled
= true;
985 static int gmc_v8_0_sw_fini(void *handle
)
987 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
989 if (adev
->vm_manager
.enabled
) {
990 amdgpu_vm_manager_fini(adev
);
991 gmc_v8_0_vm_fini(adev
);
992 adev
->vm_manager
.enabled
= false;
994 gmc_v8_0_gart_fini(adev
);
995 amdgpu_gem_force_release(adev
);
996 amdgpu_bo_fini(adev
);
1001 static int gmc_v8_0_hw_init(void *handle
)
1004 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1006 gmc_v8_0_init_golden_registers(adev
);
1008 gmc_v8_0_mc_program(adev
);
1010 if (adev
->asic_type
== CHIP_TONGA
) {
1011 r
= gmc_v8_0_mc_load_microcode(adev
);
1013 DRM_ERROR("Failed to load MC firmware!\n");
1018 r
= gmc_v8_0_gart_enable(adev
);
1025 static int gmc_v8_0_hw_fini(void *handle
)
1027 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1029 amdgpu_irq_put(adev
, &adev
->mc
.vm_fault
, 0);
1030 gmc_v8_0_gart_disable(adev
);
1035 static int gmc_v8_0_suspend(void *handle
)
1037 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1039 if (adev
->vm_manager
.enabled
) {
1040 gmc_v8_0_vm_fini(adev
);
1041 adev
->vm_manager
.enabled
= false;
1043 gmc_v8_0_hw_fini(adev
);
1048 static int gmc_v8_0_resume(void *handle
)
1051 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1053 r
= gmc_v8_0_hw_init(adev
);
1057 if (!adev
->vm_manager
.enabled
) {
1058 r
= gmc_v8_0_vm_init(adev
);
1060 dev_err(adev
->dev
, "vm manager initialization failed (%d).\n", r
);
1063 adev
->vm_manager
.enabled
= true;
1069 static bool gmc_v8_0_is_idle(void *handle
)
1071 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1072 u32 tmp
= RREG32(mmSRBM_STATUS
);
1074 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1075 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
| SRBM_STATUS__VMC_BUSY_MASK
))
1081 static int gmc_v8_0_wait_for_idle(void *handle
)
1085 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1087 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
1088 /* read MC_STATUS */
1089 tmp
= RREG32(mmSRBM_STATUS
) & (SRBM_STATUS__MCB_BUSY_MASK
|
1090 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1091 SRBM_STATUS__MCC_BUSY_MASK
|
1092 SRBM_STATUS__MCD_BUSY_MASK
|
1093 SRBM_STATUS__VMC_BUSY_MASK
|
1094 SRBM_STATUS__VMC1_BUSY_MASK
);
1103 static int gmc_v8_0_soft_reset(void *handle
)
1105 struct amdgpu_mode_mc_save save
;
1106 u32 srbm_soft_reset
= 0;
1107 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1108 u32 tmp
= RREG32(mmSRBM_STATUS
);
1110 if (tmp
& SRBM_STATUS__VMC_BUSY_MASK
)
1111 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1112 SRBM_SOFT_RESET
, SOFT_RESET_VMC
, 1);
1114 if (tmp
& (SRBM_STATUS__MCB_BUSY_MASK
| SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK
|
1115 SRBM_STATUS__MCC_BUSY_MASK
| SRBM_STATUS__MCD_BUSY_MASK
)) {
1116 if (!(adev
->flags
& AMD_IS_APU
))
1117 srbm_soft_reset
= REG_SET_FIELD(srbm_soft_reset
,
1118 SRBM_SOFT_RESET
, SOFT_RESET_MC
, 1);
1121 if (srbm_soft_reset
) {
1122 gmc_v8_0_mc_stop(adev
, &save
);
1123 if (gmc_v8_0_wait_for_idle((void *)adev
)) {
1124 dev_warn(adev
->dev
, "Wait for GMC idle timed out !\n");
1128 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1129 tmp
|= srbm_soft_reset
;
1130 dev_info(adev
->dev
, "SRBM_SOFT_RESET=0x%08X\n", tmp
);
1131 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1132 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1136 tmp
&= ~srbm_soft_reset
;
1137 WREG32(mmSRBM_SOFT_RESET
, tmp
);
1138 tmp
= RREG32(mmSRBM_SOFT_RESET
);
1140 /* Wait a little for things to settle down */
1143 gmc_v8_0_mc_resume(adev
, &save
);
1150 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device
*adev
,
1151 struct amdgpu_irq_src
*src
,
1153 enum amdgpu_interrupt_state state
)
1156 u32 bits
= (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1157 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1158 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1159 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1160 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1161 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
|
1162 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
);
1165 case AMDGPU_IRQ_STATE_DISABLE
:
1166 /* system context */
1167 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1169 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1171 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1173 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1175 case AMDGPU_IRQ_STATE_ENABLE
:
1176 /* system context */
1177 tmp
= RREG32(mmVM_CONTEXT0_CNTL
);
1179 WREG32(mmVM_CONTEXT0_CNTL
, tmp
);
1181 tmp
= RREG32(mmVM_CONTEXT1_CNTL
);
1183 WREG32(mmVM_CONTEXT1_CNTL
, tmp
);
1192 static int gmc_v8_0_process_interrupt(struct amdgpu_device
*adev
,
1193 struct amdgpu_irq_src
*source
,
1194 struct amdgpu_iv_entry
*entry
)
1196 u32 addr
, status
, mc_client
;
1198 addr
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR
);
1199 status
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS
);
1200 mc_client
= RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT
);
1201 /* reset addr and status */
1202 WREG32_P(mmVM_CONTEXT1_CNTL2
, 1, ~1);
1204 if (!addr
&& !status
)
1207 if (amdgpu_vm_fault_stop
== AMDGPU_VM_FAULT_STOP_FIRST
)
1208 gmc_v8_0_set_fault_enable_default(adev
, false);
1210 dev_err(adev
->dev
, "GPU fault detected: %d 0x%08x\n",
1211 entry
->src_id
, entry
->src_data
);
1212 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1214 dev_err(adev
->dev
, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1216 gmc_v8_0_vm_decode_fault(adev
, status
, addr
, mc_client
);
1221 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device
*adev
,
1226 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_MC_MGCG
)) {
1227 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1228 data
|= MC_HUB_MISC_HUB_CG__ENABLE_MASK
;
1229 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1231 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1232 data
|= MC_HUB_MISC_SIP_CG__ENABLE_MASK
;
1233 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1235 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1236 data
|= MC_HUB_MISC_VM_CG__ENABLE_MASK
;
1237 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1239 data
= RREG32(mmMC_XPB_CLK_GAT
);
1240 data
|= MC_XPB_CLK_GAT__ENABLE_MASK
;
1241 WREG32(mmMC_XPB_CLK_GAT
, data
);
1243 data
= RREG32(mmATC_MISC_CG
);
1244 data
|= ATC_MISC_CG__ENABLE_MASK
;
1245 WREG32(mmATC_MISC_CG
, data
);
1247 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1248 data
|= MC_CITF_MISC_WR_CG__ENABLE_MASK
;
1249 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1251 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1252 data
|= MC_CITF_MISC_RD_CG__ENABLE_MASK
;
1253 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1255 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1256 data
|= MC_CITF_MISC_VM_CG__ENABLE_MASK
;
1257 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1259 data
= RREG32(mmVM_L2_CG
);
1260 data
|= VM_L2_CG__ENABLE_MASK
;
1261 WREG32(mmVM_L2_CG
, data
);
1263 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1264 data
&= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK
;
1265 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1267 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1268 data
&= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK
;
1269 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1271 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1272 data
&= ~MC_HUB_MISC_VM_CG__ENABLE_MASK
;
1273 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1275 data
= RREG32(mmMC_XPB_CLK_GAT
);
1276 data
&= ~MC_XPB_CLK_GAT__ENABLE_MASK
;
1277 WREG32(mmMC_XPB_CLK_GAT
, data
);
1279 data
= RREG32(mmATC_MISC_CG
);
1280 data
&= ~ATC_MISC_CG__ENABLE_MASK
;
1281 WREG32(mmATC_MISC_CG
, data
);
1283 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1284 data
&= ~MC_CITF_MISC_WR_CG__ENABLE_MASK
;
1285 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1287 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1288 data
&= ~MC_CITF_MISC_RD_CG__ENABLE_MASK
;
1289 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1291 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1292 data
&= ~MC_CITF_MISC_VM_CG__ENABLE_MASK
;
1293 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1295 data
= RREG32(mmVM_L2_CG
);
1296 data
&= ~VM_L2_CG__ENABLE_MASK
;
1297 WREG32(mmVM_L2_CG
, data
);
1301 static void fiji_update_mc_light_sleep(struct amdgpu_device
*adev
,
1306 if (enable
&& (adev
->cg_flags
& AMD_CG_SUPPORT_MC_LS
)) {
1307 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1308 data
|= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK
;
1309 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1311 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1312 data
|= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK
;
1313 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1315 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1316 data
|= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1317 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1319 data
= RREG32(mmMC_XPB_CLK_GAT
);
1320 data
|= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK
;
1321 WREG32(mmMC_XPB_CLK_GAT
, data
);
1323 data
= RREG32(mmATC_MISC_CG
);
1324 data
|= ATC_MISC_CG__MEM_LS_ENABLE_MASK
;
1325 WREG32(mmATC_MISC_CG
, data
);
1327 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1328 data
|= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK
;
1329 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1331 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1332 data
|= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK
;
1333 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1335 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1336 data
|= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1337 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1339 data
= RREG32(mmVM_L2_CG
);
1340 data
|= VM_L2_CG__MEM_LS_ENABLE_MASK
;
1341 WREG32(mmVM_L2_CG
, data
);
1343 data
= RREG32(mmMC_HUB_MISC_HUB_CG
);
1344 data
&= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK
;
1345 WREG32(mmMC_HUB_MISC_HUB_CG
, data
);
1347 data
= RREG32(mmMC_HUB_MISC_SIP_CG
);
1348 data
&= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK
;
1349 WREG32(mmMC_HUB_MISC_SIP_CG
, data
);
1351 data
= RREG32(mmMC_HUB_MISC_VM_CG
);
1352 data
&= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1353 WREG32(mmMC_HUB_MISC_VM_CG
, data
);
1355 data
= RREG32(mmMC_XPB_CLK_GAT
);
1356 data
&= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK
;
1357 WREG32(mmMC_XPB_CLK_GAT
, data
);
1359 data
= RREG32(mmATC_MISC_CG
);
1360 data
&= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK
;
1361 WREG32(mmATC_MISC_CG
, data
);
1363 data
= RREG32(mmMC_CITF_MISC_WR_CG
);
1364 data
&= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK
;
1365 WREG32(mmMC_CITF_MISC_WR_CG
, data
);
1367 data
= RREG32(mmMC_CITF_MISC_RD_CG
);
1368 data
&= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK
;
1369 WREG32(mmMC_CITF_MISC_RD_CG
, data
);
1371 data
= RREG32(mmMC_CITF_MISC_VM_CG
);
1372 data
&= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK
;
1373 WREG32(mmMC_CITF_MISC_VM_CG
, data
);
1375 data
= RREG32(mmVM_L2_CG
);
1376 data
&= ~VM_L2_CG__MEM_LS_ENABLE_MASK
;
1377 WREG32(mmVM_L2_CG
, data
);
1381 static int gmc_v8_0_set_clockgating_state(void *handle
,
1382 enum amd_clockgating_state state
)
1384 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
1386 switch (adev
->asic_type
) {
1388 fiji_update_mc_medium_grain_clock_gating(adev
,
1389 state
== AMD_CG_STATE_GATE
? true : false);
1390 fiji_update_mc_light_sleep(adev
,
1391 state
== AMD_CG_STATE_GATE
? true : false);
1399 static int gmc_v8_0_set_powergating_state(void *handle
,
1400 enum amd_powergating_state state
)
1405 const struct amd_ip_funcs gmc_v8_0_ip_funcs
= {
1407 .early_init
= gmc_v8_0_early_init
,
1408 .late_init
= gmc_v8_0_late_init
,
1409 .sw_init
= gmc_v8_0_sw_init
,
1410 .sw_fini
= gmc_v8_0_sw_fini
,
1411 .hw_init
= gmc_v8_0_hw_init
,
1412 .hw_fini
= gmc_v8_0_hw_fini
,
1413 .suspend
= gmc_v8_0_suspend
,
1414 .resume
= gmc_v8_0_resume
,
1415 .is_idle
= gmc_v8_0_is_idle
,
1416 .wait_for_idle
= gmc_v8_0_wait_for_idle
,
1417 .soft_reset
= gmc_v8_0_soft_reset
,
1418 .set_clockgating_state
= gmc_v8_0_set_clockgating_state
,
1419 .set_powergating_state
= gmc_v8_0_set_powergating_state
,
1422 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs
= {
1423 .flush_gpu_tlb
= gmc_v8_0_gart_flush_gpu_tlb
,
1424 .set_pte_pde
= gmc_v8_0_gart_set_pte_pde
,
1427 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs
= {
1428 .set
= gmc_v8_0_vm_fault_interrupt_state
,
1429 .process
= gmc_v8_0_process_interrupt
,
1432 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device
*adev
)
1434 if (adev
->gart
.gart_funcs
== NULL
)
1435 adev
->gart
.gart_funcs
= &gmc_v8_0_gart_funcs
;
1438 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device
*adev
)
1440 adev
->mc
.vm_fault
.num_types
= 1;
1441 adev
->mc
.vm_fault
.funcs
= &gmc_v8_0_irq_funcs
;