2 * Copyright 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
25 * Authors: Christian König <christian.koenig@amd.com>
28 #include <linux/firmware.h>
31 #include "amdgpu_vce.h"
33 #include "vce/vce_3_0_d.h"
34 #include "vce/vce_3_0_sh_mask.h"
35 #include "oss/oss_2_0_d.h"
36 #include "oss/oss_2_0_sh_mask.h"
37 #include "gca/gfx_8_0_d.h"
38 #include "smu/smu_7_1_2_d.h"
39 #include "smu/smu_7_1_2_sh_mask.h"
41 #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
42 #define GRBM_GFX_INDEX__VCE_INSTANCE_MASK 0x10
44 #define VCE_V3_0_FW_SIZE (384 * 1024)
45 #define VCE_V3_0_STACK_SIZE (64 * 1024)
46 #define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
48 static void vce_v3_0_mc_resume(struct amdgpu_device
*adev
, int idx
);
49 static void vce_v3_0_set_ring_funcs(struct amdgpu_device
*adev
);
50 static void vce_v3_0_set_irq_funcs(struct amdgpu_device
*adev
);
53 * vce_v3_0_ring_get_rptr - get read pointer
55 * @ring: amdgpu_ring pointer
57 * Returns the current hardware read pointer
59 static uint32_t vce_v3_0_ring_get_rptr(struct amdgpu_ring
*ring
)
61 struct amdgpu_device
*adev
= ring
->adev
;
63 if (ring
== &adev
->vce
.ring
[0])
64 return RREG32(mmVCE_RB_RPTR
);
66 return RREG32(mmVCE_RB_RPTR2
);
70 * vce_v3_0_ring_get_wptr - get write pointer
72 * @ring: amdgpu_ring pointer
74 * Returns the current hardware write pointer
76 static uint32_t vce_v3_0_ring_get_wptr(struct amdgpu_ring
*ring
)
78 struct amdgpu_device
*adev
= ring
->adev
;
80 if (ring
== &adev
->vce
.ring
[0])
81 return RREG32(mmVCE_RB_WPTR
);
83 return RREG32(mmVCE_RB_WPTR2
);
87 * vce_v3_0_ring_set_wptr - set write pointer
89 * @ring: amdgpu_ring pointer
91 * Commits the write pointer to the hardware
93 static void vce_v3_0_ring_set_wptr(struct amdgpu_ring
*ring
)
95 struct amdgpu_device
*adev
= ring
->adev
;
97 if (ring
== &adev
->vce
.ring
[0])
98 WREG32(mmVCE_RB_WPTR
, ring
->wptr
);
100 WREG32(mmVCE_RB_WPTR2
, ring
->wptr
);
104 * vce_v3_0_start - start VCE block
106 * @adev: amdgpu_device pointer
108 * Setup and start the VCE block
110 static int vce_v3_0_start(struct amdgpu_device
*adev
)
112 struct amdgpu_ring
*ring
;
115 mutex_lock(&adev
->grbm_idx_mutex
);
116 for (idx
= 0; idx
< 2; ++idx
) {
118 if (adev
->vce
.harvest_config
& (1 << idx
))
122 WREG32_P(mmGRBM_GFX_INDEX
, 0,
123 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
125 WREG32_P(mmGRBM_GFX_INDEX
,
126 GRBM_GFX_INDEX__VCE_INSTANCE_MASK
,
127 ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
129 vce_v3_0_mc_resume(adev
, idx
);
132 WREG32_P(mmVCE_STATUS
, 1, ~1);
134 WREG32_P(mmVCE_VCPU_CNTL
, VCE_VCPU_CNTL__CLK_EN_MASK
,
135 ~VCE_VCPU_CNTL__CLK_EN_MASK
);
137 WREG32_P(mmVCE_SOFT_RESET
,
138 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
,
139 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
143 WREG32_P(mmVCE_SOFT_RESET
, 0,
144 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
146 for (i
= 0; i
< 10; ++i
) {
148 for (j
= 0; j
< 100; ++j
) {
149 status
= RREG32(mmVCE_STATUS
);
158 DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
159 WREG32_P(mmVCE_SOFT_RESET
,
160 VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
,
161 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
163 WREG32_P(mmVCE_SOFT_RESET
, 0,
164 ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
);
169 /* clear BUSY flag */
170 WREG32_P(mmVCE_STATUS
, 0, ~1);
173 DRM_ERROR("VCE not responding, giving up!!!\n");
174 mutex_unlock(&adev
->grbm_idx_mutex
);
179 WREG32_P(mmGRBM_GFX_INDEX
, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK
);
180 mutex_unlock(&adev
->grbm_idx_mutex
);
182 ring
= &adev
->vce
.ring
[0];
183 WREG32(mmVCE_RB_RPTR
, ring
->wptr
);
184 WREG32(mmVCE_RB_WPTR
, ring
->wptr
);
185 WREG32(mmVCE_RB_BASE_LO
, ring
->gpu_addr
);
186 WREG32(mmVCE_RB_BASE_HI
, upper_32_bits(ring
->gpu_addr
));
187 WREG32(mmVCE_RB_SIZE
, ring
->ring_size
/ 4);
189 ring
= &adev
->vce
.ring
[1];
190 WREG32(mmVCE_RB_RPTR2
, ring
->wptr
);
191 WREG32(mmVCE_RB_WPTR2
, ring
->wptr
);
192 WREG32(mmVCE_RB_BASE_LO2
, ring
->gpu_addr
);
193 WREG32(mmVCE_RB_BASE_HI2
, upper_32_bits(ring
->gpu_addr
));
194 WREG32(mmVCE_RB_SIZE2
, ring
->ring_size
/ 4);
199 #define ixVCE_HARVEST_FUSE_MACRO__ADDRESS 0xC0014074
200 #define VCE_HARVEST_FUSE_MACRO__SHIFT 27
201 #define VCE_HARVEST_FUSE_MACRO__MASK 0x18000000
203 static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device
*adev
)
208 if (adev
->flags
& AMDGPU_IS_APU
)
209 tmp
= (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS
) &
210 VCE_HARVEST_FUSE_MACRO__MASK
) >>
211 VCE_HARVEST_FUSE_MACRO__SHIFT
;
213 tmp
= (RREG32_SMC(ixCC_HARVEST_FUSES
) &
214 CC_HARVEST_FUSES__VCE_DISABLE_MASK
) >>
215 CC_HARVEST_FUSES__VCE_DISABLE__SHIFT
;
219 ret
= AMDGPU_VCE_HARVEST_VCE0
;
222 ret
= AMDGPU_VCE_HARVEST_VCE1
;
225 ret
= AMDGPU_VCE_HARVEST_VCE0
| AMDGPU_VCE_HARVEST_VCE1
;
234 static int vce_v3_0_early_init(void *handle
)
236 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
238 adev
->vce
.harvest_config
= vce_v3_0_get_harvest_config(adev
);
240 if ((adev
->vce
.harvest_config
&
241 (AMDGPU_VCE_HARVEST_VCE0
| AMDGPU_VCE_HARVEST_VCE1
)) ==
242 (AMDGPU_VCE_HARVEST_VCE0
| AMDGPU_VCE_HARVEST_VCE1
))
245 vce_v3_0_set_ring_funcs(adev
);
246 vce_v3_0_set_irq_funcs(adev
);
251 static int vce_v3_0_sw_init(void *handle
)
253 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
254 struct amdgpu_ring
*ring
;
258 r
= amdgpu_irq_add_id(adev
, 167, &adev
->vce
.irq
);
262 r
= amdgpu_vce_sw_init(adev
, VCE_V3_0_FW_SIZE
+
263 (VCE_V3_0_STACK_SIZE
+ VCE_V3_0_DATA_SIZE
) * 2);
267 r
= amdgpu_vce_resume(adev
);
271 ring
= &adev
->vce
.ring
[0];
272 sprintf(ring
->name
, "vce0");
273 r
= amdgpu_ring_init(adev
, ring
, 4096, VCE_CMD_NO_OP
, 0xf,
274 &adev
->vce
.irq
, 0, AMDGPU_RING_TYPE_VCE
);
278 ring
= &adev
->vce
.ring
[1];
279 sprintf(ring
->name
, "vce1");
280 r
= amdgpu_ring_init(adev
, ring
, 4096, VCE_CMD_NO_OP
, 0xf,
281 &adev
->vce
.irq
, 0, AMDGPU_RING_TYPE_VCE
);
288 static int vce_v3_0_sw_fini(void *handle
)
291 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
293 r
= amdgpu_vce_suspend(adev
);
297 r
= amdgpu_vce_sw_fini(adev
);
304 static int vce_v3_0_hw_init(void *handle
)
306 struct amdgpu_ring
*ring
;
308 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
310 r
= vce_v3_0_start(adev
);
314 ring
= &adev
->vce
.ring
[0];
316 r
= amdgpu_ring_test_ring(ring
);
322 ring
= &adev
->vce
.ring
[1];
324 r
= amdgpu_ring_test_ring(ring
);
330 DRM_INFO("VCE initialized successfully.\n");
335 static int vce_v3_0_hw_fini(void *handle
)
340 static int vce_v3_0_suspend(void *handle
)
343 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
345 r
= vce_v3_0_hw_fini(adev
);
349 r
= amdgpu_vce_suspend(adev
);
356 static int vce_v3_0_resume(void *handle
)
359 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
361 r
= amdgpu_vce_resume(adev
);
365 r
= vce_v3_0_hw_init(adev
);
372 static void vce_v3_0_mc_resume(struct amdgpu_device
*adev
, int idx
)
374 uint32_t offset
, size
;
376 WREG32_P(mmVCE_CLOCK_GATING_A
, 0, ~(1 << 16));
377 WREG32_P(mmVCE_UENC_CLOCK_GATING
, 0x1FF000, ~0xFF9FF000);
378 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING
, 0x3F, ~0x3F);
379 WREG32(mmVCE_CLOCK_GATING_B
, 0xf7);
381 WREG32(mmVCE_LMI_CTRL
, 0x00398000);
382 WREG32_P(mmVCE_LMI_CACHE_CTRL
, 0x0, ~0x1);
383 WREG32(mmVCE_LMI_SWAP_CNTL
, 0);
384 WREG32(mmVCE_LMI_SWAP_CNTL1
, 0);
385 WREG32(mmVCE_LMI_VM_CTRL
, 0);
387 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR
, (adev
->vce
.gpu_addr
>> 8));
388 offset
= AMDGPU_VCE_FIRMWARE_OFFSET
;
389 size
= VCE_V3_0_FW_SIZE
;
390 WREG32(mmVCE_VCPU_CACHE_OFFSET0
, offset
& 0x7fffffff);
391 WREG32(mmVCE_VCPU_CACHE_SIZE0
, size
);
395 size
= VCE_V3_0_STACK_SIZE
;
396 WREG32(mmVCE_VCPU_CACHE_OFFSET1
, offset
& 0x7fffffff);
397 WREG32(mmVCE_VCPU_CACHE_SIZE1
, size
);
399 size
= VCE_V3_0_DATA_SIZE
;
400 WREG32(mmVCE_VCPU_CACHE_OFFSET2
, offset
& 0x7fffffff);
401 WREG32(mmVCE_VCPU_CACHE_SIZE2
, size
);
403 offset
+= size
+ VCE_V3_0_STACK_SIZE
+ VCE_V3_0_DATA_SIZE
;
404 size
= VCE_V3_0_STACK_SIZE
;
405 WREG32(mmVCE_VCPU_CACHE_OFFSET1
, offset
& 0xfffffff);
406 WREG32(mmVCE_VCPU_CACHE_SIZE1
, size
);
408 size
= VCE_V3_0_DATA_SIZE
;
409 WREG32(mmVCE_VCPU_CACHE_OFFSET2
, offset
& 0xfffffff);
410 WREG32(mmVCE_VCPU_CACHE_SIZE2
, size
);
413 WREG32_P(mmVCE_LMI_CTRL2
, 0x0, ~0x100);
415 WREG32_P(mmVCE_SYS_INT_EN
, VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
,
416 ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
);
419 static bool vce_v3_0_is_idle(void *handle
)
421 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
423 return !(RREG32(mmSRBM_STATUS2
) & SRBM_STATUS2__VCE_BUSY_MASK
);
426 static int vce_v3_0_wait_for_idle(void *handle
)
429 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
431 for (i
= 0; i
< adev
->usec_timeout
; i
++) {
432 if (!(RREG32(mmSRBM_STATUS2
) & SRBM_STATUS2__VCE_BUSY_MASK
))
438 static int vce_v3_0_soft_reset(void *handle
)
440 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
442 WREG32_P(mmSRBM_SOFT_RESET
, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK
,
443 ~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK
);
446 return vce_v3_0_start(adev
);
449 static void vce_v3_0_print_status(void *handle
)
451 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
453 dev_info(adev
->dev
, "VCE 3.0 registers\n");
454 dev_info(adev
->dev
, " VCE_STATUS=0x%08X\n",
455 RREG32(mmVCE_STATUS
));
456 dev_info(adev
->dev
, " VCE_VCPU_CNTL=0x%08X\n",
457 RREG32(mmVCE_VCPU_CNTL
));
458 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
459 RREG32(mmVCE_VCPU_CACHE_OFFSET0
));
460 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
461 RREG32(mmVCE_VCPU_CACHE_SIZE0
));
462 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
463 RREG32(mmVCE_VCPU_CACHE_OFFSET1
));
464 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
465 RREG32(mmVCE_VCPU_CACHE_SIZE1
));
466 dev_info(adev
->dev
, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
467 RREG32(mmVCE_VCPU_CACHE_OFFSET2
));
468 dev_info(adev
->dev
, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
469 RREG32(mmVCE_VCPU_CACHE_SIZE2
));
470 dev_info(adev
->dev
, " VCE_SOFT_RESET=0x%08X\n",
471 RREG32(mmVCE_SOFT_RESET
));
472 dev_info(adev
->dev
, " VCE_RB_BASE_LO2=0x%08X\n",
473 RREG32(mmVCE_RB_BASE_LO2
));
474 dev_info(adev
->dev
, " VCE_RB_BASE_HI2=0x%08X\n",
475 RREG32(mmVCE_RB_BASE_HI2
));
476 dev_info(adev
->dev
, " VCE_RB_SIZE2=0x%08X\n",
477 RREG32(mmVCE_RB_SIZE2
));
478 dev_info(adev
->dev
, " VCE_RB_RPTR2=0x%08X\n",
479 RREG32(mmVCE_RB_RPTR2
));
480 dev_info(adev
->dev
, " VCE_RB_WPTR2=0x%08X\n",
481 RREG32(mmVCE_RB_WPTR2
));
482 dev_info(adev
->dev
, " VCE_RB_BASE_LO=0x%08X\n",
483 RREG32(mmVCE_RB_BASE_LO
));
484 dev_info(adev
->dev
, " VCE_RB_BASE_HI=0x%08X\n",
485 RREG32(mmVCE_RB_BASE_HI
));
486 dev_info(adev
->dev
, " VCE_RB_SIZE=0x%08X\n",
487 RREG32(mmVCE_RB_SIZE
));
488 dev_info(adev
->dev
, " VCE_RB_RPTR=0x%08X\n",
489 RREG32(mmVCE_RB_RPTR
));
490 dev_info(adev
->dev
, " VCE_RB_WPTR=0x%08X\n",
491 RREG32(mmVCE_RB_WPTR
));
492 dev_info(adev
->dev
, " VCE_CLOCK_GATING_A=0x%08X\n",
493 RREG32(mmVCE_CLOCK_GATING_A
));
494 dev_info(adev
->dev
, " VCE_CLOCK_GATING_B=0x%08X\n",
495 RREG32(mmVCE_CLOCK_GATING_B
));
496 dev_info(adev
->dev
, " VCE_UENC_CLOCK_GATING=0x%08X\n",
497 RREG32(mmVCE_UENC_CLOCK_GATING
));
498 dev_info(adev
->dev
, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
499 RREG32(mmVCE_UENC_REG_CLOCK_GATING
));
500 dev_info(adev
->dev
, " VCE_SYS_INT_EN=0x%08X\n",
501 RREG32(mmVCE_SYS_INT_EN
));
502 dev_info(adev
->dev
, " VCE_LMI_CTRL2=0x%08X\n",
503 RREG32(mmVCE_LMI_CTRL2
));
504 dev_info(adev
->dev
, " VCE_LMI_CTRL=0x%08X\n",
505 RREG32(mmVCE_LMI_CTRL
));
506 dev_info(adev
->dev
, " VCE_LMI_VM_CTRL=0x%08X\n",
507 RREG32(mmVCE_LMI_VM_CTRL
));
508 dev_info(adev
->dev
, " VCE_LMI_SWAP_CNTL=0x%08X\n",
509 RREG32(mmVCE_LMI_SWAP_CNTL
));
510 dev_info(adev
->dev
, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
511 RREG32(mmVCE_LMI_SWAP_CNTL1
));
512 dev_info(adev
->dev
, " VCE_LMI_CACHE_CTRL=0x%08X\n",
513 RREG32(mmVCE_LMI_CACHE_CTRL
));
516 static int vce_v3_0_set_interrupt_state(struct amdgpu_device
*adev
,
517 struct amdgpu_irq_src
*source
,
519 enum amdgpu_interrupt_state state
)
523 if (state
== AMDGPU_IRQ_STATE_ENABLE
)
524 val
|= VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
;
526 WREG32_P(mmVCE_SYS_INT_EN
, val
, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
);
530 static int vce_v3_0_process_interrupt(struct amdgpu_device
*adev
,
531 struct amdgpu_irq_src
*source
,
532 struct amdgpu_iv_entry
*entry
)
534 DRM_DEBUG("IH: VCE\n");
535 switch (entry
->src_data
) {
537 amdgpu_fence_process(&adev
->vce
.ring
[0]);
540 amdgpu_fence_process(&adev
->vce
.ring
[1]);
543 DRM_ERROR("Unhandled interrupt: %d %d\n",
544 entry
->src_id
, entry
->src_data
);
551 static int vce_v3_0_set_clockgating_state(void *handle
,
552 enum amd_clockgating_state state
)
557 static int vce_v3_0_set_powergating_state(void *handle
,
558 enum amd_powergating_state state
)
560 /* This doesn't actually powergate the VCE block.
561 * That's done in the dpm code via the SMC. This
562 * just re-inits the block as necessary. The actual
563 * gating still happens in the dpm code. We should
564 * revisit this when there is a cleaner line between
565 * the smc and the hw blocks
567 struct amdgpu_device
*adev
= (struct amdgpu_device
*)handle
;
569 if (state
== AMD_PG_STATE_GATE
)
570 /* XXX do we need a vce_v3_0_stop()? */
573 return vce_v3_0_start(adev
);
576 const struct amd_ip_funcs vce_v3_0_ip_funcs
= {
577 .early_init
= vce_v3_0_early_init
,
579 .sw_init
= vce_v3_0_sw_init
,
580 .sw_fini
= vce_v3_0_sw_fini
,
581 .hw_init
= vce_v3_0_hw_init
,
582 .hw_fini
= vce_v3_0_hw_fini
,
583 .suspend
= vce_v3_0_suspend
,
584 .resume
= vce_v3_0_resume
,
585 .is_idle
= vce_v3_0_is_idle
,
586 .wait_for_idle
= vce_v3_0_wait_for_idle
,
587 .soft_reset
= vce_v3_0_soft_reset
,
588 .print_status
= vce_v3_0_print_status
,
589 .set_clockgating_state
= vce_v3_0_set_clockgating_state
,
590 .set_powergating_state
= vce_v3_0_set_powergating_state
,
593 static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs
= {
594 .get_rptr
= vce_v3_0_ring_get_rptr
,
595 .get_wptr
= vce_v3_0_ring_get_wptr
,
596 .set_wptr
= vce_v3_0_ring_set_wptr
,
597 .parse_cs
= amdgpu_vce_ring_parse_cs
,
598 .emit_ib
= amdgpu_vce_ring_emit_ib
,
599 .emit_fence
= amdgpu_vce_ring_emit_fence
,
600 .emit_semaphore
= amdgpu_vce_ring_emit_semaphore
,
601 .test_ring
= amdgpu_vce_ring_test_ring
,
602 .test_ib
= amdgpu_vce_ring_test_ib
,
603 .is_lockup
= amdgpu_ring_test_lockup
,
606 static void vce_v3_0_set_ring_funcs(struct amdgpu_device
*adev
)
608 adev
->vce
.ring
[0].funcs
= &vce_v3_0_ring_funcs
;
609 adev
->vce
.ring
[1].funcs
= &vce_v3_0_ring_funcs
;
612 static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs
= {
613 .set
= vce_v3_0_set_interrupt_state
,
614 .process
= vce_v3_0_process_interrupt
,
617 static void vce_v3_0_set_irq_funcs(struct amdgpu_device
*adev
)
619 adev
->vce
.irq
.num_types
= 1;
620 adev
->vce
.irq
.funcs
= &vce_v3_0_irq_funcs
;