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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / gpu / drm / amd / powerplay / hwmgr / fiji_hwmgr.c
1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/module.h>
24 #include <linux/slab.h>
25 #include <linux/fb.h>
26 #include "linux/delay.h"
27
28 #include "hwmgr.h"
29 #include "fiji_smumgr.h"
30 #include "atombios.h"
31 #include "hardwaremanager.h"
32 #include "ppatomctrl.h"
33 #include "atombios.h"
34 #include "cgs_common.h"
35 #include "fiji_dyn_defaults.h"
36 #include "fiji_powertune.h"
37 #include "smu73.h"
38 #include "smu/smu_7_1_3_d.h"
39 #include "smu/smu_7_1_3_sh_mask.h"
40 #include "gmc/gmc_8_1_d.h"
41 #include "gmc/gmc_8_1_sh_mask.h"
42 #include "bif/bif_5_0_d.h"
43 #include "bif/bif_5_0_sh_mask.h"
44 #include "dce/dce_10_0_d.h"
45 #include "dce/dce_10_0_sh_mask.h"
46 #include "pppcielanes.h"
47 #include "fiji_hwmgr.h"
48 #include "tonga_processpptables.h"
49 #include "tonga_pptable.h"
50 #include "pp_debug.h"
51 #include "pp_acpi.h"
52 #include "amd_pcie_helpers.h"
53 #include "cgs_linux.h"
54 #include "ppinterrupt.h"
55
56 #include "fiji_clockpowergating.h"
57 #include "fiji_thermal.h"
58
59 #define VOLTAGE_SCALE 4
60 #define SMC_RAM_END 0x40000
61 #define VDDC_VDDCI_DELTA 300
62
63 #define MC_SEQ_MISC0_GDDR5_SHIFT 28
64 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
65 #define MC_SEQ_MISC0_GDDR5_VALUE 5
66
67 #define MC_CG_ARB_FREQ_F0 0x0a /* boot-up default */
68 #define MC_CG_ARB_FREQ_F1 0x0b
69 #define MC_CG_ARB_FREQ_F2 0x0c
70 #define MC_CG_ARB_FREQ_F3 0x0d
71
72 /* From smc_reg.h */
73 #define SMC_CG_IND_START 0xc0030000
74 #define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND */
75
76 #define VOLTAGE_SCALE 4
77 #define VOLTAGE_VID_OFFSET_SCALE1 625
78 #define VOLTAGE_VID_OFFSET_SCALE2 100
79
80 #define VDDC_VDDCI_DELTA 300
81
82 #define ixSWRST_COMMAND_1 0x1400103
83 #define MC_SEQ_CNTL__CAC_EN_MASK 0x40000000
84
85 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
86 enum DPM_EVENT_SRC {
87 DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
88 DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
89 DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
90 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
91 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
92 };
93
94
95 /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs
96 * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ]
97 */
98 uint16_t fiji_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0},
99 {600, 1050, 6, 1} };
100
101 /* [FF, SS] type, [] 4 voltage ranges, and
102 * [Floor Freq, Boundary Freq, VID min , VID max]
103 */
104 uint32_t fiji_clock_stretcher_ddt_table[2][4][4] =
105 { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
106 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
107
108 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
109 * (coming from PWR_CKS_CNTL.stretch_amount reg spec)
110 */
111 uint8_t fiji_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5},
112 {0, 2, 4, 5, 6, 5} };
113
114 const unsigned long PhwFiji_Magic = (unsigned long)(PHM_VIslands_Magic);
115
116 struct fiji_power_state *cast_phw_fiji_power_state(
117 struct pp_hw_power_state *hw_ps)
118 {
119 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
120 "Invalid Powerstate Type!",
121 return NULL;);
122
123 return (struct fiji_power_state *)hw_ps;
124 }
125
126 const struct fiji_power_state *cast_const_phw_fiji_power_state(
127 const struct pp_hw_power_state *hw_ps)
128 {
129 PP_ASSERT_WITH_CODE((PhwFiji_Magic == hw_ps->magic),
130 "Invalid Powerstate Type!",
131 return NULL;);
132
133 return (const struct fiji_power_state *)hw_ps;
134 }
135
136 static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
137 {
138 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
139 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
140 ? true : false;
141 }
142
143 static void fiji_init_dpm_defaults(struct pp_hwmgr *hwmgr)
144 {
145 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
146 struct fiji_ulv_parm *ulv = &data->ulv;
147
148 ulv->cg_ulv_parameter = PPFIJI_CGULVPARAMETER_DFLT;
149 data->voting_rights_clients0 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT0;
150 data->voting_rights_clients1 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT1;
151 data->voting_rights_clients2 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT2;
152 data->voting_rights_clients3 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT3;
153 data->voting_rights_clients4 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT4;
154 data->voting_rights_clients5 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT5;
155 data->voting_rights_clients6 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT6;
156 data->voting_rights_clients7 = PPFIJI_VOTINGRIGHTSCLIENTS_DFLT7;
157
158 data->static_screen_threshold_unit =
159 PPFIJI_STATICSCREENTHRESHOLDUNIT_DFLT;
160 data->static_screen_threshold =
161 PPFIJI_STATICSCREENTHRESHOLD_DFLT;
162
163 /* Unset ABM cap as it moved to DAL.
164 * Add PHM_PlatformCaps_NonABMSupportInPPLib
165 * for re-direct ABM related request to DAL
166 */
167 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
168 PHM_PlatformCaps_ABM);
169 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
170 PHM_PlatformCaps_NonABMSupportInPPLib);
171
172 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
173 PHM_PlatformCaps_DynamicACTiming);
174
175 fiji_initialize_power_tune_defaults(hwmgr);
176
177 data->mclk_stutter_mode_threshold = 60000;
178 data->pcie_gen_performance.max = PP_PCIEGen1;
179 data->pcie_gen_performance.min = PP_PCIEGen3;
180 data->pcie_gen_power_saving.max = PP_PCIEGen1;
181 data->pcie_gen_power_saving.min = PP_PCIEGen3;
182 data->pcie_lane_performance.max = 0;
183 data->pcie_lane_performance.min = 16;
184 data->pcie_lane_power_saving.max = 0;
185 data->pcie_lane_power_saving.min = 16;
186
187 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
188 PHM_PlatformCaps_DynamicUVDState);
189 }
190
191 static int fiji_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
192 phm_ppt_v1_voltage_lookup_table *lookup_table,
193 uint16_t virtual_voltage_id, int32_t *sclk)
194 {
195 uint8_t entryId;
196 uint8_t voltageId;
197 struct phm_ppt_v1_information *table_info =
198 (struct phm_ppt_v1_information *)(hwmgr->pptable);
199
200 PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -EINVAL);
201
202 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
203 for (entryId = 0; entryId < table_info->vdd_dep_on_sclk->count; entryId++) {
204 voltageId = table_info->vdd_dep_on_sclk->entries[entryId].vddInd;
205 if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
206 break;
207 }
208
209 PP_ASSERT_WITH_CODE(entryId < table_info->vdd_dep_on_sclk->count,
210 "Can't find requested voltage id in vdd_dep_on_sclk table!",
211 return -EINVAL;
212 );
213
214 *sclk = table_info->vdd_dep_on_sclk->entries[entryId].clk;
215
216 return 0;
217 }
218
219 /**
220 * Get Leakage VDDC based on leakage ID.
221 *
222 * @param hwmgr the address of the powerplay hardware manager.
223 * @return always 0
224 */
225 static int fiji_get_evv_voltages(struct pp_hwmgr *hwmgr)
226 {
227 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
228 uint16_t vv_id;
229 uint16_t vddc = 0;
230 uint16_t evv_default = 1150;
231 uint16_t i, j;
232 uint32_t sclk = 0;
233 struct phm_ppt_v1_information *table_info =
234 (struct phm_ppt_v1_information *)hwmgr->pptable;
235 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
236 table_info->vdd_dep_on_sclk;
237 int result;
238
239 for (i = 0; i < FIJI_MAX_LEAKAGE_COUNT; i++) {
240 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
241 if (!fiji_get_sclk_for_voltage_evv(hwmgr,
242 table_info->vddc_lookup_table, vv_id, &sclk)) {
243 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
244 PHM_PlatformCaps_ClockStretcher)) {
245 for (j = 1; j < sclk_table->count; j++) {
246 if (sclk_table->entries[j].clk == sclk &&
247 sclk_table->entries[j].cks_enable == 0) {
248 sclk += 5000;
249 break;
250 }
251 }
252 }
253
254 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
255 PHM_PlatformCaps_EnableDriverEVV))
256 result = atomctrl_calculate_voltage_evv_on_sclk(hwmgr,
257 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc, i, true);
258 else
259 result = -EINVAL;
260
261 if (result)
262 result = atomctrl_get_voltage_evv_on_sclk(hwmgr,
263 VOLTAGE_TYPE_VDDC, sclk,vv_id, &vddc);
264
265 /* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
266 PP_ASSERT_WITH_CODE((vddc < 2000),
267 "Invalid VDDC value, greater than 2v!", result = -EINVAL;);
268
269 if (result)
270 /* 1.15V is the default safe value for Fiji */
271 vddc = evv_default;
272
273 /* the voltage should not be zero nor equal to leakage ID */
274 if (vddc != 0 && vddc != vv_id) {
275 data->vddc_leakage.actual_voltage
276 [data->vddc_leakage.count] = vddc;
277 data->vddc_leakage.leakage_id
278 [data->vddc_leakage.count] = vv_id;
279 data->vddc_leakage.count++;
280 }
281 }
282 }
283 return 0;
284 }
285
286 /**
287 * Change virtual leakage voltage to actual value.
288 *
289 * @param hwmgr the address of the powerplay hardware manager.
290 * @param pointer to changing voltage
291 * @param pointer to leakage table
292 */
293 static void fiji_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
294 uint16_t *voltage, struct fiji_leakage_voltage *leakage_table)
295 {
296 uint32_t index;
297
298 /* search for leakage voltage ID 0xff01 ~ 0xff08 */
299 for (index = 0; index < leakage_table->count; index++) {
300 /* if this voltage matches a leakage voltage ID */
301 /* patch with actual leakage voltage */
302 if (leakage_table->leakage_id[index] == *voltage) {
303 *voltage = leakage_table->actual_voltage[index];
304 break;
305 }
306 }
307
308 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
309 printk(KERN_ERR "Voltage value looks like a Leakage ID but it's not patched \n");
310 }
311
312 /**
313 * Patch voltage lookup table by EVV leakages.
314 *
315 * @param hwmgr the address of the powerplay hardware manager.
316 * @param pointer to voltage lookup table
317 * @param pointer to leakage table
318 * @return always 0
319 */
320 static int fiji_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
321 phm_ppt_v1_voltage_lookup_table *lookup_table,
322 struct fiji_leakage_voltage *leakage_table)
323 {
324 uint32_t i;
325
326 for (i = 0; i < lookup_table->count; i++)
327 fiji_patch_with_vdd_leakage(hwmgr,
328 &lookup_table->entries[i].us_vdd, leakage_table);
329
330 return 0;
331 }
332
333 static int fiji_patch_clock_voltage_limits_with_vddc_leakage(
334 struct pp_hwmgr *hwmgr, struct fiji_leakage_voltage *leakage_table,
335 uint16_t *vddc)
336 {
337 struct phm_ppt_v1_information *table_info =
338 (struct phm_ppt_v1_information *)(hwmgr->pptable);
339 fiji_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
340 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
341 table_info->max_clock_voltage_on_dc.vddc;
342 return 0;
343 }
344
345 static int fiji_patch_voltage_dependency_tables_with_lookup_table(
346 struct pp_hwmgr *hwmgr)
347 {
348 uint8_t entryId;
349 uint8_t voltageId;
350 struct phm_ppt_v1_information *table_info =
351 (struct phm_ppt_v1_information *)(hwmgr->pptable);
352
353 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
354 table_info->vdd_dep_on_sclk;
355 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table =
356 table_info->vdd_dep_on_mclk;
357 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
358 table_info->mm_dep_table;
359
360 for (entryId = 0; entryId < sclk_table->count; ++entryId) {
361 voltageId = sclk_table->entries[entryId].vddInd;
362 sclk_table->entries[entryId].vddc =
363 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
364 }
365
366 for (entryId = 0; entryId < mclk_table->count; ++entryId) {
367 voltageId = mclk_table->entries[entryId].vddInd;
368 mclk_table->entries[entryId].vddc =
369 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
370 }
371
372 for (entryId = 0; entryId < mm_table->count; ++entryId) {
373 voltageId = mm_table->entries[entryId].vddcInd;
374 mm_table->entries[entryId].vddc =
375 table_info->vddc_lookup_table->entries[voltageId].us_vdd;
376 }
377
378 return 0;
379
380 }
381
382 static int fiji_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
383 {
384 /* Need to determine if we need calculated voltage. */
385 return 0;
386 }
387
388 static int fiji_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
389 {
390 /* Need to determine if we need calculated voltage from mm table. */
391 return 0;
392 }
393
394 static int fiji_sort_lookup_table(struct pp_hwmgr *hwmgr,
395 struct phm_ppt_v1_voltage_lookup_table *lookup_table)
396 {
397 uint32_t table_size, i, j;
398 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record;
399 table_size = lookup_table->count;
400
401 PP_ASSERT_WITH_CODE(0 != lookup_table->count,
402 "Lookup table is empty", return -EINVAL);
403
404 /* Sorting voltages */
405 for (i = 0; i < table_size - 1; i++) {
406 for (j = i + 1; j > 0; j--) {
407 if (lookup_table->entries[j].us_vdd <
408 lookup_table->entries[j - 1].us_vdd) {
409 tmp_voltage_lookup_record = lookup_table->entries[j - 1];
410 lookup_table->entries[j - 1] = lookup_table->entries[j];
411 lookup_table->entries[j] = tmp_voltage_lookup_record;
412 }
413 }
414 }
415
416 return 0;
417 }
418
419 static int fiji_complete_dependency_tables(struct pp_hwmgr *hwmgr)
420 {
421 int result = 0;
422 int tmp_result;
423 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
424 struct phm_ppt_v1_information *table_info =
425 (struct phm_ppt_v1_information *)(hwmgr->pptable);
426
427 tmp_result = fiji_patch_lookup_table_with_leakage(hwmgr,
428 table_info->vddc_lookup_table, &(data->vddc_leakage));
429 if (tmp_result)
430 result = tmp_result;
431
432 tmp_result = fiji_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
433 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc);
434 if (tmp_result)
435 result = tmp_result;
436
437 tmp_result = fiji_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
438 if (tmp_result)
439 result = tmp_result;
440
441 tmp_result = fiji_calc_voltage_dependency_tables(hwmgr);
442 if (tmp_result)
443 result = tmp_result;
444
445 tmp_result = fiji_calc_mm_voltage_dependency_table(hwmgr);
446 if (tmp_result)
447 result = tmp_result;
448
449 tmp_result = fiji_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
450 if(tmp_result)
451 result = tmp_result;
452
453 return result;
454 }
455
456 static int fiji_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
457 {
458 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
459 struct phm_ppt_v1_information *table_info =
460 (struct phm_ppt_v1_information *)(hwmgr->pptable);
461
462 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table =
463 table_info->vdd_dep_on_sclk;
464 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table =
465 table_info->vdd_dep_on_mclk;
466
467 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL,
468 "VDD dependency on SCLK table is missing. \
469 This table is mandatory", return -EINVAL);
470 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
471 "VDD dependency on SCLK table has to have is missing. \
472 This table is mandatory", return -EINVAL);
473
474 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL,
475 "VDD dependency on MCLK table is missing. \
476 This table is mandatory", return -EINVAL);
477 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
478 "VDD dependency on MCLK table has to have is missing. \
479 This table is mandatory", return -EINVAL);
480
481 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->entries[0].vddc;
482 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vdd_table->
483 entries[allowed_sclk_vdd_table->count - 1].vddc;
484
485 table_info->max_clock_voltage_on_ac.sclk =
486 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
487 table_info->max_clock_voltage_on_ac.mclk =
488 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk;
489 table_info->max_clock_voltage_on_ac.vddc =
490 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc;
491 table_info->max_clock_voltage_on_ac.vddci =
492 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci;
493
494 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
495 table_info->max_clock_voltage_on_ac.sclk;
496 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
497 table_info->max_clock_voltage_on_ac.mclk;
498 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
499 table_info->max_clock_voltage_on_ac.vddc;
500 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
501 table_info->max_clock_voltage_on_ac.vddci;
502
503 return 0;
504 }
505
506 static uint16_t fiji_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
507 {
508 uint32_t speedCntl = 0;
509
510 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
511 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
512 ixPCIE_LC_SPEED_CNTL);
513 return((uint16_t)PHM_GET_FIELD(speedCntl,
514 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE));
515 }
516
517 static int fiji_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
518 {
519 uint32_t link_width;
520
521 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */
522 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
523 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
524
525 PP_ASSERT_WITH_CODE((7 >= link_width),
526 "Invalid PCIe lane width!", return 0);
527
528 return decode_pcie_lane_width(link_width);
529 }
530
531 /** Patch the Boot State to match VBIOS boot clocks and voltage.
532 *
533 * @param hwmgr Pointer to the hardware manager.
534 * @param pPowerState The address of the PowerState instance being created.
535 *
536 */
537 static int fiji_patch_boot_state(struct pp_hwmgr *hwmgr,
538 struct pp_hw_power_state *hw_ps)
539 {
540 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
541 struct fiji_power_state *ps = (struct fiji_power_state *)hw_ps;
542 ATOM_FIRMWARE_INFO_V2_2 *fw_info;
543 uint16_t size;
544 uint8_t frev, crev;
545 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
546
547 /* First retrieve the Boot clocks and VDDC from the firmware info table.
548 * We assume here that fw_info is unchanged if this call fails.
549 */
550 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table(
551 hwmgr->device, index,
552 &size, &frev, &crev);
553 if (!fw_info)
554 /* During a test, there is no firmware info table. */
555 return 0;
556
557 /* Patch the state. */
558 data->vbios_boot_state.sclk_bootup_value =
559 le32_to_cpu(fw_info->ulDefaultEngineClock);
560 data->vbios_boot_state.mclk_bootup_value =
561 le32_to_cpu(fw_info->ulDefaultMemoryClock);
562 data->vbios_boot_state.mvdd_bootup_value =
563 le16_to_cpu(fw_info->usBootUpMVDDCVoltage);
564 data->vbios_boot_state.vddc_bootup_value =
565 le16_to_cpu(fw_info->usBootUpVDDCVoltage);
566 data->vbios_boot_state.vddci_bootup_value =
567 le16_to_cpu(fw_info->usBootUpVDDCIVoltage);
568 data->vbios_boot_state.pcie_gen_bootup_value =
569 fiji_get_current_pcie_speed(hwmgr);
570 data->vbios_boot_state.pcie_lane_bootup_value =
571 (uint16_t)fiji_get_current_pcie_lane_number(hwmgr);
572
573 /* set boot power state */
574 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value;
575 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value;
576 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value;
577 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value;
578
579 return 0;
580 }
581
582 static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
583 {
584 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
585 uint32_t i;
586 struct phm_ppt_v1_information *table_info =
587 (struct phm_ppt_v1_information *)(hwmgr->pptable);
588 bool stay_in_boot;
589 int result;
590
591 data->dll_default_on = false;
592 data->sram_end = SMC_RAM_END;
593
594 for (i = 0; i < SMU73_MAX_LEVELS_GRAPHICS; i++)
595 data->activity_target[i] = FIJI_AT_DFLT;
596
597 data->vddc_vddci_delta = VDDC_VDDCI_DELTA;
598
599 data->mclk_activity_target = PPFIJI_MCLK_TARGETACTIVITY_DFLT;
600 data->mclk_dpm0_activity_target = 0xa;
601
602 data->sclk_dpm_key_disabled = 0;
603 data->mclk_dpm_key_disabled = 0;
604 data->pcie_dpm_key_disabled = 0;
605
606 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
607 PHM_PlatformCaps_UnTabledHardwareInterface);
608 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
609 PHM_PlatformCaps_TablelessHardwareInterface);
610
611 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
612 PHM_PlatformCaps_SclkDeepSleep);
613
614 data->gpio_debug = 0;
615
616 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
617 PHM_PlatformCaps_DynamicPatchPowerState);
618
619 /* need to set voltage control types before EVV patching */
620 data->voltage_control = FIJI_VOLTAGE_CONTROL_NONE;
621 data->vddci_control = FIJI_VOLTAGE_CONTROL_NONE;
622 data->mvdd_control = FIJI_VOLTAGE_CONTROL_NONE;
623
624 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
625 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
626 data->voltage_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
627
628 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
629 PHM_PlatformCaps_EnableMVDDControl))
630 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
631 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
632 data->mvdd_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
633
634 if (data->mvdd_control == FIJI_VOLTAGE_CONTROL_NONE)
635 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
636 PHM_PlatformCaps_EnableMVDDControl);
637
638 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
639 PHM_PlatformCaps_ControlVDDCI)) {
640 if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
641 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
642 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_GPIO;
643 else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,
644 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
645 data->vddci_control = FIJI_VOLTAGE_CONTROL_BY_SVID2;
646 }
647
648 if (data->vddci_control == FIJI_VOLTAGE_CONTROL_NONE)
649 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
650 PHM_PlatformCaps_ControlVDDCI);
651
652 if (table_info && table_info->cac_dtp_table->usClockStretchAmount)
653 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
654 PHM_PlatformCaps_ClockStretcher);
655
656 fiji_init_dpm_defaults(hwmgr);
657
658 /* Get leakage voltage based on leakage ID. */
659 fiji_get_evv_voltages(hwmgr);
660
661 /* Patch our voltage dependency table with actual leakage voltage
662 * We need to perform leakage translation before it's used by other functions
663 */
664 fiji_complete_dependency_tables(hwmgr);
665
666 /* Parse pptable data read from VBIOS */
667 fiji_set_private_data_based_on_pptable(hwmgr);
668
669 /* ULV Support */
670 data->ulv.ulv_supported = true; /* ULV feature is enabled by default */
671
672 /* Initalize Dynamic State Adjustment Rule Settings */
673 result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
674
675 if (!result) {
676 data->uvd_enabled = false;
677 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
678 PHM_PlatformCaps_EnableSMU7ThermalManagement);
679 data->vddc_phase_shed_control = false;
680 }
681
682 stay_in_boot = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
683 PHM_PlatformCaps_StayInBootState);
684
685 if (0 == result) {
686 struct cgs_system_info sys_info = {0};
687
688 data->is_tlu_enabled = 0;
689 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
690 FIJI_MAX_HARDWARE_POWERLEVELS;
691 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
692 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
693
694 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
695 PHM_PlatformCaps_FanSpeedInTableIsRPM);
696
697 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp &&
698 hwmgr->thermal_controller.
699 advanceFanControlParameters.ucFanControlMode) {
700 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
701 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
702 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
703 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
704 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
705 table_info->cac_dtp_table->usOperatingTempMinLimit;
706 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
707 table_info->cac_dtp_table->usOperatingTempMaxLimit;
708 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
709 table_info->cac_dtp_table->usDefaultTargetOperatingTemp;
710 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
711 table_info->cac_dtp_table->usOperatingTempStep;
712 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
713 table_info->cac_dtp_table->usTargetOperatingTemp;
714
715 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
716 PHM_PlatformCaps_ODFuzzyFanControlSupport);
717 }
718
719 sys_info.size = sizeof(struct cgs_system_info);
720 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO;
721 result = cgs_query_system_info(hwmgr->device, &sys_info);
722 if (result)
723 data->pcie_gen_cap = 0x30007;
724 else
725 data->pcie_gen_cap = (uint32_t)sys_info.value;
726 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
727 data->pcie_spc_cap = 20;
728 sys_info.size = sizeof(struct cgs_system_info);
729 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
730 result = cgs_query_system_info(hwmgr->device, &sys_info);
731 if (result)
732 data->pcie_lane_cap = 0x2f0000;
733 else
734 data->pcie_lane_cap = (uint32_t)sys_info.value;
735 } else {
736 /* Ignore return value in here, we are cleaning up a mess. */
737 tonga_hwmgr_backend_fini(hwmgr);
738 }
739
740 return 0;
741 }
742
743 /**
744 * Read clock related registers.
745 *
746 * @param hwmgr the address of the powerplay hardware manager.
747 * @return always 0
748 */
749 static int fiji_read_clock_registers(struct pp_hwmgr *hwmgr)
750 {
751 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
752
753 data->clock_registers.vCG_SPLL_FUNC_CNTL =
754 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
755 ixCG_SPLL_FUNC_CNTL);
756 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
757 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
758 ixCG_SPLL_FUNC_CNTL_2);
759 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
760 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
761 ixCG_SPLL_FUNC_CNTL_3);
762 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
763 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
764 ixCG_SPLL_FUNC_CNTL_4);
765 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
766 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
767 ixCG_SPLL_SPREAD_SPECTRUM);
768 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
769 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
770 ixCG_SPLL_SPREAD_SPECTRUM_2);
771
772 return 0;
773 }
774
775 /**
776 * Find out if memory is GDDR5.
777 *
778 * @param hwmgr the address of the powerplay hardware manager.
779 * @return always 0
780 */
781 static int fiji_get_memory_type(struct pp_hwmgr *hwmgr)
782 {
783 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
784 uint32_t temp;
785
786 temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
787
788 data->is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
789 ((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
790 MC_SEQ_MISC0_GDDR5_SHIFT));
791
792 return 0;
793 }
794
795 /**
796 * Enables Dynamic Power Management by SMC
797 *
798 * @param hwmgr the address of the powerplay hardware manager.
799 * @return always 0
800 */
801 static int fiji_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
802 {
803 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
804 GENERAL_PWRMGT, STATIC_PM_EN, 1);
805
806 return 0;
807 }
808
809 /**
810 * Initialize PowerGating States for different engines
811 *
812 * @param hwmgr the address of the powerplay hardware manager.
813 * @return always 0
814 */
815 static int fiji_init_power_gate_state(struct pp_hwmgr *hwmgr)
816 {
817 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
818
819 data->uvd_power_gated = false;
820 data->vce_power_gated = false;
821 data->samu_power_gated = false;
822 data->acp_power_gated = false;
823 data->pg_acp_init = true;
824
825 return 0;
826 }
827
828 static int fiji_init_sclk_threshold(struct pp_hwmgr *hwmgr)
829 {
830 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
831 data->low_sclk_interrupt_threshold = 0;
832
833 return 0;
834 }
835
836 static int fiji_setup_asic_task(struct pp_hwmgr *hwmgr)
837 {
838 int tmp_result, result = 0;
839
840 tmp_result = fiji_read_clock_registers(hwmgr);
841 PP_ASSERT_WITH_CODE((0 == tmp_result),
842 "Failed to read clock registers!", result = tmp_result);
843
844 tmp_result = fiji_get_memory_type(hwmgr);
845 PP_ASSERT_WITH_CODE((0 == tmp_result),
846 "Failed to get memory type!", result = tmp_result);
847
848 tmp_result = fiji_enable_acpi_power_management(hwmgr);
849 PP_ASSERT_WITH_CODE((0 == tmp_result),
850 "Failed to enable ACPI power management!", result = tmp_result);
851
852 tmp_result = fiji_init_power_gate_state(hwmgr);
853 PP_ASSERT_WITH_CODE((0 == tmp_result),
854 "Failed to init power gate state!", result = tmp_result);
855
856 tmp_result = tonga_get_mc_microcode_version(hwmgr);
857 PP_ASSERT_WITH_CODE((0 == tmp_result),
858 "Failed to get MC microcode version!", result = tmp_result);
859
860 tmp_result = fiji_init_sclk_threshold(hwmgr);
861 PP_ASSERT_WITH_CODE((0 == tmp_result),
862 "Failed to init sclk threshold!", result = tmp_result);
863
864 return result;
865 }
866
867 /**
868 * Checks if we want to support voltage control
869 *
870 * @param hwmgr the address of the powerplay hardware manager.
871 */
872 static bool fiji_voltage_control(const struct pp_hwmgr *hwmgr)
873 {
874 const struct fiji_hwmgr *data =
875 (const struct fiji_hwmgr *)(hwmgr->backend);
876
877 return (FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control);
878 }
879
880 /**
881 * Enable voltage control
882 *
883 * @param hwmgr the address of the powerplay hardware manager.
884 * @return always 0
885 */
886 static int fiji_enable_voltage_control(struct pp_hwmgr *hwmgr)
887 {
888 /* enable voltage control */
889 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
890 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1);
891
892 return 0;
893 }
894
895 /**
896 * Remove repeated voltage values and create table with unique values.
897 *
898 * @param hwmgr the address of the powerplay hardware manager.
899 * @param vol_table the pointer to changing voltage table
900 * @return 0 in success
901 */
902
903 static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr,
904 struct pp_atomctrl_voltage_table *vol_table)
905 {
906 uint32_t i, j;
907 uint16_t vvalue;
908 bool found = false;
909 struct pp_atomctrl_voltage_table *table;
910
911 PP_ASSERT_WITH_CODE((NULL != vol_table),
912 "Voltage Table empty.", return -EINVAL);
913 table = kzalloc(sizeof(struct pp_atomctrl_voltage_table),
914 GFP_KERNEL);
915
916 if (NULL == table)
917 return -ENOMEM;
918
919 table->mask_low = vol_table->mask_low;
920 table->phase_delay = vol_table->phase_delay;
921
922 for (i = 0; i < vol_table->count; i++) {
923 vvalue = vol_table->entries[i].value;
924 found = false;
925
926 for (j = 0; j < table->count; j++) {
927 if (vvalue == table->entries[j].value) {
928 found = true;
929 break;
930 }
931 }
932
933 if (!found) {
934 table->entries[table->count].value = vvalue;
935 table->entries[table->count].smio_low =
936 vol_table->entries[i].smio_low;
937 table->count++;
938 }
939 }
940
941 memcpy(vol_table, table, sizeof(struct pp_atomctrl_voltage_table));
942 kfree(table);
943
944 return 0;
945 }
946
947 static int fiji_get_svi2_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
948 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
949 {
950 uint32_t i;
951 int result;
952 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
953 struct pp_atomctrl_voltage_table *vol_table = &(data->mvdd_voltage_table);
954
955 PP_ASSERT_WITH_CODE((0 != dep_table->count),
956 "Voltage Dependency Table empty.", return -EINVAL);
957
958 vol_table->mask_low = 0;
959 vol_table->phase_delay = 0;
960 vol_table->count = dep_table->count;
961
962 for (i = 0; i < dep_table->count; i++) {
963 vol_table->entries[i].value = dep_table->entries[i].mvdd;
964 vol_table->entries[i].smio_low = 0;
965 }
966
967 result = fiji_trim_voltage_table(hwmgr, vol_table);
968 PP_ASSERT_WITH_CODE((0 == result),
969 "Failed to trim MVDD table.", return result);
970
971 return 0;
972 }
973
974 static int fiji_get_svi2_vddci_voltage_table(struct pp_hwmgr *hwmgr,
975 phm_ppt_v1_clock_voltage_dependency_table *dep_table)
976 {
977 uint32_t i;
978 int result;
979 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
980 struct pp_atomctrl_voltage_table *vol_table = &(data->vddci_voltage_table);
981
982 PP_ASSERT_WITH_CODE((0 != dep_table->count),
983 "Voltage Dependency Table empty.", return -EINVAL);
984
985 vol_table->mask_low = 0;
986 vol_table->phase_delay = 0;
987 vol_table->count = dep_table->count;
988
989 for (i = 0; i < dep_table->count; i++) {
990 vol_table->entries[i].value = dep_table->entries[i].vddci;
991 vol_table->entries[i].smio_low = 0;
992 }
993
994 result = fiji_trim_voltage_table(hwmgr, vol_table);
995 PP_ASSERT_WITH_CODE((0 == result),
996 "Failed to trim VDDCI table.", return result);
997
998 return 0;
999 }
1000
1001 static int fiji_get_svi2_vdd_voltage_table(struct pp_hwmgr *hwmgr,
1002 phm_ppt_v1_voltage_lookup_table *lookup_table)
1003 {
1004 int i = 0;
1005 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1006 struct pp_atomctrl_voltage_table *vol_table = &(data->vddc_voltage_table);
1007
1008 PP_ASSERT_WITH_CODE((0 != lookup_table->count),
1009 "Voltage Lookup Table empty.", return -EINVAL);
1010
1011 vol_table->mask_low = 0;
1012 vol_table->phase_delay = 0;
1013
1014 vol_table->count = lookup_table->count;
1015
1016 for (i = 0; i < vol_table->count; i++) {
1017 vol_table->entries[i].value = lookup_table->entries[i].us_vdd;
1018 vol_table->entries[i].smio_low = 0;
1019 }
1020
1021 return 0;
1022 }
1023
1024 /* ---- Voltage Tables ----
1025 * If the voltage table would be bigger than
1026 * what will fit into the state table on
1027 * the SMC keep only the higher entries.
1028 */
1029 static void fiji_trim_voltage_table_to_fit_state_table(struct pp_hwmgr *hwmgr,
1030 uint32_t max_vol_steps, struct pp_atomctrl_voltage_table *vol_table)
1031 {
1032 unsigned int i, diff;
1033
1034 if (vol_table->count <= max_vol_steps)
1035 return;
1036
1037 diff = vol_table->count - max_vol_steps;
1038
1039 for (i = 0; i < max_vol_steps; i++)
1040 vol_table->entries[i] = vol_table->entries[i + diff];
1041
1042 vol_table->count = max_vol_steps;
1043
1044 return;
1045 }
1046
1047 /**
1048 * Create Voltage Tables.
1049 *
1050 * @param hwmgr the address of the powerplay hardware manager.
1051 * @return always 0
1052 */
1053 static int fiji_construct_voltage_tables(struct pp_hwmgr *hwmgr)
1054 {
1055 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1056 struct phm_ppt_v1_information *table_info =
1057 (struct phm_ppt_v1_information *)hwmgr->pptable;
1058 int result;
1059
1060 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1061 result = atomctrl_get_voltage_table_v3(hwmgr,
1062 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT,
1063 &(data->mvdd_voltage_table));
1064 PP_ASSERT_WITH_CODE((0 == result),
1065 "Failed to retrieve MVDD table.",
1066 return result);
1067 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1068 result = fiji_get_svi2_mvdd_voltage_table(hwmgr,
1069 table_info->vdd_dep_on_mclk);
1070 PP_ASSERT_WITH_CODE((0 == result),
1071 "Failed to retrieve SVI2 MVDD table from dependancy table.",
1072 return result;);
1073 }
1074
1075 if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1076 result = atomctrl_get_voltage_table_v3(hwmgr,
1077 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT,
1078 &(data->vddci_voltage_table));
1079 PP_ASSERT_WITH_CODE((0 == result),
1080 "Failed to retrieve VDDCI table.",
1081 return result);
1082 } else if (FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1083 result = fiji_get_svi2_vddci_voltage_table(hwmgr,
1084 table_info->vdd_dep_on_mclk);
1085 PP_ASSERT_WITH_CODE((0 == result),
1086 "Failed to retrieve SVI2 VDDCI table from dependancy table.",
1087 return result);
1088 }
1089
1090 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1091 result = fiji_get_svi2_vdd_voltage_table(hwmgr,
1092 table_info->vddc_lookup_table);
1093 PP_ASSERT_WITH_CODE((0 == result),
1094 "Failed to retrieve SVI2 VDDC table from lookup table.",
1095 return result);
1096 }
1097
1098 PP_ASSERT_WITH_CODE(
1099 (data->vddc_voltage_table.count <= (SMU73_MAX_LEVELS_VDDC)),
1100 "Too many voltage values for VDDC. Trimming to fit state table.",
1101 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1102 SMU73_MAX_LEVELS_VDDC, &(data->vddc_voltage_table)));
1103
1104 PP_ASSERT_WITH_CODE(
1105 (data->vddci_voltage_table.count <= (SMU73_MAX_LEVELS_VDDCI)),
1106 "Too many voltage values for VDDCI. Trimming to fit state table.",
1107 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1108 SMU73_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table)));
1109
1110 PP_ASSERT_WITH_CODE(
1111 (data->mvdd_voltage_table.count <= (SMU73_MAX_LEVELS_MVDD)),
1112 "Too many voltage values for MVDD. Trimming to fit state table.",
1113 fiji_trim_voltage_table_to_fit_state_table(hwmgr,
1114 SMU73_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table)));
1115
1116 return 0;
1117 }
1118
1119 static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
1120 {
1121 /* Program additional LP registers
1122 * that are no longer programmed by VBIOS
1123 */
1124 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
1125 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
1126 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
1127 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
1128 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
1129 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
1130 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
1131 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
1132 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
1133 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
1134 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
1135 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
1136 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
1137 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
1138
1139 return 0;
1140 }
1141
1142 /**
1143 * Programs static screed detection parameters
1144 *
1145 * @param hwmgr the address of the powerplay hardware manager.
1146 * @return always 0
1147 */
1148 static int fiji_program_static_screen_threshold_parameters(
1149 struct pp_hwmgr *hwmgr)
1150 {
1151 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1152
1153 /* Set static screen threshold unit */
1154 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1155 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT,
1156 data->static_screen_threshold_unit);
1157 /* Set static screen threshold */
1158 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1159 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD,
1160 data->static_screen_threshold);
1161
1162 return 0;
1163 }
1164
1165 /**
1166 * Setup display gap for glitch free memory clock switching.
1167 *
1168 * @param hwmgr the address of the powerplay hardware manager.
1169 * @return always 0
1170 */
1171 static int fiji_enable_display_gap(struct pp_hwmgr *hwmgr)
1172 {
1173 uint32_t displayGap =
1174 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1175 ixCG_DISPLAY_GAP_CNTL);
1176
1177 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1178 DISP_GAP, DISPLAY_GAP_IGNORE);
1179
1180 displayGap = PHM_SET_FIELD(displayGap, CG_DISPLAY_GAP_CNTL,
1181 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK);
1182
1183 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1184 ixCG_DISPLAY_GAP_CNTL, displayGap);
1185
1186 return 0;
1187 }
1188
1189 /**
1190 * Programs activity state transition voting clients
1191 *
1192 * @param hwmgr the address of the powerplay hardware manager.
1193 * @return always 0
1194 */
1195 static int fiji_program_voting_clients(struct pp_hwmgr *hwmgr)
1196 {
1197 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1198
1199 /* Clear reset for voting clients before enabling DPM */
1200 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1201 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
1202 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
1203 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
1204
1205 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1206 ixCG_FREQ_TRAN_VOTING_0, data->voting_rights_clients0);
1207 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1208 ixCG_FREQ_TRAN_VOTING_1, data->voting_rights_clients1);
1209 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1210 ixCG_FREQ_TRAN_VOTING_2, data->voting_rights_clients2);
1211 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1212 ixCG_FREQ_TRAN_VOTING_3, data->voting_rights_clients3);
1213 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1214 ixCG_FREQ_TRAN_VOTING_4, data->voting_rights_clients4);
1215 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1216 ixCG_FREQ_TRAN_VOTING_5, data->voting_rights_clients5);
1217 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1218 ixCG_FREQ_TRAN_VOTING_6, data->voting_rights_clients6);
1219 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1220 ixCG_FREQ_TRAN_VOTING_7, data->voting_rights_clients7);
1221
1222 return 0;
1223 }
1224
1225 /**
1226 * Get the location of various tables inside the FW image.
1227 *
1228 * @param hwmgr the address of the powerplay hardware manager.
1229 * @return always 0
1230 */
1231 static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
1232 {
1233 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1234 struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smumgr->backend);
1235 uint32_t tmp;
1236 int result;
1237 bool error = false;
1238
1239 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1240 SMU7_FIRMWARE_HEADER_LOCATION +
1241 offsetof(SMU73_Firmware_Header, DpmTable),
1242 &tmp, data->sram_end);
1243
1244 if (0 == result)
1245 data->dpm_table_start = tmp;
1246
1247 error |= (0 != result);
1248
1249 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1250 SMU7_FIRMWARE_HEADER_LOCATION +
1251 offsetof(SMU73_Firmware_Header, SoftRegisters),
1252 &tmp, data->sram_end);
1253
1254 if (!result) {
1255 data->soft_regs_start = tmp;
1256 smu_data->soft_regs_start = tmp;
1257 }
1258
1259 error |= (0 != result);
1260
1261 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1262 SMU7_FIRMWARE_HEADER_LOCATION +
1263 offsetof(SMU73_Firmware_Header, mcRegisterTable),
1264 &tmp, data->sram_end);
1265
1266 if (!result)
1267 data->mc_reg_table_start = tmp;
1268
1269 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1270 SMU7_FIRMWARE_HEADER_LOCATION +
1271 offsetof(SMU73_Firmware_Header, FanTable),
1272 &tmp, data->sram_end);
1273
1274 if (!result)
1275 data->fan_table_start = tmp;
1276
1277 error |= (0 != result);
1278
1279 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1280 SMU7_FIRMWARE_HEADER_LOCATION +
1281 offsetof(SMU73_Firmware_Header, mcArbDramTimingTable),
1282 &tmp, data->sram_end);
1283
1284 if (!result)
1285 data->arb_table_start = tmp;
1286
1287 error |= (0 != result);
1288
1289 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
1290 SMU7_FIRMWARE_HEADER_LOCATION +
1291 offsetof(SMU73_Firmware_Header, Version),
1292 &tmp, data->sram_end);
1293
1294 if (!result)
1295 hwmgr->microcode_version_info.SMC = tmp;
1296
1297 error |= (0 != result);
1298
1299 return error ? -1 : 0;
1300 }
1301
1302 /* Copy one arb setting to another and then switch the active set.
1303 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants.
1304 */
1305 static int fiji_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
1306 uint32_t arb_src, uint32_t arb_dest)
1307 {
1308 uint32_t mc_arb_dram_timing;
1309 uint32_t mc_arb_dram_timing2;
1310 uint32_t burst_time;
1311 uint32_t mc_cg_config;
1312
1313 switch (arb_src) {
1314 case MC_CG_ARB_FREQ_F0:
1315 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1316 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1317 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1318 break;
1319 case MC_CG_ARB_FREQ_F1:
1320 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
1321 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
1322 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
1323 break;
1324 default:
1325 return -EINVAL;
1326 }
1327
1328 switch (arb_dest) {
1329 case MC_CG_ARB_FREQ_F0:
1330 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1331 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1332 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
1333 break;
1334 case MC_CG_ARB_FREQ_F1:
1335 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1336 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1337 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
1338 break;
1339 default:
1340 return -EINVAL;
1341 }
1342
1343 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
1344 mc_cg_config |= 0x0000000F;
1345 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
1346 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
1347
1348 return 0;
1349 }
1350
1351 /**
1352 * Initial switch from ARB F0->F1
1353 *
1354 * @param hwmgr the address of the powerplay hardware manager.
1355 * @return always 0
1356 * This function is to be called from the SetPowerState table.
1357 */
1358 static int fiji_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
1359 {
1360 return fiji_copy_and_switch_arb_sets(hwmgr,
1361 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1362 }
1363
1364 static int fiji_reset_single_dpm_table(struct pp_hwmgr *hwmgr,
1365 struct fiji_single_dpm_table *dpm_table, uint32_t count)
1366 {
1367 int i;
1368 PP_ASSERT_WITH_CODE(count <= MAX_REGULAR_DPM_NUMBER,
1369 "Fatal error, can not set up single DPM table entries "
1370 "to exceed max number!",);
1371
1372 dpm_table->count = count;
1373 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
1374 dpm_table->dpm_levels[i].enabled = false;
1375
1376 return 0;
1377 }
1378
1379 static void fiji_setup_pcie_table_entry(
1380 struct fiji_single_dpm_table *dpm_table,
1381 uint32_t index, uint32_t pcie_gen,
1382 uint32_t pcie_lanes)
1383 {
1384 dpm_table->dpm_levels[index].value = pcie_gen;
1385 dpm_table->dpm_levels[index].param1 = pcie_lanes;
1386 dpm_table->dpm_levels[index].enabled = 1;
1387 }
1388
1389 static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
1390 {
1391 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1392 struct phm_ppt_v1_information *table_info =
1393 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1394 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1395 uint32_t i, max_entry;
1396
1397 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels ||
1398 data->use_pcie_power_saving_levels), "No pcie performance levels!",
1399 return -EINVAL);
1400
1401 if (data->use_pcie_performance_levels &&
1402 !data->use_pcie_power_saving_levels) {
1403 data->pcie_gen_power_saving = data->pcie_gen_performance;
1404 data->pcie_lane_power_saving = data->pcie_lane_performance;
1405 } else if (!data->use_pcie_performance_levels &&
1406 data->use_pcie_power_saving_levels) {
1407 data->pcie_gen_performance = data->pcie_gen_power_saving;
1408 data->pcie_lane_performance = data->pcie_lane_power_saving;
1409 }
1410
1411 fiji_reset_single_dpm_table(hwmgr,
1412 &data->dpm_table.pcie_speed_table, SMU73_MAX_LEVELS_LINK);
1413
1414 if (pcie_table != NULL) {
1415 /* max_entry is used to make sure we reserve one PCIE level
1416 * for boot level (fix for A+A PSPP issue).
1417 * If PCIE table from PPTable have ULV entry + 8 entries,
1418 * then ignore the last entry.*/
1419 max_entry = (SMU73_MAX_LEVELS_LINK < pcie_table->count) ?
1420 SMU73_MAX_LEVELS_LINK : pcie_table->count;
1421 for (i = 1; i < max_entry; i++) {
1422 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1,
1423 get_pcie_gen_support(data->pcie_gen_cap,
1424 pcie_table->entries[i].gen_speed),
1425 get_pcie_lane_support(data->pcie_lane_cap,
1426 pcie_table->entries[i].lane_width));
1427 }
1428 data->dpm_table.pcie_speed_table.count = max_entry - 1;
1429 } else {
1430 /* Hardcode Pcie Table */
1431 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0,
1432 get_pcie_gen_support(data->pcie_gen_cap,
1433 PP_Min_PCIEGen),
1434 get_pcie_lane_support(data->pcie_lane_cap,
1435 PP_Max_PCIELane));
1436 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1,
1437 get_pcie_gen_support(data->pcie_gen_cap,
1438 PP_Min_PCIEGen),
1439 get_pcie_lane_support(data->pcie_lane_cap,
1440 PP_Max_PCIELane));
1441 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2,
1442 get_pcie_gen_support(data->pcie_gen_cap,
1443 PP_Max_PCIEGen),
1444 get_pcie_lane_support(data->pcie_lane_cap,
1445 PP_Max_PCIELane));
1446 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3,
1447 get_pcie_gen_support(data->pcie_gen_cap,
1448 PP_Max_PCIEGen),
1449 get_pcie_lane_support(data->pcie_lane_cap,
1450 PP_Max_PCIELane));
1451 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4,
1452 get_pcie_gen_support(data->pcie_gen_cap,
1453 PP_Max_PCIEGen),
1454 get_pcie_lane_support(data->pcie_lane_cap,
1455 PP_Max_PCIELane));
1456 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5,
1457 get_pcie_gen_support(data->pcie_gen_cap,
1458 PP_Max_PCIEGen),
1459 get_pcie_lane_support(data->pcie_lane_cap,
1460 PP_Max_PCIELane));
1461
1462 data->dpm_table.pcie_speed_table.count = 6;
1463 }
1464 /* Populate last level for boot PCIE level, but do not increment count. */
1465 fiji_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table,
1466 data->dpm_table.pcie_speed_table.count,
1467 get_pcie_gen_support(data->pcie_gen_cap,
1468 PP_Min_PCIEGen),
1469 get_pcie_lane_support(data->pcie_lane_cap,
1470 PP_Max_PCIELane));
1471
1472 return 0;
1473 }
1474
1475 /*
1476 * This function is to initalize all DPM state tables
1477 * for SMU7 based on the dependency table.
1478 * Dynamic state patching function will then trim these
1479 * state tables to the allowed range based
1480 * on the power policy or external client requests,
1481 * such as UVD request, etc.
1482 */
1483 static int fiji_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
1484 {
1485 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1486 struct phm_ppt_v1_information *table_info =
1487 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1488 uint32_t i;
1489
1490 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table =
1491 table_info->vdd_dep_on_sclk;
1492 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
1493 table_info->vdd_dep_on_mclk;
1494
1495 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL,
1496 "SCLK dependency table is missing. This table is mandatory",
1497 return -EINVAL);
1498 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1,
1499 "SCLK dependency table has to have is missing. "
1500 "This table is mandatory",
1501 return -EINVAL);
1502
1503 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL,
1504 "MCLK dependency table is missing. This table is mandatory",
1505 return -EINVAL);
1506 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1,
1507 "MCLK dependency table has to have is missing. "
1508 "This table is mandatory",
1509 return -EINVAL);
1510
1511 /* clear the state table to reset everything to default */
1512 fiji_reset_single_dpm_table(hwmgr,
1513 &data->dpm_table.sclk_table, SMU73_MAX_LEVELS_GRAPHICS);
1514 fiji_reset_single_dpm_table(hwmgr,
1515 &data->dpm_table.mclk_table, SMU73_MAX_LEVELS_MEMORY);
1516
1517 /* Initialize Sclk DPM table based on allow Sclk values */
1518 data->dpm_table.sclk_table.count = 0;
1519 for (i = 0; i < dep_sclk_table->count; i++) {
1520 if (i == 0 || data->dpm_table.sclk_table.dpm_levels
1521 [data->dpm_table.sclk_table.count - 1].value !=
1522 dep_sclk_table->entries[i].clk) {
1523 data->dpm_table.sclk_table.dpm_levels
1524 [data->dpm_table.sclk_table.count].value =
1525 dep_sclk_table->entries[i].clk;
1526 data->dpm_table.sclk_table.dpm_levels
1527 [data->dpm_table.sclk_table.count].enabled =
1528 (i == 0) ? true : false;
1529 data->dpm_table.sclk_table.count++;
1530 }
1531 }
1532
1533 /* Initialize Mclk DPM table based on allow Mclk values */
1534 data->dpm_table.mclk_table.count = 0;
1535 for (i=0; i<dep_mclk_table->count; i++) {
1536 if ( i==0 || data->dpm_table.mclk_table.dpm_levels
1537 [data->dpm_table.mclk_table.count - 1].value !=
1538 dep_mclk_table->entries[i].clk) {
1539 data->dpm_table.mclk_table.dpm_levels
1540 [data->dpm_table.mclk_table.count].value =
1541 dep_mclk_table->entries[i].clk;
1542 data->dpm_table.mclk_table.dpm_levels
1543 [data->dpm_table.mclk_table.count].enabled =
1544 (i == 0) ? true : false;
1545 data->dpm_table.mclk_table.count++;
1546 }
1547 }
1548
1549 /* setup PCIE gen speed levels */
1550 fiji_setup_default_pcie_table(hwmgr);
1551
1552 /* save a copy of the default DPM table */
1553 memcpy(&(data->golden_dpm_table), &(data->dpm_table),
1554 sizeof(struct fiji_dpm_table));
1555
1556 return 0;
1557 }
1558
1559 /**
1560 * @brief PhwFiji_GetVoltageOrder
1561 * Returns index of requested voltage record in lookup(table)
1562 * @param lookup_table - lookup list to search in
1563 * @param voltage - voltage to look for
1564 * @return 0 on success
1565 */
1566 uint8_t fiji_get_voltage_index(
1567 struct phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t voltage)
1568 {
1569 uint8_t count = (uint8_t) (lookup_table->count);
1570 uint8_t i;
1571
1572 PP_ASSERT_WITH_CODE((NULL != lookup_table),
1573 "Lookup Table empty.", return 0);
1574 PP_ASSERT_WITH_CODE((0 != count),
1575 "Lookup Table empty.", return 0);
1576
1577 for (i = 0; i < lookup_table->count; i++) {
1578 /* find first voltage equal or bigger than requested */
1579 if (lookup_table->entries[i].us_vdd >= voltage)
1580 return i;
1581 }
1582 /* voltage is bigger than max voltage in the table */
1583 return i - 1;
1584 }
1585
1586 /**
1587 * Preparation of vddc and vddgfx CAC tables for SMC.
1588 *
1589 * @param hwmgr the address of the hardware manager
1590 * @param table the SMC DPM table structure to be populated
1591 * @return always 0
1592 */
1593 static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
1594 struct SMU73_Discrete_DpmTable *table)
1595 {
1596 uint32_t count;
1597 uint8_t index;
1598 int result = 0;
1599 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1600 struct phm_ppt_v1_information *table_info =
1601 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1602 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
1603 table_info->vddc_lookup_table;
1604 /* tables is already swapped, so in order to use the value from it,
1605 * we need to swap it back.
1606 * We are populating vddc CAC data to BapmVddc table
1607 * in split and merged mode
1608 */
1609 for( count = 0; count<lookup_table->count; count++) {
1610 index = fiji_get_voltage_index(lookup_table,
1611 data->vddc_voltage_table.entries[count].value);
1612 table->BapmVddcVidLoSidd[count] = (uint8_t) ((6200 -
1613 (lookup_table->entries[index].us_cac_low *
1614 VOLTAGE_SCALE)) / 25);
1615 table->BapmVddcVidHiSidd[count] = (uint8_t) ((6200 -
1616 (lookup_table->entries[index].us_cac_high *
1617 VOLTAGE_SCALE)) / 25);
1618 }
1619
1620 return result;
1621 }
1622
1623 /**
1624 * Preparation of voltage tables for SMC.
1625 *
1626 * @param hwmgr the address of the hardware manager
1627 * @param table the SMC DPM table structure to be populated
1628 * @return always 0
1629 */
1630
1631 int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
1632 struct SMU73_Discrete_DpmTable *table)
1633 {
1634 int result;
1635
1636 result = fiji_populate_cac_table(hwmgr, table);
1637 PP_ASSERT_WITH_CODE(0 == result,
1638 "can not populate CAC voltage tables to SMC",
1639 return -EINVAL);
1640
1641 return 0;
1642 }
1643
1644 static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
1645 struct SMU73_Discrete_Ulv *state)
1646 {
1647 int result = 0;
1648 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1649 struct phm_ppt_v1_information *table_info =
1650 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1651
1652 state->CcPwrDynRm = 0;
1653 state->CcPwrDynRm1 = 0;
1654
1655 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
1656 state->VddcOffsetVid = (uint8_t)( table_info->us_ulv_voltage_offset *
1657 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1 );
1658
1659 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
1660
1661 if (!result) {
1662 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
1663 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
1664 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
1665 }
1666 return result;
1667 }
1668
1669 static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
1670 struct SMU73_Discrete_DpmTable *table)
1671 {
1672 return fiji_populate_ulv_level(hwmgr, &table->Ulv);
1673 }
1674
1675 static int32_t fiji_get_dpm_level_enable_mask_value(
1676 struct fiji_single_dpm_table* dpm_table)
1677 {
1678 int32_t i;
1679 int32_t mask = 0;
1680
1681 for (i = dpm_table->count; i > 0; i--) {
1682 mask = mask << 1;
1683 if (dpm_table->dpm_levels[i - 1].enabled)
1684 mask |= 0x1;
1685 else
1686 mask &= 0xFFFFFFFE;
1687 }
1688 return mask;
1689 }
1690
1691 static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
1692 struct SMU73_Discrete_DpmTable *table)
1693 {
1694 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1695 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1696 int i;
1697
1698 /* Index (dpm_table->pcie_speed_table.count)
1699 * is reserved for PCIE boot level. */
1700 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
1701 table->LinkLevel[i].PcieGenSpeed =
1702 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
1703 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
1704 dpm_table->pcie_speed_table.dpm_levels[i].param1);
1705 table->LinkLevel[i].EnabledForActivity = 1;
1706 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
1707 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
1708 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1709 }
1710
1711 data->smc_state_table.LinkLevelCount =
1712 (uint8_t)dpm_table->pcie_speed_table.count;
1713 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
1714 fiji_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
1715
1716 return 0;
1717 }
1718
1719 /**
1720 * Calculates the SCLK dividers using the provided engine clock
1721 *
1722 * @param hwmgr the address of the hardware manager
1723 * @param clock the engine clock to use to populate the structure
1724 * @param sclk the SMC SCLK structure to be populated
1725 */
1726 static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
1727 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
1728 {
1729 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1730 struct pp_atomctrl_clock_dividers_vi dividers;
1731 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
1732 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1733 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1734 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1735 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1736 uint32_t ref_clock;
1737 uint32_t ref_divider;
1738 uint32_t fbdiv;
1739 int result;
1740
1741 /* get the engine clock dividers for this clock value */
1742 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);
1743
1744 PP_ASSERT_WITH_CODE(result == 0,
1745 "Error retrieving Engine Clock dividers from VBIOS.",
1746 return result);
1747
1748 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref. */
1749 ref_clock = atomctrl_get_reference_clock(hwmgr);
1750 ref_divider = 1 + dividers.uc_pll_ref_div;
1751
1752 /* low 14 bits is fraction and high 12 bits is divider */
1753 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
1754
1755 /* SPLL_FUNC_CNTL setup */
1756 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1757 SPLL_REF_DIV, dividers.uc_pll_ref_div);
1758 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
1759 SPLL_PDIV_A, dividers.uc_pll_post_div);
1760
1761 /* SPLL_FUNC_CNTL_3 setup*/
1762 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1763 SPLL_FB_DIV, fbdiv);
1764
1765 /* set to use fractional accumulation*/
1766 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
1767 SPLL_DITHEN, 1);
1768
1769 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1770 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
1771 struct pp_atomctrl_internal_ss_info ssInfo;
1772
1773 uint32_t vco_freq = clock * dividers.uc_pll_post_div;
1774 if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
1775 vco_freq, &ssInfo)) {
1776 /*
1777 * ss_info.speed_spectrum_percentage -- in unit of 0.01%
1778 * ss_info.speed_spectrum_rate -- in unit of khz
1779 *
1780 * clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2
1781 */
1782 uint32_t clk_s = ref_clock * 5 /
1783 (ref_divider * ssInfo.speed_spectrum_rate);
1784 /* clkv = 2 * D * fbdiv / NS */
1785 uint32_t clk_v = 4 * ssInfo.speed_spectrum_percentage *
1786 fbdiv / (clk_s * 10000);
1787
1788 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1789 CG_SPLL_SPREAD_SPECTRUM, CLKS, clk_s);
1790 cg_spll_spread_spectrum = PHM_SET_FIELD(cg_spll_spread_spectrum,
1791 CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
1792 cg_spll_spread_spectrum_2 = PHM_SET_FIELD(cg_spll_spread_spectrum_2,
1793 CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clk_v);
1794 }
1795 }
1796
1797 sclk->SclkFrequency = clock;
1798 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
1799 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
1800 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
1801 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
1802 sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
1803
1804 return 0;
1805 }
1806
1807 static uint16_t fiji_find_closest_vddci(struct pp_hwmgr *hwmgr, uint16_t vddci)
1808 {
1809 uint32_t i;
1810 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1811 struct pp_atomctrl_voltage_table *vddci_table =
1812 &(data->vddci_voltage_table);
1813
1814 for (i = 0; i < vddci_table->count; i++) {
1815 if (vddci_table->entries[i].value >= vddci)
1816 return vddci_table->entries[i].value;
1817 }
1818
1819 PP_ASSERT_WITH_CODE(false,
1820 "VDDCI is larger than max VDDCI in VDDCI Voltage Table!",
1821 return vddci_table->entries[i].value);
1822 }
1823
1824 static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
1825 struct phm_ppt_v1_clock_voltage_dependency_table* dep_table,
1826 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
1827 {
1828 uint32_t i;
1829 uint16_t vddci;
1830 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1831
1832 *voltage = *mvdd = 0;
1833
1834 /* clock - voltage dependency table is empty table */
1835 if (dep_table->count == 0)
1836 return -EINVAL;
1837
1838 for (i = 0; i < dep_table->count; i++) {
1839 /* find first sclk bigger than request */
1840 if (dep_table->entries[i].clk >= clock) {
1841 *voltage |= (dep_table->entries[i].vddc *
1842 VOLTAGE_SCALE) << VDDC_SHIFT;
1843 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1844 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1845 VOLTAGE_SCALE) << VDDCI_SHIFT;
1846 else if (dep_table->entries[i].vddci)
1847 *voltage |= (dep_table->entries[i].vddci *
1848 VOLTAGE_SCALE) << VDDCI_SHIFT;
1849 else {
1850 vddci = fiji_find_closest_vddci(hwmgr,
1851 (dep_table->entries[i].vddc -
1852 (uint16_t)data->vddc_vddci_delta));
1853 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1854 }
1855
1856 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1857 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
1858 VOLTAGE_SCALE;
1859 else if (dep_table->entries[i].mvdd)
1860 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
1861 VOLTAGE_SCALE;
1862
1863 *voltage |= 1 << PHASES_SHIFT;
1864 return 0;
1865 }
1866 }
1867
1868 /* sclk is bigger than max sclk in the dependence table */
1869 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1870
1871 if (FIJI_VOLTAGE_CONTROL_NONE == data->vddci_control)
1872 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
1873 VOLTAGE_SCALE) << VDDCI_SHIFT;
1874 else if (dep_table->entries[i-1].vddci) {
1875 vddci = fiji_find_closest_vddci(hwmgr,
1876 (dep_table->entries[i].vddc -
1877 (uint16_t)data->vddc_vddci_delta));
1878 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1879 }
1880
1881 if (FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control)
1882 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
1883 else if (dep_table->entries[i].mvdd)
1884 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
1885
1886 return 0;
1887 }
1888 /**
1889 * Populates single SMC SCLK structure using the provided engine clock
1890 *
1891 * @param hwmgr the address of the hardware manager
1892 * @param clock the engine clock to use to populate the structure
1893 * @param sclk the SMC SCLK structure to be populated
1894 */
1895
1896 static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
1897 uint32_t clock, uint16_t sclk_al_threshold,
1898 struct SMU73_Discrete_GraphicsLevel *level)
1899 {
1900 int result;
1901 /* PP_Clocks minClocks; */
1902 uint32_t threshold, mvdd;
1903 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1904 struct phm_ppt_v1_information *table_info =
1905 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1906
1907 result = fiji_calculate_sclk_params(hwmgr, clock, level);
1908
1909 /* populate graphics levels */
1910 result = fiji_get_dependency_volt_by_clk(hwmgr,
1911 table_info->vdd_dep_on_sclk, clock,
1912 &level->MinVoltage, &mvdd);
1913 PP_ASSERT_WITH_CODE((0 == result),
1914 "can not find VDDC voltage value for "
1915 "VDDC engine clock dependency table",
1916 return result);
1917
1918 level->SclkFrequency = clock;
1919 level->ActivityLevel = sclk_al_threshold;
1920 level->CcPwrDynRm = 0;
1921 level->CcPwrDynRm1 = 0;
1922 level->EnabledForActivity = 0;
1923 level->EnabledForThrottle = 1;
1924 level->UpHyst = 10;
1925 level->DownHyst = 0;
1926 level->VoltageDownHyst = 0;
1927 level->PowerThrottle = 0;
1928
1929 threshold = clock * data->fast_watermark_threshold / 100;
1930
1931 /*
1932 * TODO: get minimum clocks from dal configaration
1933 * PECI_GetMinClockSettings(hwmgr->pPECI, &minClocks);
1934 */
1935 /* data->DisplayTiming.minClockInSR = minClocks.engineClockInSR; */
1936
1937 /* get level->DeepSleepDivId
1938 if (phm_cap_enabled(hwmgr->platformDescriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
1939 {
1940 level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR);
1941 } */
1942
1943 /* Default to slow, highest DPM level will be
1944 * set to PPSMC_DISPLAY_WATERMARK_LOW later.
1945 */
1946 level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1947
1948 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1949 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkFrequency);
1950 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1951 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl3);
1952 CONVERT_FROM_HOST_TO_SMC_UL(level->CgSpllFuncCntl4);
1953 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum);
1954 CONVERT_FROM_HOST_TO_SMC_UL(level->SpllSpreadSpectrum2);
1955 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1956 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1957
1958 return 0;
1959 }
1960 /**
1961 * Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
1962 *
1963 * @param hwmgr the address of the hardware manager
1964 */
1965 static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1966 {
1967 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
1968 struct fiji_dpm_table *dpm_table = &data->dpm_table;
1969 struct phm_ppt_v1_information *table_info =
1970 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1971 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1972 uint8_t pcie_entry_cnt = (uint8_t) data->dpm_table.pcie_speed_table.count;
1973 int result = 0;
1974 uint32_t array = data->dpm_table_start +
1975 offsetof(SMU73_Discrete_DpmTable, GraphicsLevel);
1976 uint32_t array_size = sizeof(struct SMU73_Discrete_GraphicsLevel) *
1977 SMU73_MAX_LEVELS_GRAPHICS;
1978 struct SMU73_Discrete_GraphicsLevel *levels =
1979 data->smc_state_table.GraphicsLevel;
1980 uint32_t i, max_entry;
1981 uint8_t hightest_pcie_level_enabled = 0,
1982 lowest_pcie_level_enabled = 0,
1983 mid_pcie_level_enabled = 0,
1984 count = 0;
1985
1986 for (i = 0; i < dpm_table->sclk_table.count; i++) {
1987 result = fiji_populate_single_graphic_level(hwmgr,
1988 dpm_table->sclk_table.dpm_levels[i].value,
1989 (uint16_t)data->activity_target[i],
1990 &levels[i]);
1991 if (result)
1992 return result;
1993
1994 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1995 if (i > 1)
1996 levels[i].DeepSleepDivId = 0;
1997 }
1998
1999 /* Only enable level 0 for now.*/
2000 levels[0].EnabledForActivity = 1;
2001
2002 /* set highest level watermark to high */
2003 levels[dpm_table->sclk_table.count - 1].DisplayWatermark =
2004 PPSMC_DISPLAY_WATERMARK_HIGH;
2005
2006 data->smc_state_table.GraphicsDpmLevelCount =
2007 (uint8_t)dpm_table->sclk_table.count;
2008 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
2009 fiji_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2010
2011 if (pcie_table != NULL) {
2012 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
2013 "There must be 1 or more PCIE levels defined in PPTable.",
2014 return -EINVAL);
2015 max_entry = pcie_entry_cnt - 1;
2016 for (i = 0; i < dpm_table->sclk_table.count; i++)
2017 levels[i].pcieDpmLevel =
2018 (uint8_t) ((i < max_entry)? i : max_entry);
2019 } else {
2020 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2021 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2022 (1 << (hightest_pcie_level_enabled + 1))) != 0 ))
2023 hightest_pcie_level_enabled++;
2024
2025 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
2026 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2027 (1 << lowest_pcie_level_enabled)) == 0 ))
2028 lowest_pcie_level_enabled++;
2029
2030 while ((count < hightest_pcie_level_enabled) &&
2031 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
2032 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0 ))
2033 count++;
2034
2035 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1+ count) <
2036 hightest_pcie_level_enabled?
2037 (lowest_pcie_level_enabled + 1 + count) :
2038 hightest_pcie_level_enabled;
2039
2040 /* set pcieDpmLevel to hightest_pcie_level_enabled */
2041 for(i = 2; i < dpm_table->sclk_table.count; i++)
2042 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
2043
2044 /* set pcieDpmLevel to lowest_pcie_level_enabled */
2045 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
2046
2047 /* set pcieDpmLevel to mid_pcie_level_enabled */
2048 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
2049 }
2050 /* level count will send to smc once at init smc table and never change */
2051 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2052 (uint32_t)array_size, data->sram_end);
2053
2054 return result;
2055 }
2056
2057 /**
2058 * MCLK Frequency Ratio
2059 * SEQ_CG_RESP Bit[31:24] - 0x0
2060 * Bit[27:24] \96 DDR3 Frequency ratio
2061 * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz
2062 * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz
2063 * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz
2064 * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz
2065 * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz
2066 * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz
2067 * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz
2068 * 400 < 0x7 <= 450MHz, 800 < 0xF
2069 */
2070 static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock)
2071 {
2072 if (mem_clock <= 10000) return 0x0;
2073 if (mem_clock <= 15000) return 0x1;
2074 if (mem_clock <= 20000) return 0x2;
2075 if (mem_clock <= 25000) return 0x3;
2076 if (mem_clock <= 30000) return 0x4;
2077 if (mem_clock <= 35000) return 0x5;
2078 if (mem_clock <= 40000) return 0x6;
2079 if (mem_clock <= 45000) return 0x7;
2080 if (mem_clock <= 50000) return 0x8;
2081 if (mem_clock <= 55000) return 0x9;
2082 if (mem_clock <= 60000) return 0xa;
2083 if (mem_clock <= 65000) return 0xb;
2084 if (mem_clock <= 70000) return 0xc;
2085 if (mem_clock <= 75000) return 0xd;
2086 if (mem_clock <= 80000) return 0xe;
2087 /* mem_clock > 800MHz */
2088 return 0xf;
2089 }
2090
2091 /**
2092 * Populates the SMC MCLK structure using the provided memory clock
2093 *
2094 * @param hwmgr the address of the hardware manager
2095 * @param clock the memory clock to use to populate the structure
2096 * @param sclk the SMC SCLK structure to be populated
2097 */
2098 static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
2099 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)
2100 {
2101 struct pp_atomctrl_memory_clock_param mem_param;
2102 int result;
2103
2104 result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
2105 PP_ASSERT_WITH_CODE((0 == result),
2106 "Failed to get Memory PLL Dividers.",);
2107
2108 /* Save the result data to outpupt memory level structure */
2109 mclk->MclkFrequency = clock;
2110 mclk->MclkDivider = (uint8_t)mem_param.mpll_post_divider;
2111 mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);
2112
2113 return result;
2114 }
2115
2116 static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
2117 uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)
2118 {
2119 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2120 struct phm_ppt_v1_information *table_info =
2121 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2122 int result = 0;
2123
2124 if (table_info->vdd_dep_on_mclk) {
2125 result = fiji_get_dependency_volt_by_clk(hwmgr,
2126 table_info->vdd_dep_on_mclk, clock,
2127 &mem_level->MinVoltage, &mem_level->MinMvdd);
2128 PP_ASSERT_WITH_CODE((0 == result),
2129 "can not find MinVddc voltage value from memory "
2130 "VDDC voltage dependency table", return result);
2131 }
2132
2133 mem_level->EnabledForThrottle = 1;
2134 mem_level->EnabledForActivity = 0;
2135 mem_level->UpHyst = 0;
2136 mem_level->DownHyst = 100;
2137 mem_level->VoltageDownHyst = 0;
2138 mem_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
2139 mem_level->StutterEnable = false;
2140
2141 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2142
2143 /* enable stutter mode if all the follow condition applied
2144 * PECI_GetNumberOfActiveDisplays(hwmgr->pPECI,
2145 * &(data->DisplayTiming.numExistingDisplays));
2146 */
2147 data->display_timing.num_existing_displays = 1;
2148
2149 if ((data->mclk_stutter_mode_threshold) &&
2150 (clock <= data->mclk_stutter_mode_threshold) &&
2151 (!data->is_uvd_enabled) &&
2152 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
2153 STUTTER_ENABLE) & 0x1))
2154 mem_level->StutterEnable = true;
2155
2156 result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
2157 if (!result) {
2158 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
2159 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
2160 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
2161 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
2162 }
2163 return result;
2164 }
2165
2166 /**
2167 * Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
2168 *
2169 * @param hwmgr the address of the hardware manager
2170 */
2171 static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
2172 {
2173 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2174 struct fiji_dpm_table *dpm_table = &data->dpm_table;
2175 int result;
2176 /* populate MCLK dpm table to SMU7 */
2177 uint32_t array = data->dpm_table_start +
2178 offsetof(SMU73_Discrete_DpmTable, MemoryLevel);
2179 uint32_t array_size = sizeof(SMU73_Discrete_MemoryLevel) *
2180 SMU73_MAX_LEVELS_MEMORY;
2181 struct SMU73_Discrete_MemoryLevel *levels =
2182 data->smc_state_table.MemoryLevel;
2183 uint32_t i;
2184
2185 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2186 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
2187 "can not populate memory level as memory clock is zero",
2188 return -EINVAL);
2189 result = fiji_populate_single_memory_level(hwmgr,
2190 dpm_table->mclk_table.dpm_levels[i].value,
2191 &levels[i]);
2192 if (result)
2193 return result;
2194 }
2195
2196 /* Only enable level 0 for now. */
2197 levels[0].EnabledForActivity = 1;
2198
2199 /* in order to prevent MC activity from stutter mode to push DPM up.
2200 * the UVD change complements this by putting the MCLK in
2201 * a higher state by default such that we are not effected by
2202 * up threshold or and MCLK DPM latency.
2203 */
2204 levels[0].ActivityLevel = (uint16_t)data->mclk_dpm0_activity_target;
2205 CONVERT_FROM_HOST_TO_SMC_US(levels[0].ActivityLevel);
2206
2207 data->smc_state_table.MemoryDpmLevelCount =
2208 (uint8_t)dpm_table->mclk_table.count;
2209 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
2210 fiji_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2211 /* set highest level watermark to high */
2212 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
2213 PPSMC_DISPLAY_WATERMARK_HIGH;
2214
2215 /* level count will send to smc once at init smc table and never change */
2216 result = fiji_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels,
2217 (uint32_t)array_size, data->sram_end);
2218
2219 return result;
2220 }
2221
2222 /**
2223 * Populates the SMC MVDD structure using the provided memory clock.
2224 *
2225 * @param hwmgr the address of the hardware manager
2226 * @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
2227 * @param voltage the SMC VOLTAGE structure to be populated
2228 */
2229 int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
2230 uint32_t mclk, SMIO_Pattern *smio_pat)
2231 {
2232 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2233 struct phm_ppt_v1_information *table_info =
2234 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2235 uint32_t i = 0;
2236
2237 if (FIJI_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
2238 /* find mvdd value which clock is more than request */
2239 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
2240 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
2241 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
2242 break;
2243 }
2244 }
2245 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
2246 "MVDD Voltage is outside the supported range.",
2247 return -EINVAL);
2248 } else
2249 return -EINVAL;
2250
2251 return 0;
2252 }
2253
2254 static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
2255 SMU73_Discrete_DpmTable *table)
2256 {
2257 int result = 0;
2258 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2259 struct phm_ppt_v1_information *table_info =
2260 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2261 struct pp_atomctrl_clock_dividers_vi dividers;
2262 SMIO_Pattern vol_level;
2263 uint32_t mvdd;
2264 uint16_t us_mvdd;
2265 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
2266 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
2267
2268 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2269
2270 if (!data->sclk_dpm_key_disabled) {
2271 /* Get MinVoltage and Frequency from DPM0,
2272 * already converted to SMC_UL */
2273 table->ACPILevel.SclkFrequency =
2274 data->dpm_table.sclk_table.dpm_levels[0].value;
2275 result = fiji_get_dependency_volt_by_clk(hwmgr,
2276 table_info->vdd_dep_on_sclk,
2277 table->ACPILevel.SclkFrequency,
2278 &table->ACPILevel.MinVoltage, &mvdd);
2279 PP_ASSERT_WITH_CODE((0 == result),
2280 "Cannot find ACPI VDDC voltage value "
2281 "in Clock Dependency Table",);
2282 } else {
2283 table->ACPILevel.SclkFrequency =
2284 data->vbios_boot_state.sclk_bootup_value;
2285 table->ACPILevel.MinVoltage =
2286 data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE;
2287 }
2288
2289 /* get the engine clock dividers for this clock value */
2290 result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
2291 table->ACPILevel.SclkFrequency, &dividers);
2292 PP_ASSERT_WITH_CODE(result == 0,
2293 "Error retrieving Engine Clock dividers from VBIOS.",
2294 return result);
2295
2296 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
2297 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2298 table->ACPILevel.DeepSleepDivId = 0;
2299
2300 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2301 SPLL_PWRON, 0);
2302 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL,
2303 SPLL_RESET, 1);
2304 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
2305 SCLK_MUX_SEL, 4);
2306
2307 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2308 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2309 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
2310 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
2311 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
2312 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
2313 table->ACPILevel.CcPwrDynRm = 0;
2314 table->ACPILevel.CcPwrDynRm1 = 0;
2315
2316 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
2317 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
2318 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
2319 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
2320 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
2321 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
2322 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
2323 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
2324 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
2325 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
2326 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
2327
2328 if (!data->mclk_dpm_key_disabled) {
2329 /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
2330 table->MemoryACPILevel.MclkFrequency =
2331 data->dpm_table.mclk_table.dpm_levels[0].value;
2332 result = fiji_get_dependency_volt_by_clk(hwmgr,
2333 table_info->vdd_dep_on_mclk,
2334 table->MemoryACPILevel.MclkFrequency,
2335 &table->MemoryACPILevel.MinVoltage, &mvdd);
2336 PP_ASSERT_WITH_CODE((0 == result),
2337 "Cannot find ACPI VDDCI voltage value "
2338 "in Clock Dependency Table",);
2339 } else {
2340 table->MemoryACPILevel.MclkFrequency =
2341 data->vbios_boot_state.mclk_bootup_value;
2342 table->MemoryACPILevel.MinVoltage =
2343 data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE;
2344 }
2345
2346 us_mvdd = 0;
2347 if ((FIJI_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
2348 (data->mclk_dpm_key_disabled))
2349 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
2350 else {
2351 if (!fiji_populate_mvdd_value(hwmgr,
2352 data->dpm_table.mclk_table.dpm_levels[0].value,
2353 &vol_level))
2354 us_mvdd = vol_level.Voltage;
2355 }
2356
2357 table->MemoryACPILevel.MinMvdd =
2358 PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
2359
2360 table->MemoryACPILevel.EnabledForThrottle = 0;
2361 table->MemoryACPILevel.EnabledForActivity = 0;
2362 table->MemoryACPILevel.UpHyst = 0;
2363 table->MemoryACPILevel.DownHyst = 100;
2364 table->MemoryACPILevel.VoltageDownHyst = 0;
2365 table->MemoryACPILevel.ActivityLevel =
2366 PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
2367
2368 table->MemoryACPILevel.StutterEnable = false;
2369 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
2370 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
2371
2372 return result;
2373 }
2374
2375 static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2376 SMU73_Discrete_DpmTable *table)
2377 {
2378 int result = -EINVAL;
2379 uint8_t count;
2380 struct pp_atomctrl_clock_dividers_vi dividers;
2381 struct phm_ppt_v1_information *table_info =
2382 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2383 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2384 table_info->mm_dep_table;
2385 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2386
2387 table->VceLevelCount = (uint8_t)(mm_table->count);
2388 table->VceBootLevel = 0;
2389
2390 for(count = 0; count < table->VceLevelCount; count++) {
2391 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2392 table->VceLevel[count].MinVoltage = 0;
2393 table->VceLevel[count].MinVoltage |=
2394 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2395 table->VceLevel[count].MinVoltage |=
2396 ((mm_table->entries[count].vddc - data->vddc_vddci_delta) *
2397 VOLTAGE_SCALE) << VDDCI_SHIFT;
2398 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2399
2400 /*retrieve divider value for VBIOS */
2401 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2402 table->VceLevel[count].Frequency, &dividers);
2403 PP_ASSERT_WITH_CODE((0 == result),
2404 "can not find divide id for VCE engine clock",
2405 return result);
2406
2407 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2408
2409 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
2410 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
2411 }
2412 return result;
2413 }
2414
2415 static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
2416 SMU73_Discrete_DpmTable *table)
2417 {
2418 int result = -EINVAL;
2419 uint8_t count;
2420 struct pp_atomctrl_clock_dividers_vi dividers;
2421 struct phm_ppt_v1_information *table_info =
2422 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2423 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2424 table_info->mm_dep_table;
2425 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2426
2427 table->AcpLevelCount = (uint8_t)(mm_table->count);
2428 table->AcpBootLevel = 0;
2429
2430 for (count = 0; count < table->AcpLevelCount; count++) {
2431 table->AcpLevel[count].Frequency = mm_table->entries[count].aclk;
2432 table->AcpLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2433 VOLTAGE_SCALE) << VDDC_SHIFT;
2434 table->AcpLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2435 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2436 table->AcpLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2437
2438 /* retrieve divider value for VBIOS */
2439 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2440 table->AcpLevel[count].Frequency, &dividers);
2441 PP_ASSERT_WITH_CODE((0 == result),
2442 "can not find divide id for engine clock", return result);
2443
2444 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2445
2446 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
2447 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].MinVoltage);
2448 }
2449 return result;
2450 }
2451
2452 static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2453 SMU73_Discrete_DpmTable *table)
2454 {
2455 int result = -EINVAL;
2456 uint8_t count;
2457 struct pp_atomctrl_clock_dividers_vi dividers;
2458 struct phm_ppt_v1_information *table_info =
2459 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2460 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2461 table_info->mm_dep_table;
2462 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2463
2464 table->SamuBootLevel = 0;
2465 table->SamuLevelCount = (uint8_t)(mm_table->count);
2466
2467 for (count = 0; count < table->SamuLevelCount; count++) {
2468 /* not sure whether we need evclk or not */
2469 table->SamuLevel[count].MinVoltage = 0;
2470 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2471 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2472 VOLTAGE_SCALE) << VDDC_SHIFT;
2473 table->SamuLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2474 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2475 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2476
2477 /* retrieve divider value for VBIOS */
2478 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2479 table->SamuLevel[count].Frequency, &dividers);
2480 PP_ASSERT_WITH_CODE((0 == result),
2481 "can not find divide id for samu clock", return result);
2482
2483 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
2484
2485 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
2486 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
2487 }
2488 return result;
2489 }
2490
2491 static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
2492 int32_t eng_clock, int32_t mem_clock,
2493 struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs)
2494 {
2495 uint32_t dram_timing;
2496 uint32_t dram_timing2;
2497 uint32_t burstTime;
2498 ULONG state, trrds, trrdl;
2499 int result;
2500
2501 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
2502 eng_clock, mem_clock);
2503 PP_ASSERT_WITH_CODE(result == 0,
2504 "Error calling VBIOS to set DRAM_TIMING.", return result);
2505
2506 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
2507 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
2508 burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
2509
2510 state = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, STATE0);
2511 trrds = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDS0);
2512 trrdl = PHM_GET_FIELD(burstTime, MC_ARB_BURST_TIME, TRRDL0);
2513
2514 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
2515 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2516 arb_regs->McArbBurstTime = (uint8_t)burstTime;
2517 arb_regs->TRRDS = (uint8_t)trrds;
2518 arb_regs->TRRDL = (uint8_t)trrdl;
2519
2520 return 0;
2521 }
2522
2523 static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
2524 {
2525 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2526 struct SMU73_Discrete_MCArbDramTimingTable arb_regs;
2527 uint32_t i, j;
2528 int result = 0;
2529
2530 for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
2531 for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
2532 result = fiji_populate_memory_timing_parameters(hwmgr,
2533 data->dpm_table.sclk_table.dpm_levels[i].value,
2534 data->dpm_table.mclk_table.dpm_levels[j].value,
2535 &arb_regs.entries[i][j]);
2536 if (result)
2537 break;
2538 }
2539 }
2540
2541 if (!result)
2542 result = fiji_copy_bytes_to_smc(
2543 hwmgr->smumgr,
2544 data->arb_table_start,
2545 (uint8_t *)&arb_regs,
2546 sizeof(SMU73_Discrete_MCArbDramTimingTable),
2547 data->sram_end);
2548 return result;
2549 }
2550
2551 static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2552 struct SMU73_Discrete_DpmTable *table)
2553 {
2554 int result = -EINVAL;
2555 uint8_t count;
2556 struct pp_atomctrl_clock_dividers_vi dividers;
2557 struct phm_ppt_v1_information *table_info =
2558 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2559 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
2560 table_info->mm_dep_table;
2561 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2562
2563 table->UvdLevelCount = (uint8_t)(mm_table->count);
2564 table->UvdBootLevel = 0;
2565
2566 for (count = 0; count < table->UvdLevelCount; count++) {
2567 table->UvdLevel[count].MinVoltage = 0;
2568 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2569 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2570 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2571 VOLTAGE_SCALE) << VDDC_SHIFT;
2572 table->UvdLevel[count].MinVoltage |= ((mm_table->entries[count].vddc -
2573 data->vddc_vddci_delta) * VOLTAGE_SCALE) << VDDCI_SHIFT;
2574 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
2575
2576 /* retrieve divider value for VBIOS */
2577 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2578 table->UvdLevel[count].VclkFrequency, &dividers);
2579 PP_ASSERT_WITH_CODE((0 == result),
2580 "can not find divide id for Vclk clock", return result);
2581
2582 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
2583
2584 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2585 table->UvdLevel[count].DclkFrequency, &dividers);
2586 PP_ASSERT_WITH_CODE((0 == result),
2587 "can not find divide id for Dclk clock", return result);
2588
2589 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
2590
2591 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
2592 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
2593 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
2594
2595 }
2596 return result;
2597 }
2598
2599 static int fiji_find_boot_level(struct fiji_single_dpm_table *table,
2600 uint32_t value, uint32_t *boot_level)
2601 {
2602 int result = -EINVAL;
2603 uint32_t i;
2604
2605 for (i = 0; i < table->count; i++) {
2606 if (value == table->dpm_levels[i].value) {
2607 *boot_level = i;
2608 result = 0;
2609 }
2610 }
2611 return result;
2612 }
2613
2614 static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
2615 struct SMU73_Discrete_DpmTable *table)
2616 {
2617 int result = 0;
2618 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2619
2620 table->GraphicsBootLevel = 0;
2621 table->MemoryBootLevel = 0;
2622
2623 /* find boot level from dpm table */
2624 result = fiji_find_boot_level(&(data->dpm_table.sclk_table),
2625 data->vbios_boot_state.sclk_bootup_value,
2626 (uint32_t *)&(table->GraphicsBootLevel));
2627
2628 result = fiji_find_boot_level(&(data->dpm_table.mclk_table),
2629 data->vbios_boot_state.mclk_bootup_value,
2630 (uint32_t *)&(table->MemoryBootLevel));
2631
2632 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
2633 VOLTAGE_SCALE;
2634 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
2635 VOLTAGE_SCALE;
2636 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
2637 VOLTAGE_SCALE;
2638
2639 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
2640 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
2641 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
2642
2643 return 0;
2644 }
2645
2646 static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
2647 {
2648 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2649 struct phm_ppt_v1_information *table_info =
2650 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2651 uint8_t count, level;
2652
2653 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
2654 for (level = 0; level < count; level++) {
2655 if(table_info->vdd_dep_on_sclk->entries[level].clk >=
2656 data->vbios_boot_state.sclk_bootup_value) {
2657 data->smc_state_table.GraphicsBootLevel = level;
2658 break;
2659 }
2660 }
2661
2662 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
2663 for (level = 0; level < count; level++) {
2664 if(table_info->vdd_dep_on_mclk->entries[level].clk >=
2665 data->vbios_boot_state.mclk_bootup_value) {
2666 data->smc_state_table.MemoryBootLevel = level;
2667 break;
2668 }
2669 }
2670
2671 return 0;
2672 }
2673
2674 static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
2675 {
2676 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks,
2677 volt_with_cks, value;
2678 uint16_t clock_freq_u16;
2679 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2680 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2,
2681 volt_offset = 0;
2682 struct phm_ppt_v1_information *table_info =
2683 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2684 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
2685 table_info->vdd_dep_on_sclk;
2686
2687 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
2688
2689 /* Read SMU_Eefuse to read and calculate RO and determine
2690 * if the part is SS or FF. if RO >= 1660MHz, part is FF.
2691 */
2692 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2693 ixSMU_EFUSE_0 + (146 * 4));
2694 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2695 ixSMU_EFUSE_0 + (148 * 4));
2696 efuse &= 0xFF000000;
2697 efuse = efuse >> 24;
2698 efuse2 &= 0xF;
2699
2700 if (efuse2 == 1)
2701 ro = (2300 - 1350) * efuse / 255 + 1350;
2702 else
2703 ro = (2500 - 1000) * efuse / 255 + 1000;
2704
2705 if (ro >= 1660)
2706 type = 0;
2707 else
2708 type = 1;
2709
2710 /* Populate Stretch amount */
2711 data->smc_state_table.ClockStretcherAmount = stretch_amount;
2712
2713 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
2714 for (i = 0; i < sclk_table->count; i++) {
2715 data->smc_state_table.Sclk_CKS_masterEn0_7 |=
2716 sclk_table->entries[i].cks_enable << i;
2717 volt_without_cks = (uint32_t)((14041 *
2718 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 /
2719 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000)));
2720 volt_with_cks = (uint32_t)((13946 *
2721 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 /
2722 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000)));
2723 if (volt_without_cks >= volt_with_cks)
2724 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
2725 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1);
2726 data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
2727 }
2728
2729 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2730 STRETCH_ENABLE, 0x0);
2731 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2732 masterReset, 0x1);
2733 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2734 staticEnable, 0x1);
2735 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
2736 masterReset, 0x0);
2737
2738 /* Populate CKS Lookup Table */
2739 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
2740 stretch_amount2 = 0;
2741 else if (stretch_amount == 3 || stretch_amount == 4)
2742 stretch_amount2 = 1;
2743 else {
2744 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2745 PHM_PlatformCaps_ClockStretcher);
2746 PP_ASSERT_WITH_CODE(false,
2747 "Stretch Amount in PPTable not supported\n",
2748 return -EINVAL);
2749 }
2750
2751 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2752 ixPWR_CKS_CNTL);
2753 value &= 0xFFC2FF87;
2754 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq =
2755 fiji_clock_stretcher_lookup_table[stretch_amount2][0];
2756 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq =
2757 fiji_clock_stretcher_lookup_table[stretch_amount2][1];
2758 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table.
2759 GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].
2760 SclkFrequency) / 100);
2761 if (fiji_clock_stretcher_lookup_table[stretch_amount2][0] <
2762 clock_freq_u16 &&
2763 fiji_clock_stretcher_lookup_table[stretch_amount2][1] >
2764 clock_freq_u16) {
2765 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */
2766 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 16;
2767 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */
2768 value |= (fiji_clock_stretcher_lookup_table[stretch_amount2][2]) << 18;
2769 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */
2770 value |= (fiji_clock_stretch_amount_conversion
2771 [fiji_clock_stretcher_lookup_table[stretch_amount2][3]]
2772 [stretch_amount]) << 3;
2773 }
2774 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2775 CKS_LOOKUPTableEntry[0].minFreq);
2776 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.
2777 CKS_LOOKUPTableEntry[0].maxFreq);
2778 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting =
2779 fiji_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F;
2780 data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |=
2781 (fiji_clock_stretcher_lookup_table[stretch_amount2][3]) << 7;
2782
2783 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2784 ixPWR_CKS_CNTL, value);
2785
2786 /* Populate DDT Lookup Table */
2787 for (i = 0; i < 4; i++) {
2788 /* Assign the minimum and maximum VID stored
2789 * in the last row of Clock Stretcher Voltage Table.
2790 */
2791 data->smc_state_table.ClockStretcherDataTable.
2792 ClockStretcherDataTableEntry[i].minVID =
2793 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][2];
2794 data->smc_state_table.ClockStretcherDataTable.
2795 ClockStretcherDataTableEntry[i].maxVID =
2796 (uint8_t) fiji_clock_stretcher_ddt_table[type][i][3];
2797 /* Loop through each SCLK and check the frequency
2798 * to see if it lies within the frequency for clock stretcher.
2799 */
2800 for (j = 0; j < data->smc_state_table.GraphicsDpmLevelCount; j++) {
2801 cks_setting = 0;
2802 clock_freq = PP_SMC_TO_HOST_UL(
2803 data->smc_state_table.GraphicsLevel[j].SclkFrequency);
2804 /* Check the allowed frequency against the sclk level[j].
2805 * Sclk's endianness has already been converted,
2806 * and it's in 10Khz unit,
2807 * as opposed to Data table, which is in Mhz unit.
2808 */
2809 if (clock_freq >=
2810 (fiji_clock_stretcher_ddt_table[type][i][0]) * 100) {
2811 cks_setting |= 0x2;
2812 if (clock_freq <
2813 (fiji_clock_stretcher_ddt_table[type][i][1]) * 100)
2814 cks_setting |= 0x1;
2815 }
2816 data->smc_state_table.ClockStretcherDataTable.
2817 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2);
2818 }
2819 CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.
2820 ClockStretcherDataTable.
2821 ClockStretcherDataTableEntry[i].setting);
2822 }
2823
2824 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
2825 value &= 0xFFFFFFFE;
2826 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
2827
2828 return 0;
2829 }
2830
2831 /**
2832 * Populates the SMC VRConfig field in DPM table.
2833 *
2834 * @param hwmgr the address of the hardware manager
2835 * @param table the SMC DPM table structure to be populated
2836 * @return always 0
2837 */
2838 static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
2839 struct SMU73_Discrete_DpmTable *table)
2840 {
2841 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2842 uint16_t config;
2843
2844 config = VR_MERGED_WITH_VDDC;
2845 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
2846
2847 /* Set Vddc Voltage Controller */
2848 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
2849 config = VR_SVI2_PLANE_1;
2850 table->VRConfig |= config;
2851 } else {
2852 PP_ASSERT_WITH_CODE(false,
2853 "VDDC should be on SVI2 control in merged mode!",);
2854 }
2855 /* Set Vddci Voltage Controller */
2856 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
2857 config = VR_SVI2_PLANE_2; /* only in merged mode */
2858 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2859 } else if (FIJI_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
2860 config = VR_SMIO_PATTERN_1;
2861 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2862 } else {
2863 config = VR_STATIC_VOLTAGE;
2864 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
2865 }
2866 /* Set Mvdd Voltage Controller */
2867 if(FIJI_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
2868 config = VR_SVI2_PLANE_2;
2869 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2870 } else if(FIJI_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
2871 config = VR_SMIO_PATTERN_2;
2872 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2873 } else {
2874 config = VR_STATIC_VOLTAGE;
2875 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
2876 }
2877
2878 return 0;
2879 }
2880
2881 /**
2882 * Initializes the SMC table and uploads it
2883 *
2884 * @param hwmgr the address of the powerplay hardware manager.
2885 * @param pInput the pointer to input data (PowerState)
2886 * @return always 0
2887 */
2888 static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2889 {
2890 int result;
2891 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
2892 struct phm_ppt_v1_information *table_info =
2893 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2894 struct SMU73_Discrete_DpmTable *table = &(data->smc_state_table);
2895 const struct fiji_ulv_parm *ulv = &(data->ulv);
2896 uint8_t i;
2897 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2898
2899 result = fiji_setup_default_dpm_tables(hwmgr);
2900 PP_ASSERT_WITH_CODE(0 == result,
2901 "Failed to setup default DPM tables!", return result);
2902
2903 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2904 fiji_populate_smc_voltage_tables(hwmgr, table);
2905
2906 table->SystemFlags = 0;
2907
2908 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2909 PHM_PlatformCaps_AutomaticDCTransition))
2910 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2911
2912 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2913 PHM_PlatformCaps_StepVddc))
2914 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2915
2916 if (data->is_memory_gddr5)
2917 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2918
2919 if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) {
2920 result = fiji_populate_ulv_state(hwmgr, table);
2921 PP_ASSERT_WITH_CODE(0 == result,
2922 "Failed to initialize ULV state!", return result);
2923 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2924 ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter);
2925 }
2926
2927 result = fiji_populate_smc_link_level(hwmgr, table);
2928 PP_ASSERT_WITH_CODE(0 == result,
2929 "Failed to initialize Link Level!", return result);
2930
2931 result = fiji_populate_all_graphic_levels(hwmgr);
2932 PP_ASSERT_WITH_CODE(0 == result,
2933 "Failed to initialize Graphics Level!", return result);
2934
2935 result = fiji_populate_all_memory_levels(hwmgr);
2936 PP_ASSERT_WITH_CODE(0 == result,
2937 "Failed to initialize Memory Level!", return result);
2938
2939 result = fiji_populate_smc_acpi_level(hwmgr, table);
2940 PP_ASSERT_WITH_CODE(0 == result,
2941 "Failed to initialize ACPI Level!", return result);
2942
2943 result = fiji_populate_smc_vce_level(hwmgr, table);
2944 PP_ASSERT_WITH_CODE(0 == result,
2945 "Failed to initialize VCE Level!", return result);
2946
2947 result = fiji_populate_smc_acp_level(hwmgr, table);
2948 PP_ASSERT_WITH_CODE(0 == result,
2949 "Failed to initialize ACP Level!", return result);
2950
2951 result = fiji_populate_smc_samu_level(hwmgr, table);
2952 PP_ASSERT_WITH_CODE(0 == result,
2953 "Failed to initialize SAMU Level!", return result);
2954
2955 /* Since only the initial state is completely set up at this point
2956 * (the other states are just copies of the boot state) we only
2957 * need to populate the ARB settings for the initial state.
2958 */
2959 result = fiji_program_memory_timing_parameters(hwmgr);
2960 PP_ASSERT_WITH_CODE(0 == result,
2961 "Failed to Write ARB settings for the initial state.", return result);
2962
2963 result = fiji_populate_smc_uvd_level(hwmgr, table);
2964 PP_ASSERT_WITH_CODE(0 == result,
2965 "Failed to initialize UVD Level!", return result);
2966
2967 result = fiji_populate_smc_boot_level(hwmgr, table);
2968 PP_ASSERT_WITH_CODE(0 == result,
2969 "Failed to initialize Boot Level!", return result);
2970
2971 result = fiji_populate_smc_initailial_state(hwmgr);
2972 PP_ASSERT_WITH_CODE(0 == result,
2973 "Failed to initialize Boot State!", return result);
2974
2975 result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
2976 PP_ASSERT_WITH_CODE(0 == result,
2977 "Failed to populate BAPM Parameters!", return result);
2978
2979 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2980 PHM_PlatformCaps_ClockStretcher)) {
2981 result = fiji_populate_clock_stretcher_data_table(hwmgr);
2982 PP_ASSERT_WITH_CODE(0 == result,
2983 "Failed to populate Clock Stretcher Data Table!",
2984 return result);
2985 }
2986
2987 table->GraphicsVoltageChangeEnable = 1;
2988 table->GraphicsThermThrottleEnable = 1;
2989 table->GraphicsInterval = 1;
2990 table->VoltageInterval = 1;
2991 table->ThermalInterval = 1;
2992 table->TemperatureLimitHigh =
2993 table_info->cac_dtp_table->usTargetOperatingTemp *
2994 FIJI_Q88_FORMAT_CONVERSION_UNIT;
2995 table->TemperatureLimitLow =
2996 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2997 FIJI_Q88_FORMAT_CONVERSION_UNIT;
2998 table->MemoryVoltageChangeEnable = 1;
2999 table->MemoryInterval = 1;
3000 table->VoltageResponseTime = 0;
3001 table->PhaseResponseTime = 0;
3002 table->MemoryThermThrottleEnable = 1;
3003 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
3004 table->PCIeGenInterval = 1;
3005 table->VRConfig = 0;
3006
3007 result = fiji_populate_vr_config(hwmgr, table);
3008 PP_ASSERT_WITH_CODE(0 == result,
3009 "Failed to populate VRConfig setting!", return result);
3010
3011 table->ThermGpio = 17;
3012 table->SclkStepSize = 0x4000;
3013
3014 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
3015 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
3016 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3017 PHM_PlatformCaps_RegulatorHot);
3018 } else {
3019 table->VRHotGpio = FIJI_UNUSED_GPIO_PIN;
3020 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3021 PHM_PlatformCaps_RegulatorHot);
3022 }
3023
3024 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
3025 &gpio_pin)) {
3026 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
3027 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3028 PHM_PlatformCaps_AutomaticDCTransition);
3029 } else {
3030 table->AcDcGpio = FIJI_UNUSED_GPIO_PIN;
3031 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3032 PHM_PlatformCaps_AutomaticDCTransition);
3033 }
3034
3035 /* Thermal Output GPIO */
3036 if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
3037 &gpio_pin)) {
3038 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
3039 PHM_PlatformCaps_ThermalOutGPIO);
3040
3041 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
3042
3043 /* For porlarity read GPIOPAD_A with assigned Gpio pin
3044 * since VBIOS will program this register to set 'inactive state',
3045 * driver can then determine 'active state' from this and
3046 * program SMU with correct polarity
3047 */
3048 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
3049 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
3050 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
3051
3052 /* if required, combine VRHot/PCC with thermal out GPIO */
3053 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3054 PHM_PlatformCaps_RegulatorHot) &&
3055 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3056 PHM_PlatformCaps_CombinePCCWithThermalSignal))
3057 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
3058 } else {
3059 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
3060 PHM_PlatformCaps_ThermalOutGPIO);
3061 table->ThermOutGpio = 17;
3062 table->ThermOutPolarity = 1;
3063 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
3064 }
3065
3066 for (i = 0; i < SMU73_MAX_ENTRIES_SMIO; i++)
3067 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
3068
3069 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
3070 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
3071 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
3072 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
3073 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
3074 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
3075 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
3076 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
3077 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
3078
3079 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
3080 result = fiji_copy_bytes_to_smc(hwmgr->smumgr,
3081 data->dpm_table_start +
3082 offsetof(SMU73_Discrete_DpmTable, SystemFlags),
3083 (uint8_t *)&(table->SystemFlags),
3084 sizeof(SMU73_Discrete_DpmTable) - 3 * sizeof(SMU73_PIDController),
3085 data->sram_end);
3086 PP_ASSERT_WITH_CODE(0 == result,
3087 "Failed to upload dpm data to SMC memory!", return result);
3088
3089 return 0;
3090 }
3091
3092 /**
3093 * Initialize the ARB DRAM timing table's index field.
3094 *
3095 * @param hwmgr the address of the powerplay hardware manager.
3096 * @return always 0
3097 */
3098 static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
3099 {
3100 const struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3101 uint32_t tmp;
3102 int result;
3103
3104 /* This is a read-modify-write on the first byte of the ARB table.
3105 * The first byte in the SMU73_Discrete_MCArbDramTimingTable structure
3106 * is the field 'current'.
3107 * This solution is ugly, but we never write the whole table only
3108 * individual fields in it.
3109 * In reality this field should not be in that structure
3110 * but in a soft register.
3111 */
3112 result = fiji_read_smc_sram_dword(hwmgr->smumgr,
3113 data->arb_table_start, &tmp, data->sram_end);
3114
3115 if (result)
3116 return result;
3117
3118 tmp &= 0x00FFFFFF;
3119 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24;
3120
3121 return fiji_write_smc_sram_dword(hwmgr->smumgr,
3122 data->arb_table_start, tmp, data->sram_end);
3123 }
3124
3125 static int fiji_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
3126 {
3127 if(phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3128 PHM_PlatformCaps_RegulatorHot))
3129 return smum_send_msg_to_smc(hwmgr->smumgr,
3130 PPSMC_MSG_EnableVRHotGPIOInterrupt);
3131
3132 return 0;
3133 }
3134
3135 static int fiji_enable_sclk_control(struct pp_hwmgr *hwmgr)
3136 {
3137 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3138 SCLK_PWRMGT_OFF, 0);
3139 return 0;
3140 }
3141
3142 static int fiji_enable_ulv(struct pp_hwmgr *hwmgr)
3143 {
3144 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3145 struct fiji_ulv_parm *ulv = &(data->ulv);
3146
3147 if (ulv->ulv_supported)
3148 return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV);
3149
3150 return 0;
3151 }
3152
3153 static int fiji_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
3154 {
3155 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3156 PHM_PlatformCaps_SclkDeepSleep)) {
3157 if (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_MASTER_DeepSleep_ON))
3158 PP_ASSERT_WITH_CODE(false,
3159 "Attempt to enable Master Deep Sleep switch failed!",
3160 return -1);
3161 } else {
3162 if (smum_send_msg_to_smc(hwmgr->smumgr,
3163 PPSMC_MSG_MASTER_DeepSleep_OFF)) {
3164 PP_ASSERT_WITH_CODE(false,
3165 "Attempt to disable Master Deep Sleep switch failed!",
3166 return -1);
3167 }
3168 }
3169
3170 return 0;
3171 }
3172
3173 static int fiji_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
3174 {
3175 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3176 uint32_t val, val0, val2;
3177 uint32_t i, cpl_cntl, cpl_threshold, mc_threshold;
3178
3179 /* enable SCLK dpm */
3180 if(!data->sclk_dpm_key_disabled)
3181 PP_ASSERT_WITH_CODE(
3182 (0 == smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_DPM_Enable)),
3183 "Failed to enable SCLK DPM during DPM Start Function!",
3184 return -1);
3185
3186 /* enable MCLK dpm */
3187 if(0 == data->mclk_dpm_key_disabled) {
3188 cpl_threshold = 0;
3189 mc_threshold = 0;
3190
3191 /* Read per MCD tile (0 - 7) */
3192 for (i = 0; i < 8; i++) {
3193 PHM_WRITE_FIELD(hwmgr->device, MC_CONFIG_MCD, MC_RD_ENABLE, i);
3194 val = cgs_read_register(hwmgr->device, mmMC_SEQ_RESERVE_0_S) & 0xf0000000;
3195 if (0xf0000000 != val) {
3196 /* count number of MCQ that has channel(s) enabled */
3197 cpl_threshold++;
3198 /* only harvest 3 or full 4 supported */
3199 mc_threshold = val ? 3 : 4;
3200 }
3201 }
3202 PP_ASSERT_WITH_CODE(0 != cpl_threshold,
3203 "Number of MCQ is zero!", return -EINVAL;);
3204
3205 mc_threshold = ((mc_threshold & LCAC_MC0_CNTL__MC0_THRESHOLD_MASK) <<
3206 LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT) |
3207 LCAC_MC0_CNTL__MC0_ENABLE_MASK;
3208 cpl_cntl = ((cpl_threshold & LCAC_CPL_CNTL__CPL_THRESHOLD_MASK) <<
3209 LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT) |
3210 LCAC_CPL_CNTL__CPL_ENABLE_MASK;
3211 cpl_cntl = (cpl_cntl | (8 << LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT));
3212 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3213 ixLCAC_MC0_CNTL, mc_threshold);
3214 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3215 ixLCAC_MC1_CNTL, mc_threshold);
3216 if (8 == cpl_threshold) {
3217 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3218 ixLCAC_MC2_CNTL, mc_threshold);
3219 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3220 ixLCAC_MC3_CNTL, mc_threshold);
3221 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3222 ixLCAC_MC4_CNTL, mc_threshold);
3223 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3224 ixLCAC_MC5_CNTL, mc_threshold);
3225 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3226 ixLCAC_MC6_CNTL, mc_threshold);
3227 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3228 ixLCAC_MC7_CNTL, mc_threshold);
3229 }
3230 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3231 ixLCAC_CPL_CNTL, cpl_cntl);
3232
3233 udelay(5);
3234
3235 mc_threshold = mc_threshold |
3236 (1 << LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT);
3237 cpl_cntl = cpl_cntl | (1 << LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT);
3238 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3239 ixLCAC_MC0_CNTL, mc_threshold);
3240 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3241 ixLCAC_MC1_CNTL, mc_threshold);
3242 if (8 == cpl_threshold) {
3243 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3244 ixLCAC_MC2_CNTL, mc_threshold);
3245 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3246 ixLCAC_MC3_CNTL, mc_threshold);
3247 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3248 ixLCAC_MC4_CNTL, mc_threshold);
3249 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3250 ixLCAC_MC5_CNTL, mc_threshold);
3251 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3252 ixLCAC_MC6_CNTL, mc_threshold);
3253 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3254 ixLCAC_MC7_CNTL, mc_threshold);
3255 }
3256 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3257 ixLCAC_CPL_CNTL, cpl_cntl);
3258
3259 /* Program CAC_EN per MCD (0-7) Tile */
3260 val0 = val = cgs_read_register(hwmgr->device, mmMC_CONFIG_MCD);
3261 val &= ~(MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK |
3262 MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK |
3263 MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK |
3264 MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK |
3265 MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK |
3266 MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK |
3267 MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK |
3268 MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK |
3269 MC_CONFIG_MCD__MC_RD_ENABLE_MASK);
3270
3271 for (i = 0; i < 8; i++) {
3272 /* Enable MCD i Tile read & write */
3273 val2 = (val | (i << MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT) |
3274 (1 << i));
3275 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val2);
3276 /* Enbale CAC_ON MCD i Tile */
3277 val2 = cgs_read_register(hwmgr->device, mmMC_SEQ_CNTL);
3278 val2 |= MC_SEQ_CNTL__CAC_EN_MASK;
3279 cgs_write_register(hwmgr->device, mmMC_SEQ_CNTL, val2);
3280 }
3281 /* Set MC_CONFIG_MCD back to its default setting val0 */
3282 cgs_write_register(hwmgr->device, mmMC_CONFIG_MCD, val0);
3283
3284 PP_ASSERT_WITH_CODE(
3285 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3286 PPSMC_MSG_MCLKDPM_Enable)),
3287 "Failed to enable MCLK DPM during DPM Start Function!",
3288 return -1);
3289 }
3290 return 0;
3291 }
3292
3293 static int fiji_start_dpm(struct pp_hwmgr *hwmgr)
3294 {
3295 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3296
3297 /*enable general power management */
3298 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3299 GLOBAL_PWRMGT_EN, 1);
3300 /* enable sclk deep sleep */
3301 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
3302 DYNAMIC_PM_EN, 1);
3303 /* prepare for PCIE DPM */
3304 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
3305 data->soft_regs_start + offsetof(SMU73_SoftRegisters,
3306 VoltageChangeTimeout), 0x1000);
3307 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
3308 SWRST_COMMAND_1, RESETLC, 0x0);
3309
3310 PP_ASSERT_WITH_CODE(
3311 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3312 PPSMC_MSG_Voltage_Cntl_Enable)),
3313 "Failed to enable voltage DPM during DPM Start Function!",
3314 return -1);
3315
3316 if (fiji_enable_sclk_mclk_dpm(hwmgr)) {
3317 printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!");
3318 return -1;
3319 }
3320
3321 /* enable PCIE dpm */
3322 if(!data->pcie_dpm_key_disabled) {
3323 PP_ASSERT_WITH_CODE(
3324 (0 == smum_send_msg_to_smc(hwmgr->smumgr,
3325 PPSMC_MSG_PCIeDPM_Enable)),
3326 "Failed to enable pcie DPM during DPM Start Function!",
3327 return -1);
3328 }
3329
3330 return 0;
3331 }
3332
3333 static void fiji_set_dpm_event_sources(struct pp_hwmgr *hwmgr,
3334 uint32_t sources)
3335 {
3336 bool protection;
3337 enum DPM_EVENT_SRC src;
3338
3339 switch (sources) {
3340 default:
3341 printk(KERN_ERR "Unknown throttling event sources.");
3342 /* fall through */
3343 case 0:
3344 protection = false;
3345 /* src is unused */
3346 break;
3347 case (1 << PHM_AutoThrottleSource_Thermal):
3348 protection = true;
3349 src = DPM_EVENT_SRC_DIGITAL;
3350 break;
3351 case (1 << PHM_AutoThrottleSource_External):
3352 protection = true;
3353 src = DPM_EVENT_SRC_EXTERNAL;
3354 break;
3355 case (1 << PHM_AutoThrottleSource_External) |
3356 (1 << PHM_AutoThrottleSource_Thermal):
3357 protection = true;
3358 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL;
3359 break;
3360 }
3361 /* Order matters - don't enable thermal protection for the wrong source. */
3362 if (protection) {
3363 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
3364 DPM_EVENT_SRC, src);
3365 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3366 THERMAL_PROTECTION_DIS,
3367 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3368 PHM_PlatformCaps_ThermalController));
3369 } else
3370 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
3371 THERMAL_PROTECTION_DIS, 1);
3372 }
3373
3374 static int fiji_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
3375 PHM_AutoThrottleSource source)
3376 {
3377 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3378
3379 if (!(data->active_auto_throttle_sources & (1 << source))) {
3380 data->active_auto_throttle_sources |= 1 << source;
3381 fiji_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
3382 }
3383 return 0;
3384 }
3385
3386 static int fiji_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
3387 {
3388 return fiji_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
3389 }
3390
3391 static int fiji_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
3392 {
3393 int tmp_result, result = 0;
3394
3395 tmp_result = (!fiji_is_dpm_running(hwmgr))? 0 : -1;
3396 PP_ASSERT_WITH_CODE(result == 0,
3397 "DPM is already running right now, no need to enable DPM!",
3398 return 0);
3399
3400 if (fiji_voltage_control(hwmgr)) {
3401 tmp_result = fiji_enable_voltage_control(hwmgr);
3402 PP_ASSERT_WITH_CODE(tmp_result == 0,
3403 "Failed to enable voltage control!",
3404 result = tmp_result);
3405 }
3406
3407 if (fiji_voltage_control(hwmgr)) {
3408 tmp_result = fiji_construct_voltage_tables(hwmgr);
3409 PP_ASSERT_WITH_CODE((0 == tmp_result),
3410 "Failed to contruct voltage tables!",
3411 result = tmp_result);
3412 }
3413
3414 tmp_result = fiji_initialize_mc_reg_table(hwmgr);
3415 PP_ASSERT_WITH_CODE((0 == tmp_result),
3416 "Failed to initialize MC reg table!", result = tmp_result);
3417
3418 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3419 PHM_PlatformCaps_EngineSpreadSpectrumSupport))
3420 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3421 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1);
3422
3423 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3424 PHM_PlatformCaps_ThermalController))
3425 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
3426 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0);
3427
3428 tmp_result = fiji_program_static_screen_threshold_parameters(hwmgr);
3429 PP_ASSERT_WITH_CODE((0 == tmp_result),
3430 "Failed to program static screen threshold parameters!",
3431 result = tmp_result);
3432
3433 tmp_result = fiji_enable_display_gap(hwmgr);
3434 PP_ASSERT_WITH_CODE((0 == tmp_result),
3435 "Failed to enable display gap!", result = tmp_result);
3436
3437 tmp_result = fiji_program_voting_clients(hwmgr);
3438 PP_ASSERT_WITH_CODE((0 == tmp_result),
3439 "Failed to program voting clients!", result = tmp_result);
3440
3441 tmp_result = fiji_process_firmware_header(hwmgr);
3442 PP_ASSERT_WITH_CODE((0 == tmp_result),
3443 "Failed to process firmware header!", result = tmp_result);
3444
3445 tmp_result = fiji_initial_switch_from_arbf0_to_f1(hwmgr);
3446 PP_ASSERT_WITH_CODE((0 == tmp_result),
3447 "Failed to initialize switch from ArbF0 to F1!",
3448 result = tmp_result);
3449
3450 tmp_result = fiji_init_smc_table(hwmgr);
3451 PP_ASSERT_WITH_CODE((0 == tmp_result),
3452 "Failed to initialize SMC table!", result = tmp_result);
3453
3454 tmp_result = fiji_init_arb_table_index(hwmgr);
3455 PP_ASSERT_WITH_CODE((0 == tmp_result),
3456 "Failed to initialize ARB table index!", result = tmp_result);
3457
3458 tmp_result = fiji_populate_pm_fuses(hwmgr);
3459 PP_ASSERT_WITH_CODE((0 == tmp_result),
3460 "Failed to populate PM fuses!", result = tmp_result);
3461
3462 tmp_result = fiji_enable_vrhot_gpio_interrupt(hwmgr);
3463 PP_ASSERT_WITH_CODE((0 == tmp_result),
3464 "Failed to enable VR hot GPIO interrupt!", result = tmp_result);
3465
3466 tmp_result = tonga_notify_smc_display_change(hwmgr, false);
3467 PP_ASSERT_WITH_CODE((0 == tmp_result),
3468 "Failed to notify no display!", result = tmp_result);
3469
3470 tmp_result = fiji_enable_sclk_control(hwmgr);
3471 PP_ASSERT_WITH_CODE((0 == tmp_result),
3472 "Failed to enable SCLK control!", result = tmp_result);
3473
3474 tmp_result = fiji_enable_ulv(hwmgr);
3475 PP_ASSERT_WITH_CODE((0 == tmp_result),
3476 "Failed to enable ULV!", result = tmp_result);
3477
3478 tmp_result = fiji_enable_deep_sleep_master_switch(hwmgr);
3479 PP_ASSERT_WITH_CODE((0 == tmp_result),
3480 "Failed to enable deep sleep master switch!", result = tmp_result);
3481
3482 tmp_result = fiji_start_dpm(hwmgr);
3483 PP_ASSERT_WITH_CODE((0 == tmp_result),
3484 "Failed to start DPM!", result = tmp_result);
3485
3486 tmp_result = fiji_enable_smc_cac(hwmgr);
3487 PP_ASSERT_WITH_CODE((0 == tmp_result),
3488 "Failed to enable SMC CAC!", result = tmp_result);
3489
3490 tmp_result = fiji_enable_power_containment(hwmgr);
3491 PP_ASSERT_WITH_CODE((0 == tmp_result),
3492 "Failed to enable power containment!", result = tmp_result);
3493
3494 tmp_result = fiji_power_control_set_level(hwmgr);
3495 PP_ASSERT_WITH_CODE((0 == tmp_result),
3496 "Failed to power control set level!", result = tmp_result);
3497
3498 tmp_result = fiji_enable_thermal_auto_throttle(hwmgr);
3499 PP_ASSERT_WITH_CODE((0 == tmp_result),
3500 "Failed to enable thermal auto throttle!", result = tmp_result);
3501
3502 return result;
3503 }
3504
3505 static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
3506 {
3507 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3508 uint32_t level, tmp;
3509
3510 if (!data->sclk_dpm_key_disabled) {
3511 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3512 level = 0;
3513 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
3514 while (tmp >>= 1)
3515 level++;
3516 if (level)
3517 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3518 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3519 (1 << level));
3520 }
3521 }
3522
3523 if (!data->mclk_dpm_key_disabled) {
3524 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3525 level = 0;
3526 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask;
3527 while (tmp >>= 1)
3528 level++;
3529 if (level)
3530 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3531 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3532 (1 << level));
3533 }
3534 }
3535
3536 if (!data->pcie_dpm_key_disabled) {
3537 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3538 level = 0;
3539 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask;
3540 while (tmp >>= 1)
3541 level++;
3542 if (level)
3543 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3544 PPSMC_MSG_PCIeDPM_ForceLevel,
3545 (1 << level));
3546 }
3547 }
3548 return 0;
3549 }
3550
3551 static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
3552 {
3553 struct phm_ppt_v1_information *table_info =
3554 (struct phm_ppt_v1_information *)hwmgr->pptable;
3555 struct phm_clock_voltage_dependency_table *table =
3556 table_info->vddc_dep_on_dal_pwrl;
3557 struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
3558 enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
3559 uint32_t req_vddc = 0, req_volt, i;
3560
3561 if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
3562 dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
3563 return;
3564
3565 for (i= 0; i < table->count; i++) {
3566 if (dal_power_level == table->entries[i].clk) {
3567 req_vddc = table->entries[i].v;
3568 break;
3569 }
3570 }
3571
3572 vddc_table = table_info->vdd_dep_on_sclk;
3573 for (i= 0; i < vddc_table->count; i++) {
3574 if (req_vddc <= vddc_table->entries[i].vddc) {
3575 req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
3576 << VDDC_SHIFT;
3577 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3578 PPSMC_MSG_VddC_Request, req_volt);
3579 return;
3580 }
3581 }
3582 printk(KERN_ERR "DAL requested level can not"
3583 " found a available voltage in VDDC DPM Table \n");
3584 }
3585
3586 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
3587 {
3588 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3589
3590 fiji_apply_dal_min_voltage_request(hwmgr);
3591
3592 if (!data->sclk_dpm_key_disabled) {
3593 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
3594 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3595 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3596 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3597 }
3598 return 0;
3599 }
3600
3601 static int fiji_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
3602 {
3603 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3604
3605 if (!fiji_is_dpm_running(hwmgr))
3606 return -EINVAL;
3607
3608 if (!data->pcie_dpm_key_disabled) {
3609 smum_send_msg_to_smc(hwmgr->smumgr,
3610 PPSMC_MSG_PCIeDPM_UnForceLevel);
3611 }
3612
3613 return fiji_upload_dpmlevel_enable_mask(hwmgr);
3614 }
3615
3616 static uint32_t fiji_get_lowest_enabled_level(
3617 struct pp_hwmgr *hwmgr, uint32_t mask)
3618 {
3619 uint32_t level = 0;
3620
3621 while(0 == (mask & (1 << level)))
3622 level++;
3623
3624 return level;
3625 }
3626
3627 static int fiji_force_dpm_lowest(struct pp_hwmgr *hwmgr)
3628 {
3629 struct fiji_hwmgr *data =
3630 (struct fiji_hwmgr *)(hwmgr->backend);
3631 uint32_t level;
3632
3633 if (!data->sclk_dpm_key_disabled)
3634 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3635 level = fiji_get_lowest_enabled_level(hwmgr,
3636 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
3637 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3638 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3639 (1 << level));
3640
3641 }
3642
3643 if (!data->mclk_dpm_key_disabled) {
3644 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3645 level = fiji_get_lowest_enabled_level(hwmgr,
3646 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
3647 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3648 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3649 (1 << level));
3650 }
3651 }
3652
3653 if (!data->pcie_dpm_key_disabled) {
3654 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3655 level = fiji_get_lowest_enabled_level(hwmgr,
3656 data->dpm_level_enable_mask.pcie_dpm_enable_mask);
3657 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
3658 PPSMC_MSG_PCIeDPM_ForceLevel,
3659 (1 << level));
3660 }
3661 }
3662
3663 return 0;
3664
3665 }
3666 static int fiji_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
3667 enum amd_dpm_forced_level level)
3668 {
3669 int ret = 0;
3670
3671 switch (level) {
3672 case AMD_DPM_FORCED_LEVEL_HIGH:
3673 ret = fiji_force_dpm_highest(hwmgr);
3674 if (ret)
3675 return ret;
3676 break;
3677 case AMD_DPM_FORCED_LEVEL_LOW:
3678 ret = fiji_force_dpm_lowest(hwmgr);
3679 if (ret)
3680 return ret;
3681 break;
3682 case AMD_DPM_FORCED_LEVEL_AUTO:
3683 ret = fiji_unforce_dpm_levels(hwmgr);
3684 if (ret)
3685 return ret;
3686 break;
3687 default:
3688 break;
3689 }
3690
3691 hwmgr->dpm_level = level;
3692
3693 return ret;
3694 }
3695
3696 static int fiji_get_power_state_size(struct pp_hwmgr *hwmgr)
3697 {
3698 return sizeof(struct fiji_power_state);
3699 }
3700
3701 static int fiji_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
3702 void *state, struct pp_power_state *power_state,
3703 void *pp_table, uint32_t classification_flag)
3704 {
3705 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3706 struct fiji_power_state *fiji_power_state =
3707 (struct fiji_power_state *)(&(power_state->hardware));
3708 struct fiji_performance_level *performance_level;
3709 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state;
3710 ATOM_Tonga_POWERPLAYTABLE *powerplay_table =
3711 (ATOM_Tonga_POWERPLAYTABLE *)pp_table;
3712 ATOM_Tonga_SCLK_Dependency_Table *sclk_dep_table =
3713 (ATOM_Tonga_SCLK_Dependency_Table *)
3714 (((unsigned long)powerplay_table) +
3715 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset));
3716 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table =
3717 (ATOM_Tonga_MCLK_Dependency_Table *)
3718 (((unsigned long)powerplay_table) +
3719 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset));
3720
3721 /* The following fields are not initialized here: id orderedList allStatesList */
3722 power_state->classification.ui_label =
3723 (le16_to_cpu(state_entry->usClassification) &
3724 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >>
3725 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT;
3726 power_state->classification.flags = classification_flag;
3727 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */
3728
3729 power_state->classification.temporary_state = false;
3730 power_state->classification.to_be_deleted = false;
3731
3732 power_state->validation.disallowOnDC =
3733 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3734 ATOM_Tonga_DISALLOW_ON_DC));
3735
3736 power_state->pcie.lanes = 0;
3737
3738 power_state->display.disableFrameModulation = false;
3739 power_state->display.limitRefreshrate = false;
3740 power_state->display.enableVariBright =
3741 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) &
3742 ATOM_Tonga_ENABLE_VARIBRIGHT));
3743
3744 power_state->validation.supportedPowerLevels = 0;
3745 power_state->uvd_clocks.VCLK = 0;
3746 power_state->uvd_clocks.DCLK = 0;
3747 power_state->temperatures.min = 0;
3748 power_state->temperatures.max = 0;
3749
3750 performance_level = &(fiji_power_state->performance_levels
3751 [fiji_power_state->performance_level_count++]);
3752
3753 PP_ASSERT_WITH_CODE(
3754 (fiji_power_state->performance_level_count < SMU73_MAX_LEVELS_GRAPHICS),
3755 "Performance levels exceeds SMC limit!",
3756 return -1);
3757
3758 PP_ASSERT_WITH_CODE(
3759 (fiji_power_state->performance_level_count <=
3760 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
3761 "Performance levels exceeds Driver limit!",
3762 return -1);
3763
3764 /* Performance levels are arranged from low to high. */
3765 performance_level->memory_clock = mclk_dep_table->entries
3766 [state_entry->ucMemoryClockIndexLow].ulMclk;
3767 performance_level->engine_clock = sclk_dep_table->entries
3768 [state_entry->ucEngineClockIndexLow].ulSclk;
3769 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3770 state_entry->ucPCIEGenLow);
3771 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3772 state_entry->ucPCIELaneHigh);
3773
3774 performance_level = &(fiji_power_state->performance_levels
3775 [fiji_power_state->performance_level_count++]);
3776 performance_level->memory_clock = mclk_dep_table->entries
3777 [state_entry->ucMemoryClockIndexHigh].ulMclk;
3778 performance_level->engine_clock = sclk_dep_table->entries
3779 [state_entry->ucEngineClockIndexHigh].ulSclk;
3780 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
3781 state_entry->ucPCIEGenHigh);
3782 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
3783 state_entry->ucPCIELaneHigh);
3784
3785 return 0;
3786 }
3787
3788 static int fiji_get_pp_table_entry(struct pp_hwmgr *hwmgr,
3789 unsigned long entry_index, struct pp_power_state *state)
3790 {
3791 int result;
3792 struct fiji_power_state *ps;
3793 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3794 struct phm_ppt_v1_information *table_info =
3795 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3796 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table =
3797 table_info->vdd_dep_on_mclk;
3798
3799 state->hardware.magic = PHM_VIslands_Magic;
3800
3801 ps = (struct fiji_power_state *)(&state->hardware);
3802
3803 result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state,
3804 fiji_get_pp_table_entry_callback_func);
3805
3806 /* This is the earliest time we have all the dependency table and the VBIOS boot state
3807 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state
3808 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state
3809 */
3810 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) {
3811 if (dep_mclk_table->entries[0].clk !=
3812 data->vbios_boot_state.mclk_bootup_value)
3813 printk(KERN_ERR "Single MCLK entry VDDCI/MCLK dependency table "
3814 "does not match VBIOS boot MCLK level");
3815 if (dep_mclk_table->entries[0].vddci !=
3816 data->vbios_boot_state.vddci_bootup_value)
3817 printk(KERN_ERR "Single VDDCI entry VDDCI/MCLK dependency table "
3818 "does not match VBIOS boot VDDCI level");
3819 }
3820
3821 /* set DC compatible flag if this state supports DC */
3822 if (!state->validation.disallowOnDC)
3823 ps->dc_compatible = true;
3824
3825 if (state->classification.flags & PP_StateClassificationFlag_ACPI)
3826 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen;
3827
3828 ps->uvd_clks.vclk = state->uvd_clocks.VCLK;
3829 ps->uvd_clks.dclk = state->uvd_clocks.DCLK;
3830
3831 if (!result) {
3832 uint32_t i;
3833
3834 switch (state->classification.ui_label) {
3835 case PP_StateUILabel_Performance:
3836 data->use_pcie_performance_levels = true;
3837
3838 for (i = 0; i < ps->performance_level_count; i++) {
3839 if (data->pcie_gen_performance.max <
3840 ps->performance_levels[i].pcie_gen)
3841 data->pcie_gen_performance.max =
3842 ps->performance_levels[i].pcie_gen;
3843
3844 if (data->pcie_gen_performance.min >
3845 ps->performance_levels[i].pcie_gen)
3846 data->pcie_gen_performance.min =
3847 ps->performance_levels[i].pcie_gen;
3848
3849 if (data->pcie_lane_performance.max <
3850 ps->performance_levels[i].pcie_lane)
3851 data->pcie_lane_performance.max =
3852 ps->performance_levels[i].pcie_lane;
3853
3854 if (data->pcie_lane_performance.min >
3855 ps->performance_levels[i].pcie_lane)
3856 data->pcie_lane_performance.min =
3857 ps->performance_levels[i].pcie_lane;
3858 }
3859 break;
3860 case PP_StateUILabel_Battery:
3861 data->use_pcie_power_saving_levels = true;
3862
3863 for (i = 0; i < ps->performance_level_count; i++) {
3864 if (data->pcie_gen_power_saving.max <
3865 ps->performance_levels[i].pcie_gen)
3866 data->pcie_gen_power_saving.max =
3867 ps->performance_levels[i].pcie_gen;
3868
3869 if (data->pcie_gen_power_saving.min >
3870 ps->performance_levels[i].pcie_gen)
3871 data->pcie_gen_power_saving.min =
3872 ps->performance_levels[i].pcie_gen;
3873
3874 if (data->pcie_lane_power_saving.max <
3875 ps->performance_levels[i].pcie_lane)
3876 data->pcie_lane_power_saving.max =
3877 ps->performance_levels[i].pcie_lane;
3878
3879 if (data->pcie_lane_power_saving.min >
3880 ps->performance_levels[i].pcie_lane)
3881 data->pcie_lane_power_saving.min =
3882 ps->performance_levels[i].pcie_lane;
3883 }
3884 break;
3885 default:
3886 break;
3887 }
3888 }
3889 return 0;
3890 }
3891
3892 static int fiji_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
3893 struct pp_power_state *request_ps,
3894 const struct pp_power_state *current_ps)
3895 {
3896 struct fiji_power_state *fiji_ps =
3897 cast_phw_fiji_power_state(&request_ps->hardware);
3898 uint32_t sclk;
3899 uint32_t mclk;
3900 struct PP_Clocks minimum_clocks = {0};
3901 bool disable_mclk_switching;
3902 bool disable_mclk_switching_for_frame_lock;
3903 struct cgs_display_info info = {0};
3904 const struct phm_clock_and_voltage_limits *max_limits;
3905 uint32_t i;
3906 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
3907 struct phm_ppt_v1_information *table_info =
3908 (struct phm_ppt_v1_information *)(hwmgr->pptable);
3909 int32_t count;
3910 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
3911
3912 data->battery_state = (PP_StateUILabel_Battery ==
3913 request_ps->classification.ui_label);
3914
3915 PP_ASSERT_WITH_CODE(fiji_ps->performance_level_count == 2,
3916 "VI should always have 2 performance levels",);
3917
3918 max_limits = (PP_PowerSource_AC == hwmgr->power_source) ?
3919 &(hwmgr->dyn_state.max_clock_voltage_on_ac) :
3920 &(hwmgr->dyn_state.max_clock_voltage_on_dc);
3921
3922 /* Cap clock DPM tables at DC MAX if it is in DC. */
3923 if (PP_PowerSource_DC == hwmgr->power_source) {
3924 for (i = 0; i < fiji_ps->performance_level_count; i++) {
3925 if (fiji_ps->performance_levels[i].memory_clock > max_limits->mclk)
3926 fiji_ps->performance_levels[i].memory_clock = max_limits->mclk;
3927 if (fiji_ps->performance_levels[i].engine_clock > max_limits->sclk)
3928 fiji_ps->performance_levels[i].engine_clock = max_limits->sclk;
3929 }
3930 }
3931
3932 fiji_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk;
3933 fiji_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk;
3934
3935 fiji_ps->acp_clk = hwmgr->acp_arbiter.acpclk;
3936
3937 cgs_get_active_displays_info(hwmgr->device, &info);
3938
3939 /*TO DO result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/
3940
3941 /* TO DO GetMinClockSettings(hwmgr->pPECI, &minimum_clocks); */
3942
3943 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
3944 PHM_PlatformCaps_StablePState)) {
3945 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
3946 stable_pstate_sclk = (max_limits->sclk * 75) / 100;
3947
3948 for (count = table_info->vdd_dep_on_sclk->count - 1;
3949 count >= 0; count--) {
3950 if (stable_pstate_sclk >=
3951 table_info->vdd_dep_on_sclk->entries[count].clk) {
3952 stable_pstate_sclk =
3953 table_info->vdd_dep_on_sclk->entries[count].clk;
3954 break;
3955 }
3956 }
3957
3958 if (count < 0)
3959 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk;
3960
3961 stable_pstate_mclk = max_limits->mclk;
3962
3963 minimum_clocks.engineClock = stable_pstate_sclk;
3964 minimum_clocks.memoryClock = stable_pstate_mclk;
3965 }
3966
3967 if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk)
3968 minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk;
3969
3970 if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk)
3971 minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
3972
3973 fiji_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold;
3974
3975 if (0 != hwmgr->gfx_arbiter.sclk_over_drive) {
3976 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <=
3977 hwmgr->platform_descriptor.overdriveLimit.engineClock),
3978 "Overdrive sclk exceeds limit",
3979 hwmgr->gfx_arbiter.sclk_over_drive =
3980 hwmgr->platform_descriptor.overdriveLimit.engineClock);
3981
3982 if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk)
3983 fiji_ps->performance_levels[1].engine_clock =
3984 hwmgr->gfx_arbiter.sclk_over_drive;
3985 }
3986
3987 if (0 != hwmgr->gfx_arbiter.mclk_over_drive) {
3988 PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <=
3989 hwmgr->platform_descriptor.overdriveLimit.memoryClock),
3990 "Overdrive mclk exceeds limit",
3991 hwmgr->gfx_arbiter.mclk_over_drive =
3992 hwmgr->platform_descriptor.overdriveLimit.memoryClock);
3993
3994 if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk)
3995 fiji_ps->performance_levels[1].memory_clock =
3996 hwmgr->gfx_arbiter.mclk_over_drive;
3997 }
3998
3999 disable_mclk_switching_for_frame_lock = phm_cap_enabled(
4000 hwmgr->platform_descriptor.platformCaps,
4001 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
4002
4003 disable_mclk_switching = (1 < info.display_count) ||
4004 disable_mclk_switching_for_frame_lock;
4005
4006 sclk = fiji_ps->performance_levels[0].engine_clock;
4007 mclk = fiji_ps->performance_levels[0].memory_clock;
4008
4009 if (disable_mclk_switching)
4010 mclk = fiji_ps->performance_levels
4011 [fiji_ps->performance_level_count - 1].memory_clock;
4012
4013 if (sclk < minimum_clocks.engineClock)
4014 sclk = (minimum_clocks.engineClock > max_limits->sclk) ?
4015 max_limits->sclk : minimum_clocks.engineClock;
4016
4017 if (mclk < minimum_clocks.memoryClock)
4018 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ?
4019 max_limits->mclk : minimum_clocks.memoryClock;
4020
4021 fiji_ps->performance_levels[0].engine_clock = sclk;
4022 fiji_ps->performance_levels[0].memory_clock = mclk;
4023
4024 fiji_ps->performance_levels[1].engine_clock =
4025 (fiji_ps->performance_levels[1].engine_clock >=
4026 fiji_ps->performance_levels[0].engine_clock) ?
4027 fiji_ps->performance_levels[1].engine_clock :
4028 fiji_ps->performance_levels[0].engine_clock;
4029
4030 if (disable_mclk_switching) {
4031 if (mclk < fiji_ps->performance_levels[1].memory_clock)
4032 mclk = fiji_ps->performance_levels[1].memory_clock;
4033
4034 fiji_ps->performance_levels[0].memory_clock = mclk;
4035 fiji_ps->performance_levels[1].memory_clock = mclk;
4036 } else {
4037 if (fiji_ps->performance_levels[1].memory_clock <
4038 fiji_ps->performance_levels[0].memory_clock)
4039 fiji_ps->performance_levels[1].memory_clock =
4040 fiji_ps->performance_levels[0].memory_clock;
4041 }
4042
4043 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4044 PHM_PlatformCaps_StablePState)) {
4045 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4046 fiji_ps->performance_levels[i].engine_clock = stable_pstate_sclk;
4047 fiji_ps->performance_levels[i].memory_clock = stable_pstate_mclk;
4048 fiji_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max;
4049 fiji_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max;
4050 }
4051 }
4052
4053 return 0;
4054 }
4055
4056 static int fiji_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
4057 {
4058 const struct phm_set_power_state_input *states =
4059 (const struct phm_set_power_state_input *)input;
4060 const struct fiji_power_state *fiji_ps =
4061 cast_const_phw_fiji_power_state(states->pnew_state);
4062 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4063 struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4064 uint32_t sclk = fiji_ps->performance_levels
4065 [fiji_ps->performance_level_count - 1].engine_clock;
4066 struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4067 uint32_t mclk = fiji_ps->performance_levels
4068 [fiji_ps->performance_level_count - 1].memory_clock;
4069 struct PP_Clocks min_clocks = {0};
4070 uint32_t i;
4071 struct cgs_display_info info = {0};
4072
4073 data->need_update_smu7_dpm_table = 0;
4074
4075 for (i = 0; i < sclk_table->count; i++) {
4076 if (sclk == sclk_table->dpm_levels[i].value)
4077 break;
4078 }
4079
4080 if (i >= sclk_table->count)
4081 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
4082 else {
4083 /* TODO: Check SCLK in DAL's minimum clocks
4084 * in case DeepSleep divider update is required.
4085 */
4086 if(data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR)
4087 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
4088 }
4089
4090 for (i = 0; i < mclk_table->count; i++) {
4091 if (mclk == mclk_table->dpm_levels[i].value)
4092 break;
4093 }
4094
4095 if (i >= mclk_table->count)
4096 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
4097
4098 cgs_get_active_displays_info(hwmgr->device, &info);
4099
4100 if (data->display_timing.num_existing_displays != info.display_count)
4101 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
4102
4103 return 0;
4104 }
4105
4106 static uint16_t fiji_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
4107 const struct fiji_power_state *fiji_ps)
4108 {
4109 uint32_t i;
4110 uint32_t sclk, max_sclk = 0;
4111 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4112 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4113
4114 for (i = 0; i < fiji_ps->performance_level_count; i++) {
4115 sclk = fiji_ps->performance_levels[i].engine_clock;
4116 if (max_sclk < sclk)
4117 max_sclk = sclk;
4118 }
4119
4120 for (i = 0; i < dpm_table->sclk_table.count; i++) {
4121 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk)
4122 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ?
4123 dpm_table->pcie_speed_table.dpm_levels
4124 [dpm_table->pcie_speed_table.count - 1].value :
4125 dpm_table->pcie_speed_table.dpm_levels[i].value);
4126 }
4127
4128 return 0;
4129 }
4130
4131 static int fiji_request_link_speed_change_before_state_change(
4132 struct pp_hwmgr *hwmgr, const void *input)
4133 {
4134 const struct phm_set_power_state_input *states =
4135 (const struct phm_set_power_state_input *)input;
4136 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4137 const struct fiji_power_state *fiji_nps =
4138 cast_const_phw_fiji_power_state(states->pnew_state);
4139 const struct fiji_power_state *fiji_cps =
4140 cast_const_phw_fiji_power_state(states->pcurrent_state);
4141
4142 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_nps);
4143 uint16_t current_link_speed;
4144
4145 if (data->force_pcie_gen == PP_PCIEGenInvalid)
4146 current_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_cps);
4147 else
4148 current_link_speed = data->force_pcie_gen;
4149
4150 data->force_pcie_gen = PP_PCIEGenInvalid;
4151 data->pspp_notify_required = false;
4152 if (target_link_speed > current_link_speed) {
4153 switch(target_link_speed) {
4154 case PP_PCIEGen3:
4155 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN3, false))
4156 break;
4157 data->force_pcie_gen = PP_PCIEGen2;
4158 if (current_link_speed == PP_PCIEGen2)
4159 break;
4160 case PP_PCIEGen2:
4161 if (0 == acpi_pcie_perf_request(hwmgr->device, PCIE_PERF_REQ_GEN2, false))
4162 break;
4163 default:
4164 data->force_pcie_gen = fiji_get_current_pcie_speed(hwmgr);
4165 break;
4166 }
4167 } else {
4168 if (target_link_speed < current_link_speed)
4169 data->pspp_notify_required = true;
4170 }
4171
4172 return 0;
4173 }
4174
4175 static int fiji_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4176 {
4177 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4178
4179 if (0 == data->need_update_smu7_dpm_table)
4180 return 0;
4181
4182 if ((0 == data->sclk_dpm_key_disabled) &&
4183 (data->need_update_smu7_dpm_table &
4184 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4185 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4186 "Trying to freeze SCLK DPM when DPM is disabled",);
4187 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4188 PPSMC_MSG_SCLKDPM_FreezeLevel),
4189 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!",
4190 return -1);
4191 }
4192
4193 if ((0 == data->mclk_dpm_key_disabled) &&
4194 (data->need_update_smu7_dpm_table &
4195 DPMTABLE_OD_UPDATE_MCLK)) {
4196 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4197 "Trying to freeze MCLK DPM when DPM is disabled",);
4198 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4199 PPSMC_MSG_MCLKDPM_FreezeLevel),
4200 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!",
4201 return -1);
4202 }
4203
4204 return 0;
4205 }
4206
4207 static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
4208 struct pp_hwmgr *hwmgr, const void *input)
4209 {
4210 int result = 0;
4211 const struct phm_set_power_state_input *states =
4212 (const struct phm_set_power_state_input *)input;
4213 const struct fiji_power_state *fiji_ps =
4214 cast_const_phw_fiji_power_state(states->pnew_state);
4215 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4216 uint32_t sclk = fiji_ps->performance_levels
4217 [fiji_ps->performance_level_count - 1].engine_clock;
4218 uint32_t mclk = fiji_ps->performance_levels
4219 [fiji_ps->performance_level_count - 1].memory_clock;
4220 struct fiji_dpm_table *dpm_table = &data->dpm_table;
4221
4222 struct fiji_dpm_table *golden_dpm_table = &data->golden_dpm_table;
4223 uint32_t dpm_count, clock_percent;
4224 uint32_t i;
4225
4226 if (0 == data->need_update_smu7_dpm_table)
4227 return 0;
4228
4229 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
4230 dpm_table->sclk_table.dpm_levels
4231 [dpm_table->sclk_table.count - 1].value = sclk;
4232
4233 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4234 PHM_PlatformCaps_OD6PlusinACSupport) ||
4235 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4236 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4237 /* Need to do calculation based on the golden DPM table
4238 * as the Heatmap GPU Clock axis is also based on the default values
4239 */
4240 PP_ASSERT_WITH_CODE(
4241 (golden_dpm_table->sclk_table.dpm_levels
4242 [golden_dpm_table->sclk_table.count - 1].value != 0),
4243 "Divide by 0!",
4244 return -1);
4245 dpm_count = dpm_table->sclk_table.count < 2 ?
4246 0 : dpm_table->sclk_table.count - 2;
4247 for (i = dpm_count; i > 1; i--) {
4248 if (sclk > golden_dpm_table->sclk_table.dpm_levels
4249 [golden_dpm_table->sclk_table.count-1].value) {
4250 clock_percent =
4251 ((sclk - golden_dpm_table->sclk_table.dpm_levels
4252 [golden_dpm_table->sclk_table.count-1].value) * 100) /
4253 golden_dpm_table->sclk_table.dpm_levels
4254 [golden_dpm_table->sclk_table.count-1].value;
4255
4256 dpm_table->sclk_table.dpm_levels[i].value =
4257 golden_dpm_table->sclk_table.dpm_levels[i].value +
4258 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4259 clock_percent)/100;
4260
4261 } else if (golden_dpm_table->sclk_table.dpm_levels
4262 [dpm_table->sclk_table.count-1].value > sclk) {
4263 clock_percent =
4264 ((golden_dpm_table->sclk_table.dpm_levels
4265 [golden_dpm_table->sclk_table.count - 1].value - sclk) *
4266 100) /
4267 golden_dpm_table->sclk_table.dpm_levels
4268 [golden_dpm_table->sclk_table.count-1].value;
4269
4270 dpm_table->sclk_table.dpm_levels[i].value =
4271 golden_dpm_table->sclk_table.dpm_levels[i].value -
4272 (golden_dpm_table->sclk_table.dpm_levels[i].value *
4273 clock_percent) / 100;
4274 } else
4275 dpm_table->sclk_table.dpm_levels[i].value =
4276 golden_dpm_table->sclk_table.dpm_levels[i].value;
4277 }
4278 }
4279 }
4280
4281 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
4282 dpm_table->mclk_table.dpm_levels
4283 [dpm_table->mclk_table.count - 1].value = mclk;
4284 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4285 PHM_PlatformCaps_OD6PlusinACSupport) ||
4286 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4287 PHM_PlatformCaps_OD6PlusinDCSupport)) {
4288
4289 PP_ASSERT_WITH_CODE(
4290 (golden_dpm_table->mclk_table.dpm_levels
4291 [golden_dpm_table->mclk_table.count-1].value != 0),
4292 "Divide by 0!",
4293 return -1);
4294 dpm_count = dpm_table->mclk_table.count < 2 ?
4295 0 : dpm_table->mclk_table.count - 2;
4296 for (i = dpm_count; i > 1; i--) {
4297 if (mclk > golden_dpm_table->mclk_table.dpm_levels
4298 [golden_dpm_table->mclk_table.count-1].value) {
4299 clock_percent = ((mclk -
4300 golden_dpm_table->mclk_table.dpm_levels
4301 [golden_dpm_table->mclk_table.count-1].value) * 100) /
4302 golden_dpm_table->mclk_table.dpm_levels
4303 [golden_dpm_table->mclk_table.count-1].value;
4304
4305 dpm_table->mclk_table.dpm_levels[i].value =
4306 golden_dpm_table->mclk_table.dpm_levels[i].value +
4307 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4308 clock_percent) / 100;
4309
4310 } else if (golden_dpm_table->mclk_table.dpm_levels
4311 [dpm_table->mclk_table.count-1].value > mclk) {
4312 clock_percent = ((golden_dpm_table->mclk_table.dpm_levels
4313 [golden_dpm_table->mclk_table.count-1].value - mclk) * 100) /
4314 golden_dpm_table->mclk_table.dpm_levels
4315 [golden_dpm_table->mclk_table.count-1].value;
4316
4317 dpm_table->mclk_table.dpm_levels[i].value =
4318 golden_dpm_table->mclk_table.dpm_levels[i].value -
4319 (golden_dpm_table->mclk_table.dpm_levels[i].value *
4320 clock_percent) / 100;
4321 } else
4322 dpm_table->mclk_table.dpm_levels[i].value =
4323 golden_dpm_table->mclk_table.dpm_levels[i].value;
4324 }
4325 }
4326 }
4327
4328 if (data->need_update_smu7_dpm_table &
4329 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
4330 result = fiji_populate_all_memory_levels(hwmgr);
4331 PP_ASSERT_WITH_CODE((0 == result),
4332 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
4333 return result);
4334 }
4335
4336 if (data->need_update_smu7_dpm_table &
4337 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
4338 /*populate MCLK dpm table to SMU7 */
4339 result = fiji_populate_all_memory_levels(hwmgr);
4340 PP_ASSERT_WITH_CODE((0 == result),
4341 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
4342 return result);
4343 }
4344
4345 return result;
4346 }
4347
4348 static int fiji_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
4349 struct fiji_single_dpm_table * dpm_table,
4350 uint32_t low_limit, uint32_t high_limit)
4351 {
4352 uint32_t i;
4353
4354 for (i = 0; i < dpm_table->count; i++) {
4355 if ((dpm_table->dpm_levels[i].value < low_limit) ||
4356 (dpm_table->dpm_levels[i].value > high_limit))
4357 dpm_table->dpm_levels[i].enabled = false;
4358 else
4359 dpm_table->dpm_levels[i].enabled = true;
4360 }
4361 return 0;
4362 }
4363
4364 static int fiji_trim_dpm_states(struct pp_hwmgr *hwmgr,
4365 const struct fiji_power_state *fiji_ps)
4366 {
4367 int result = 0;
4368 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4369 uint32_t high_limit_count;
4370
4371 PP_ASSERT_WITH_CODE((fiji_ps->performance_level_count >= 1),
4372 "power state did not have any performance level",
4373 return -1);
4374
4375 high_limit_count = (1 == fiji_ps->performance_level_count) ? 0 : 1;
4376
4377 fiji_trim_single_dpm_states(hwmgr,
4378 &(data->dpm_table.sclk_table),
4379 fiji_ps->performance_levels[0].engine_clock,
4380 fiji_ps->performance_levels[high_limit_count].engine_clock);
4381
4382 fiji_trim_single_dpm_states(hwmgr,
4383 &(data->dpm_table.mclk_table),
4384 fiji_ps->performance_levels[0].memory_clock,
4385 fiji_ps->performance_levels[high_limit_count].memory_clock);
4386
4387 return result;
4388 }
4389
4390 static int fiji_generate_dpm_level_enable_mask(
4391 struct pp_hwmgr *hwmgr, const void *input)
4392 {
4393 int result;
4394 const struct phm_set_power_state_input *states =
4395 (const struct phm_set_power_state_input *)input;
4396 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4397 const struct fiji_power_state *fiji_ps =
4398 cast_const_phw_fiji_power_state(states->pnew_state);
4399
4400 result = fiji_trim_dpm_states(hwmgr, fiji_ps);
4401 if (result)
4402 return result;
4403
4404 data->dpm_level_enable_mask.sclk_dpm_enable_mask =
4405 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table);
4406 data->dpm_level_enable_mask.mclk_dpm_enable_mask =
4407 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table);
4408 data->last_mclk_dpm_enable_mask =
4409 data->dpm_level_enable_mask.mclk_dpm_enable_mask;
4410
4411 if (data->uvd_enabled) {
4412 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4413 data->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4414 }
4415
4416 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
4417 fiji_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table);
4418
4419 return 0;
4420 }
4421
4422 int fiji_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
4423 {
4424 return smum_send_msg_to_smc(hwmgr->smumgr, enable ?
4425 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Enable :
4426 (PPSMC_Msg)PPSMC_MSG_UVDDPM_Disable);
4427 }
4428
4429 int fiji_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
4430 {
4431 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4432 PPSMC_MSG_VCEDPM_Enable :
4433 PPSMC_MSG_VCEDPM_Disable);
4434 }
4435
4436 int fiji_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable)
4437 {
4438 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4439 PPSMC_MSG_SAMUDPM_Enable :
4440 PPSMC_MSG_SAMUDPM_Disable);
4441 }
4442
4443 int fiji_enable_disable_acp_dpm(struct pp_hwmgr *hwmgr, bool enable)
4444 {
4445 return smum_send_msg_to_smc(hwmgr->smumgr, enable?
4446 PPSMC_MSG_ACPDPM_Enable :
4447 PPSMC_MSG_ACPDPM_Disable);
4448 }
4449
4450 int fiji_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4451 {
4452 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4453 uint32_t mm_boot_level_offset, mm_boot_level_value;
4454 struct phm_ppt_v1_information *table_info =
4455 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4456
4457 if (!bgate) {
4458 data->smc_state_table.UvdBootLevel = 0;
4459 if (table_info->mm_dep_table->count > 0)
4460 data->smc_state_table.UvdBootLevel =
4461 (uint8_t) (table_info->mm_dep_table->count - 1);
4462 mm_boot_level_offset = data->dpm_table_start +
4463 offsetof(SMU73_Discrete_DpmTable, UvdBootLevel);
4464 mm_boot_level_offset /= 4;
4465 mm_boot_level_offset *= 4;
4466 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4467 CGS_IND_REG__SMC, mm_boot_level_offset);
4468 mm_boot_level_value &= 0x00FFFFFF;
4469 mm_boot_level_value |= data->smc_state_table.UvdBootLevel << 24;
4470 cgs_write_ind_register(hwmgr->device,
4471 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4472
4473 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4474 PHM_PlatformCaps_UVDDPM) ||
4475 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4476 PHM_PlatformCaps_StablePState))
4477 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4478 PPSMC_MSG_UVDDPM_SetEnabledMask,
4479 (uint32_t)(1 << data->smc_state_table.UvdBootLevel));
4480 }
4481
4482 return fiji_enable_disable_uvd_dpm(hwmgr, !bgate);
4483 }
4484
4485 int fiji_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
4486 {
4487 const struct phm_set_power_state_input *states =
4488 (const struct phm_set_power_state_input *)input;
4489 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4490 const struct fiji_power_state *fiji_nps =
4491 cast_const_phw_fiji_power_state(states->pnew_state);
4492 const struct fiji_power_state *fiji_cps =
4493 cast_const_phw_fiji_power_state(states->pcurrent_state);
4494
4495 uint32_t mm_boot_level_offset, mm_boot_level_value;
4496 struct phm_ppt_v1_information *table_info =
4497 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4498
4499 if (fiji_nps->vce_clks.evclk >0 &&
4500 (fiji_cps == NULL || fiji_cps->vce_clks.evclk == 0)) {
4501 data->smc_state_table.VceBootLevel =
4502 (uint8_t) (table_info->mm_dep_table->count - 1);
4503
4504 mm_boot_level_offset = data->dpm_table_start +
4505 offsetof(SMU73_Discrete_DpmTable, VceBootLevel);
4506 mm_boot_level_offset /= 4;
4507 mm_boot_level_offset *= 4;
4508 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4509 CGS_IND_REG__SMC, mm_boot_level_offset);
4510 mm_boot_level_value &= 0xFF00FFFF;
4511 mm_boot_level_value |= data->smc_state_table.VceBootLevel << 16;
4512 cgs_write_ind_register(hwmgr->device,
4513 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4514
4515 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4516 PHM_PlatformCaps_StablePState)) {
4517 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4518 PPSMC_MSG_VCEDPM_SetEnabledMask,
4519 (uint32_t)1 << data->smc_state_table.VceBootLevel);
4520
4521 fiji_enable_disable_vce_dpm(hwmgr, true);
4522 } else if (fiji_nps->vce_clks.evclk == 0 &&
4523 fiji_cps != NULL &&
4524 fiji_cps->vce_clks.evclk > 0)
4525 fiji_enable_disable_vce_dpm(hwmgr, false);
4526 }
4527
4528 return 0;
4529 }
4530
4531 int fiji_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4532 {
4533 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4534 uint32_t mm_boot_level_offset, mm_boot_level_value;
4535 struct phm_ppt_v1_information *table_info =
4536 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4537
4538 if (!bgate) {
4539 data->smc_state_table.SamuBootLevel =
4540 (uint8_t) (table_info->mm_dep_table->count - 1);
4541 mm_boot_level_offset = data->dpm_table_start +
4542 offsetof(SMU73_Discrete_DpmTable, SamuBootLevel);
4543 mm_boot_level_offset /= 4;
4544 mm_boot_level_offset *= 4;
4545 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4546 CGS_IND_REG__SMC, mm_boot_level_offset);
4547 mm_boot_level_value &= 0xFFFFFF00;
4548 mm_boot_level_value |= data->smc_state_table.SamuBootLevel << 0;
4549 cgs_write_ind_register(hwmgr->device,
4550 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4551
4552 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4553 PHM_PlatformCaps_StablePState))
4554 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4555 PPSMC_MSG_SAMUDPM_SetEnabledMask,
4556 (uint32_t)(1 << data->smc_state_table.SamuBootLevel));
4557 }
4558
4559 return fiji_enable_disable_samu_dpm(hwmgr, !bgate);
4560 }
4561
4562 int fiji_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate)
4563 {
4564 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4565 uint32_t mm_boot_level_offset, mm_boot_level_value;
4566 struct phm_ppt_v1_information *table_info =
4567 (struct phm_ppt_v1_information *)(hwmgr->pptable);
4568
4569 if (!bgate) {
4570 data->smc_state_table.AcpBootLevel =
4571 (uint8_t) (table_info->mm_dep_table->count - 1);
4572 mm_boot_level_offset = data->dpm_table_start +
4573 offsetof(SMU73_Discrete_DpmTable, AcpBootLevel);
4574 mm_boot_level_offset /= 4;
4575 mm_boot_level_offset *= 4;
4576 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
4577 CGS_IND_REG__SMC, mm_boot_level_offset);
4578 mm_boot_level_value &= 0xFFFF00FF;
4579 mm_boot_level_value |= data->smc_state_table.AcpBootLevel << 8;
4580 cgs_write_ind_register(hwmgr->device,
4581 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
4582
4583 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4584 PHM_PlatformCaps_StablePState))
4585 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4586 PPSMC_MSG_ACPDPM_SetEnabledMask,
4587 (uint32_t)(1 << data->smc_state_table.AcpBootLevel));
4588 }
4589
4590 return fiji_enable_disable_acp_dpm(hwmgr, !bgate);
4591 }
4592
4593 static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
4594 {
4595 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4596
4597 int result = 0;
4598 uint32_t low_sclk_interrupt_threshold = 0;
4599
4600 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4601 PHM_PlatformCaps_SclkThrottleLowNotification)
4602 && (hwmgr->gfx_arbiter.sclk_threshold !=
4603 data->low_sclk_interrupt_threshold)) {
4604 data->low_sclk_interrupt_threshold =
4605 hwmgr->gfx_arbiter.sclk_threshold;
4606 low_sclk_interrupt_threshold =
4607 data->low_sclk_interrupt_threshold;
4608
4609 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
4610
4611 result = fiji_copy_bytes_to_smc(
4612 hwmgr->smumgr,
4613 data->dpm_table_start +
4614 offsetof(SMU73_Discrete_DpmTable,
4615 LowSclkInterruptThreshold),
4616 (uint8_t *)&low_sclk_interrupt_threshold,
4617 sizeof(uint32_t),
4618 data->sram_end);
4619 }
4620
4621 return result;
4622 }
4623
4624 static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
4625 {
4626 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4627
4628 if (data->need_update_smu7_dpm_table &
4629 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
4630 return fiji_program_memory_timing_parameters(hwmgr);
4631
4632 return 0;
4633 }
4634
4635 static int fiji_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
4636 {
4637 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4638
4639 if (0 == data->need_update_smu7_dpm_table)
4640 return 0;
4641
4642 if ((0 == data->sclk_dpm_key_disabled) &&
4643 (data->need_update_smu7_dpm_table &
4644 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
4645
4646 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4647 "Trying to Unfreeze SCLK DPM when DPM is disabled",);
4648 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4649 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4650 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!",
4651 return -1);
4652 }
4653
4654 if ((0 == data->mclk_dpm_key_disabled) &&
4655 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
4656
4657 PP_ASSERT_WITH_CODE(true == fiji_is_dpm_running(hwmgr),
4658 "Trying to Unfreeze MCLK DPM when DPM is disabled",);
4659 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr,
4660 PPSMC_MSG_SCLKDPM_UnfreezeLevel),
4661 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!",
4662 return -1);
4663 }
4664
4665 data->need_update_smu7_dpm_table = 0;
4666
4667 return 0;
4668 }
4669
4670 /* Look up the voltaged based on DAL's requested level.
4671 * and then send the requested VDDC voltage to SMC
4672 */
4673 static void fiji_apply_dal_minimum_voltage_request(struct pp_hwmgr *hwmgr)
4674 {
4675 return;
4676 }
4677
4678 int fiji_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
4679 {
4680 int result;
4681 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4682
4683 /* Apply minimum voltage based on DAL's request level */
4684 fiji_apply_dal_minimum_voltage_request(hwmgr);
4685
4686 if (0 == data->sclk_dpm_key_disabled) {
4687 /* Checking if DPM is running. If we discover hang because of this,
4688 * we should skip this message.
4689 */
4690 if (!fiji_is_dpm_running(hwmgr))
4691 printk(KERN_ERR "[ powerplay ] "
4692 "Trying to set Enable Mask when DPM is disabled \n");
4693
4694 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4695 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4696 PPSMC_MSG_SCLKDPM_SetEnabledMask,
4697 data->dpm_level_enable_mask.sclk_dpm_enable_mask);
4698 PP_ASSERT_WITH_CODE((0 == result),
4699 "Set Sclk Dpm enable Mask failed", return -1);
4700 }
4701 }
4702
4703 if (0 == data->mclk_dpm_key_disabled) {
4704 /* Checking if DPM is running. If we discover hang because of this,
4705 * we should skip this message.
4706 */
4707 if (!fiji_is_dpm_running(hwmgr))
4708 printk(KERN_ERR "[ powerplay ]"
4709 " Trying to set Enable Mask when DPM is disabled \n");
4710
4711 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4712 result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4713 PPSMC_MSG_MCLKDPM_SetEnabledMask,
4714 data->dpm_level_enable_mask.mclk_dpm_enable_mask);
4715 PP_ASSERT_WITH_CODE((0 == result),
4716 "Set Mclk Dpm enable Mask failed", return -1);
4717 }
4718 }
4719
4720 return 0;
4721 }
4722
4723 static int fiji_notify_link_speed_change_after_state_change(
4724 struct pp_hwmgr *hwmgr, const void *input)
4725 {
4726 const struct phm_set_power_state_input *states =
4727 (const struct phm_set_power_state_input *)input;
4728 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4729 const struct fiji_power_state *fiji_ps =
4730 cast_const_phw_fiji_power_state(states->pnew_state);
4731 uint16_t target_link_speed = fiji_get_maximum_link_speed(hwmgr, fiji_ps);
4732 uint8_t request;
4733
4734 if (data->pspp_notify_required) {
4735 if (target_link_speed == PP_PCIEGen3)
4736 request = PCIE_PERF_REQ_GEN3;
4737 else if (target_link_speed == PP_PCIEGen2)
4738 request = PCIE_PERF_REQ_GEN2;
4739 else
4740 request = PCIE_PERF_REQ_GEN1;
4741
4742 if(request == PCIE_PERF_REQ_GEN1 &&
4743 fiji_get_current_pcie_speed(hwmgr) > 0)
4744 return 0;
4745
4746 if (acpi_pcie_perf_request(hwmgr->device, request, false)) {
4747 if (PP_PCIEGen2 == target_link_speed)
4748 printk("PSPP request to switch to Gen2 from Gen3 Failed!");
4749 else
4750 printk("PSPP request to switch to Gen1 from Gen2 Failed!");
4751 }
4752 }
4753
4754 return 0;
4755 }
4756
4757 static int fiji_set_power_state_tasks(struct pp_hwmgr *hwmgr,
4758 const void *input)
4759 {
4760 int tmp_result, result = 0;
4761
4762 tmp_result = fiji_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
4763 PP_ASSERT_WITH_CODE((0 == tmp_result),
4764 "Failed to find DPM states clocks in DPM table!",
4765 result = tmp_result);
4766
4767 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4768 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4769 tmp_result =
4770 fiji_request_link_speed_change_before_state_change(hwmgr, input);
4771 PP_ASSERT_WITH_CODE((0 == tmp_result),
4772 "Failed to request link speed change before state change!",
4773 result = tmp_result);
4774 }
4775
4776 tmp_result = fiji_freeze_sclk_mclk_dpm(hwmgr);
4777 PP_ASSERT_WITH_CODE((0 == tmp_result),
4778 "Failed to freeze SCLK MCLK DPM!", result = tmp_result);
4779
4780 tmp_result = fiji_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
4781 PP_ASSERT_WITH_CODE((0 == tmp_result),
4782 "Failed to populate and upload SCLK MCLK DPM levels!",
4783 result = tmp_result);
4784
4785 tmp_result = fiji_generate_dpm_level_enable_mask(hwmgr, input);
4786 PP_ASSERT_WITH_CODE((0 == tmp_result),
4787 "Failed to generate DPM level enabled mask!",
4788 result = tmp_result);
4789
4790 tmp_result = fiji_update_vce_dpm(hwmgr, input);
4791 PP_ASSERT_WITH_CODE((0 == tmp_result),
4792 "Failed to update VCE DPM!",
4793 result = tmp_result);
4794
4795 tmp_result = fiji_update_sclk_threshold(hwmgr);
4796 PP_ASSERT_WITH_CODE((0 == tmp_result),
4797 "Failed to update SCLK threshold!",
4798 result = tmp_result);
4799
4800 tmp_result = fiji_program_mem_timing_parameters(hwmgr);
4801 PP_ASSERT_WITH_CODE((0 == tmp_result),
4802 "Failed to program memory timing parameters!",
4803 result = tmp_result);
4804
4805 tmp_result = fiji_unfreeze_sclk_mclk_dpm(hwmgr);
4806 PP_ASSERT_WITH_CODE((0 == tmp_result),
4807 "Failed to unfreeze SCLK MCLK DPM!",
4808 result = tmp_result);
4809
4810 tmp_result = fiji_upload_dpm_level_enable_mask(hwmgr);
4811 PP_ASSERT_WITH_CODE((0 == tmp_result),
4812 "Failed to upload DPM level enabled mask!",
4813 result = tmp_result);
4814
4815 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
4816 PHM_PlatformCaps_PCIEPerformanceRequest)) {
4817 tmp_result =
4818 fiji_notify_link_speed_change_after_state_change(hwmgr, input);
4819 PP_ASSERT_WITH_CODE((0 == tmp_result),
4820 "Failed to notify link speed change after state change!",
4821 result = tmp_result);
4822 }
4823
4824 return result;
4825 }
4826
4827 static int fiji_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
4828 {
4829 struct pp_power_state *ps;
4830 struct fiji_power_state *fiji_ps;
4831
4832 if (hwmgr == NULL)
4833 return -EINVAL;
4834
4835 ps = hwmgr->request_ps;
4836
4837 if (ps == NULL)
4838 return -EINVAL;
4839
4840 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4841
4842 if (low)
4843 return fiji_ps->performance_levels[0].engine_clock;
4844 else
4845 return fiji_ps->performance_levels
4846 [fiji_ps->performance_level_count-1].engine_clock;
4847 }
4848
4849 static int fiji_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
4850 {
4851 struct pp_power_state *ps;
4852 struct fiji_power_state *fiji_ps;
4853
4854 if (hwmgr == NULL)
4855 return -EINVAL;
4856
4857 ps = hwmgr->request_ps;
4858
4859 if (ps == NULL)
4860 return -EINVAL;
4861
4862 fiji_ps = cast_phw_fiji_power_state(&ps->hardware);
4863
4864 if (low)
4865 return fiji_ps->performance_levels[0].memory_clock;
4866 else
4867 return fiji_ps->performance_levels
4868 [fiji_ps->performance_level_count-1].memory_clock;
4869 }
4870
4871 static void fiji_print_current_perforce_level(
4872 struct pp_hwmgr *hwmgr, struct seq_file *m)
4873 {
4874 uint32_t sclk, mclk, activity_percent = 0;
4875 uint32_t offset;
4876 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4877
4878 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
4879
4880 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4881
4882 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
4883
4884 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
4885 seq_printf(m, "\n [ mclk ]: %u MHz\n\n [ sclk ]: %u MHz\n",
4886 mclk / 100, sclk / 100);
4887
4888 offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, AverageGraphicsActivity);
4889 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
4890 activity_percent += 0x80;
4891 activity_percent >>= 8;
4892
4893 seq_printf(m, "\n [GPU load]: %u%%\n\n", activity_percent > 100 ? 100 : activity_percent);
4894
4895 seq_printf(m, "uvd %sabled\n", data->uvd_power_gated ? "dis" : "en");
4896
4897 seq_printf(m, "vce %sabled\n", data->vce_power_gated ? "dis" : "en");
4898 }
4899
4900 static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
4901 {
4902 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
4903 uint32_t num_active_displays = 0;
4904 uint32_t display_gap = cgs_read_ind_register(hwmgr->device,
4905 CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
4906 uint32_t display_gap2;
4907 uint32_t pre_vbi_time_in_us;
4908 uint32_t frame_time_in_us;
4909 uint32_t ref_clock;
4910 uint32_t refresh_rate = 0;
4911 struct cgs_display_info info = {0};
4912 struct cgs_mode_info mode_info;
4913
4914 info.mode_info = &mode_info;
4915
4916 cgs_get_active_displays_info(hwmgr->device, &info);
4917 num_active_displays = info.display_count;
4918
4919 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL,
4920 DISP_GAP, (num_active_displays > 0)?
4921 DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
4922 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4923 ixCG_DISPLAY_GAP_CNTL, display_gap);
4924
4925 ref_clock = mode_info.ref_clock;
4926 refresh_rate = mode_info.refresh_rate;
4927
4928 if (refresh_rate == 0)
4929 refresh_rate = 60;
4930
4931 frame_time_in_us = 1000000 / refresh_rate;
4932
4933 pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;
4934 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);
4935
4936 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4937 ixCG_DISPLAY_GAP_CNTL2, display_gap2);
4938
4939 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4940 data->soft_regs_start +
4941 offsetof(SMU73_SoftRegisters, PreVBlankGap), 0x64);
4942
4943 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
4944 data->soft_regs_start +
4945 offsetof(SMU73_SoftRegisters, VBlankTimeout),
4946 (frame_time_in_us - pre_vbi_time_in_us));
4947
4948 if (num_active_displays == 1)
4949 tonga_notify_smc_display_change(hwmgr, true);
4950
4951 return 0;
4952 }
4953
4954 int fiji_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
4955 {
4956 return fiji_program_display_gap(hwmgr);
4957 }
4958
4959 static int fiji_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr,
4960 uint16_t us_max_fan_pwm)
4961 {
4962 hwmgr->thermal_controller.
4963 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm;
4964
4965 if (phm_is_hw_access_blocked(hwmgr))
4966 return 0;
4967
4968 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4969 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm);
4970 }
4971
4972 static int fiji_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr,
4973 uint16_t us_max_fan_rpm)
4974 {
4975 hwmgr->thermal_controller.
4976 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm;
4977
4978 if (phm_is_hw_access_blocked(hwmgr))
4979 return 0;
4980
4981 return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
4982 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm);
4983 }
4984
4985 int fiji_dpm_set_interrupt_state(void *private_data,
4986 unsigned src_id, unsigned type,
4987 int enabled)
4988 {
4989 uint32_t cg_thermal_int;
4990 struct pp_hwmgr *hwmgr = ((struct pp_eventmgr *)private_data)->hwmgr;
4991
4992 if (hwmgr == NULL)
4993 return -EINVAL;
4994
4995 switch (type) {
4996 case AMD_THERMAL_IRQ_LOW_TO_HIGH:
4997 if (enabled) {
4998 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
4999 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5000 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5001 cgs_write_ind_register(hwmgr->device,
5002 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5003 } else {
5004 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5005 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5006 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK;
5007 cgs_write_ind_register(hwmgr->device,
5008 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5009 }
5010 break;
5011
5012 case AMD_THERMAL_IRQ_HIGH_TO_LOW:
5013 if (enabled) {
5014 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5015 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5016 cg_thermal_int |= CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5017 cgs_write_ind_register(hwmgr->device,
5018 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5019 } else {
5020 cg_thermal_int = cgs_read_ind_register(hwmgr->device,
5021 CGS_IND_REG__SMC, ixCG_THERMAL_INT);
5022 cg_thermal_int &= ~CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK;
5023 cgs_write_ind_register(hwmgr->device,
5024 CGS_IND_REG__SMC, ixCG_THERMAL_INT, cg_thermal_int);
5025 }
5026 break;
5027 default:
5028 break;
5029 }
5030 return 0;
5031 }
5032
5033 int fiji_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr,
5034 const void *thermal_interrupt_info)
5035 {
5036 int result;
5037 const struct pp_interrupt_registration_info *info =
5038 (const struct pp_interrupt_registration_info *)
5039 thermal_interrupt_info;
5040
5041 if (info == NULL)
5042 return -EINVAL;
5043
5044 result = cgs_add_irq_source(hwmgr->device, 230, AMD_THERMAL_IRQ_LAST,
5045 fiji_dpm_set_interrupt_state,
5046 info->call_back, info->context);
5047
5048 if (result)
5049 return -EINVAL;
5050
5051 result = cgs_add_irq_source(hwmgr->device, 231, AMD_THERMAL_IRQ_LAST,
5052 fiji_dpm_set_interrupt_state,
5053 info->call_back, info->context);
5054
5055 if (result)
5056 return -EINVAL;
5057
5058 return 0;
5059 }
5060
5061 static int fiji_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
5062 {
5063 if (mode) {
5064 /* stop auto-manage */
5065 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
5066 PHM_PlatformCaps_MicrocodeFanControl))
5067 fiji_fan_ctrl_stop_smc_fan_control(hwmgr);
5068 fiji_fan_ctrl_set_static_mode(hwmgr, mode);
5069 } else
5070 /* restart auto-manage */
5071 fiji_fan_ctrl_reset_fan_speed_to_default(hwmgr);
5072
5073 return 0;
5074 }
5075
5076 static int fiji_get_fan_control_mode(struct pp_hwmgr *hwmgr)
5077 {
5078 if (hwmgr->fan_ctrl_is_in_default_mode)
5079 return hwmgr->fan_ctrl_default_mode;
5080 else
5081 return PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
5082 CG_FDO_CTRL2, FDO_PWM_MODE);
5083 }
5084
5085 static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
5086 {
5087 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5088
5089 *table = (char *)&data->smc_state_table;
5090
5091 return sizeof(struct SMU73_Discrete_DpmTable);
5092 }
5093
5094 static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size)
5095 {
5096 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5097
5098 void *table = (void *)&data->smc_state_table;
5099
5100 memcpy(table, buf, size);
5101
5102 return 0;
5103 }
5104
5105 static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
5106 enum pp_clock_type type, int level)
5107 {
5108 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5109
5110 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
5111 return -EINVAL;
5112
5113 switch (type) {
5114 case PP_SCLK:
5115 if (!data->sclk_dpm_key_disabled)
5116 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5117 PPSMC_MSG_SCLKDPM_SetEnabledMask,
5118 (1 << level));
5119 break;
5120 case PP_MCLK:
5121 if (!data->mclk_dpm_key_disabled)
5122 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5123 PPSMC_MSG_MCLKDPM_SetEnabledMask,
5124 (1 << level));
5125 break;
5126 case PP_PCIE:
5127 if (!data->pcie_dpm_key_disabled)
5128 smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
5129 PPSMC_MSG_PCIeDPM_ForceLevel,
5130 (1 << level));
5131 break;
5132 default:
5133 break;
5134 }
5135
5136 return 0;
5137 }
5138
5139 static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5140 enum pp_clock_type type, char *buf)
5141 {
5142 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5143 struct fiji_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
5144 struct fiji_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
5145 struct fiji_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table);
5146 int i, now, size = 0;
5147 uint32_t clock, pcie_speed;
5148
5149 switch (type) {
5150 case PP_SCLK:
5151 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency);
5152 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5153
5154 for (i = 0; i < sclk_table->count; i++) {
5155 if (clock > sclk_table->dpm_levels[i].value)
5156 continue;
5157 break;
5158 }
5159 now = i;
5160
5161 for (i = 0; i < sclk_table->count; i++)
5162 size += sprintf(buf + size, "%d: %uMhz %s\n",
5163 i, sclk_table->dpm_levels[i].value / 100,
5164 (i == now) ? "*" : "");
5165 break;
5166 case PP_MCLK:
5167 smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency);
5168 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
5169
5170 for (i = 0; i < mclk_table->count; i++) {
5171 if (clock > mclk_table->dpm_levels[i].value)
5172 continue;
5173 break;
5174 }
5175 now = i;
5176
5177 for (i = 0; i < mclk_table->count; i++)
5178 size += sprintf(buf + size, "%d: %uMhz %s\n",
5179 i, mclk_table->dpm_levels[i].value / 100,
5180 (i == now) ? "*" : "");
5181 break;
5182 case PP_PCIE:
5183 pcie_speed = fiji_get_current_pcie_speed(hwmgr);
5184 for (i = 0; i < pcie_table->count; i++) {
5185 if (pcie_speed != pcie_table->dpm_levels[i].value)
5186 continue;
5187 break;
5188 }
5189 now = i;
5190
5191 for (i = 0; i < pcie_table->count; i++)
5192 size += sprintf(buf + size, "%d: %s %s\n", i,
5193 (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x1" :
5194 (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" :
5195 (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "",
5196 (i == now) ? "*" : "");
5197 break;
5198 default:
5199 break;
5200 }
5201 return size;
5202 }
5203
5204 static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5205 const struct fiji_performance_level *pl2)
5206 {
5207 return ((pl1->memory_clock == pl2->memory_clock) &&
5208 (pl1->engine_clock == pl2->engine_clock) &&
5209 (pl1->pcie_gen == pl2->pcie_gen) &&
5210 (pl1->pcie_lane == pl2->pcie_lane));
5211 }
5212
5213 int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5214 {
5215 const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5216 const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5217 int i;
5218
5219 if (equal == NULL || psa == NULL || psb == NULL)
5220 return -EINVAL;
5221
5222 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5223 if (psa->performance_level_count != psb->performance_level_count) {
5224 *equal = false;
5225 return 0;
5226 }
5227
5228 for (i = 0; i < psa->performance_level_count; i++) {
5229 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5230 /* If we have found even one performance level pair that is different the states are different. */
5231 *equal = false;
5232 return 0;
5233 }
5234 }
5235
5236 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5237 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5238 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5239 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5240 *equal &= (psa->acp_clk == psb->acp_clk);
5241
5242 return 0;
5243 }
5244
5245 bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5246 {
5247 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5248 bool is_update_required = false;
5249 struct cgs_display_info info = {0,0,NULL};
5250
5251 cgs_get_active_displays_info(hwmgr->device, &info);
5252
5253 if (data->display_timing.num_existing_displays != info.display_count)
5254 is_update_required = true;
5255 /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5256 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5257 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5258 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5259 is_update_required = true;
5260 */
5261 return is_update_required;
5262 }
5263
5264
5265 static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5266 .backend_init = &fiji_hwmgr_backend_init,
5267 .backend_fini = &tonga_hwmgr_backend_fini,
5268 .asic_setup = &fiji_setup_asic_task,
5269 .dynamic_state_management_enable = &fiji_enable_dpm_tasks,
5270 .force_dpm_level = &fiji_dpm_force_dpm_level,
5271 .get_num_of_pp_table_entries = &tonga_get_number_of_powerplay_table_entries,
5272 .get_power_state_size = &fiji_get_power_state_size,
5273 .get_pp_table_entry = &fiji_get_pp_table_entry,
5274 .patch_boot_state = &fiji_patch_boot_state,
5275 .apply_state_adjust_rules = &fiji_apply_state_adjust_rules,
5276 .power_state_set = &fiji_set_power_state_tasks,
5277 .get_sclk = &fiji_dpm_get_sclk,
5278 .get_mclk = &fiji_dpm_get_mclk,
5279 .print_current_perforce_level = &fiji_print_current_perforce_level,
5280 .powergate_uvd = &fiji_phm_powergate_uvd,
5281 .powergate_vce = &fiji_phm_powergate_vce,
5282 .disable_clock_power_gating = &fiji_phm_disable_clock_power_gating,
5283 .notify_smc_display_config_after_ps_adjustment =
5284 &tonga_notify_smc_display_config_after_ps_adjustment,
5285 .display_config_changed = &fiji_display_configuration_changed_task,
5286 .set_max_fan_pwm_output = fiji_set_max_fan_pwm_output,
5287 .set_max_fan_rpm_output = fiji_set_max_fan_rpm_output,
5288 .get_temperature = fiji_thermal_get_temperature,
5289 .stop_thermal_controller = fiji_thermal_stop_thermal_controller,
5290 .get_fan_speed_info = fiji_fan_ctrl_get_fan_speed_info,
5291 .get_fan_speed_percent = fiji_fan_ctrl_get_fan_speed_percent,
5292 .set_fan_speed_percent = fiji_fan_ctrl_set_fan_speed_percent,
5293 .reset_fan_speed_to_default = fiji_fan_ctrl_reset_fan_speed_to_default,
5294 .get_fan_speed_rpm = fiji_fan_ctrl_get_fan_speed_rpm,
5295 .set_fan_speed_rpm = fiji_fan_ctrl_set_fan_speed_rpm,
5296 .uninitialize_thermal_controller = fiji_thermal_ctrl_uninitialize_thermal_controller,
5297 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5298 .set_fan_control_mode = fiji_set_fan_control_mode,
5299 .get_fan_control_mode = fiji_get_fan_control_mode,
5300 .check_states_equal = fiji_check_states_equal,
5301 .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5302 .get_pp_table = fiji_get_pp_table,
5303 .set_pp_table = fiji_set_pp_table,
5304 .force_clock_level = fiji_force_clock_level,
5305 .print_clock_levels = fiji_print_clock_levels,
5306 };
5307
5308 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
5309 {
5310 struct fiji_hwmgr *data;
5311 int ret = 0;
5312
5313 data = kzalloc(sizeof(struct fiji_hwmgr), GFP_KERNEL);
5314 if (data == NULL)
5315 return -ENOMEM;
5316
5317 hwmgr->backend = data;
5318 hwmgr->hwmgr_func = &fiji_hwmgr_funcs;
5319 hwmgr->pptable_func = &tonga_pptable_funcs;
5320 pp_fiji_thermal_initialize(hwmgr);
5321 return ret;
5322 }
Linux kernel - Deliverables
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