drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui <ray.huang@amd.com>
  23  *
  24  */
  25 #ifndef ICELAND_HWMGR_H
  26 #define ICELAND_HWMGR_H
  27
  28 #include "hwmgr.h"
  29 #include "ppatomctrl.h"
  30 #include "ppinterrupt.h"
  31 #include "ppsmc.h"
  32 #include "iceland_powertune.h"
  33 #include "pp_endian.h"
  34 #include "smu71_discrete.h"
  35
  36 #define ICELAND_MAX_HARDWARE_POWERLEVELS 2
  37 #define ICELAND_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS 15
  38
  39 struct iceland_performance_level {
  40         uint32_t        memory_clock;
  41         uint32_t        engine_clock;
  42         uint16_t        pcie_gen;
  43         uint16_t        pcie_lane;
  44 };
  45
  46 struct _phw_iceland_bacos {
  47         uint32_t                          best_match;
  48         uint32_t                          baco_flags;
  49         struct iceland_performance_level                  performance_level;
  50 };
  51 typedef struct _phw_iceland_bacos phw_iceland_bacos;
  52
  53 struct _phw_iceland_uvd_clocks {
  54         uint32_t   VCLK;
  55         uint32_t   DCLK;
  56 };
  57
  58 typedef struct _phw_iceland_uvd_clocks phw_iceland_uvd_clocks;
  59
  60 struct _phw_iceland_vce_clocks {
  61         uint32_t   EVCLK;
  62         uint32_t   ECCLK;
  63 };
  64
  65 typedef struct _phw_iceland_vce_clocks phw_iceland_vce_clocks;
  66
  67 struct iceland_power_state {
  68         uint32_t                    magic;
  69         phw_iceland_uvd_clocks        uvd_clocks;
  70         phw_iceland_vce_clocks        vce_clocks;
  71         uint32_t                    sam_clk;
  72         uint32_t                    acp_clk;
  73         uint16_t                    performance_level_count;
  74         bool                        dc_compatible;
  75         uint32_t                    sclk_threshold;
  76         struct iceland_performance_level performance_levels[ICELAND_MAX_HARDWARE_POWERLEVELS];
  77 };
  78
  79 struct _phw_iceland_dpm_level {
  80         bool            enabled;
  81         uint32_t    value;
  82         uint32_t    param1;
  83 };
  84 typedef struct _phw_iceland_dpm_level phw_iceland_dpm_level;
  85
  86 #define ICELAND_MAX_DEEPSLEEP_DIVIDER_ID 5
  87 #define MAX_REGULAR_DPM_NUMBER 8
  88 #define ICELAND_MINIMUM_ENGINE_CLOCK 5000
  89
  90 struct iceland_single_dpm_table {
  91         uint32_t count;
  92         phw_iceland_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
  93 };
  94
  95 struct iceland_dpm_table {
  96         struct iceland_single_dpm_table  sclk_table;
  97         struct iceland_single_dpm_table  mclk_table;
  98         struct iceland_single_dpm_table  pcie_speed_table;
  99         struct iceland_single_dpm_table  vddc_table;
 100         struct iceland_single_dpm_table  vdd_gfx_table;
 101         struct iceland_single_dpm_table  vdd_ci_table;
 102         struct iceland_single_dpm_table  mvdd_table;
 103 };
 104 typedef struct _phw_iceland_dpm_table phw_iceland_dpm_table;
 105
 106
 107 struct _phw_iceland_clock_regisiters {
 108         uint32_t  vCG_SPLL_FUNC_CNTL;
 109         uint32_t  vCG_SPLL_FUNC_CNTL_2;
 110         uint32_t  vCG_SPLL_FUNC_CNTL_3;
 111         uint32_t  vCG_SPLL_FUNC_CNTL_4;
 112         uint32_t  vCG_SPLL_SPREAD_SPECTRUM;
 113         uint32_t  vCG_SPLL_SPREAD_SPECTRUM_2;
 114         uint32_t  vDLL_CNTL;
 115         uint32_t  vMCLK_PWRMGT_CNTL;
 116         uint32_t  vMPLL_AD_FUNC_CNTL;
 117         uint32_t  vMPLL_DQ_FUNC_CNTL;
 118         uint32_t  vMPLL_FUNC_CNTL;
 119         uint32_t  vMPLL_FUNC_CNTL_1;
 120         uint32_t  vMPLL_FUNC_CNTL_2;
 121         uint32_t  vMPLL_SS1;
 122         uint32_t  vMPLL_SS2;
 123 };
 124 typedef struct _phw_iceland_clock_regisiters phw_iceland_clock_registers;
 125
 126 struct _phw_iceland_voltage_smio_registers {
 127         uint32_t vs0_vid_lower_smio_cntl;
 128 };
 129 typedef struct _phw_iceland_voltage_smio_registers phw_iceland_voltage_smio_registers;
 130
 131
 132 struct _phw_iceland_mc_reg_entry {
 133         uint32_t mclk_max;
 134         uint32_t mc_data[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
 135 };
 136 typedef struct _phw_iceland_mc_reg_entry phw_iceland_mc_reg_entry;
 137
 138 struct _phw_iceland_mc_reg_table {
 139         uint8_t   last;               /* number of registers*/
 140         uint8_t   num_entries;        /* number of entries in mc_reg_table_entry used*/
 141         uint16_t  validflag;          /* indicate the corresponding register is valid or not. 1: valid, 0: invalid. bit0->address[0], bit1->address[1], etc.*/
 142         phw_iceland_mc_reg_entry    mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
 143         SMU71_Discrete_MCRegisterAddress mc_reg_address[SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE];
 144 };
 145 typedef struct _phw_iceland_mc_reg_table phw_iceland_mc_reg_table;
 146
 147 #define DISABLE_MC_LOADMICROCODE   1
 148 #define DISABLE_MC_CFGPROGRAMMING  2
 149
 150
 151 /*Ultra Low Voltage parameter structure */
 152 struct phw_iceland_ulv_parm{
 153         bool                                    ulv_supported;
 154         uint32_t                                ch_ulv_parameter;
 155         uint32_t                                ulv_volt_change_delay;
 156         struct iceland_performance_level        ulv_power_level;
 157 };
 158
 159 #define ICELAND_MAX_LEAKAGE_COUNT  8
 160
 161 struct phw_iceland_leakage_voltage {
 162         uint16_t  count;
 163         uint16_t  leakage_id[ICELAND_MAX_LEAKAGE_COUNT];
 164         uint16_t  actual_voltage[ICELAND_MAX_LEAKAGE_COUNT];
 165 };
 166
 167 struct _phw_iceland_display_timing {
 168         uint32_t min_clock_insr;
 169         uint32_t num_existing_displays;
 170 };
 171 typedef struct _phw_iceland_display_timing phw_iceland_display_timing;
 172
 173
 174 struct phw_iceland_thermal_temperature_setting
 175 {
 176         long temperature_low;
 177         long temperature_high;
 178         long temperature_shutdown;
 179 };
 180
 181 struct _phw_iceland_dpmlevel_enable_mask {
 182         uint32_t uvd_dpm_enable_mask;
 183         uint32_t vce_dpm_enable_mask;
 184         uint32_t acp_dpm_enable_mask;
 185         uint32_t samu_dpm_enable_mask;
 186         uint32_t sclk_dpm_enable_mask;
 187         uint32_t mclk_dpm_enable_mask;
 188         uint32_t pcie_dpm_enable_mask;
 189 };
 190 typedef struct _phw_iceland_dpmlevel_enable_mask phw_iceland_dpmlevel_enable_mask;
 191
 192 struct _phw_iceland_pcie_perf_range {
 193         uint16_t max;
 194         uint16_t min;
 195 };
 196 typedef struct _phw_iceland_pcie_perf_range phw_iceland_pcie_perf_range;
 197
 198 struct _phw_iceland_vbios_boot_state {
 199         uint16_t                                        mvdd_bootup_value;
 200         uint16_t                                        vddc_bootup_value;
 201         uint16_t                                        vddci_bootup_value;
 202         uint16_t                                        vddgfx_bootup_value;
 203         uint32_t                                        sclk_bootup_value;
 204         uint32_t                                        mclk_bootup_value;
 205         uint16_t                                        pcie_gen_bootup_value;
 206         uint16_t                                        pcie_lane_bootup_value;
 207 };
 208 typedef struct _phw_iceland_vbios_boot_state phw_iceland_vbios_boot_state;
 209
 210 #define DPMTABLE_OD_UPDATE_SCLK     0x00000001
 211 #define DPMTABLE_OD_UPDATE_MCLK     0x00000002
 212 #define DPMTABLE_UPDATE_SCLK        0x00000004
 213 #define DPMTABLE_UPDATE_MCLK        0x00000008
 214
 215 /* We need to review which fields are needed. */
 216 /* This is mostly a copy of the RV7xx/Evergreen structure which is close, but not identical to the N.Islands one. */
 217 struct iceland_hwmgr {
 218         struct iceland_dpm_table               dpm_table;
 219         struct iceland_dpm_table               golden_dpm_table;
 220
 221         uint32_t                           voting_rights_clients0;
 222         uint32_t                           voting_rights_clients1;
 223         uint32_t                           voting_rights_clients2;
 224         uint32_t                           voting_rights_clients3;
 225         uint32_t                           voting_rights_clients4;
 226         uint32_t                           voting_rights_clients5;
 227         uint32_t                           voting_rights_clients6;
 228         uint32_t                           voting_rights_clients7;
 229         uint32_t                           static_screen_threshold_unit;
 230         uint32_t                           static_screen_threshold;
 231         uint32_t                           voltage_control;
 232         uint32_t                           vdd_gfx_control;
 233
 234         uint32_t                           vddc_vddci_delta;
 235         uint32_t                           vddc_vddgfx_delta;
 236
 237         struct pp_interrupt_registration_info    internal_high_thermal_interrupt_info;
 238         struct pp_interrupt_registration_info    internal_low_thermal_interrupt_info;
 239         struct pp_interrupt_registration_info    smc_to_host_interrupt_info;
 240         uint32_t                          active_auto_throttle_sources;
 241
 242         struct pp_interrupt_registration_info    external_throttle_interrupt;
 243         irq_handler_func_t             external_throttle_callback;
 244         void                             *external_throttle_context;
 245
 246         struct pp_interrupt_registration_info    ctf_interrupt_info;
 247         irq_handler_func_t             ctf_callback;
 248         void                             *ctf_context;
 249
 250         phw_iceland_clock_registers       clock_registers;
 251         phw_iceland_voltage_smio_registers  voltage_smio_registers;
 252
 253         bool    is_memory_GDDR5;
 254         uint16_t                          acpi_vddc;
 255         bool    pspp_notify_required;        /* Flag to indicate if PSPP notification to SBIOS is required */
 256         uint16_t                          force_pcie_gen;            /* The forced PCI-E speed if not 0xffff */
 257         uint16_t                          acpi_pcie_gen;             /* The PCI-E speed at ACPI time */
 258         uint32_t                           pcie_gen_cap;             /* The PCI-E speed capabilities bitmap from CAIL */
 259         uint32_t                           pcie_lane_cap;            /* The PCI-E lane capabilities bitmap from CAIL */
 260         uint32_t                           pcie_spc_cap;             /* Symbol Per Clock Capabilities from registry */
 261         struct phw_iceland_leakage_voltage      vddc_leakage;        /* The Leakage VDDC supported (based on leakage ID).*/
 262         struct phw_iceland_leakage_voltage      vddcgfx_leakage;     /* The Leakage VDDC supported (based on leakage ID). */
 263         struct phw_iceland_leakage_voltage      vddci_leakage;       /* The Leakage VDDCI supported (based on leakage ID). */
 264
 265         uint32_t                           mvdd_control;
 266         uint32_t                           vddc_mask_low;
 267         uint32_t                           mvdd_mask_low;
 268         uint16_t                          max_vddc_in_pp_table;        /* the maximum VDDC value in the powerplay table*/
 269         uint16_t                          min_vddc_in_pp_table;
 270         uint16_t                          max_vddci_in_pp_table;       /* the maximum VDDCI value in the powerplay table */
 271         uint16_t                          min_vddci_in_pp_table;
 272         uint32_t                           mclk_strobe_mode_threshold;
 273         uint32_t                           mclk_stutter_mode_threshold;
 274         uint32_t                           mclk_edc_enable_threshold;
 275         uint32_t                           mclk_edc_wr_enable_threshold;
 276         bool    is_uvd_enabled;
 277         bool    is_xdma_enabled;
 278         phw_iceland_vbios_boot_state      vbios_boot_state;
 279
 280         bool                         battery_state;
 281         bool                         is_tlu_enabled;
 282         bool                         pcie_performance_request;
 283
 284         /* -------------- SMC SRAM Address of firmware header tables ----------------*/
 285         uint32_t                        sram_end;           /* The first address after the SMC SRAM. */
 286         uint32_t                        dpm_table_start;    /* The start of the dpm table in the SMC SRAM. */
 287         uint32_t                        soft_regs_start;    /* The start of the soft registers in the SMC SRAM. */
 288         uint32_t                        mc_reg_table_start; /* The start of the mc register table in the SMC SRAM. */
 289         uint32_t                        fan_table_start;    /* The start of the fan table in the SMC SRAM. */
 290         uint32_t                        arb_table_start;    /* The start of the ARB setting table in the SMC SRAM. */
 291         uint32_t                        ulv_settings_start;
 292         SMU71_Discrete_DpmTable         smc_state_table;    /* The carbon copy of the SMC state table. */
 293         SMU71_Discrete_MCRegisters      mc_reg_table;
 294         SMU71_Discrete_Ulv              ulv_setting;         /* The carbon copy of ULV setting. */
 295
 296         /* -------------- Stuff originally coming from Evergreen --------------------*/
 297         phw_iceland_mc_reg_table         iceland_mc_reg_table;
 298         uint32_t                         vdd_ci_control;
 299         pp_atomctrl_voltage_table        vddc_voltage_table;
 300         pp_atomctrl_voltage_table        vddci_voltage_table;
 301         pp_atomctrl_voltage_table        vddgfx_voltage_table;
 302         pp_atomctrl_voltage_table        mvdd_voltage_table;
 303
 304         uint32_t                           mgcg_cgtt_local2;
 305         uint32_t                           mgcg_cgtt_local3;
 306         uint32_t                           gpio_debug;
 307         uint32_t                        mc_micro_code_feature;
 308         uint32_t                        highest_mclk;
 309         uint16_t                          acpi_vdd_ci;
 310         uint8_t                           mvdd_high_index;
 311         uint8_t                           mvdd_low_index;
 312         bool                         dll_defaule_on;
 313         bool                         performance_request_registered;
 314
 315         /* ----------------- Low Power Features ---------------------*/
 316         phw_iceland_bacos                                       bacos;
 317         struct phw_iceland_ulv_parm                     ulv;
 318
 319         /* ----------------- CAC Stuff ---------------------*/
 320         uint32_t                                        cac_table_start;
 321         bool                         cac_configuration_required;    /* TRUE if PP_CACConfigurationRequired == 1 */
 322         bool                         driver_calculate_cac_leakage;  /* TRUE if PP_DriverCalculateCACLeakage == 1 */
 323         bool                         cac_enabled;
 324
 325         /* ----------------- DPM2 Parameters ---------------------*/
 326         uint32_t                power_containment_features;
 327         bool                         enable_bapm_feature;
 328         bool                         enable_dte_feature;
 329         bool                         enable_tdc_limit_feature;
 330         bool                         enable_pkg_pwr_tracking_feature;
 331         bool                         disable_uvd_power_tune_feature;
 332         struct iceland_pt_defaults           *power_tune_defaults;
 333         SMU71_Discrete_PmFuses           power_tune_table;
 334         uint32_t                           ul_dte_tj_offset;     /* Fudge factor in DPM table to correct HW DTE errors */
 335         uint32_t                           fast_watermark_threshold;  /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
 336
 337         /* ----------------- Phase Shedding ---------------------*/
 338         bool                         vddc_phase_shed_control;
 339
 340         /* --------------------- DI/DT --------------------------*/
 341         phw_iceland_display_timing       display_timing;
 342
 343         /* --------- ReadRegistry data for memory and engine clock margins ---- */
 344         uint32_t                           engine_clock_data;
 345         uint32_t                           memory_clock_data;
 346
 347         /* -------- Thermal Temperature Setting --------------*/
 348         struct phw_iceland_thermal_temperature_setting  thermal_temp_setting;
 349         phw_iceland_dpmlevel_enable_mask     dpm_level_enable_mask;
 350
 351         uint32_t                                need_update_smu7_dpm_table;
 352         uint32_t                                sclk_dpm_key_disabled;
 353         uint32_t                                mclk_dpm_key_disabled;
 354         uint32_t                                pcie_dpm_key_disabled;
 355         /* used to store the previous dal min sclock */
 356         uint32_t                           min_engine_clocks;
 357         phw_iceland_pcie_perf_range       pcie_gen_performance;
 358         phw_iceland_pcie_perf_range       pcie_lane_performance;
 359         phw_iceland_pcie_perf_range       pcie_gen_power_saving;
 360         phw_iceland_pcie_perf_range       pcie_lane_power_saving;
 361         bool                            use_pcie_performance_levels;
 362         bool                            use_pcie_power_saving_levels;
 363         /* percentage value from 0-100, default 50 */
 364         uint32_t                           activity_target[SMU71_MAX_LEVELS_GRAPHICS];
 365         uint32_t                           mclk_activity_target;
 366         uint32_t                           low_sclk_interrupt_threshold;
 367         uint32_t                           last_mclk_dpm_enable_mask;
 368         bool                                                            uvd_enabled;
 369         uint32_t                           pcc_monitor_enabled;
 370
 371         /* --------- Power Gating States ------------*/
 372         bool                           uvd_power_gated;  /* 1: gated, 0:not gated */
 373         bool                           vce_power_gated;  /* 1: gated, 0:not gated */
 374         bool                           samu_power_gated; /* 1: gated, 0:not gated */
 375         bool                           acp_power_gated;  /* 1: gated, 0:not gated */
 376         bool                           pg_acp_init;
 377
 378         /* soft pptable for re-uploading into smu */
 379         void *soft_pp_table;
 380 };
 381
 382 typedef struct iceland_hwmgr iceland_hwmgr;
 383
 384 int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);
 385 int iceland_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
 386 uint32_t iceland_get_xclk(struct pp_hwmgr *hwmgr);
 387 int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr);
 388 int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr);
 389
 390 #define ICELAND_DPM2_NEAR_TDP_DEC          10
 391 #define ICELAND_DPM2_ABOVE_SAFE_INC        5
 392 #define ICELAND_DPM2_BELOW_SAFE_INC        20
 393
 394 /*
 395  * Log2 of the LTA window size (l2numWin_TDP). Eg. If LTA windows size
 396  * is 128, then this value should be Log2(128) = 7.
 397  */
 398 #define ICELAND_DPM2_LTA_WINDOW_SIZE       7
 399
 400 #define ICELAND_DPM2_LTS_TRUNCATE          0
 401
 402 #define ICELAND_DPM2_TDP_SAFE_LIMIT_PERCENT            80  // Maximum 100
 403
 404 #define ICELAND_DPM2_MAXPS_PERCENT_H                   90  // Maximum 0xFF
 405 #define ICELAND_DPM2_MAXPS_PERCENT_M                   90  // Maximum 0xFF
 406
 407 #define ICELAND_DPM2_PWREFFICIENCYRATIO_MARGIN         50
 408
 409 #define ICELAND_DPM2_SQ_RAMP_MAX_POWER                 0x3FFF
 410 #define ICELAND_DPM2_SQ_RAMP_MIN_POWER                 0x12
 411 #define ICELAND_DPM2_SQ_RAMP_MAX_POWER_DELTA           0x15
 412 #define ICELAND_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE  0x1E
 413 #define ICELAND_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO  0xF
 414
 415 #define ICELAND_VOLTAGE_CONTROL_NONE                   0x0
 416 #define ICELAND_VOLTAGE_CONTROL_BY_GPIO                0x1
 417 #define ICELAND_VOLTAGE_CONTROL_BY_SVID2               0x2
 418
 419 /* convert to Q8.8 format for firmware */
 420 #define ICELAND_Q88_FORMAT_CONVERSION_UNIT             256
 421
 422 #define ICELAND_UNUSED_GPIO_PIN 0x7F
 423
 424 #endif