2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef _AMD_POWERPLAY_H_
24 #define _AMD_POWERPLAY_H_
26 #include <linux/seq_file.h>
27 #include <linux/types.h>
28 #include "amd_shared.h"
29 #include "cgs_common.h"
32 AMD_PP_EVENT_INITIALIZE
= 0,
33 AMD_PP_EVENT_UNINITIALIZE
,
34 AMD_PP_EVENT_POWER_SOURCE_CHANGE
,
37 AMD_PP_EVENT_ENTER_REST_STATE
,
38 AMD_PP_EVENT_EXIT_REST_STATE
,
39 AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE
,
40 AMD_PP_EVENT_THERMAL_NOTIFICATION
,
41 AMD_PP_EVENT_VBIOS_NOTIFICATION
,
42 AMD_PP_EVENT_ENTER_THERMAL_STATE
,
43 AMD_PP_EVENT_EXIT_THERMAL_STATE
,
44 AMD_PP_EVENT_ENTER_FORCED_STATE
,
45 AMD_PP_EVENT_EXIT_FORCED_STATE
,
46 AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE
,
47 AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE
,
48 AMD_PP_EVENT_ENTER_SCREEN_SAVER
,
49 AMD_PP_EVENT_EXIT_SCREEN_SAVER
,
50 AMD_PP_EVENT_VPU_RECOVERY_BEGIN
,
51 AMD_PP_EVENT_VPU_RECOVERY_END
,
52 AMD_PP_EVENT_ENABLE_POWER_PLAY
,
53 AMD_PP_EVENT_DISABLE_POWER_PLAY
,
54 AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL
,
55 AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE
,
56 AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE
,
57 AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE
,
58 AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE
,
59 AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST
,
60 AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST
,
61 AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE
,
62 AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE
,
63 AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING
,
64 AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING
,
65 AMD_PP_EVENT_ENABLE_CGPG
,
66 AMD_PP_EVENT_DISABLE_CGPG
,
67 AMD_PP_EVENT_ENTER_TEXT_MODE
,
68 AMD_PP_EVENT_EXIT_TEXT_MODE
,
69 AMD_PP_EVENT_VIDEO_START
,
70 AMD_PP_EVENT_VIDEO_STOP
,
71 AMD_PP_EVENT_ENABLE_USER_STATE
,
72 AMD_PP_EVENT_DISABLE_USER_STATE
,
73 AMD_PP_EVENT_READJUST_POWER_STATE
,
74 AMD_PP_EVENT_START_INACTIVITY
,
75 AMD_PP_EVENT_STOP_INACTIVITY
,
76 AMD_PP_EVENT_LINKED_ADAPTERS_READY
,
77 AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE
,
78 AMD_PP_EVENT_COMPLETE_INIT
,
79 AMD_PP_EVENT_CRITICAL_THERMAL_FAULT
,
80 AMD_PP_EVENT_BACKLIGHT_CHANGED
,
81 AMD_PP_EVENT_ENABLE_VARI_BRIGHT
,
82 AMD_PP_EVENT_DISABLE_VARI_BRIGHT
,
83 AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS
,
84 AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS
,
85 AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL
,
86 AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT
,
87 AMD_PP_EVENT_SCREEN_ON
,
88 AMD_PP_EVENT_SCREEN_OFF
,
89 AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE
,
90 AMD_PP_EVENT_ENTER_ULP_STATE
,
91 AMD_PP_EVENT_EXIT_ULP_STATE
,
92 AMD_PP_EVENT_REGISTER_IP_STATE
,
93 AMD_PP_EVENT_UNREGISTER_IP_STATE
,
94 AMD_PP_EVENT_ENTER_MGPU_MODE
,
95 AMD_PP_EVENT_EXIT_MGPU_MODE
,
96 AMD_PP_EVENT_ENTER_MULTI_GPU_MODE
,
97 AMD_PP_EVENT_PRE_SUSPEND
,
98 AMD_PP_EVENT_PRE_RESUME
,
99 AMD_PP_EVENT_ENTER_BACOS
,
100 AMD_PP_EVENT_EXIT_BACOS
,
101 AMD_PP_EVENT_RESUME_BACO
,
102 AMD_PP_EVENT_RESET_BACO
,
103 AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS
,
104 AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS
,
105 AMD_PP_EVENT_START_COMPUTE_APPLICATION
,
106 AMD_PP_EVENT_STOP_COMPUTE_APPLICATION
,
107 AMD_PP_EVENT_REDUCE_POWER_LIMIT
,
108 AMD_PP_EVENT_ENTER_FRAME_LOCK
,
109 AMD_PP_EVENT_EXIT_FRAME_LOOCK
,
110 AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO
,
111 AMD_PP_EVENT_LONG_IDLE_ENTER_BACO
,
112 AMD_PP_EVENT_LONG_IDLE_EXIT_BACO
,
113 AMD_PP_EVENT_HIBERNATE
,
114 AMD_PP_EVENT_CONNECTED_STANDBY
,
115 AMD_PP_EVENT_ENTER_SELF_REFRESH
,
116 AMD_PP_EVENT_EXIT_SELF_REFRESH
,
117 AMD_PP_EVENT_START_AVFS_BTC
,
121 enum amd_dpm_forced_level
{
122 AMD_DPM_FORCED_LEVEL_AUTO
= 0,
123 AMD_DPM_FORCED_LEVEL_LOW
= 1,
124 AMD_DPM_FORCED_LEVEL_HIGH
= 2,
128 struct cgs_device
*device
;
129 uint32_t chip_family
;
134 struct amd_pp_display_configuration
{
135 bool nb_pstate_switch_disable
;/* controls NB PState switch */
136 bool cpu_cc6_disable
; /* controls CPU CState switch ( on or off) */
137 bool cpu_pstate_disable
;
138 uint32_t cpu_pstate_separation_time
;
141 struct amd_pp_dal_clock_info
{
142 uint32_t engine_max_clock
;
143 uint32_t memory_max_clock
;
148 PP_GROUP_UNKNOWN
= 0,
154 #define PP_GROUP_MASK 0xF0000000
155 #define PP_GROUP_SHIFT 28
157 #define PP_BLOCK_MASK 0x0FFFFF00
158 #define PP_BLOCK_SHIFT 8
160 #define PP_BLOCK_GFX_CG 0x01
161 #define PP_BLOCK_GFX_MG 0x02
162 #define PP_BLOCK_SYS_BIF 0x01
163 #define PP_BLOCK_SYS_MC 0x02
164 #define PP_BLOCK_SYS_ROM 0x04
165 #define PP_BLOCK_SYS_DRM 0x08
166 #define PP_BLOCK_SYS_HDP 0x10
167 #define PP_BLOCK_SYS_SDMA 0x20
169 #define PP_STATE_MASK 0x0000000F
170 #define PP_STATE_SHIFT 0
171 #define PP_STATE_SUPPORT_MASK 0x000000F0
172 #define PP_STATE_SUPPORT_SHIFT 0
174 #define PP_STATE_CG 0x01
175 #define PP_STATE_LS 0x02
176 #define PP_STATE_DS 0x04
177 #define PP_STATE_SD 0x08
178 #define PP_STATE_SUPPORT_CG 0x10
179 #define PP_STATE_SUPPORT_LS 0x20
180 #define PP_STATE_SUPPORT_DS 0x40
181 #define PP_STATE_SUPPORT_SD 0x80
183 #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
184 block << PP_BLOCK_SHIFT |\
185 support << PP_STATE_SUPPORT_SHIFT |\
186 state << PP_STATE_SHIFT)
188 struct amd_powerplay_funcs
{
189 int (*get_temperature
)(void *handle
);
190 int (*load_firmware
)(void *handle
);
191 int (*wait_for_fw_loading_complete
)(void *handle
);
192 int (*force_performance_level
)(void *handle
, enum amd_dpm_forced_level level
);
193 enum amd_dpm_forced_level (*get_performance_level
)(void *handle
);
194 enum amd_pm_state_type (*get_current_power_state
)(void *handle
);
195 int (*get_sclk
)(void *handle
, bool low
);
196 int (*get_mclk
)(void *handle
, bool low
);
197 int (*powergate_vce
)(void *handle
, bool gate
);
198 int (*powergate_uvd
)(void *handle
, bool gate
);
199 int (*dispatch_tasks
)(void *handle
, enum amd_pp_event event_id
,
200 void *input
, void *output
);
201 void (*print_current_performance_level
)(void *handle
,
203 int (*set_fan_control_mode
)(void *handle
, uint32_t mode
);
204 int (*get_fan_control_mode
)(void *handle
);
205 int (*set_fan_speed_percent
)(void *handle
, uint32_t percent
);
206 int (*get_fan_speed_percent
)(void *handle
, uint32_t *speed
);
209 struct amd_powerplay
{
211 const struct amd_ip_funcs
*ip_funcs
;
212 const struct amd_powerplay_funcs
*pp_funcs
;
215 int amd_powerplay_init(struct amd_pp_init
*pp_init
,
216 struct amd_powerplay
*amd_pp
);
217 int amd_powerplay_fini(void *handle
);
219 int amd_powerplay_display_configuration_change(void *handle
, const void *input
);
221 int amd_powerplay_get_display_power_level(void *handle
, void *output
);
224 #endif /* _AMD_POWERPLAY_H_ */