drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #ifndef _AMD_POWERPLAY_H_
  24 #define _AMD_POWERPLAY_H_
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include "amd_shared.h"
  30 #include "cgs_common.h"
  31
  32
  33 enum amd_pp_event {
  34         AMD_PP_EVENT_INITIALIZE = 0,
  35         AMD_PP_EVENT_UNINITIALIZE,
  36         AMD_PP_EVENT_POWER_SOURCE_CHANGE,
  37         AMD_PP_EVENT_SUSPEND,
  38         AMD_PP_EVENT_RESUME,
  39         AMD_PP_EVENT_ENTER_REST_STATE,
  40         AMD_PP_EVENT_EXIT_REST_STATE,
  41         AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
  42         AMD_PP_EVENT_THERMAL_NOTIFICATION,
  43         AMD_PP_EVENT_VBIOS_NOTIFICATION,
  44         AMD_PP_EVENT_ENTER_THERMAL_STATE,
  45         AMD_PP_EVENT_EXIT_THERMAL_STATE,
  46         AMD_PP_EVENT_ENTER_FORCED_STATE,
  47         AMD_PP_EVENT_EXIT_FORCED_STATE,
  48         AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
  49         AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
  50         AMD_PP_EVENT_ENTER_SCREEN_SAVER,
  51         AMD_PP_EVENT_EXIT_SCREEN_SAVER,
  52         AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
  53         AMD_PP_EVENT_VPU_RECOVERY_END,
  54         AMD_PP_EVENT_ENABLE_POWER_PLAY,
  55         AMD_PP_EVENT_DISABLE_POWER_PLAY,
  56         AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
  57         AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
  58         AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
  59         AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
  60         AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
  61         AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
  62         AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
  63         AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
  64         AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
  65         AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
  66         AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
  67         AMD_PP_EVENT_ENABLE_CGPG,
  68         AMD_PP_EVENT_DISABLE_CGPG,
  69         AMD_PP_EVENT_ENTER_TEXT_MODE,
  70         AMD_PP_EVENT_EXIT_TEXT_MODE,
  71         AMD_PP_EVENT_VIDEO_START,
  72         AMD_PP_EVENT_VIDEO_STOP,
  73         AMD_PP_EVENT_ENABLE_USER_STATE,
  74         AMD_PP_EVENT_DISABLE_USER_STATE,
  75         AMD_PP_EVENT_READJUST_POWER_STATE,
  76         AMD_PP_EVENT_START_INACTIVITY,
  77         AMD_PP_EVENT_STOP_INACTIVITY,
  78         AMD_PP_EVENT_LINKED_ADAPTERS_READY,
  79         AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
  80         AMD_PP_EVENT_COMPLETE_INIT,
  81         AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
  82         AMD_PP_EVENT_BACKLIGHT_CHANGED,
  83         AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
  84         AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
  85         AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
  86         AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
  87         AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
  88         AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
  89         AMD_PP_EVENT_SCREEN_ON,
  90         AMD_PP_EVENT_SCREEN_OFF,
  91         AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
  92         AMD_PP_EVENT_ENTER_ULP_STATE,
  93         AMD_PP_EVENT_EXIT_ULP_STATE,
  94         AMD_PP_EVENT_REGISTER_IP_STATE,
  95         AMD_PP_EVENT_UNREGISTER_IP_STATE,
  96         AMD_PP_EVENT_ENTER_MGPU_MODE,
  97         AMD_PP_EVENT_EXIT_MGPU_MODE,
  98         AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
  99         AMD_PP_EVENT_PRE_SUSPEND,
 100         AMD_PP_EVENT_PRE_RESUME,
 101         AMD_PP_EVENT_ENTER_BACOS,
 102         AMD_PP_EVENT_EXIT_BACOS,
 103         AMD_PP_EVENT_RESUME_BACO,
 104         AMD_PP_EVENT_RESET_BACO,
 105         AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
 106         AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
 107         AMD_PP_EVENT_START_COMPUTE_APPLICATION,
 108         AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
 109         AMD_PP_EVENT_REDUCE_POWER_LIMIT,
 110         AMD_PP_EVENT_ENTER_FRAME_LOCK,
 111         AMD_PP_EVENT_EXIT_FRAME_LOOCK,
 112         AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
 113         AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
 114         AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
 115         AMD_PP_EVENT_HIBERNATE,
 116         AMD_PP_EVENT_CONNECTED_STANDBY,
 117         AMD_PP_EVENT_ENTER_SELF_REFRESH,
 118         AMD_PP_EVENT_EXIT_SELF_REFRESH,
 119         AMD_PP_EVENT_START_AVFS_BTC,
 120         AMD_PP_EVENT_MAX
 121 };
 122
 123 enum amd_dpm_forced_level {
 124         AMD_DPM_FORCED_LEVEL_AUTO = 0,
 125         AMD_DPM_FORCED_LEVEL_LOW = 1,
 126         AMD_DPM_FORCED_LEVEL_HIGH = 2,
 127         AMD_DPM_FORCED_LEVEL_MANUAL = 3,
 128 };
 129
 130 struct amd_pp_init {
 131         struct cgs_device *device;
 132         uint32_t chip_family;
 133         uint32_t chip_id;
 134         uint32_t rev_id;
 135         uint16_t sub_sys_id;
 136         uint16_t sub_vendor_id;
 137 };
 138
 139 enum amd_pp_display_config_type{
 140         AMD_PP_DisplayConfigType_None = 0,
 141         AMD_PP_DisplayConfigType_DP54 ,
 142         AMD_PP_DisplayConfigType_DP432 ,
 143         AMD_PP_DisplayConfigType_DP324 ,
 144         AMD_PP_DisplayConfigType_DP27,
 145         AMD_PP_DisplayConfigType_DP243,
 146         AMD_PP_DisplayConfigType_DP216,
 147         AMD_PP_DisplayConfigType_DP162,
 148         AMD_PP_DisplayConfigType_HDMI6G ,
 149         AMD_PP_DisplayConfigType_HDMI297 ,
 150         AMD_PP_DisplayConfigType_HDMI162,
 151         AMD_PP_DisplayConfigType_LVDS,
 152         AMD_PP_DisplayConfigType_DVI,
 153         AMD_PP_DisplayConfigType_WIRELESS,
 154         AMD_PP_DisplayConfigType_VGA
 155 };
 156
 157 struct single_display_configuration
 158 {
 159         uint32_t controller_index;
 160         uint32_t controller_id;
 161         uint32_t signal_type;
 162         uint32_t display_state;
 163         /* phy id for the primary internal transmitter */
 164         uint8_t primary_transmitter_phyi_d;
 165         /* bitmap with the active lanes */
 166         uint8_t primary_transmitter_active_lanemap;
 167         /* phy id for the secondary internal transmitter (for dual-link dvi) */
 168         uint8_t secondary_transmitter_phy_id;
 169         /* bitmap with the active lanes */
 170         uint8_t secondary_transmitter_active_lanemap;
 171         /* misc phy settings for SMU. */
 172         uint32_t config_flags;
 173         uint32_t display_type;
 174         uint32_t view_resolution_cx;
 175         uint32_t view_resolution_cy;
 176         enum amd_pp_display_config_type displayconfigtype;
 177         uint32_t vertical_refresh; /* for active display */
 178 };
 179
 180 #define MAX_NUM_DISPLAY 32
 181
 182 struct amd_pp_display_configuration {
 183         bool nb_pstate_switch_disable;/* controls NB PState switch */
 184         bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
 185         bool cpu_pstate_disable;
 186         uint32_t cpu_pstate_separation_time;
 187
 188         uint32_t num_display;  /* total number of display*/
 189         uint32_t num_path_including_non_display;
 190         uint32_t crossfire_display_index;
 191         uint32_t min_mem_set_clock;
 192         uint32_t min_core_set_clock;
 193         /* unit 10KHz x bit*/
 194         uint32_t min_bus_bandwidth;
 195         /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
 196         uint32_t min_core_set_clock_in_sr;
 197
 198         struct single_display_configuration displays[MAX_NUM_DISPLAY];
 199
 200         uint32_t vrefresh; /* for active display*/
 201
 202         uint32_t min_vblank_time; /* for active display*/
 203         bool multi_monitor_in_sync;
 204         /* Controller Index of primary display - used in MCLK SMC switching hang
 205          * SW Workaround*/
 206         uint32_t crtc_index;
 207         /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
 208         uint32_t line_time_in_us;
 209         bool invalid_vblank_time;
 210
 211         uint32_t display_clk;
 212         /*
 213          * for given display configuration if multimonitormnsync == false then
 214          * Memory clock DPMS with this latency or below is allowed, DPMS with
 215          * higher latency not allowed.
 216          */
 217         uint32_t dce_tolerable_mclk_in_active_latency;
 218 };
 219
 220 struct amd_pp_simple_clock_info {
 221         uint32_t        engine_max_clock;
 222         uint32_t        memory_max_clock;
 223         uint32_t        level;
 224 };
 225
 226 enum PP_DAL_POWERLEVEL {
 227         PP_DAL_POWERLEVEL_INVALID = 0,
 228         PP_DAL_POWERLEVEL_ULTRALOW,
 229         PP_DAL_POWERLEVEL_LOW,
 230         PP_DAL_POWERLEVEL_NOMINAL,
 231         PP_DAL_POWERLEVEL_PERFORMANCE,
 232
 233         PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
 234         PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
 235         PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
 236         PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
 237         PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
 238         PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
 239         PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
 240         PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
 241 };
 242
 243 struct amd_pp_clock_info {
 244         uint32_t min_engine_clock;
 245         uint32_t max_engine_clock;
 246         uint32_t min_memory_clock;
 247         uint32_t max_memory_clock;
 248         uint32_t min_bus_bandwidth;
 249         uint32_t max_bus_bandwidth;
 250         uint32_t max_engine_clock_in_sr;
 251         uint32_t min_engine_clock_in_sr;
 252         enum PP_DAL_POWERLEVEL max_clocks_state;
 253 };
 254
 255 enum amd_pp_clock_type {
 256         amd_pp_disp_clock = 1,
 257         amd_pp_sys_clock,
 258         amd_pp_mem_clock
 259 };
 260
 261 #define MAX_NUM_CLOCKS 16
 262
 263 struct amd_pp_clocks {
 264         uint32_t count;
 265         uint32_t clock[MAX_NUM_CLOCKS];
 266 };
 267
 268
 269 enum {
 270         PP_GROUP_UNKNOWN = 0,
 271         PP_GROUP_GFX = 1,
 272         PP_GROUP_SYS,
 273         PP_GROUP_MAX
 274 };
 275
 276 enum pp_clock_type {
 277         PP_SCLK,
 278         PP_MCLK,
 279         PP_PCIE,
 280 };
 281
 282 struct pp_states_info {
 283         uint32_t nums;
 284         uint32_t states[16];
 285 };
 286
 287 #define PP_GROUP_MASK        0xF0000000
 288 #define PP_GROUP_SHIFT       28
 289
 290 #define PP_BLOCK_MASK        0x0FFFFF00
 291 #define PP_BLOCK_SHIFT       8
 292
 293 #define PP_BLOCK_GFX_CG         0x01
 294 #define PP_BLOCK_GFX_MG         0x02
 295 #define PP_BLOCK_GFX_3D         0x04
 296 #define PP_BLOCK_GFX_RLC        0x08
 297 #define PP_BLOCK_GFX_CP         0x10
 298 #define PP_BLOCK_SYS_BIF        0x01
 299 #define PP_BLOCK_SYS_MC         0x02
 300 #define PP_BLOCK_SYS_ROM        0x04
 301 #define PP_BLOCK_SYS_DRM        0x08
 302 #define PP_BLOCK_SYS_HDP        0x10
 303 #define PP_BLOCK_SYS_SDMA       0x20
 304
 305 #define PP_STATE_MASK           0x0000000F
 306 #define PP_STATE_SHIFT          0
 307 #define PP_STATE_SUPPORT_MASK   0x000000F0
 308 #define PP_STATE_SUPPORT_SHIFT  0
 309
 310 #define PP_STATE_CG             0x01
 311 #define PP_STATE_LS             0x02
 312 #define PP_STATE_DS             0x04
 313 #define PP_STATE_SD             0x08
 314 #define PP_STATE_SUPPORT_CG     0x10
 315 #define PP_STATE_SUPPORT_LS     0x20
 316 #define PP_STATE_SUPPORT_DS     0x40
 317 #define PP_STATE_SUPPORT_SD     0x80
 318
 319 #define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
 320                                                                 block << PP_BLOCK_SHIFT |\
 321                                                                 support << PP_STATE_SUPPORT_SHIFT |\
 322                                                                 state << PP_STATE_SHIFT)
 323
 324 struct amd_powerplay_funcs {
 325         int (*get_temperature)(void *handle);
 326         int (*load_firmware)(void *handle);
 327         int (*wait_for_fw_loading_complete)(void *handle);
 328         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 329         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 330         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 331         int (*get_sclk)(void *handle, bool low);
 332         int (*get_mclk)(void *handle, bool low);
 333         int (*powergate_vce)(void *handle, bool gate);
 334         int (*powergate_uvd)(void *handle, bool gate);
 335         int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
 336                                    void *input, void *output);
 337         void (*print_current_performance_level)(void *handle,
 338                                                       struct seq_file *m);
 339         int (*set_fan_control_mode)(void *handle, uint32_t mode);
 340         int (*get_fan_control_mode)(void *handle);
 341         int (*set_fan_speed_percent)(void *handle, uint32_t percent);
 342         int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
 343         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 344         int (*get_pp_table)(void *handle, char **table);
 345         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 346         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 347         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 348         int (*get_sclk_od)(void *handle);
 349         int (*set_sclk_od)(void *handle, uint32_t value);
 350         int (*get_mclk_od)(void *handle);
 351         int (*set_mclk_od)(void *handle, uint32_t value);
 352 };
 353
 354 struct amd_powerplay {
 355         void *pp_handle;
 356         const struct amd_ip_funcs *ip_funcs;
 357         const struct amd_powerplay_funcs *pp_funcs;
 358 };
 359
 360 int amd_powerplay_init(struct amd_pp_init *pp_init,
 361                        struct amd_powerplay *amd_pp);
 362
 363 int amd_powerplay_fini(void *handle);
 364
 365 int amd_powerplay_reset(void *handle);
 366
 367 int amd_powerplay_display_configuration_change(void *handle,
 368                 const struct amd_pp_display_configuration *input);
 369
 370 int amd_powerplay_get_display_power_level(void *handle,
 371                 struct amd_pp_simple_clock_info *output);
 372
 373 int amd_powerplay_get_current_clocks(void *handle,
 374                 struct amd_pp_clock_info *output);
 375
 376 int amd_powerplay_get_clock_by_type(void *handle,
 377                 enum amd_pp_clock_type type,
 378                 struct amd_pp_clocks *clocks);
 379
 380 int amd_powerplay_get_display_mode_validation_clocks(void *handle,
 381                 struct amd_pp_simple_clock_info *output);
 382
 383 #endif /* _AMD_POWERPLAY_H_ */