drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.h

   1 /*
   2  * Copyright (C) 2014 Free Electrons
   3  * Copyright (C) 2014 Atmel
   4  *
   5  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef DRM_ATMEL_HLCDC_LAYER_H
  21 #define DRM_ATMEL_HLCDC_LAYER_H
  22
  23 #include <linux/mfd/atmel-hlcdc.h>
  24
  25 #include <drm/drm_crtc.h>
  26 #include <drm/drm_flip_work.h>
  27 #include <drm/drmP.h>
  28
  29 #define ATMEL_HLCDC_LAYER_CHER                  0x0
  30 #define ATMEL_HLCDC_LAYER_CHDR                  0x4
  31 #define ATMEL_HLCDC_LAYER_CHSR                  0x8
  32 #define ATMEL_HLCDC_LAYER_DMA_CHAN              BIT(0)
  33 #define ATMEL_HLCDC_LAYER_UPDATE                BIT(1)
  34 #define ATMEL_HLCDC_LAYER_A2Q                   BIT(2)
  35 #define ATMEL_HLCDC_LAYER_RST                   BIT(8)
  36
  37 #define ATMEL_HLCDC_LAYER_IER                   0xc
  38 #define ATMEL_HLCDC_LAYER_IDR                   0x10
  39 #define ATMEL_HLCDC_LAYER_IMR                   0x14
  40 #define ATMEL_HLCDC_LAYER_ISR                   0x18
  41 #define ATMEL_HLCDC_LAYER_DFETCH                BIT(0)
  42 #define ATMEL_HLCDC_LAYER_LFETCH                BIT(1)
  43 #define ATMEL_HLCDC_LAYER_DMA_IRQ               BIT(2)
  44 #define ATMEL_HLCDC_LAYER_DSCR_IRQ              BIT(3)
  45 #define ATMEL_HLCDC_LAYER_ADD_IRQ               BIT(4)
  46 #define ATMEL_HLCDC_LAYER_DONE_IRQ              BIT(5)
  47 #define ATMEL_HLCDC_LAYER_OVR_IRQ               BIT(6)
  48
  49 #define ATMEL_HLCDC_LAYER_PLANE_HEAD(n)         (((n) * 0x10) + 0x1c)
  50 #define ATMEL_HLCDC_LAYER_PLANE_ADDR(n)         (((n) * 0x10) + 0x20)
  51 #define ATMEL_HLCDC_LAYER_PLANE_CTRL(n)         (((n) * 0x10) + 0x24)
  52 #define ATMEL_HLCDC_LAYER_PLANE_NEXT(n)         (((n) * 0x10) + 0x28)
  53 #define ATMEL_HLCDC_LAYER_CFG(p, c)             (((c) * 4) + ((p)->max_planes * 0x10) + 0x1c)
  54
  55 #define ATMEL_HLCDC_LAYER_DMA_CFG_ID            0
  56 #define ATMEL_HLCDC_LAYER_DMA_CFG(p)            ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_DMA_CFG_ID)
  57 #define ATMEL_HLCDC_LAYER_DMA_SIF               BIT(0)
  58 #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK         GENMASK(5, 4)
  59 #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE       (0 << 4)
  60 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4        (1 << 4)
  61 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8        (2 << 4)
  62 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16       (3 << 4)
  63 #define ATMEL_HLCDC_LAYER_DMA_DLBO              BIT(8)
  64 #define ATMEL_HLCDC_LAYER_DMA_ROTDIS            BIT(12)
  65 #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS           BIT(13)
  66
  67 #define ATMEL_HLCDC_LAYER_FORMAT_CFG_ID         1
  68 #define ATMEL_HLCDC_LAYER_FORMAT_CFG(p)         ATMEL_HLCDC_LAYER_CFG(p, ATMEL_HLCDC_LAYER_FORMAT_CFG_ID)
  69 #define ATMEL_HLCDC_LAYER_RGB                   (0 << 0)
  70 #define ATMEL_HLCDC_LAYER_CLUT                  (1 << 0)
  71 #define ATMEL_HLCDC_LAYER_YUV                   (2 << 0)
  72 #define ATMEL_HLCDC_RGB_MODE(m)                 (((m) & 0xf) << 4)
  73 #define ATMEL_HLCDC_CLUT_MODE(m)                (((m) & 0x3) << 8)
  74 #define ATMEL_HLCDC_YUV_MODE(m)                 (((m) & 0xf) << 12)
  75 #define ATMEL_HLCDC_YUV422ROT                   BIT(16)
  76 #define ATMEL_HLCDC_YUV422SWP                   BIT(17)
  77 #define ATMEL_HLCDC_DSCALEOPT                   BIT(20)
  78
  79 #define ATMEL_HLCDC_XRGB4444_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(0))
  80 #define ATMEL_HLCDC_ARGB4444_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(1))
  81 #define ATMEL_HLCDC_RGBA4444_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(2))
  82 #define ATMEL_HLCDC_RGB565_MODE                 (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(3))
  83 #define ATMEL_HLCDC_ARGB1555_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(4))
  84 #define ATMEL_HLCDC_XRGB8888_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(9))
  85 #define ATMEL_HLCDC_RGB888_MODE                 (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(10))
  86 #define ATMEL_HLCDC_ARGB8888_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(12))
  87 #define ATMEL_HLCDC_RGBA8888_MODE               (ATMEL_HLCDC_LAYER_RGB | ATMEL_HLCDC_RGB_MODE(13))
  88
  89 #define ATMEL_HLCDC_AYUV_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(0))
  90 #define ATMEL_HLCDC_YUYV_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(1))
  91 #define ATMEL_HLCDC_UYVY_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(2))
  92 #define ATMEL_HLCDC_YVYU_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(3))
  93 #define ATMEL_HLCDC_VYUY_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(4))
  94 #define ATMEL_HLCDC_NV61_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(5))
  95 #define ATMEL_HLCDC_YUV422_MODE                 (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(6))
  96 #define ATMEL_HLCDC_NV21_MODE                   (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(7))
  97 #define ATMEL_HLCDC_YUV420_MODE                 (ATMEL_HLCDC_LAYER_YUV | ATMEL_HLCDC_YUV_MODE(8))
  98
  99 #define ATMEL_HLCDC_LAYER_POS_CFG(p)            ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pos)
 100 #define ATMEL_HLCDC_LAYER_SIZE_CFG(p)           ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.size)
 101 #define ATMEL_HLCDC_LAYER_MEMSIZE_CFG(p)        ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.memsize)
 102 #define ATMEL_HLCDC_LAYER_XSTRIDE_CFG(p)        ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.xstride)
 103 #define ATMEL_HLCDC_LAYER_PSTRIDE_CFG(p)        ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.pstride)
 104 #define ATMEL_HLCDC_LAYER_DFLTCOLOR_CFG(p)      ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.default_color)
 105 #define ATMEL_HLCDC_LAYER_CRKEY_CFG(p)          ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key)
 106 #define ATMEL_HLCDC_LAYER_CRKEY_MASK_CFG(p)     ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.chroma_key_mask)
 107
 108 #define ATMEL_HLCDC_LAYER_GENERAL_CFG(p)        ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.general_config)
 109 #define ATMEL_HLCDC_LAYER_CRKEY                 BIT(0)
 110 #define ATMEL_HLCDC_LAYER_INV                   BIT(1)
 111 #define ATMEL_HLCDC_LAYER_ITER2BL               BIT(2)
 112 #define ATMEL_HLCDC_LAYER_ITER                  BIT(3)
 113 #define ATMEL_HLCDC_LAYER_REVALPHA              BIT(4)
 114 #define ATMEL_HLCDC_LAYER_GAEN                  BIT(5)
 115 #define ATMEL_HLCDC_LAYER_LAEN                  BIT(6)
 116 #define ATMEL_HLCDC_LAYER_OVR                   BIT(7)
 117 #define ATMEL_HLCDC_LAYER_DMA                   BIT(8)
 118 #define ATMEL_HLCDC_LAYER_REP                   BIT(9)
 119 #define ATMEL_HLCDC_LAYER_DSTKEY                BIT(10)
 120 #define ATMEL_HLCDC_LAYER_DISCEN                BIT(11)
 121 #define ATMEL_HLCDC_LAYER_GA_SHIFT              16
 122 #define ATMEL_HLCDC_LAYER_GA_MASK               GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT)
 123
 124 #define ATMEL_HLCDC_LAYER_CSC_CFG(p, o)         ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.csc + o)
 125
 126 #define ATMEL_HLCDC_LAYER_DISC_POS_CFG(p)       ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_pos)
 127
 128 #define ATMEL_HLCDC_LAYER_DISC_SIZE_CFG(p)      ATMEL_HLCDC_LAYER_CFG(p, (p)->desc->layout.disc_size)
 129
 130 #define ATMEL_HLCDC_MAX_PLANES                  3
 131
 132 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED   BIT(0)
 133 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED     BIT(1)
 134 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE       BIT(2)
 135 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN    BIT(3)
 136
 137 /**
 138  * Atmel HLCDC Layer registers layout structure
 139  *
 140  * Each HLCDC layer has its own register organization and a given register
 141  * can be placed differently on 2 different layers depending on its
 142  * capabilities.
 143  * This structure stores common registers layout for a given layer and is
 144  * used by HLCDC layer code to choose the appropriate register to write to
 145  * or to read from.
 146  *
 147  * For all fields, a value of zero means "unsupported".
 148  *
 149  * See Atmel's datasheet for a detailled description of these registers.
 150  *
 151  * @xstride: xstride registers
 152  * @pstride: pstride registers
 153  * @pos: position register
 154  * @size: displayed size register
 155  * @memsize: memory size register
 156  * @default_color: default color register
 157  * @chroma_key: chroma key register
 158  * @chroma_key_mask: chroma key mask register
 159  * @general_config: general layer config register
 160  * @disc_pos: discard area position register
 161  * @disc_size: discard area size register
 162  * @csc: color space conversion register
 163  */
 164 struct atmel_hlcdc_layer_cfg_layout {
 165         int xstride[ATMEL_HLCDC_MAX_PLANES];
 166         int pstride[ATMEL_HLCDC_MAX_PLANES];
 167         int pos;
 168         int size;
 169         int memsize;
 170         int default_color;
 171         int chroma_key;
 172         int chroma_key_mask;
 173         int general_config;
 174         int disc_pos;
 175         int disc_size;
 176         int csc;
 177 };
 178
 179 /**
 180  * Atmel HLCDC framebuffer flip structure
 181  *
 182  * This structure is allocated when someone asked for a layer update (most
 183  * likely a DRM plane update, either primary, overlay or cursor plane) and
 184  * released when the layer do not need to reference the framebuffer object
 185  * anymore (i.e. the layer was disabled or updated).
 186  *
 187  * @dscrs: DMA descriptors
 188  * @fb: the referenced framebuffer object
 189  * @ngems: number of GEM objects referenced by the fb element
 190  * @status: fb flip operation status
 191  */
 192 struct atmel_hlcdc_layer_fb_flip {
 193         struct atmel_hlcdc_dma_channel_dscr *dscrs[ATMEL_HLCDC_MAX_PLANES];
 194         struct drm_flip_task *task;
 195         struct drm_framebuffer *fb;
 196         int ngems;
 197         u32 status;
 198 };
 199
 200 /**
 201  * Atmel HLCDC DMA descriptor structure
 202  *
 203  * This structure is used by the HLCDC DMA engine to schedule a DMA transfer.
 204  *
 205  * The structure fields must remain in this specific order, because they're
 206  * used by the HLCDC DMA engine, which expect them in this order.
 207  * HLCDC DMA descriptors must be aligned on 64 bits.
 208  *
 209  * @addr: buffer DMA address
 210  * @ctrl: DMA transfer options
 211  * @next: next DMA descriptor to fetch
 212  * @gem_flip: the attached gem_flip operation
 213  */
 214 struct atmel_hlcdc_dma_channel_dscr {
 215         dma_addr_t addr;
 216         u32 ctrl;
 217         dma_addr_t next;
 218         u32 status;
 219 } __aligned(sizeof(u64));
 220
 221 /**
 222  * Atmel HLCDC layer types
 223  */
 224 enum atmel_hlcdc_layer_type {
 225         ATMEL_HLCDC_BASE_LAYER,
 226         ATMEL_HLCDC_OVERLAY_LAYER,
 227         ATMEL_HLCDC_CURSOR_LAYER,
 228         ATMEL_HLCDC_PP_LAYER,
 229 };
 230
 231 /**
 232  * Atmel HLCDC Supported formats structure
 233  *
 234  * This structure list all the formats supported by a given layer.
 235  *
 236  * @nformats: number of supported formats
 237  * @formats: supported formats
 238  */
 239 struct atmel_hlcdc_formats {
 240         int nformats;
 241         uint32_t *formats;
 242 };
 243
 244 /**
 245  * Atmel HLCDC Layer description structure
 246  *
 247  * This structure describe the capabilities provided by a given layer.
 248  *
 249  * @name: layer name
 250  * @type: layer type
 251  * @id: layer id
 252  * @regs_offset: offset of the layer registers from the HLCDC registers base
 253  * @nconfigs: number of config registers provided by this layer
 254  * @formats: supported formats
 255  * @layout: config registers layout
 256  * @max_width: maximum width supported by this layer (0 means unlimited)
 257  * @max_height: maximum height supported by this layer (0 means unlimited)
 258  */
 259 struct atmel_hlcdc_layer_desc {
 260         const char *name;
 261         enum atmel_hlcdc_layer_type type;
 262         int id;
 263         int regs_offset;
 264         int nconfigs;
 265         struct atmel_hlcdc_formats *formats;
 266         struct atmel_hlcdc_layer_cfg_layout layout;
 267         int max_width;
 268         int max_height;
 269 };
 270
 271 /**
 272  * Atmel HLCDC Layer Update Slot structure
 273  *
 274  * This structure stores layer update requests to be applied on next frame.
 275  * This is the base structure behind the atomic layer update infrastructure.
 276  *
 277  * Atomic layer update provides a way to update all layer's parameters
 278  * simultaneously. This is needed to avoid incompatible sequential updates
 279  * like this one:
 280  * 1) update layer format from RGB888 (1 plane/buffer) to YUV422
 281  *    (2 planes/buffers)
 282  * 2) the format update is applied but the DMA channel for the second
 283  *    plane/buffer is not enabled
 284  * 3) enable the DMA channel for the second plane
 285  *
 286  * @fb_flip: fb_flip object
 287  * @updated_configs: bitmask used to record modified configs
 288  * @configs: new config values
 289  */
 290 struct atmel_hlcdc_layer_update_slot {
 291         struct atmel_hlcdc_layer_fb_flip *fb_flip;
 292         unsigned long *updated_configs;
 293         u32 *configs;
 294 };
 295
 296 /**
 297  * Atmel HLCDC Layer Update structure
 298  *
 299  * This structure provides a way to queue layer update requests.
 300  *
 301  * At a given time there is at most:
 302  *  - one pending update request, which means the update request has been
 303  *    committed (or validated) and is waiting for the DMA channel(s) to be
 304  *    available
 305  *  - one request being prepared, which means someone started a layer update
 306  *    but has not committed it yet. There cannot be more than one started
 307  *    request, because the update lock is taken when starting a layer update
 308  *    and release when committing or rolling back the request.
 309  *
 310  * @slots: update slots. One is used for pending request and the other one
 311  *         for started update request
 312  * @pending: the pending slot index or -1 if no request is pending
 313  * @next: the started update slot index or -1 no update has been started
 314  */
 315 struct atmel_hlcdc_layer_update {
 316         struct atmel_hlcdc_layer_update_slot slots[2];
 317         int pending;
 318         int next;
 319 };
 320
 321 enum atmel_hlcdc_layer_dma_channel_status {
 322         ATMEL_HLCDC_LAYER_DISABLED,
 323         ATMEL_HLCDC_LAYER_ENABLED,
 324         ATMEL_HLCDC_LAYER_DISABLING,
 325 };
 326
 327 /**
 328  * Atmel HLCDC Layer DMA channel structure
 329  *
 330  * This structure stores information on the DMA channel associated to a
 331  * given layer.
 332  *
 333  * @status: DMA channel status
 334  * @cur: current framebuffer
 335  * @queue: next framebuffer
 336  * @dscrs: allocated DMA descriptors
 337  */
 338 struct atmel_hlcdc_layer_dma_channel {
 339         enum atmel_hlcdc_layer_dma_channel_status status;
 340         struct atmel_hlcdc_layer_fb_flip *cur;
 341         struct atmel_hlcdc_layer_fb_flip *queue;
 342         struct atmel_hlcdc_dma_channel_dscr *dscrs;
 343 };
 344
 345 /**
 346  * Atmel HLCDC Layer structure
 347  *
 348  * This structure stores information on the layer instance.
 349  *
 350  * @desc: layer description
 351  * @max_planes: maximum planes/buffers that can be associated with this layer.
 352  *             This depends on the supported formats.
 353  * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device
 354  * @dma: dma channel
 355  * @gc: fb flip garbage collector
 356  * @update: update handler
 357  * @lock: layer lock
 358  */
 359 struct atmel_hlcdc_layer {
 360         const struct atmel_hlcdc_layer_desc *desc;
 361         int max_planes;
 362         struct atmel_hlcdc *hlcdc;
 363         struct workqueue_struct *wq;
 364         struct drm_flip_work gc;
 365         struct atmel_hlcdc_layer_dma_channel dma;
 366         struct atmel_hlcdc_layer_update update;
 367         spinlock_t lock;
 368 };
 369
 370 void atmel_hlcdc_layer_irq(struct atmel_hlcdc_layer *layer);
 371
 372 int atmel_hlcdc_layer_init(struct drm_device *dev,
 373                            struct atmel_hlcdc_layer *layer,
 374                            const struct atmel_hlcdc_layer_desc *desc);
 375
 376 void atmel_hlcdc_layer_cleanup(struct drm_device *dev,
 377                                struct atmel_hlcdc_layer *layer);
 378
 379 int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer);
 380
 381 int atmel_hlcdc_layer_update_start(struct atmel_hlcdc_layer *layer);
 382
 383 void atmel_hlcdc_layer_update_cfg(struct atmel_hlcdc_layer *layer, int cfg,
 384                                   u32 mask, u32 val);
 385
 386 void atmel_hlcdc_layer_update_set_fb(struct atmel_hlcdc_layer *layer,
 387                                      struct drm_framebuffer *fb,
 388                                      unsigned int *offsets);
 389
 390 void atmel_hlcdc_layer_update_set_finished(struct atmel_hlcdc_layer *layer,
 391                                            void (*finished)(void *data),
 392                                            void *finished_data);
 393
 394 void atmel_hlcdc_layer_update_rollback(struct atmel_hlcdc_layer *layer);
 395
 396 void atmel_hlcdc_layer_update_commit(struct atmel_hlcdc_layer *layer);
 397
 398 #endif /* DRM_ATMEL_HLCDC_LAYER_H */