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Merge remote-tracking branches 'asoc/fix/ab8500', 'asoc/fix/adau17x1', 'asoc/fix...
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos7_drm_decon.c
1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
2 *
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
4 * Authors:
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15 #include <drm/exynos_drm.h>
16
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
29
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_plane.h"
32 #include "exynos_drm_drv.h"
33 #include "exynos_drm_fb.h"
34 #include "exynos_drm_fbdev.h"
35 #include "exynos_drm_iommu.h"
36
37 /*
38 * DECON stands for Display and Enhancement controller.
39 */
40
41 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
42
43 #define WINDOWS_NR 2
44
45 struct decon_context {
46 struct device *dev;
47 struct drm_device *drm_dev;
48 struct exynos_drm_crtc *crtc;
49 struct exynos_drm_plane planes[WINDOWS_NR];
50 struct exynos_drm_plane_config configs[WINDOWS_NR];
51 struct clk *pclk;
52 struct clk *aclk;
53 struct clk *eclk;
54 struct clk *vclk;
55 void __iomem *regs;
56 unsigned long irq_flags;
57 bool i80_if;
58 bool suspended;
59 int pipe;
60 wait_queue_head_t wait_vsync_queue;
61 atomic_t wait_vsync_event;
62
63 struct exynos_drm_panel_info panel;
64 struct drm_encoder *encoder;
65 };
66
67 static const struct of_device_id decon_driver_dt_match[] = {
68 {.compatible = "samsung,exynos7-decon"},
69 {},
70 };
71 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
72
73 static const uint32_t decon_formats[] = {
74 DRM_FORMAT_RGB565,
75 DRM_FORMAT_XRGB8888,
76 DRM_FORMAT_XBGR8888,
77 DRM_FORMAT_RGBX8888,
78 DRM_FORMAT_BGRX8888,
79 DRM_FORMAT_ARGB8888,
80 DRM_FORMAT_ABGR8888,
81 DRM_FORMAT_RGBA8888,
82 DRM_FORMAT_BGRA8888,
83 };
84
85 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
86 DRM_PLANE_TYPE_PRIMARY,
87 DRM_PLANE_TYPE_CURSOR,
88 };
89
90 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
91 {
92 struct decon_context *ctx = crtc->ctx;
93
94 if (ctx->suspended)
95 return;
96
97 atomic_set(&ctx->wait_vsync_event, 1);
98
99 /*
100 * wait for DECON to signal VSYNC interrupt or return after
101 * timeout which is set to 50ms (refresh rate of 20).
102 */
103 if (!wait_event_timeout(ctx->wait_vsync_queue,
104 !atomic_read(&ctx->wait_vsync_event),
105 HZ/20))
106 DRM_DEBUG_KMS("vblank wait timed out.\n");
107 }
108
109 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
110 {
111 struct decon_context *ctx = crtc->ctx;
112 unsigned int win, ch_enabled = 0;
113
114 DRM_DEBUG_KMS("%s\n", __FILE__);
115
116 /* Check if any channel is enabled. */
117 for (win = 0; win < WINDOWS_NR; win++) {
118 u32 val = readl(ctx->regs + WINCON(win));
119
120 if (val & WINCONx_ENWIN) {
121 val &= ~WINCONx_ENWIN;
122 writel(val, ctx->regs + WINCON(win));
123 ch_enabled = 1;
124 }
125 }
126
127 /* Wait for vsync, as disable channel takes effect at next vsync */
128 if (ch_enabled)
129 decon_wait_for_vblank(ctx->crtc);
130 }
131
132 static int decon_ctx_initialize(struct decon_context *ctx,
133 struct drm_device *drm_dev)
134 {
135 struct exynos_drm_private *priv = drm_dev->dev_private;
136 int ret;
137
138 ctx->drm_dev = drm_dev;
139 ctx->pipe = priv->pipe++;
140
141 decon_clear_channels(ctx->crtc);
142
143 ret = drm_iommu_attach_device(drm_dev, ctx->dev);
144 if (ret)
145 priv->pipe--;
146
147 return ret;
148 }
149
150 static void decon_ctx_remove(struct decon_context *ctx)
151 {
152 /* detach this sub driver from iommu mapping if supported. */
153 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
154 }
155
156 static u32 decon_calc_clkdiv(struct decon_context *ctx,
157 const struct drm_display_mode *mode)
158 {
159 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
160 u32 clkdiv;
161
162 /* Find the clock divider value that gets us closest to ideal_clk */
163 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
164
165 return (clkdiv < 0x100) ? clkdiv : 0xff;
166 }
167
168 static void decon_commit(struct exynos_drm_crtc *crtc)
169 {
170 struct decon_context *ctx = crtc->ctx;
171 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
172 u32 val, clkdiv;
173
174 if (ctx->suspended)
175 return;
176
177 /* nothing to do if we haven't set the mode yet */
178 if (mode->htotal == 0 || mode->vtotal == 0)
179 return;
180
181 if (!ctx->i80_if) {
182 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
183 /* setup vertical timing values. */
184 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
185 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
186 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
187
188 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
189 writel(val, ctx->regs + VIDTCON0);
190
191 val = VIDTCON1_VSPW(vsync_len - 1);
192 writel(val, ctx->regs + VIDTCON1);
193
194 /* setup horizontal timing values. */
195 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
196 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
197 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
198
199 /* setup horizontal timing values. */
200 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
201 writel(val, ctx->regs + VIDTCON2);
202
203 val = VIDTCON3_HSPW(hsync_len - 1);
204 writel(val, ctx->regs + VIDTCON3);
205 }
206
207 /* setup horizontal and vertical display size. */
208 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
209 VIDTCON4_HOZVAL(mode->hdisplay - 1);
210 writel(val, ctx->regs + VIDTCON4);
211
212 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
213
214 /*
215 * fields of register with prefix '_F' would be updated
216 * at vsync(same as dma start)
217 */
218 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
219 writel(val, ctx->regs + VIDCON0);
220
221 clkdiv = decon_calc_clkdiv(ctx, mode);
222 if (clkdiv > 1) {
223 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
224 writel(val, ctx->regs + VCLKCON1);
225 writel(val, ctx->regs + VCLKCON2);
226 }
227
228 val = readl(ctx->regs + DECON_UPDATE);
229 val |= DECON_UPDATE_STANDALONE_F;
230 writel(val, ctx->regs + DECON_UPDATE);
231 }
232
233 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
234 {
235 struct decon_context *ctx = crtc->ctx;
236 u32 val;
237
238 if (ctx->suspended)
239 return -EPERM;
240
241 if (!test_and_set_bit(0, &ctx->irq_flags)) {
242 val = readl(ctx->regs + VIDINTCON0);
243
244 val |= VIDINTCON0_INT_ENABLE;
245
246 if (!ctx->i80_if) {
247 val |= VIDINTCON0_INT_FRAME;
248 val &= ~VIDINTCON0_FRAMESEL0_MASK;
249 val |= VIDINTCON0_FRAMESEL0_VSYNC;
250 }
251
252 writel(val, ctx->regs + VIDINTCON0);
253 }
254
255 return 0;
256 }
257
258 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
259 {
260 struct decon_context *ctx = crtc->ctx;
261 u32 val;
262
263 if (ctx->suspended)
264 return;
265
266 if (test_and_clear_bit(0, &ctx->irq_flags)) {
267 val = readl(ctx->regs + VIDINTCON0);
268
269 val &= ~VIDINTCON0_INT_ENABLE;
270 if (!ctx->i80_if)
271 val &= ~VIDINTCON0_INT_FRAME;
272
273 writel(val, ctx->regs + VIDINTCON0);
274 }
275 }
276
277 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
278 struct drm_framebuffer *fb)
279 {
280 unsigned long val;
281 int padding;
282
283 val = readl(ctx->regs + WINCON(win));
284 val &= ~WINCONx_BPPMODE_MASK;
285
286 switch (fb->pixel_format) {
287 case DRM_FORMAT_RGB565:
288 val |= WINCONx_BPPMODE_16BPP_565;
289 val |= WINCONx_BURSTLEN_16WORD;
290 break;
291 case DRM_FORMAT_XRGB8888:
292 val |= WINCONx_BPPMODE_24BPP_xRGB;
293 val |= WINCONx_BURSTLEN_16WORD;
294 break;
295 case DRM_FORMAT_XBGR8888:
296 val |= WINCONx_BPPMODE_24BPP_xBGR;
297 val |= WINCONx_BURSTLEN_16WORD;
298 break;
299 case DRM_FORMAT_RGBX8888:
300 val |= WINCONx_BPPMODE_24BPP_RGBx;
301 val |= WINCONx_BURSTLEN_16WORD;
302 break;
303 case DRM_FORMAT_BGRX8888:
304 val |= WINCONx_BPPMODE_24BPP_BGRx;
305 val |= WINCONx_BURSTLEN_16WORD;
306 break;
307 case DRM_FORMAT_ARGB8888:
308 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
309 WINCONx_ALPHA_SEL;
310 val |= WINCONx_BURSTLEN_16WORD;
311 break;
312 case DRM_FORMAT_ABGR8888:
313 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
314 WINCONx_ALPHA_SEL;
315 val |= WINCONx_BURSTLEN_16WORD;
316 break;
317 case DRM_FORMAT_RGBA8888:
318 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
319 WINCONx_ALPHA_SEL;
320 val |= WINCONx_BURSTLEN_16WORD;
321 break;
322 case DRM_FORMAT_BGRA8888:
323 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
324 WINCONx_ALPHA_SEL;
325 val |= WINCONx_BURSTLEN_16WORD;
326 break;
327 default:
328 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
329
330 val |= WINCONx_BPPMODE_24BPP_xRGB;
331 val |= WINCONx_BURSTLEN_16WORD;
332 break;
333 }
334
335 DRM_DEBUG_KMS("bpp = %d\n", fb->bits_per_pixel);
336
337 /*
338 * In case of exynos, setting dma-burst to 16Word causes permanent
339 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
340 * switching which is based on plane size is not recommended as
341 * plane size varies a lot towards the end of the screen and rapid
342 * movement causes unstable DMA which results into iommu crash/tear.
343 */
344
345 padding = (fb->pitches[0] / (fb->bits_per_pixel >> 3)) - fb->width;
346 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
347 val &= ~WINCONx_BURSTLEN_MASK;
348 val |= WINCONx_BURSTLEN_8WORD;
349 }
350
351 writel(val, ctx->regs + WINCON(win));
352 }
353
354 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
355 {
356 unsigned int keycon0 = 0, keycon1 = 0;
357
358 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
359 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
360
361 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
362
363 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
364 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
365 }
366
367 /**
368 * shadow_protect_win() - disable updating values from shadow registers at vsync
369 *
370 * @win: window to protect registers for
371 * @protect: 1 to protect (disable updates)
372 */
373 static void decon_shadow_protect_win(struct decon_context *ctx,
374 unsigned int win, bool protect)
375 {
376 u32 bits, val;
377
378 bits = SHADOWCON_WINx_PROTECT(win);
379
380 val = readl(ctx->regs + SHADOWCON);
381 if (protect)
382 val |= bits;
383 else
384 val &= ~bits;
385 writel(val, ctx->regs + SHADOWCON);
386 }
387
388 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
389 {
390 struct decon_context *ctx = crtc->ctx;
391 int i;
392
393 if (ctx->suspended)
394 return;
395
396 for (i = 0; i < WINDOWS_NR; i++)
397 decon_shadow_protect_win(ctx, i, true);
398 }
399
400 static void decon_update_plane(struct exynos_drm_crtc *crtc,
401 struct exynos_drm_plane *plane)
402 {
403 struct exynos_drm_plane_state *state =
404 to_exynos_plane_state(plane->base.state);
405 struct decon_context *ctx = crtc->ctx;
406 struct drm_framebuffer *fb = state->base.fb;
407 int padding;
408 unsigned long val, alpha;
409 unsigned int last_x;
410 unsigned int last_y;
411 unsigned int win = plane->index;
412 unsigned int bpp = fb->bits_per_pixel >> 3;
413 unsigned int pitch = fb->pitches[0];
414
415 if (ctx->suspended)
416 return;
417
418 /*
419 * SHADOWCON/PRTCON register is used for enabling timing.
420 *
421 * for example, once only width value of a register is set,
422 * if the dma is started then decon hardware could malfunction so
423 * with protect window setting, the register fields with prefix '_F'
424 * wouldn't be updated at vsync also but updated once unprotect window
425 * is set.
426 */
427
428 /* buffer start address */
429 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
430 writel(val, ctx->regs + VIDW_BUF_START(win));
431
432 padding = (pitch / bpp) - fb->width;
433
434 /* buffer size */
435 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
436 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
437
438 /* offset from the start of the buffer to read */
439 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
440 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
441
442 DRM_DEBUG_KMS("start addr = 0x%lx\n",
443 (unsigned long)val);
444 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
445 state->crtc.w, state->crtc.h);
446
447 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
448 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
449 writel(val, ctx->regs + VIDOSD_A(win));
450
451 last_x = state->crtc.x + state->crtc.w;
452 if (last_x)
453 last_x--;
454 last_y = state->crtc.y + state->crtc.h;
455 if (last_y)
456 last_y--;
457
458 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
459
460 writel(val, ctx->regs + VIDOSD_B(win));
461
462 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
463 state->crtc.x, state->crtc.y, last_x, last_y);
464
465 /* OSD alpha */
466 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
467 VIDOSDxC_ALPHA0_G_F(0x0) |
468 VIDOSDxC_ALPHA0_B_F(0x0);
469
470 writel(alpha, ctx->regs + VIDOSD_C(win));
471
472 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
473 VIDOSDxD_ALPHA1_G_F(0xff) |
474 VIDOSDxD_ALPHA1_B_F(0xff);
475
476 writel(alpha, ctx->regs + VIDOSD_D(win));
477
478 decon_win_set_pixfmt(ctx, win, fb);
479
480 /* hardware window 0 doesn't support color key. */
481 if (win != 0)
482 decon_win_set_colkey(ctx, win);
483
484 /* wincon */
485 val = readl(ctx->regs + WINCON(win));
486 val |= WINCONx_TRIPLE_BUF_MODE;
487 val |= WINCONx_ENWIN;
488 writel(val, ctx->regs + WINCON(win));
489
490 /* Enable DMA channel and unprotect windows */
491 decon_shadow_protect_win(ctx, win, false);
492
493 val = readl(ctx->regs + DECON_UPDATE);
494 val |= DECON_UPDATE_STANDALONE_F;
495 writel(val, ctx->regs + DECON_UPDATE);
496 }
497
498 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
499 struct exynos_drm_plane *plane)
500 {
501 struct decon_context *ctx = crtc->ctx;
502 unsigned int win = plane->index;
503 u32 val;
504
505 if (ctx->suspended)
506 return;
507
508 /* protect windows */
509 decon_shadow_protect_win(ctx, win, true);
510
511 /* wincon */
512 val = readl(ctx->regs + WINCON(win));
513 val &= ~WINCONx_ENWIN;
514 writel(val, ctx->regs + WINCON(win));
515
516 val = readl(ctx->regs + DECON_UPDATE);
517 val |= DECON_UPDATE_STANDALONE_F;
518 writel(val, ctx->regs + DECON_UPDATE);
519 }
520
521 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
522 {
523 struct decon_context *ctx = crtc->ctx;
524 int i;
525
526 if (ctx->suspended)
527 return;
528
529 for (i = 0; i < WINDOWS_NR; i++)
530 decon_shadow_protect_win(ctx, i, false);
531 }
532
533 static void decon_init(struct decon_context *ctx)
534 {
535 u32 val;
536
537 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
538
539 val = VIDOUTCON0_DISP_IF_0_ON;
540 if (!ctx->i80_if)
541 val |= VIDOUTCON0_RGBIF;
542 writel(val, ctx->regs + VIDOUTCON0);
543
544 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
545
546 if (!ctx->i80_if)
547 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
548 }
549
550 static void decon_enable(struct exynos_drm_crtc *crtc)
551 {
552 struct decon_context *ctx = crtc->ctx;
553
554 if (!ctx->suspended)
555 return;
556
557 pm_runtime_get_sync(ctx->dev);
558
559 decon_init(ctx);
560
561 /* if vblank was enabled status, enable it again. */
562 if (test_and_clear_bit(0, &ctx->irq_flags))
563 decon_enable_vblank(ctx->crtc);
564
565 decon_commit(ctx->crtc);
566
567 ctx->suspended = false;
568 }
569
570 static void decon_disable(struct exynos_drm_crtc *crtc)
571 {
572 struct decon_context *ctx = crtc->ctx;
573 int i;
574
575 if (ctx->suspended)
576 return;
577
578 /*
579 * We need to make sure that all windows are disabled before we
580 * suspend that connector. Otherwise we might try to scan from
581 * a destroyed buffer later.
582 */
583 for (i = 0; i < WINDOWS_NR; i++)
584 decon_disable_plane(crtc, &ctx->planes[i]);
585
586 pm_runtime_put_sync(ctx->dev);
587
588 ctx->suspended = true;
589 }
590
591 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
592 .enable = decon_enable,
593 .disable = decon_disable,
594 .commit = decon_commit,
595 .enable_vblank = decon_enable_vblank,
596 .disable_vblank = decon_disable_vblank,
597 .wait_for_vblank = decon_wait_for_vblank,
598 .atomic_begin = decon_atomic_begin,
599 .update_plane = decon_update_plane,
600 .disable_plane = decon_disable_plane,
601 .atomic_flush = decon_atomic_flush,
602 };
603
604
605 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
606 {
607 struct decon_context *ctx = (struct decon_context *)dev_id;
608 u32 val, clear_bit;
609 int win;
610
611 val = readl(ctx->regs + VIDINTCON1);
612
613 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
614 if (val & clear_bit)
615 writel(clear_bit, ctx->regs + VIDINTCON1);
616
617 /* check the crtc is detached already from encoder */
618 if (ctx->pipe < 0 || !ctx->drm_dev)
619 goto out;
620
621 if (!ctx->i80_if) {
622 drm_crtc_handle_vblank(&ctx->crtc->base);
623 for (win = 0 ; win < WINDOWS_NR ; win++) {
624 struct exynos_drm_plane *plane = &ctx->planes[win];
625
626 if (!plane->pending_fb)
627 continue;
628
629 exynos_drm_crtc_finish_update(ctx->crtc, plane);
630 }
631
632 /* set wait vsync event to zero and wake up queue. */
633 if (atomic_read(&ctx->wait_vsync_event)) {
634 atomic_set(&ctx->wait_vsync_event, 0);
635 wake_up(&ctx->wait_vsync_queue);
636 }
637 }
638 out:
639 return IRQ_HANDLED;
640 }
641
642 static int decon_bind(struct device *dev, struct device *master, void *data)
643 {
644 struct decon_context *ctx = dev_get_drvdata(dev);
645 struct drm_device *drm_dev = data;
646 struct exynos_drm_plane *exynos_plane;
647 unsigned int i;
648 int ret;
649
650 ret = decon_ctx_initialize(ctx, drm_dev);
651 if (ret) {
652 DRM_ERROR("decon_ctx_initialize failed.\n");
653 return ret;
654 }
655
656 for (i = 0; i < WINDOWS_NR; i++) {
657 ctx->configs[i].pixel_formats = decon_formats;
658 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
659 ctx->configs[i].zpos = i;
660 ctx->configs[i].type = decon_win_types[i];
661
662 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
663 1 << ctx->pipe, &ctx->configs[i]);
664 if (ret)
665 return ret;
666 }
667
668 exynos_plane = &ctx->planes[DEFAULT_WIN];
669 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
670 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
671 &decon_crtc_ops, ctx);
672 if (IS_ERR(ctx->crtc)) {
673 decon_ctx_remove(ctx);
674 return PTR_ERR(ctx->crtc);
675 }
676
677 if (ctx->encoder)
678 exynos_dpi_bind(drm_dev, ctx->encoder);
679
680 return 0;
681
682 }
683
684 static void decon_unbind(struct device *dev, struct device *master,
685 void *data)
686 {
687 struct decon_context *ctx = dev_get_drvdata(dev);
688
689 decon_disable(ctx->crtc);
690
691 if (ctx->encoder)
692 exynos_dpi_remove(ctx->encoder);
693
694 decon_ctx_remove(ctx);
695 }
696
697 static const struct component_ops decon_component_ops = {
698 .bind = decon_bind,
699 .unbind = decon_unbind,
700 };
701
702 static int decon_probe(struct platform_device *pdev)
703 {
704 struct device *dev = &pdev->dev;
705 struct decon_context *ctx;
706 struct device_node *i80_if_timings;
707 struct resource *res;
708 int ret;
709
710 if (!dev->of_node)
711 return -ENODEV;
712
713 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
714 if (!ctx)
715 return -ENOMEM;
716
717 ctx->dev = dev;
718 ctx->suspended = true;
719
720 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
721 if (i80_if_timings)
722 ctx->i80_if = true;
723 of_node_put(i80_if_timings);
724
725 ctx->regs = of_iomap(dev->of_node, 0);
726 if (!ctx->regs)
727 return -ENOMEM;
728
729 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
730 if (IS_ERR(ctx->pclk)) {
731 dev_err(dev, "failed to get bus clock pclk\n");
732 ret = PTR_ERR(ctx->pclk);
733 goto err_iounmap;
734 }
735
736 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
737 if (IS_ERR(ctx->aclk)) {
738 dev_err(dev, "failed to get bus clock aclk\n");
739 ret = PTR_ERR(ctx->aclk);
740 goto err_iounmap;
741 }
742
743 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
744 if (IS_ERR(ctx->eclk)) {
745 dev_err(dev, "failed to get eclock\n");
746 ret = PTR_ERR(ctx->eclk);
747 goto err_iounmap;
748 }
749
750 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
751 if (IS_ERR(ctx->vclk)) {
752 dev_err(dev, "failed to get vclock\n");
753 ret = PTR_ERR(ctx->vclk);
754 goto err_iounmap;
755 }
756
757 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
758 ctx->i80_if ? "lcd_sys" : "vsync");
759 if (!res) {
760 dev_err(dev, "irq request failed.\n");
761 ret = -ENXIO;
762 goto err_iounmap;
763 }
764
765 ret = devm_request_irq(dev, res->start, decon_irq_handler,
766 0, "drm_decon", ctx);
767 if (ret) {
768 dev_err(dev, "irq request failed.\n");
769 goto err_iounmap;
770 }
771
772 init_waitqueue_head(&ctx->wait_vsync_queue);
773 atomic_set(&ctx->wait_vsync_event, 0);
774
775 platform_set_drvdata(pdev, ctx);
776
777 ctx->encoder = exynos_dpi_probe(dev);
778 if (IS_ERR(ctx->encoder)) {
779 ret = PTR_ERR(ctx->encoder);
780 goto err_iounmap;
781 }
782
783 pm_runtime_enable(dev);
784
785 ret = component_add(dev, &decon_component_ops);
786 if (ret)
787 goto err_disable_pm_runtime;
788
789 return ret;
790
791 err_disable_pm_runtime:
792 pm_runtime_disable(dev);
793
794 err_iounmap:
795 iounmap(ctx->regs);
796
797 return ret;
798 }
799
800 static int decon_remove(struct platform_device *pdev)
801 {
802 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
803
804 pm_runtime_disable(&pdev->dev);
805
806 iounmap(ctx->regs);
807
808 component_del(&pdev->dev, &decon_component_ops);
809
810 return 0;
811 }
812
813 #ifdef CONFIG_PM
814 static int exynos7_decon_suspend(struct device *dev)
815 {
816 struct decon_context *ctx = dev_get_drvdata(dev);
817
818 clk_disable_unprepare(ctx->vclk);
819 clk_disable_unprepare(ctx->eclk);
820 clk_disable_unprepare(ctx->aclk);
821 clk_disable_unprepare(ctx->pclk);
822
823 return 0;
824 }
825
826 static int exynos7_decon_resume(struct device *dev)
827 {
828 struct decon_context *ctx = dev_get_drvdata(dev);
829 int ret;
830
831 ret = clk_prepare_enable(ctx->pclk);
832 if (ret < 0) {
833 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
834 return ret;
835 }
836
837 ret = clk_prepare_enable(ctx->aclk);
838 if (ret < 0) {
839 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
840 return ret;
841 }
842
843 ret = clk_prepare_enable(ctx->eclk);
844 if (ret < 0) {
845 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
846 return ret;
847 }
848
849 ret = clk_prepare_enable(ctx->vclk);
850 if (ret < 0) {
851 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
852 return ret;
853 }
854
855 return 0;
856 }
857 #endif
858
859 static const struct dev_pm_ops exynos7_decon_pm_ops = {
860 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
861 NULL)
862 };
863
864 struct platform_driver decon_driver = {
865 .probe = decon_probe,
866 .remove = decon_remove,
867 .driver = {
868 .name = "exynos-decon",
869 .pm = &exynos7_decon_pm_ops,
870 .of_match_table = decon_driver_dt_match,
871 },
872 };
Linux kernel - Deliverables
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