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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[deliverable/linux.git] / drivers / gpu / drm / exynos / exynos_drm_fimd.c
1 /* exynos_drm_fimd.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Authors:
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14 #include <drm/drmP.h>
15
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
25
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
30
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fb.h"
33 #include "exynos_drm_fbdev.h"
34 #include "exynos_drm_crtc.h"
35 #include "exynos_drm_plane.h"
36 #include "exynos_drm_iommu.h"
37
38 /*
39 * FIMD stands for Fully Interactive Mobile Display and
40 * as a display controller, it transfers contents drawn on memory
41 * to a LCD Panel through Display Interfaces such as RGB or
42 * CPU Interface.
43 */
44
45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46
47 /* position control register for hardware window 0, 2 ~ 4.*/
48 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
49 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 /*
51 * size control register for hardware windows 0 and alpha control register
52 * for hardware windows 1 ~ 4
53 */
54 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
55 /* size control register for hardware windows 1 ~ 2. */
56 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57
58 #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
59 #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
60
61 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
62 #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
63 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
64 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
65
66 /* color key control register for hardware window 1 ~ 4. */
67 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
68 /* color key value register for hardware window 1 ~ 4. */
69 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
70
71 /* I80 / RGB trigger control register */
72 #define TRIGCON 0x1A4
73 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
74 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
75
76 /* display mode change control register except exynos4 */
77 #define VIDOUT_CON 0x000
78 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
79
80 /* I80 interface control for main LDI register */
81 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
82 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
83 #define LCD_CS_SETUP(x) ((x) << 16)
84 #define LCD_WR_SETUP(x) ((x) << 12)
85 #define LCD_WR_ACTIVE(x) ((x) << 8)
86 #define LCD_WR_HOLD(x) ((x) << 4)
87 #define I80IFEN_ENABLE (1 << 0)
88
89 /* FIMD has totally five hardware windows. */
90 #define WINDOWS_NR 5
91
92 struct fimd_driver_data {
93 unsigned int timing_base;
94 unsigned int lcdblk_offset;
95 unsigned int lcdblk_vt_shift;
96 unsigned int lcdblk_bypass_shift;
97
98 unsigned int has_shadowcon:1;
99 unsigned int has_clksel:1;
100 unsigned int has_limited_fmt:1;
101 unsigned int has_vidoutcon:1;
102 unsigned int has_vtsel:1;
103 };
104
105 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
106 .timing_base = 0x0,
107 .has_clksel = 1,
108 .has_limited_fmt = 1,
109 };
110
111 static struct fimd_driver_data exynos3_fimd_driver_data = {
112 .timing_base = 0x20000,
113 .lcdblk_offset = 0x210,
114 .lcdblk_bypass_shift = 1,
115 .has_shadowcon = 1,
116 .has_vidoutcon = 1,
117 };
118
119 static struct fimd_driver_data exynos4_fimd_driver_data = {
120 .timing_base = 0x0,
121 .lcdblk_offset = 0x210,
122 .lcdblk_vt_shift = 10,
123 .lcdblk_bypass_shift = 1,
124 .has_shadowcon = 1,
125 .has_vtsel = 1,
126 };
127
128 static struct fimd_driver_data exynos4415_fimd_driver_data = {
129 .timing_base = 0x20000,
130 .lcdblk_offset = 0x210,
131 .lcdblk_vt_shift = 10,
132 .lcdblk_bypass_shift = 1,
133 .has_shadowcon = 1,
134 .has_vidoutcon = 1,
135 .has_vtsel = 1,
136 };
137
138 static struct fimd_driver_data exynos5_fimd_driver_data = {
139 .timing_base = 0x20000,
140 .lcdblk_offset = 0x214,
141 .lcdblk_vt_shift = 24,
142 .lcdblk_bypass_shift = 15,
143 .has_shadowcon = 1,
144 .has_vidoutcon = 1,
145 .has_vtsel = 1,
146 };
147
148 struct fimd_context {
149 struct device *dev;
150 struct drm_device *drm_dev;
151 struct exynos_drm_crtc *crtc;
152 struct exynos_drm_plane planes[WINDOWS_NR];
153 struct exynos_drm_plane_config configs[WINDOWS_NR];
154 struct clk *bus_clk;
155 struct clk *lcd_clk;
156 void __iomem *regs;
157 struct regmap *sysreg;
158 unsigned long irq_flags;
159 u32 vidcon0;
160 u32 vidcon1;
161 u32 vidout_con;
162 u32 i80ifcon;
163 bool i80_if;
164 bool suspended;
165 int pipe;
166 wait_queue_head_t wait_vsync_queue;
167 atomic_t wait_vsync_event;
168 atomic_t win_updated;
169 atomic_t triggering;
170
171 struct exynos_drm_panel_info panel;
172 struct fimd_driver_data *driver_data;
173 struct drm_encoder *encoder;
174 };
175
176 static const struct of_device_id fimd_driver_dt_match[] = {
177 { .compatible = "samsung,s3c6400-fimd",
178 .data = &s3c64xx_fimd_driver_data },
179 { .compatible = "samsung,exynos3250-fimd",
180 .data = &exynos3_fimd_driver_data },
181 { .compatible = "samsung,exynos4210-fimd",
182 .data = &exynos4_fimd_driver_data },
183 { .compatible = "samsung,exynos4415-fimd",
184 .data = &exynos4415_fimd_driver_data },
185 { .compatible = "samsung,exynos5250-fimd",
186 .data = &exynos5_fimd_driver_data },
187 {},
188 };
189 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
190
191 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
192 DRM_PLANE_TYPE_PRIMARY,
193 DRM_PLANE_TYPE_OVERLAY,
194 DRM_PLANE_TYPE_OVERLAY,
195 DRM_PLANE_TYPE_OVERLAY,
196 DRM_PLANE_TYPE_CURSOR,
197 };
198
199 static const uint32_t fimd_formats[] = {
200 DRM_FORMAT_C8,
201 DRM_FORMAT_XRGB1555,
202 DRM_FORMAT_RGB565,
203 DRM_FORMAT_XRGB8888,
204 DRM_FORMAT_ARGB8888,
205 };
206
207 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
208 struct platform_device *pdev)
209 {
210 const struct of_device_id *of_id =
211 of_match_device(fimd_driver_dt_match, &pdev->dev);
212
213 return (struct fimd_driver_data *)of_id->data;
214 }
215
216 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
217 {
218 struct fimd_context *ctx = crtc->ctx;
219 u32 val;
220
221 if (ctx->suspended)
222 return -EPERM;
223
224 if (!test_and_set_bit(0, &ctx->irq_flags)) {
225 val = readl(ctx->regs + VIDINTCON0);
226
227 val |= VIDINTCON0_INT_ENABLE;
228
229 if (ctx->i80_if) {
230 val |= VIDINTCON0_INT_I80IFDONE;
231 val |= VIDINTCON0_INT_SYSMAINCON;
232 val &= ~VIDINTCON0_INT_SYSSUBCON;
233 } else {
234 val |= VIDINTCON0_INT_FRAME;
235
236 val &= ~VIDINTCON0_FRAMESEL0_MASK;
237 val |= VIDINTCON0_FRAMESEL0_VSYNC;
238 val &= ~VIDINTCON0_FRAMESEL1_MASK;
239 val |= VIDINTCON0_FRAMESEL1_NONE;
240 }
241
242 writel(val, ctx->regs + VIDINTCON0);
243 }
244
245 return 0;
246 }
247
248 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
249 {
250 struct fimd_context *ctx = crtc->ctx;
251 u32 val;
252
253 if (ctx->suspended)
254 return;
255
256 if (test_and_clear_bit(0, &ctx->irq_flags)) {
257 val = readl(ctx->regs + VIDINTCON0);
258
259 val &= ~VIDINTCON0_INT_ENABLE;
260
261 if (ctx->i80_if) {
262 val &= ~VIDINTCON0_INT_I80IFDONE;
263 val &= ~VIDINTCON0_INT_SYSMAINCON;
264 val &= ~VIDINTCON0_INT_SYSSUBCON;
265 } else
266 val &= ~VIDINTCON0_INT_FRAME;
267
268 writel(val, ctx->regs + VIDINTCON0);
269 }
270 }
271
272 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
273 {
274 struct fimd_context *ctx = crtc->ctx;
275
276 if (ctx->suspended)
277 return;
278
279 atomic_set(&ctx->wait_vsync_event, 1);
280
281 /*
282 * wait for FIMD to signal VSYNC interrupt or return after
283 * timeout which is set to 50ms (refresh rate of 20).
284 */
285 if (!wait_event_timeout(ctx->wait_vsync_queue,
286 !atomic_read(&ctx->wait_vsync_event),
287 HZ/20))
288 DRM_DEBUG_KMS("vblank wait timed out.\n");
289 }
290
291 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
292 bool enable)
293 {
294 u32 val = readl(ctx->regs + WINCON(win));
295
296 if (enable)
297 val |= WINCONx_ENWIN;
298 else
299 val &= ~WINCONx_ENWIN;
300
301 writel(val, ctx->regs + WINCON(win));
302 }
303
304 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
305 unsigned int win,
306 bool enable)
307 {
308 u32 val = readl(ctx->regs + SHADOWCON);
309
310 if (enable)
311 val |= SHADOWCON_CHx_ENABLE(win);
312 else
313 val &= ~SHADOWCON_CHx_ENABLE(win);
314
315 writel(val, ctx->regs + SHADOWCON);
316 }
317
318 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
319 {
320 struct fimd_context *ctx = crtc->ctx;
321 unsigned int win, ch_enabled = 0;
322
323 DRM_DEBUG_KMS("%s\n", __FILE__);
324
325 /* Hardware is in unknown state, so ensure it gets enabled properly */
326 pm_runtime_get_sync(ctx->dev);
327
328 clk_prepare_enable(ctx->bus_clk);
329 clk_prepare_enable(ctx->lcd_clk);
330
331 /* Check if any channel is enabled. */
332 for (win = 0; win < WINDOWS_NR; win++) {
333 u32 val = readl(ctx->regs + WINCON(win));
334
335 if (val & WINCONx_ENWIN) {
336 fimd_enable_video_output(ctx, win, false);
337
338 if (ctx->driver_data->has_shadowcon)
339 fimd_enable_shadow_channel_path(ctx, win,
340 false);
341
342 ch_enabled = 1;
343 }
344 }
345
346 /* Wait for vsync, as disable channel takes effect at next vsync */
347 if (ch_enabled) {
348 int pipe = ctx->pipe;
349
350 /* ensure that vblank interrupt won't be reported to core */
351 ctx->suspended = false;
352 ctx->pipe = -1;
353
354 fimd_enable_vblank(ctx->crtc);
355 fimd_wait_for_vblank(ctx->crtc);
356 fimd_disable_vblank(ctx->crtc);
357
358 ctx->suspended = true;
359 ctx->pipe = pipe;
360 }
361
362 clk_disable_unprepare(ctx->lcd_clk);
363 clk_disable_unprepare(ctx->bus_clk);
364
365 pm_runtime_put(ctx->dev);
366 }
367
368 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
369 const struct drm_display_mode *mode)
370 {
371 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
372 u32 clkdiv;
373
374 if (ctx->i80_if) {
375 /*
376 * The frame done interrupt should be occurred prior to the
377 * next TE signal.
378 */
379 ideal_clk *= 2;
380 }
381
382 /* Find the clock divider value that gets us closest to ideal_clk */
383 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
384
385 return (clkdiv < 0x100) ? clkdiv : 0xff;
386 }
387
388 static void fimd_commit(struct exynos_drm_crtc *crtc)
389 {
390 struct fimd_context *ctx = crtc->ctx;
391 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
392 struct fimd_driver_data *driver_data = ctx->driver_data;
393 void *timing_base = ctx->regs + driver_data->timing_base;
394 u32 val, clkdiv;
395
396 if (ctx->suspended)
397 return;
398
399 /* nothing to do if we haven't set the mode yet */
400 if (mode->htotal == 0 || mode->vtotal == 0)
401 return;
402
403 if (ctx->i80_if) {
404 val = ctx->i80ifcon | I80IFEN_ENABLE;
405 writel(val, timing_base + I80IFCONFAx(0));
406
407 /* disable auto frame rate */
408 writel(0, timing_base + I80IFCONFBx(0));
409
410 /* set video type selection to I80 interface */
411 if (driver_data->has_vtsel && ctx->sysreg &&
412 regmap_update_bits(ctx->sysreg,
413 driver_data->lcdblk_offset,
414 0x3 << driver_data->lcdblk_vt_shift,
415 0x1 << driver_data->lcdblk_vt_shift)) {
416 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
417 return;
418 }
419 } else {
420 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
421 u32 vidcon1;
422
423 /* setup polarity values */
424 vidcon1 = ctx->vidcon1;
425 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
426 vidcon1 |= VIDCON1_INV_VSYNC;
427 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
428 vidcon1 |= VIDCON1_INV_HSYNC;
429 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
430
431 /* setup vertical timing values. */
432 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
433 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
434 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
435
436 val = VIDTCON0_VBPD(vbpd - 1) |
437 VIDTCON0_VFPD(vfpd - 1) |
438 VIDTCON0_VSPW(vsync_len - 1);
439 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
440
441 /* setup horizontal timing values. */
442 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
443 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
444 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
445
446 val = VIDTCON1_HBPD(hbpd - 1) |
447 VIDTCON1_HFPD(hfpd - 1) |
448 VIDTCON1_HSPW(hsync_len - 1);
449 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
450 }
451
452 if (driver_data->has_vidoutcon)
453 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
454
455 /* set bypass selection */
456 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
457 driver_data->lcdblk_offset,
458 0x1 << driver_data->lcdblk_bypass_shift,
459 0x1 << driver_data->lcdblk_bypass_shift)) {
460 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
461 return;
462 }
463
464 /* setup horizontal and vertical display size. */
465 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
466 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
467 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
468 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
469 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
470
471 /*
472 * fields of register with prefix '_F' would be updated
473 * at vsync(same as dma start)
474 */
475 val = ctx->vidcon0;
476 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
477
478 if (ctx->driver_data->has_clksel)
479 val |= VIDCON0_CLKSEL_LCD;
480
481 clkdiv = fimd_calc_clkdiv(ctx, mode);
482 if (clkdiv > 1)
483 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
484
485 writel(val, ctx->regs + VIDCON0);
486 }
487
488
489 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
490 uint32_t pixel_format, int width)
491 {
492 unsigned long val;
493
494 val = WINCONx_ENWIN;
495
496 /*
497 * In case of s3c64xx, window 0 doesn't support alpha channel.
498 * So the request format is ARGB8888 then change it to XRGB8888.
499 */
500 if (ctx->driver_data->has_limited_fmt && !win) {
501 if (pixel_format == DRM_FORMAT_ARGB8888)
502 pixel_format = DRM_FORMAT_XRGB8888;
503 }
504
505 switch (pixel_format) {
506 case DRM_FORMAT_C8:
507 val |= WINCON0_BPPMODE_8BPP_PALETTE;
508 val |= WINCONx_BURSTLEN_8WORD;
509 val |= WINCONx_BYTSWP;
510 break;
511 case DRM_FORMAT_XRGB1555:
512 val |= WINCON0_BPPMODE_16BPP_1555;
513 val |= WINCONx_HAWSWP;
514 val |= WINCONx_BURSTLEN_16WORD;
515 break;
516 case DRM_FORMAT_RGB565:
517 val |= WINCON0_BPPMODE_16BPP_565;
518 val |= WINCONx_HAWSWP;
519 val |= WINCONx_BURSTLEN_16WORD;
520 break;
521 case DRM_FORMAT_XRGB8888:
522 val |= WINCON0_BPPMODE_24BPP_888;
523 val |= WINCONx_WSWP;
524 val |= WINCONx_BURSTLEN_16WORD;
525 break;
526 case DRM_FORMAT_ARGB8888:
527 val |= WINCON1_BPPMODE_25BPP_A1888
528 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
529 val |= WINCONx_WSWP;
530 val |= WINCONx_BURSTLEN_16WORD;
531 break;
532 default:
533 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
534
535 val |= WINCON0_BPPMODE_24BPP_888;
536 val |= WINCONx_WSWP;
537 val |= WINCONx_BURSTLEN_16WORD;
538 break;
539 }
540
541 /*
542 * Setting dma-burst to 16Word causes permanent tearing for very small
543 * buffers, e.g. cursor buffer. Burst Mode switching which based on
544 * plane size is not recommended as plane size varies alot towards the
545 * end of the screen and rapid movement causes unstable DMA, but it is
546 * still better to change dma-burst than displaying garbage.
547 */
548
549 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
550 val &= ~WINCONx_BURSTLEN_MASK;
551 val |= WINCONx_BURSTLEN_4WORD;
552 }
553
554 writel(val, ctx->regs + WINCON(win));
555
556 /* hardware window 0 doesn't support alpha channel. */
557 if (win != 0) {
558 /* OSD alpha */
559 val = VIDISD14C_ALPHA0_R(0xf) |
560 VIDISD14C_ALPHA0_G(0xf) |
561 VIDISD14C_ALPHA0_B(0xf) |
562 VIDISD14C_ALPHA1_R(0xf) |
563 VIDISD14C_ALPHA1_G(0xf) |
564 VIDISD14C_ALPHA1_B(0xf);
565
566 writel(val, ctx->regs + VIDOSD_C(win));
567
568 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
569 VIDW_ALPHA_G(0xf);
570 writel(val, ctx->regs + VIDWnALPHA0(win));
571 writel(val, ctx->regs + VIDWnALPHA1(win));
572 }
573 }
574
575 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
576 {
577 unsigned int keycon0 = 0, keycon1 = 0;
578
579 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
580 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
581
582 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
583
584 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
585 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
586 }
587
588 /**
589 * shadow_protect_win() - disable updating values from shadow registers at vsync
590 *
591 * @win: window to protect registers for
592 * @protect: 1 to protect (disable updates)
593 */
594 static void fimd_shadow_protect_win(struct fimd_context *ctx,
595 unsigned int win, bool protect)
596 {
597 u32 reg, bits, val;
598
599 /*
600 * SHADOWCON/PRTCON register is used for enabling timing.
601 *
602 * for example, once only width value of a register is set,
603 * if the dma is started then fimd hardware could malfunction so
604 * with protect window setting, the register fields with prefix '_F'
605 * wouldn't be updated at vsync also but updated once unprotect window
606 * is set.
607 */
608
609 if (ctx->driver_data->has_shadowcon) {
610 reg = SHADOWCON;
611 bits = SHADOWCON_WINx_PROTECT(win);
612 } else {
613 reg = PRTCON;
614 bits = PRTCON_PROTECT;
615 }
616
617 val = readl(ctx->regs + reg);
618 if (protect)
619 val |= bits;
620 else
621 val &= ~bits;
622 writel(val, ctx->regs + reg);
623 }
624
625 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
626 {
627 struct fimd_context *ctx = crtc->ctx;
628 int i;
629
630 if (ctx->suspended)
631 return;
632
633 for (i = 0; i < WINDOWS_NR; i++)
634 fimd_shadow_protect_win(ctx, i, true);
635 }
636
637 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
638 {
639 struct fimd_context *ctx = crtc->ctx;
640 int i;
641
642 if (ctx->suspended)
643 return;
644
645 for (i = 0; i < WINDOWS_NR; i++)
646 fimd_shadow_protect_win(ctx, i, false);
647 }
648
649 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
650 struct exynos_drm_plane *plane)
651 {
652 struct exynos_drm_plane_state *state =
653 to_exynos_plane_state(plane->base.state);
654 struct fimd_context *ctx = crtc->ctx;
655 struct drm_framebuffer *fb = state->base.fb;
656 dma_addr_t dma_addr;
657 unsigned long val, size, offset;
658 unsigned int last_x, last_y, buf_offsize, line_size;
659 unsigned int win = plane->index;
660 unsigned int bpp = fb->bits_per_pixel >> 3;
661 unsigned int pitch = fb->pitches[0];
662
663 if (ctx->suspended)
664 return;
665
666 offset = state->src.x * bpp;
667 offset += state->src.y * pitch;
668
669 /* buffer start address */
670 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
671 val = (unsigned long)dma_addr;
672 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
673
674 /* buffer end address */
675 size = pitch * state->crtc.h;
676 val = (unsigned long)(dma_addr + size);
677 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
678
679 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
680 (unsigned long)dma_addr, val, size);
681 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
682 state->crtc.w, state->crtc.h);
683
684 /* buffer size */
685 buf_offsize = pitch - (state->crtc.w * bpp);
686 line_size = state->crtc.w * bpp;
687 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
688 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
689 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
690 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
691 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
692
693 /* OSD position */
694 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
695 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
696 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
697 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
698 writel(val, ctx->regs + VIDOSD_A(win));
699
700 last_x = state->crtc.x + state->crtc.w;
701 if (last_x)
702 last_x--;
703 last_y = state->crtc.y + state->crtc.h;
704 if (last_y)
705 last_y--;
706
707 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
708 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
709
710 writel(val, ctx->regs + VIDOSD_B(win));
711
712 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
713 state->crtc.x, state->crtc.y, last_x, last_y);
714
715 /* OSD size */
716 if (win != 3 && win != 4) {
717 u32 offset = VIDOSD_D(win);
718 if (win == 0)
719 offset = VIDOSD_C(win);
720 val = state->crtc.w * state->crtc.h;
721 writel(val, ctx->regs + offset);
722
723 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
724 }
725
726 fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w);
727
728 /* hardware window 0 doesn't support color key. */
729 if (win != 0)
730 fimd_win_set_colkey(ctx, win);
731
732 fimd_enable_video_output(ctx, win, true);
733
734 if (ctx->driver_data->has_shadowcon)
735 fimd_enable_shadow_channel_path(ctx, win, true);
736
737 if (ctx->i80_if)
738 atomic_set(&ctx->win_updated, 1);
739 }
740
741 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
742 struct exynos_drm_plane *plane)
743 {
744 struct fimd_context *ctx = crtc->ctx;
745 unsigned int win = plane->index;
746
747 if (ctx->suspended)
748 return;
749
750 fimd_enable_video_output(ctx, win, false);
751
752 if (ctx->driver_data->has_shadowcon)
753 fimd_enable_shadow_channel_path(ctx, win, false);
754 }
755
756 static void fimd_enable(struct exynos_drm_crtc *crtc)
757 {
758 struct fimd_context *ctx = crtc->ctx;
759
760 if (!ctx->suspended)
761 return;
762
763 ctx->suspended = false;
764
765 pm_runtime_get_sync(ctx->dev);
766
767 /* if vblank was enabled status, enable it again. */
768 if (test_and_clear_bit(0, &ctx->irq_flags))
769 fimd_enable_vblank(ctx->crtc);
770
771 fimd_commit(ctx->crtc);
772 }
773
774 static void fimd_disable(struct exynos_drm_crtc *crtc)
775 {
776 struct fimd_context *ctx = crtc->ctx;
777 int i;
778
779 if (ctx->suspended)
780 return;
781
782 /*
783 * We need to make sure that all windows are disabled before we
784 * suspend that connector. Otherwise we might try to scan from
785 * a destroyed buffer later.
786 */
787 for (i = 0; i < WINDOWS_NR; i++)
788 fimd_disable_plane(crtc, &ctx->planes[i]);
789
790 fimd_enable_vblank(crtc);
791 fimd_wait_for_vblank(crtc);
792 fimd_disable_vblank(crtc);
793
794 writel(0, ctx->regs + VIDCON0);
795
796 pm_runtime_put_sync(ctx->dev);
797 ctx->suspended = true;
798 }
799
800 static void fimd_trigger(struct device *dev)
801 {
802 struct fimd_context *ctx = dev_get_drvdata(dev);
803 struct fimd_driver_data *driver_data = ctx->driver_data;
804 void *timing_base = ctx->regs + driver_data->timing_base;
805 u32 reg;
806
807 /*
808 * Skips triggering if in triggering state, because multiple triggering
809 * requests can cause panel reset.
810 */
811 if (atomic_read(&ctx->triggering))
812 return;
813
814 /* Enters triggering mode */
815 atomic_set(&ctx->triggering, 1);
816
817 reg = readl(timing_base + TRIGCON);
818 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
819 writel(reg, timing_base + TRIGCON);
820
821 /*
822 * Exits triggering mode if vblank is not enabled yet, because when the
823 * VIDINTCON0 register is not set, it can not exit from triggering mode.
824 */
825 if (!test_bit(0, &ctx->irq_flags))
826 atomic_set(&ctx->triggering, 0);
827 }
828
829 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
830 {
831 struct fimd_context *ctx = crtc->ctx;
832
833 /* Checks the crtc is detached already from encoder */
834 if (ctx->pipe < 0 || !ctx->drm_dev)
835 return;
836
837 /*
838 * If there is a page flip request, triggers and handles the page flip
839 * event so that current fb can be updated into panel GRAM.
840 */
841 if (atomic_add_unless(&ctx->win_updated, -1, 0))
842 fimd_trigger(ctx->dev);
843
844 /* Wakes up vsync event queue */
845 if (atomic_read(&ctx->wait_vsync_event)) {
846 atomic_set(&ctx->wait_vsync_event, 0);
847 wake_up(&ctx->wait_vsync_queue);
848 }
849
850 if (test_bit(0, &ctx->irq_flags))
851 drm_crtc_handle_vblank(&ctx->crtc->base);
852 }
853
854 static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable)
855 {
856 struct fimd_context *ctx = crtc->ctx;
857 u32 val;
858
859 /*
860 * Only Exynos 5250, 5260, 5410 and 542x requires enabling DP/MIE
861 * clock. On these SoCs the bootloader may enable it but any
862 * power domain off/on will reset it to disable state.
863 */
864 if (ctx->driver_data != &exynos5_fimd_driver_data)
865 return;
866
867 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
868 writel(val, ctx->regs + DP_MIE_CLKCON);
869 }
870
871 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
872 .enable = fimd_enable,
873 .disable = fimd_disable,
874 .commit = fimd_commit,
875 .enable_vblank = fimd_enable_vblank,
876 .disable_vblank = fimd_disable_vblank,
877 .wait_for_vblank = fimd_wait_for_vblank,
878 .atomic_begin = fimd_atomic_begin,
879 .update_plane = fimd_update_plane,
880 .disable_plane = fimd_disable_plane,
881 .atomic_flush = fimd_atomic_flush,
882 .te_handler = fimd_te_handler,
883 .clock_enable = fimd_dp_clock_enable,
884 };
885
886 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
887 {
888 struct fimd_context *ctx = (struct fimd_context *)dev_id;
889 u32 val, clear_bit, start, start_s;
890 int win;
891
892 val = readl(ctx->regs + VIDINTCON1);
893
894 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
895 if (val & clear_bit)
896 writel(clear_bit, ctx->regs + VIDINTCON1);
897
898 /* check the crtc is detached already from encoder */
899 if (ctx->pipe < 0 || !ctx->drm_dev)
900 goto out;
901
902 if (!ctx->i80_if)
903 drm_crtc_handle_vblank(&ctx->crtc->base);
904
905 for (win = 0 ; win < WINDOWS_NR ; win++) {
906 struct exynos_drm_plane *plane = &ctx->planes[win];
907
908 if (!plane->pending_fb)
909 continue;
910
911 start = readl(ctx->regs + VIDWx_BUF_START(win, 0));
912 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0));
913 if (start == start_s)
914 exynos_drm_crtc_finish_update(ctx->crtc, plane);
915 }
916
917 if (ctx->i80_if) {
918 /* Exits triggering mode */
919 atomic_set(&ctx->triggering, 0);
920 } else {
921 /* set wait vsync event to zero and wake up queue. */
922 if (atomic_read(&ctx->wait_vsync_event)) {
923 atomic_set(&ctx->wait_vsync_event, 0);
924 wake_up(&ctx->wait_vsync_queue);
925 }
926 }
927
928 out:
929 return IRQ_HANDLED;
930 }
931
932 static int fimd_bind(struct device *dev, struct device *master, void *data)
933 {
934 struct fimd_context *ctx = dev_get_drvdata(dev);
935 struct drm_device *drm_dev = data;
936 struct exynos_drm_private *priv = drm_dev->dev_private;
937 struct exynos_drm_plane *exynos_plane;
938 unsigned int i;
939 int ret;
940
941 ctx->drm_dev = drm_dev;
942 ctx->pipe = priv->pipe++;
943
944 for (i = 0; i < WINDOWS_NR; i++) {
945 ctx->configs[i].pixel_formats = fimd_formats;
946 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
947 ctx->configs[i].zpos = i;
948 ctx->configs[i].type = fimd_win_types[i];
949 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
950 1 << ctx->pipe, &ctx->configs[i]);
951 if (ret)
952 return ret;
953 }
954
955 exynos_plane = &ctx->planes[DEFAULT_WIN];
956 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
957 ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
958 &fimd_crtc_ops, ctx);
959 if (IS_ERR(ctx->crtc))
960 return PTR_ERR(ctx->crtc);
961
962 if (ctx->encoder)
963 exynos_dpi_bind(drm_dev, ctx->encoder);
964
965 if (is_drm_iommu_supported(drm_dev))
966 fimd_clear_channels(ctx->crtc);
967
968 ret = drm_iommu_attach_device(drm_dev, dev);
969 if (ret)
970 priv->pipe--;
971
972 return ret;
973 }
974
975 static void fimd_unbind(struct device *dev, struct device *master,
976 void *data)
977 {
978 struct fimd_context *ctx = dev_get_drvdata(dev);
979
980 fimd_disable(ctx->crtc);
981
982 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
983
984 if (ctx->encoder)
985 exynos_dpi_remove(ctx->encoder);
986 }
987
988 static const struct component_ops fimd_component_ops = {
989 .bind = fimd_bind,
990 .unbind = fimd_unbind,
991 };
992
993 static int fimd_probe(struct platform_device *pdev)
994 {
995 struct device *dev = &pdev->dev;
996 struct fimd_context *ctx;
997 struct device_node *i80_if_timings;
998 struct resource *res;
999 int ret;
1000
1001 if (!dev->of_node)
1002 return -ENODEV;
1003
1004 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1005 if (!ctx)
1006 return -ENOMEM;
1007
1008 ctx->dev = dev;
1009 ctx->suspended = true;
1010 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1011
1012 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1013 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1014 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1015 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1016
1017 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1018 if (i80_if_timings) {
1019 u32 val;
1020
1021 ctx->i80_if = true;
1022
1023 if (ctx->driver_data->has_vidoutcon)
1024 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1025 else
1026 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1027 /*
1028 * The user manual describes that this "DSI_EN" bit is required
1029 * to enable I80 24-bit data interface.
1030 */
1031 ctx->vidcon0 |= VIDCON0_DSI_EN;
1032
1033 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1034 val = 0;
1035 ctx->i80ifcon = LCD_CS_SETUP(val);
1036 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1037 val = 0;
1038 ctx->i80ifcon |= LCD_WR_SETUP(val);
1039 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1040 val = 1;
1041 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1042 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1043 val = 0;
1044 ctx->i80ifcon |= LCD_WR_HOLD(val);
1045 }
1046 of_node_put(i80_if_timings);
1047
1048 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1049 "samsung,sysreg");
1050 if (IS_ERR(ctx->sysreg)) {
1051 dev_warn(dev, "failed to get system register.\n");
1052 ctx->sysreg = NULL;
1053 }
1054
1055 ctx->bus_clk = devm_clk_get(dev, "fimd");
1056 if (IS_ERR(ctx->bus_clk)) {
1057 dev_err(dev, "failed to get bus clock\n");
1058 return PTR_ERR(ctx->bus_clk);
1059 }
1060
1061 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1062 if (IS_ERR(ctx->lcd_clk)) {
1063 dev_err(dev, "failed to get lcd clock\n");
1064 return PTR_ERR(ctx->lcd_clk);
1065 }
1066
1067 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1068
1069 ctx->regs = devm_ioremap_resource(dev, res);
1070 if (IS_ERR(ctx->regs))
1071 return PTR_ERR(ctx->regs);
1072
1073 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1074 ctx->i80_if ? "lcd_sys" : "vsync");
1075 if (!res) {
1076 dev_err(dev, "irq request failed.\n");
1077 return -ENXIO;
1078 }
1079
1080 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1081 0, "drm_fimd", ctx);
1082 if (ret) {
1083 dev_err(dev, "irq request failed.\n");
1084 return ret;
1085 }
1086
1087 init_waitqueue_head(&ctx->wait_vsync_queue);
1088 atomic_set(&ctx->wait_vsync_event, 0);
1089
1090 platform_set_drvdata(pdev, ctx);
1091
1092 ctx->encoder = exynos_dpi_probe(dev);
1093 if (IS_ERR(ctx->encoder))
1094 return PTR_ERR(ctx->encoder);
1095
1096 pm_runtime_enable(dev);
1097
1098 ret = component_add(dev, &fimd_component_ops);
1099 if (ret)
1100 goto err_disable_pm_runtime;
1101
1102 return ret;
1103
1104 err_disable_pm_runtime:
1105 pm_runtime_disable(dev);
1106
1107 return ret;
1108 }
1109
1110 static int fimd_remove(struct platform_device *pdev)
1111 {
1112 pm_runtime_disable(&pdev->dev);
1113
1114 component_del(&pdev->dev, &fimd_component_ops);
1115
1116 return 0;
1117 }
1118
1119 #ifdef CONFIG_PM
1120 static int exynos_fimd_suspend(struct device *dev)
1121 {
1122 struct fimd_context *ctx = dev_get_drvdata(dev);
1123
1124 clk_disable_unprepare(ctx->lcd_clk);
1125 clk_disable_unprepare(ctx->bus_clk);
1126
1127 return 0;
1128 }
1129
1130 static int exynos_fimd_resume(struct device *dev)
1131 {
1132 struct fimd_context *ctx = dev_get_drvdata(dev);
1133 int ret;
1134
1135 ret = clk_prepare_enable(ctx->bus_clk);
1136 if (ret < 0) {
1137 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1138 return ret;
1139 }
1140
1141 ret = clk_prepare_enable(ctx->lcd_clk);
1142 if (ret < 0) {
1143 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1144 return ret;
1145 }
1146
1147 return 0;
1148 }
1149 #endif
1150
1151 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1152 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1153 };
1154
1155 struct platform_driver fimd_driver = {
1156 .probe = fimd_probe,
1157 .remove = fimd_remove,
1158 .driver = {
1159 .name = "exynos4-fb",
1160 .owner = THIS_MODULE,
1161 .pm = &exynos_fimd_pm_ops,
1162 .of_match_table = fimd_driver_dt_match,
1163 },
1164 };
Linux kernel - Deliverables
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