3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
22 #include <video/samsung_fimd.h>
23 #include <drm/exynos_drm.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_fbdev.h"
27 #include "exynos_drm_crtc.h"
30 * FIMD is stand for Fully Interactive Mobile Display and
31 * as a display controller, it transfers contents drawn on memory
32 * to a LCD Panel through Display Interfaces such as RGB or
36 /* position control register for hardware window 0, 2 ~ 4.*/
37 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
38 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
39 /* size control register for hardware window 0. */
40 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
41 /* alpha control register for hardware window 1 ~ 4. */
42 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
43 /* size control register for hardware window 1 ~ 4. */
44 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
46 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
47 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
48 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
50 /* color key control register for hardware window 1 ~ 4. */
51 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
52 /* color key value register for hardware window 1 ~ 4. */
53 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
55 /* FIMD has totally five hardware windows. */
58 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
60 struct fimd_driver_data
{
61 unsigned int timing_base
;
64 static struct fimd_driver_data exynos4_fimd_driver_data
= {
68 static struct fimd_driver_data exynos5_fimd_driver_data
= {
69 .timing_base
= 0x20000,
72 struct fimd_win_data
{
73 unsigned int offset_x
;
74 unsigned int offset_y
;
75 unsigned int ovl_width
;
76 unsigned int ovl_height
;
77 unsigned int fb_width
;
78 unsigned int fb_height
;
82 unsigned int buf_offsize
;
83 unsigned int line_size
; /* bytes */
88 struct exynos_drm_subdrv subdrv
;
90 struct drm_crtc
*crtc
;
94 struct fimd_win_data win_data
[WINDOWS_NR
];
96 unsigned int default_win
;
97 unsigned long irq_flags
;
103 struct exynos_drm_panel_info
*panel
;
106 static inline struct fimd_driver_data
*drm_fimd_get_driver_data(
107 struct platform_device
*pdev
)
109 return (struct fimd_driver_data
*)
110 platform_get_device_id(pdev
)->driver_data
;
113 static bool fimd_display_is_connected(struct device
*dev
)
115 DRM_DEBUG_KMS("%s\n", __FILE__
);
122 static void *fimd_get_panel(struct device
*dev
)
124 struct fimd_context
*ctx
= get_fimd_context(dev
);
126 DRM_DEBUG_KMS("%s\n", __FILE__
);
131 static int fimd_check_timing(struct device
*dev
, void *timing
)
133 DRM_DEBUG_KMS("%s\n", __FILE__
);
140 static int fimd_display_power_on(struct device
*dev
, int mode
)
142 DRM_DEBUG_KMS("%s\n", __FILE__
);
149 static struct exynos_drm_display_ops fimd_display_ops
= {
150 .type
= EXYNOS_DISPLAY_TYPE_LCD
,
151 .is_connected
= fimd_display_is_connected
,
152 .get_panel
= fimd_get_panel
,
153 .check_timing
= fimd_check_timing
,
154 .power_on
= fimd_display_power_on
,
157 static void fimd_dpms(struct device
*subdrv_dev
, int mode
)
159 struct fimd_context
*ctx
= get_fimd_context(subdrv_dev
);
161 DRM_DEBUG_KMS("%s, %d\n", __FILE__
, mode
);
163 mutex_lock(&ctx
->lock
);
166 case DRM_MODE_DPMS_ON
:
168 * enable fimd hardware only if suspended status.
170 * P.S. fimd_dpms function would be called at booting time so
171 * clk_enable could be called double time.
174 pm_runtime_get_sync(subdrv_dev
);
176 case DRM_MODE_DPMS_STANDBY
:
177 case DRM_MODE_DPMS_SUSPEND
:
178 case DRM_MODE_DPMS_OFF
:
180 pm_runtime_put_sync(subdrv_dev
);
183 DRM_DEBUG_KMS("unspecified mode %d\n", mode
);
187 mutex_unlock(&ctx
->lock
);
190 static void fimd_apply(struct device
*subdrv_dev
)
192 struct fimd_context
*ctx
= get_fimd_context(subdrv_dev
);
193 struct exynos_drm_manager
*mgr
= ctx
->subdrv
.manager
;
194 struct exynos_drm_manager_ops
*mgr_ops
= mgr
->ops
;
195 struct exynos_drm_overlay_ops
*ovl_ops
= mgr
->overlay_ops
;
196 struct fimd_win_data
*win_data
;
199 DRM_DEBUG_KMS("%s\n", __FILE__
);
201 for (i
= 0; i
< WINDOWS_NR
; i
++) {
202 win_data
= &ctx
->win_data
[i
];
203 if (win_data
->enabled
&& (ovl_ops
&& ovl_ops
->commit
))
204 ovl_ops
->commit(subdrv_dev
, i
);
207 if (mgr_ops
&& mgr_ops
->commit
)
208 mgr_ops
->commit(subdrv_dev
);
211 static void fimd_commit(struct device
*dev
)
213 struct fimd_context
*ctx
= get_fimd_context(dev
);
214 struct exynos_drm_panel_info
*panel
= ctx
->panel
;
215 struct fb_videomode
*timing
= &panel
->timing
;
216 struct fimd_driver_data
*driver_data
;
217 struct platform_device
*pdev
= to_platform_device(dev
);
220 driver_data
= drm_fimd_get_driver_data(pdev
);
224 DRM_DEBUG_KMS("%s\n", __FILE__
);
226 /* setup polarity values from machine code. */
227 writel(ctx
->vidcon1
, ctx
->regs
+ driver_data
->timing_base
+ VIDCON1
);
229 /* setup vertical timing values. */
230 val
= VIDTCON0_VBPD(timing
->upper_margin
- 1) |
231 VIDTCON0_VFPD(timing
->lower_margin
- 1) |
232 VIDTCON0_VSPW(timing
->vsync_len
- 1);
233 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON0
);
235 /* setup horizontal timing values. */
236 val
= VIDTCON1_HBPD(timing
->left_margin
- 1) |
237 VIDTCON1_HFPD(timing
->right_margin
- 1) |
238 VIDTCON1_HSPW(timing
->hsync_len
- 1);
239 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON1
);
241 /* setup horizontal and vertical display size. */
242 val
= VIDTCON2_LINEVAL(timing
->yres
- 1) |
243 VIDTCON2_HOZVAL(timing
->xres
- 1);
244 writel(val
, ctx
->regs
+ driver_data
->timing_base
+ VIDTCON2
);
246 /* setup clock source, clock divider, enable dma. */
248 val
&= ~(VIDCON0_CLKVAL_F_MASK
| VIDCON0_CLKDIR
);
251 val
|= VIDCON0_CLKVAL_F(ctx
->clkdiv
- 1) | VIDCON0_CLKDIR
;
253 val
&= ~VIDCON0_CLKDIR
; /* 1:1 clock */
256 * fields of register with prefix '_F' would be updated
257 * at vsync(same as dma start)
259 val
|= VIDCON0_ENVID
| VIDCON0_ENVID_F
;
260 writel(val
, ctx
->regs
+ VIDCON0
);
263 static int fimd_enable_vblank(struct device
*dev
)
265 struct fimd_context
*ctx
= get_fimd_context(dev
);
268 DRM_DEBUG_KMS("%s\n", __FILE__
);
273 if (!test_and_set_bit(0, &ctx
->irq_flags
)) {
274 val
= readl(ctx
->regs
+ VIDINTCON0
);
276 val
|= VIDINTCON0_INT_ENABLE
;
277 val
|= VIDINTCON0_INT_FRAME
;
279 val
&= ~VIDINTCON0_FRAMESEL0_MASK
;
280 val
|= VIDINTCON0_FRAMESEL0_VSYNC
;
281 val
&= ~VIDINTCON0_FRAMESEL1_MASK
;
282 val
|= VIDINTCON0_FRAMESEL1_NONE
;
284 writel(val
, ctx
->regs
+ VIDINTCON0
);
290 static void fimd_disable_vblank(struct device
*dev
)
292 struct fimd_context
*ctx
= get_fimd_context(dev
);
295 DRM_DEBUG_KMS("%s\n", __FILE__
);
300 if (test_and_clear_bit(0, &ctx
->irq_flags
)) {
301 val
= readl(ctx
->regs
+ VIDINTCON0
);
303 val
&= ~VIDINTCON0_INT_FRAME
;
304 val
&= ~VIDINTCON0_INT_ENABLE
;
306 writel(val
, ctx
->regs
+ VIDINTCON0
);
310 static struct exynos_drm_manager_ops fimd_manager_ops
= {
313 .commit
= fimd_commit
,
314 .enable_vblank
= fimd_enable_vblank
,
315 .disable_vblank
= fimd_disable_vblank
,
318 static void fimd_win_mode_set(struct device
*dev
,
319 struct exynos_drm_overlay
*overlay
)
321 struct fimd_context
*ctx
= get_fimd_context(dev
);
322 struct fimd_win_data
*win_data
;
324 unsigned long offset
;
326 DRM_DEBUG_KMS("%s\n", __FILE__
);
329 dev_err(dev
, "overlay is NULL\n");
334 if (win
== DEFAULT_ZPOS
)
335 win
= ctx
->default_win
;
337 if (win
< 0 || win
> WINDOWS_NR
)
340 offset
= overlay
->fb_x
* (overlay
->bpp
>> 3);
341 offset
+= overlay
->fb_y
* overlay
->pitch
;
343 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset
, overlay
->pitch
);
345 win_data
= &ctx
->win_data
[win
];
347 win_data
->offset_x
= overlay
->crtc_x
;
348 win_data
->offset_y
= overlay
->crtc_y
;
349 win_data
->ovl_width
= overlay
->crtc_width
;
350 win_data
->ovl_height
= overlay
->crtc_height
;
351 win_data
->fb_width
= overlay
->fb_width
;
352 win_data
->fb_height
= overlay
->fb_height
;
353 win_data
->dma_addr
= overlay
->dma_addr
[0] + offset
;
354 win_data
->vaddr
= overlay
->vaddr
[0] + offset
;
355 win_data
->bpp
= overlay
->bpp
;
356 win_data
->buf_offsize
= (overlay
->fb_width
- overlay
->crtc_width
) *
358 win_data
->line_size
= overlay
->crtc_width
* (overlay
->bpp
>> 3);
360 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
361 win_data
->offset_x
, win_data
->offset_y
);
362 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
363 win_data
->ovl_width
, win_data
->ovl_height
);
364 DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
365 (unsigned long)win_data
->dma_addr
,
366 (unsigned long)win_data
->vaddr
);
367 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
368 overlay
->fb_width
, overlay
->crtc_width
);
371 static void fimd_win_set_pixfmt(struct device
*dev
, unsigned int win
)
373 struct fimd_context
*ctx
= get_fimd_context(dev
);
374 struct fimd_win_data
*win_data
= &ctx
->win_data
[win
];
377 DRM_DEBUG_KMS("%s\n", __FILE__
);
381 switch (win_data
->bpp
) {
383 val
|= WINCON0_BPPMODE_1BPP
;
384 val
|= WINCONx_BITSWP
;
385 val
|= WINCONx_BURSTLEN_4WORD
;
388 val
|= WINCON0_BPPMODE_2BPP
;
389 val
|= WINCONx_BITSWP
;
390 val
|= WINCONx_BURSTLEN_8WORD
;
393 val
|= WINCON0_BPPMODE_4BPP
;
394 val
|= WINCONx_BITSWP
;
395 val
|= WINCONx_BURSTLEN_8WORD
;
398 val
|= WINCON0_BPPMODE_8BPP_PALETTE
;
399 val
|= WINCONx_BURSTLEN_8WORD
;
400 val
|= WINCONx_BYTSWP
;
403 val
|= WINCON0_BPPMODE_16BPP_565
;
404 val
|= WINCONx_HAWSWP
;
405 val
|= WINCONx_BURSTLEN_16WORD
;
408 val
|= WINCON0_BPPMODE_24BPP_888
;
410 val
|= WINCONx_BURSTLEN_16WORD
;
413 val
|= WINCON1_BPPMODE_28BPP_A4888
414 | WINCON1_BLD_PIX
| WINCON1_ALPHA_SEL
;
416 val
|= WINCONx_BURSTLEN_16WORD
;
419 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
421 val
|= WINCON0_BPPMODE_24BPP_888
;
423 val
|= WINCONx_BURSTLEN_16WORD
;
427 DRM_DEBUG_KMS("bpp = %d\n", win_data
->bpp
);
429 writel(val
, ctx
->regs
+ WINCON(win
));
432 static void fimd_win_set_colkey(struct device
*dev
, unsigned int win
)
434 struct fimd_context
*ctx
= get_fimd_context(dev
);
435 unsigned int keycon0
= 0, keycon1
= 0;
437 DRM_DEBUG_KMS("%s\n", __FILE__
);
439 keycon0
= ~(WxKEYCON0_KEYBL_EN
| WxKEYCON0_KEYEN_F
|
440 WxKEYCON0_DIRCON
) | WxKEYCON0_COMPKEY(0);
442 keycon1
= WxKEYCON1_COLVAL(0xffffffff);
444 writel(keycon0
, ctx
->regs
+ WKEYCON0_BASE(win
));
445 writel(keycon1
, ctx
->regs
+ WKEYCON1_BASE(win
));
448 static void fimd_win_commit(struct device
*dev
, int zpos
)
450 struct fimd_context
*ctx
= get_fimd_context(dev
);
451 struct fimd_win_data
*win_data
;
453 unsigned long val
, alpha
, size
;
455 DRM_DEBUG_KMS("%s\n", __FILE__
);
460 if (win
== DEFAULT_ZPOS
)
461 win
= ctx
->default_win
;
463 if (win
< 0 || win
> WINDOWS_NR
)
466 win_data
= &ctx
->win_data
[win
];
469 * SHADOWCON register is used for enabling timing.
471 * for example, once only width value of a register is set,
472 * if the dma is started then fimd hardware could malfunction so
473 * with protect window setting, the register fields with prefix '_F'
474 * wouldn't be updated at vsync also but updated once unprotect window
478 /* protect windows */
479 val
= readl(ctx
->regs
+ SHADOWCON
);
480 val
|= SHADOWCON_WINx_PROTECT(win
);
481 writel(val
, ctx
->regs
+ SHADOWCON
);
483 /* buffer start address */
484 val
= (unsigned long)win_data
->dma_addr
;
485 writel(val
, ctx
->regs
+ VIDWx_BUF_START(win
, 0));
487 /* buffer end address */
488 size
= win_data
->fb_width
* win_data
->ovl_height
* (win_data
->bpp
>> 3);
489 val
= (unsigned long)(win_data
->dma_addr
+ size
);
490 writel(val
, ctx
->regs
+ VIDWx_BUF_END(win
, 0));
492 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
493 (unsigned long)win_data
->dma_addr
, val
, size
);
494 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
495 win_data
->ovl_width
, win_data
->ovl_height
);
498 val
= VIDW_BUF_SIZE_OFFSET(win_data
->buf_offsize
) |
499 VIDW_BUF_SIZE_PAGEWIDTH(win_data
->line_size
);
500 writel(val
, ctx
->regs
+ VIDWx_BUF_SIZE(win
, 0));
503 val
= VIDOSDxA_TOPLEFT_X(win_data
->offset_x
) |
504 VIDOSDxA_TOPLEFT_Y(win_data
->offset_y
);
505 writel(val
, ctx
->regs
+ VIDOSD_A(win
));
507 val
= VIDOSDxB_BOTRIGHT_X(win_data
->offset_x
+
508 win_data
->ovl_width
- 1) |
509 VIDOSDxB_BOTRIGHT_Y(win_data
->offset_y
+
510 win_data
->ovl_height
- 1);
511 writel(val
, ctx
->regs
+ VIDOSD_B(win
));
513 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
514 win_data
->offset_x
, win_data
->offset_y
,
515 win_data
->offset_x
+ win_data
->ovl_width
- 1,
516 win_data
->offset_y
+ win_data
->ovl_height
- 1);
518 /* hardware window 0 doesn't support alpha channel. */
521 alpha
= VIDISD14C_ALPHA1_R(0xf) |
522 VIDISD14C_ALPHA1_G(0xf) |
523 VIDISD14C_ALPHA1_B(0xf);
525 writel(alpha
, ctx
->regs
+ VIDOSD_C(win
));
529 if (win
!= 3 && win
!= 4) {
530 u32 offset
= VIDOSD_D(win
);
532 offset
= VIDOSD_C_SIZE_W0
;
533 val
= win_data
->ovl_width
* win_data
->ovl_height
;
534 writel(val
, ctx
->regs
+ offset
);
536 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val
);
539 fimd_win_set_pixfmt(dev
, win
);
541 /* hardware window 0 doesn't support color key. */
543 fimd_win_set_colkey(dev
, win
);
546 val
= readl(ctx
->regs
+ WINCON(win
));
547 val
|= WINCONx_ENWIN
;
548 writel(val
, ctx
->regs
+ WINCON(win
));
550 /* Enable DMA channel and unprotect windows */
551 val
= readl(ctx
->regs
+ SHADOWCON
);
552 val
|= SHADOWCON_CHx_ENABLE(win
);
553 val
&= ~SHADOWCON_WINx_PROTECT(win
);
554 writel(val
, ctx
->regs
+ SHADOWCON
);
556 win_data
->enabled
= true;
559 static void fimd_win_disable(struct device
*dev
, int zpos
)
561 struct fimd_context
*ctx
= get_fimd_context(dev
);
562 struct fimd_win_data
*win_data
;
566 DRM_DEBUG_KMS("%s\n", __FILE__
);
568 if (win
== DEFAULT_ZPOS
)
569 win
= ctx
->default_win
;
571 if (win
< 0 || win
> WINDOWS_NR
)
574 win_data
= &ctx
->win_data
[win
];
576 /* protect windows */
577 val
= readl(ctx
->regs
+ SHADOWCON
);
578 val
|= SHADOWCON_WINx_PROTECT(win
);
579 writel(val
, ctx
->regs
+ SHADOWCON
);
582 val
= readl(ctx
->regs
+ WINCON(win
));
583 val
&= ~WINCONx_ENWIN
;
584 writel(val
, ctx
->regs
+ WINCON(win
));
586 /* unprotect windows */
587 val
= readl(ctx
->regs
+ SHADOWCON
);
588 val
&= ~SHADOWCON_CHx_ENABLE(win
);
589 val
&= ~SHADOWCON_WINx_PROTECT(win
);
590 writel(val
, ctx
->regs
+ SHADOWCON
);
592 win_data
->enabled
= false;
595 static void fimd_wait_for_vblank(struct device
*dev
)
597 struct fimd_context
*ctx
= get_fimd_context(dev
);
600 ret
= wait_for((__raw_readl(ctx
->regs
+ VIDCON1
) &
601 VIDCON1_VSTATUS_VSYNC
), 50);
603 DRM_DEBUG_KMS("vblank wait timed out.\n");
606 static struct exynos_drm_overlay_ops fimd_overlay_ops
= {
607 .mode_set
= fimd_win_mode_set
,
608 .commit
= fimd_win_commit
,
609 .disable
= fimd_win_disable
,
610 .wait_for_vblank
= fimd_wait_for_vblank
,
613 static struct exynos_drm_manager fimd_manager
= {
615 .ops
= &fimd_manager_ops
,
616 .overlay_ops
= &fimd_overlay_ops
,
617 .display_ops
= &fimd_display_ops
,
620 static void fimd_finish_pageflip(struct drm_device
*drm_dev
, int crtc
)
622 struct exynos_drm_private
*dev_priv
= drm_dev
->dev_private
;
623 struct drm_pending_vblank_event
*e
, *t
;
627 spin_lock_irqsave(&drm_dev
->event_lock
, flags
);
629 list_for_each_entry_safe(e
, t
, &dev_priv
->pageflip_event_list
,
631 /* if event's pipe isn't same as crtc then ignore it. */
635 do_gettimeofday(&now
);
636 e
->event
.sequence
= 0;
637 e
->event
.tv_sec
= now
.tv_sec
;
638 e
->event
.tv_usec
= now
.tv_usec
;
640 list_move_tail(&e
->base
.link
, &e
->base
.file_priv
->event_list
);
641 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
642 drm_vblank_put(drm_dev
, crtc
);
645 spin_unlock_irqrestore(&drm_dev
->event_lock
, flags
);
648 static irqreturn_t
fimd_irq_handler(int irq
, void *dev_id
)
650 struct fimd_context
*ctx
= (struct fimd_context
*)dev_id
;
651 struct exynos_drm_subdrv
*subdrv
= &ctx
->subdrv
;
652 struct drm_device
*drm_dev
= subdrv
->drm_dev
;
653 struct exynos_drm_manager
*manager
= subdrv
->manager
;
656 val
= readl(ctx
->regs
+ VIDINTCON1
);
658 if (val
& VIDINTCON1_INT_FRAME
)
659 /* VSYNC interrupt */
660 writel(VIDINTCON1_INT_FRAME
, ctx
->regs
+ VIDINTCON1
);
662 /* check the crtc is detached already from encoder */
663 if (manager
->pipe
< 0)
666 drm_handle_vblank(drm_dev
, manager
->pipe
);
667 fimd_finish_pageflip(drm_dev
, manager
->pipe
);
673 static int fimd_subdrv_probe(struct drm_device
*drm_dev
, struct device
*dev
)
675 DRM_DEBUG_KMS("%s\n", __FILE__
);
678 * enable drm irq mode.
679 * - with irq_enabled = 1, we can use the vblank feature.
681 * P.S. note that we wouldn't use drm irq handler but
682 * just specific driver own one instead because
683 * drm framework supports only one irq handler.
685 drm_dev
->irq_enabled
= 1;
688 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
689 * by drm timer once a current process gives up ownership of
690 * vblank event.(after drm_vblank_put function is called)
692 drm_dev
->vblank_disable_allowed
= 1;
697 static void fimd_subdrv_remove(struct drm_device
*drm_dev
, struct device
*dev
)
699 DRM_DEBUG_KMS("%s\n", __FILE__
);
704 static int fimd_calc_clkdiv(struct fimd_context
*ctx
,
705 struct fb_videomode
*timing
)
707 unsigned long clk
= clk_get_rate(ctx
->lcd_clk
);
710 u32 best_framerate
= 0;
713 DRM_DEBUG_KMS("%s\n", __FILE__
);
715 retrace
= timing
->left_margin
+ timing
->hsync_len
+
716 timing
->right_margin
+ timing
->xres
;
717 retrace
*= timing
->upper_margin
+ timing
->vsync_len
+
718 timing
->lower_margin
+ timing
->yres
;
720 /* default framerate is 60Hz */
721 if (!timing
->refresh
)
722 timing
->refresh
= 60;
726 for (clkdiv
= 1; clkdiv
< 0x100; clkdiv
++) {
729 /* get best framerate */
730 framerate
= clk
/ clkdiv
;
731 tmp
= timing
->refresh
- framerate
;
733 best_framerate
= framerate
;
737 best_framerate
= framerate
;
738 else if (tmp
< (best_framerate
- framerate
))
739 best_framerate
= framerate
;
747 static void fimd_clear_win(struct fimd_context
*ctx
, int win
)
751 DRM_DEBUG_KMS("%s\n", __FILE__
);
753 writel(0, ctx
->regs
+ WINCON(win
));
754 writel(0, ctx
->regs
+ VIDOSD_A(win
));
755 writel(0, ctx
->regs
+ VIDOSD_B(win
));
756 writel(0, ctx
->regs
+ VIDOSD_C(win
));
758 if (win
== 1 || win
== 2)
759 writel(0, ctx
->regs
+ VIDOSD_D(win
));
761 val
= readl(ctx
->regs
+ SHADOWCON
);
762 val
&= ~SHADOWCON_WINx_PROTECT(win
);
763 writel(val
, ctx
->regs
+ SHADOWCON
);
766 static int fimd_clock(struct fimd_context
*ctx
, bool enable
)
768 DRM_DEBUG_KMS("%s\n", __FILE__
);
773 ret
= clk_enable(ctx
->bus_clk
);
777 ret
= clk_enable(ctx
->lcd_clk
);
779 clk_disable(ctx
->bus_clk
);
783 clk_disable(ctx
->lcd_clk
);
784 clk_disable(ctx
->bus_clk
);
790 static int fimd_activate(struct fimd_context
*ctx
, bool enable
)
794 struct device
*dev
= ctx
->subdrv
.dev
;
796 ret
= fimd_clock(ctx
, true);
800 ctx
->suspended
= false;
802 /* if vblank was enabled status, enable it again. */
803 if (test_and_clear_bit(0, &ctx
->irq_flags
))
804 fimd_enable_vblank(dev
);
806 fimd_clock(ctx
, false);
807 ctx
->suspended
= true;
813 static int __devinit
fimd_probe(struct platform_device
*pdev
)
815 struct device
*dev
= &pdev
->dev
;
816 struct fimd_context
*ctx
;
817 struct exynos_drm_subdrv
*subdrv
;
818 struct exynos_drm_fimd_pdata
*pdata
;
819 struct exynos_drm_panel_info
*panel
;
820 struct resource
*res
;
824 DRM_DEBUG_KMS("%s\n", __FILE__
);
826 pdata
= pdev
->dev
.platform_data
;
828 dev_err(dev
, "no platform data specified\n");
832 panel
= &pdata
->panel
;
834 dev_err(dev
, "panel is null.\n");
838 ctx
= devm_kzalloc(&pdev
->dev
, sizeof(*ctx
), GFP_KERNEL
);
842 ctx
->bus_clk
= clk_get(dev
, "fimd");
843 if (IS_ERR(ctx
->bus_clk
)) {
844 dev_err(dev
, "failed to get bus clock\n");
845 ret
= PTR_ERR(ctx
->bus_clk
);
849 ctx
->lcd_clk
= clk_get(dev
, "sclk_fimd");
850 if (IS_ERR(ctx
->lcd_clk
)) {
851 dev_err(dev
, "failed to get lcd clock\n");
852 ret
= PTR_ERR(ctx
->lcd_clk
);
856 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
858 ctx
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
860 dev_err(dev
, "failed to map registers\n");
865 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
867 dev_err(dev
, "irq request failed.\n");
871 ctx
->irq
= res
->start
;
873 ret
= devm_request_irq(&pdev
->dev
, ctx
->irq
, fimd_irq_handler
,
876 dev_err(dev
, "irq request failed.\n");
880 ctx
->vidcon0
= pdata
->vidcon0
;
881 ctx
->vidcon1
= pdata
->vidcon1
;
882 ctx
->default_win
= pdata
->default_win
;
885 subdrv
= &ctx
->subdrv
;
888 subdrv
->manager
= &fimd_manager
;
889 subdrv
->probe
= fimd_subdrv_probe
;
890 subdrv
->remove
= fimd_subdrv_remove
;
892 mutex_init(&ctx
->lock
);
894 platform_set_drvdata(pdev
, ctx
);
896 pm_runtime_enable(dev
);
897 pm_runtime_get_sync(dev
);
899 ctx
->clkdiv
= fimd_calc_clkdiv(ctx
, &panel
->timing
);
900 panel
->timing
.pixclock
= clk_get_rate(ctx
->lcd_clk
) / ctx
->clkdiv
;
902 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
903 panel
->timing
.pixclock
, ctx
->clkdiv
);
905 for (win
= 0; win
< WINDOWS_NR
; win
++)
906 fimd_clear_win(ctx
, win
);
908 exynos_drm_subdrv_register(subdrv
);
913 clk_disable(ctx
->lcd_clk
);
914 clk_put(ctx
->lcd_clk
);
917 clk_disable(ctx
->bus_clk
);
918 clk_put(ctx
->bus_clk
);
924 static int __devexit
fimd_remove(struct platform_device
*pdev
)
926 struct device
*dev
= &pdev
->dev
;
927 struct fimd_context
*ctx
= platform_get_drvdata(pdev
);
929 DRM_DEBUG_KMS("%s\n", __FILE__
);
931 exynos_drm_subdrv_unregister(&ctx
->subdrv
);
936 clk_disable(ctx
->lcd_clk
);
937 clk_disable(ctx
->bus_clk
);
939 pm_runtime_set_suspended(dev
);
940 pm_runtime_put_sync(dev
);
943 pm_runtime_disable(dev
);
945 clk_put(ctx
->lcd_clk
);
946 clk_put(ctx
->bus_clk
);
951 #ifdef CONFIG_PM_SLEEP
952 static int fimd_suspend(struct device
*dev
)
954 struct fimd_context
*ctx
= get_fimd_context(dev
);
957 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
958 * called here, an error would be returned by that interface
959 * because the usage_count of pm runtime is more than 1.
961 if (!pm_runtime_suspended(dev
))
962 return fimd_activate(ctx
, false);
967 static int fimd_resume(struct device
*dev
)
969 struct fimd_context
*ctx
= get_fimd_context(dev
);
972 * if entered to sleep when lcd panel was on, the usage_count
973 * of pm runtime would still be 1 so in this case, fimd driver
974 * should be on directly not drawing on pm runtime interface.
976 if (pm_runtime_suspended(dev
)) {
979 ret
= fimd_activate(ctx
, true);
984 * in case of dpms on(standby), fimd_apply function will
985 * be called by encoder's dpms callback to update fimd's
986 * registers but in case of sleep wakeup, it's not.
987 * so fimd_apply function should be called at here.
996 #ifdef CONFIG_PM_RUNTIME
997 static int fimd_runtime_suspend(struct device
*dev
)
999 struct fimd_context
*ctx
= get_fimd_context(dev
);
1001 DRM_DEBUG_KMS("%s\n", __FILE__
);
1003 return fimd_activate(ctx
, false);
1006 static int fimd_runtime_resume(struct device
*dev
)
1008 struct fimd_context
*ctx
= get_fimd_context(dev
);
1010 DRM_DEBUG_KMS("%s\n", __FILE__
);
1012 return fimd_activate(ctx
, true);
1016 static struct platform_device_id fimd_driver_ids
[] = {
1018 .name
= "exynos4-fb",
1019 .driver_data
= (unsigned long)&exynos4_fimd_driver_data
,
1021 .name
= "exynos5-fb",
1022 .driver_data
= (unsigned long)&exynos5_fimd_driver_data
,
1026 MODULE_DEVICE_TABLE(platform
, fimd_driver_ids
);
1028 static const struct dev_pm_ops fimd_pm_ops
= {
1029 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend
, fimd_resume
)
1030 SET_RUNTIME_PM_OPS(fimd_runtime_suspend
, fimd_runtime_resume
, NULL
)
1033 struct platform_driver fimd_driver
= {
1034 .probe
= fimd_probe
,
1035 .remove
= __devexit_p(fimd_remove
),
1036 .id_table
= fimd_driver_ids
,
1038 .name
= "exynos4-fb",
1039 .owner
= THIS_MODULE
,