2 * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver
4 * Copyright (c) 2016 Linaro Limited.
5 * Copyright (c) 2014-2016 Hisilicon Limited.
8 * Xinliang Liu <z.liuxinliang@hisilicon.com>
9 * Xinliang Liu <xinliang.liu@linaro.org>
10 * Xinwei Kong <kong.kongxinwei@hisilicon.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <video/display_timing.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_plane_helper.h>
31 #include <drm/drm_gem_cma_helper.h>
32 #include <drm/drm_fb_cma_helper.h>
34 #include "kirin_drm_drv.h"
35 #include "kirin_ade_reg.h"
37 #define PRIMARY_CH ADE_CH1 /* primary plane */
38 #define OUT_OVLY ADE_OVLY2 /* output overlay compositor */
41 #define to_ade_crtc(crtc) \
42 container_of(crtc, struct ade_crtc, base)
44 #define to_ade_plane(plane) \
45 container_of(plane, struct ade_plane, base)
49 struct regmap
*noc_regmap
;
50 struct clk
*ade_core_clk
;
51 struct clk
*media_noc_clk
;
52 struct clk
*ade_pix_clk
;
53 struct reset_control
*reset
;
60 struct ade_hw_ctx
*ctx
;
66 struct drm_plane base
;
72 struct ade_crtc acrtc
;
73 struct ade_plane aplane
[ADE_CH_NUM
];
74 struct ade_hw_ctx ctx
;
77 /* ade-format info: */
80 enum ade_fb_format ade_format
;
83 static const struct ade_format ade_formats
[] = {
85 { DRM_FORMAT_RGB565
, ADE_RGB_565
},
86 { DRM_FORMAT_BGR565
, ADE_BGR_565
},
88 { DRM_FORMAT_RGB888
, ADE_RGB_888
},
89 { DRM_FORMAT_BGR888
, ADE_BGR_888
},
91 { DRM_FORMAT_XRGB8888
, ADE_XRGB_8888
},
92 { DRM_FORMAT_XBGR8888
, ADE_XBGR_8888
},
93 { DRM_FORMAT_RGBA8888
, ADE_RGBA_8888
},
94 { DRM_FORMAT_BGRA8888
, ADE_BGRA_8888
},
95 { DRM_FORMAT_ARGB8888
, ADE_ARGB_8888
},
96 { DRM_FORMAT_ABGR8888
, ADE_ABGR_8888
},
99 static const u32 channel_formats1
[] = {
100 /* channel 1,2,3,4 */
101 DRM_FORMAT_RGB565
, DRM_FORMAT_BGR565
, DRM_FORMAT_RGB888
,
102 DRM_FORMAT_BGR888
, DRM_FORMAT_XRGB8888
, DRM_FORMAT_XBGR8888
,
103 DRM_FORMAT_RGBA8888
, DRM_FORMAT_BGRA8888
, DRM_FORMAT_ARGB8888
,
107 u32
ade_get_channel_formats(u8 ch
, const u32
**formats
)
111 *formats
= channel_formats1
;
112 return ARRAY_SIZE(channel_formats1
);
114 DRM_ERROR("no this channel %d\n", ch
);
120 /* convert from fourcc format to ade format */
121 static u32
ade_get_format(u32 pixel_format
)
125 for (i
= 0; i
< ARRAY_SIZE(ade_formats
); i
++)
126 if (ade_formats
[i
].pixel_format
== pixel_format
)
127 return ade_formats
[i
].ade_format
;
130 DRM_ERROR("Not found pixel format!!fourcc_format= %d\n",
132 return ADE_FORMAT_UNSUPPORT
;
135 static void ade_update_reload_bit(void __iomem
*base
, u32 bit_num
, u32 val
)
137 u32 bit_ofst
, reg_num
;
139 bit_ofst
= bit_num
% 32;
140 reg_num
= bit_num
/ 32;
142 ade_update_bits(base
+ ADE_RELOAD_DIS(reg_num
), bit_ofst
,
146 static u32
ade_read_reload_bit(void __iomem
*base
, u32 bit_num
)
148 u32 tmp
, bit_ofst
, reg_num
;
150 bit_ofst
= bit_num
% 32;
151 reg_num
= bit_num
/ 32;
153 tmp
= readl(base
+ ADE_RELOAD_DIS(reg_num
));
154 return !!(BIT(bit_ofst
) & tmp
);
157 static void ade_init(struct ade_hw_ctx
*ctx
)
159 void __iomem
*base
= ctx
->base
;
161 /* enable clk gate */
162 ade_update_bits(base
+ ADE_CTRL1
, AUTO_CLK_GATE_EN_OFST
,
163 AUTO_CLK_GATE_EN
, ADE_ENABLE
);
165 writel(0, base
+ ADE_OVLY1_TRANS_CFG
);
166 writel(0, base
+ ADE_OVLY_CTL
);
167 writel(0, base
+ ADE_OVLYX_CTL(OUT_OVLY
));
168 /* clear reset and reload regs */
169 writel(MASK(32), base
+ ADE_SOFT_RST_SEL(0));
170 writel(MASK(32), base
+ ADE_SOFT_RST_SEL(1));
171 writel(MASK(32), base
+ ADE_RELOAD_DIS(0));
172 writel(MASK(32), base
+ ADE_RELOAD_DIS(1));
174 * for video mode, all the ade registers should
175 * become effective at frame end.
177 ade_update_bits(base
+ ADE_CTRL
, FRM_END_START_OFST
,
178 FRM_END_START_MASK
, REG_EFFECTIVE_IN_ADEEN_FRMEND
);
181 static void ade_set_pix_clk(struct ade_hw_ctx
*ctx
,
182 struct drm_display_mode
*mode
,
183 struct drm_display_mode
*adj_mode
)
185 u32 clk_Hz
= mode
->clock
* 1000;
189 * Success should be guaranteed in mode_valid call back,
190 * so failure shouldn't happen here
192 ret
= clk_set_rate(ctx
->ade_pix_clk
, clk_Hz
);
194 DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz
, ret
);
195 adj_mode
->clock
= clk_get_rate(ctx
->ade_pix_clk
) / 1000;
198 static void ade_ldi_set_mode(struct ade_crtc
*acrtc
,
199 struct drm_display_mode
*mode
,
200 struct drm_display_mode
*adj_mode
)
202 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
203 void __iomem
*base
= ctx
->base
;
204 u32 width
= mode
->hdisplay
;
205 u32 height
= mode
->vdisplay
;
206 u32 hfp
, hbp
, hsw
, vfp
, vbp
, vsw
;
209 plr_flags
= (mode
->flags
& DRM_MODE_FLAG_NVSYNC
) ? FLAG_NVSYNC
: 0;
210 plr_flags
|= (mode
->flags
& DRM_MODE_FLAG_NHSYNC
) ? FLAG_NHSYNC
: 0;
211 hfp
= mode
->hsync_start
- mode
->hdisplay
;
212 hbp
= mode
->htotal
- mode
->hsync_end
;
213 hsw
= mode
->hsync_end
- mode
->hsync_start
;
214 vfp
= mode
->vsync_start
- mode
->vdisplay
;
215 vbp
= mode
->vtotal
- mode
->vsync_end
;
216 vsw
= mode
->vsync_end
- mode
->vsync_start
;
218 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
222 writel((hbp
<< HBP_OFST
) | hfp
, base
+ LDI_HRZ_CTRL0
);
223 /* the configured value is actual value - 1 */
224 writel(hsw
- 1, base
+ LDI_HRZ_CTRL1
);
225 writel((vbp
<< VBP_OFST
) | vfp
, base
+ LDI_VRT_CTRL0
);
226 /* the configured value is actual value - 1 */
227 writel(vsw
- 1, base
+ LDI_VRT_CTRL1
);
228 /* the configured value is actual value - 1 */
229 writel(((height
- 1) << VSIZE_OFST
) | (width
- 1),
230 base
+ LDI_DSP_SIZE
);
231 writel(plr_flags
, base
+ LDI_PLR_CTRL
);
233 /* set overlay compositor output size */
234 writel(((width
- 1) << OUTPUT_XSIZE_OFST
) | (height
- 1),
235 base
+ ADE_OVLY_OUTPUT_SIZE(OUT_OVLY
));
238 writel(CTRAN_BYPASS_ON
, base
+ ADE_CTRAN_DIS(ADE_CTRAN6
));
239 /* the configured value is actual value - 1 */
240 writel(width
* height
- 1, base
+ ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6
));
241 ade_update_reload_bit(base
, CTRAN_OFST
+ ADE_CTRAN6
, 0);
243 ade_set_pix_clk(ctx
, mode
, adj_mode
);
245 DRM_DEBUG_DRIVER("set mode: %dx%d\n", width
, height
);
248 static int ade_power_up(struct ade_hw_ctx
*ctx
)
252 ret
= clk_prepare_enable(ctx
->media_noc_clk
);
254 DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret
);
258 ret
= reset_control_deassert(ctx
->reset
);
260 DRM_ERROR("failed to deassert reset\n");
264 ret
= clk_prepare_enable(ctx
->ade_core_clk
);
266 DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret
);
271 ctx
->power_on
= true;
275 static void ade_power_down(struct ade_hw_ctx
*ctx
)
277 void __iomem
*base
= ctx
->base
;
279 writel(ADE_DISABLE
, base
+ LDI_CTRL
);
281 writel(DSI_PCLK_OFF
, base
+ LDI_HDMI_DSI_GT
);
283 clk_disable_unprepare(ctx
->ade_core_clk
);
284 reset_control_assert(ctx
->reset
);
285 clk_disable_unprepare(ctx
->media_noc_clk
);
286 ctx
->power_on
= false;
289 static void ade_set_medianoc_qos(struct ade_crtc
*acrtc
)
291 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
292 struct regmap
*map
= ctx
->noc_regmap
;
294 regmap_update_bits(map
, ADE0_QOSGENERATOR_MODE
,
295 QOSGENERATOR_MODE_MASK
, BYPASS_MODE
);
296 regmap_update_bits(map
, ADE0_QOSGENERATOR_EXTCONTROL
,
297 SOCKET_QOS_EN
, SOCKET_QOS_EN
);
299 regmap_update_bits(map
, ADE1_QOSGENERATOR_MODE
,
300 QOSGENERATOR_MODE_MASK
, BYPASS_MODE
);
301 regmap_update_bits(map
, ADE1_QOSGENERATOR_EXTCONTROL
,
302 SOCKET_QOS_EN
, SOCKET_QOS_EN
);
305 static int ade_enable_vblank(struct drm_device
*dev
, unsigned int pipe
)
307 struct kirin_drm_private
*priv
= dev
->dev_private
;
308 struct ade_crtc
*acrtc
= to_ade_crtc(priv
->crtc
[pipe
]);
309 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
310 void __iomem
*base
= ctx
->base
;
313 (void)ade_power_up(ctx
);
315 ade_update_bits(base
+ LDI_INT_EN
, FRAME_END_INT_EN_OFST
,
321 static void ade_disable_vblank(struct drm_device
*dev
, unsigned int pipe
)
323 struct kirin_drm_private
*priv
= dev
->dev_private
;
324 struct ade_crtc
*acrtc
= to_ade_crtc(priv
->crtc
[pipe
]);
325 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
326 void __iomem
*base
= ctx
->base
;
328 if (!ctx
->power_on
) {
329 DRM_ERROR("power is down! vblank disable fail\n");
333 ade_update_bits(base
+ LDI_INT_EN
, FRAME_END_INT_EN_OFST
,
337 static irqreturn_t
ade_irq_handler(int irq
, void *data
)
339 struct ade_crtc
*acrtc
= data
;
340 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
341 struct drm_crtc
*crtc
= &acrtc
->base
;
342 void __iomem
*base
= ctx
->base
;
345 status
= readl(base
+ LDI_MSK_INT
);
346 DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status
);
349 if (status
& BIT(FRAME_END_INT_EN_OFST
)) {
350 ade_update_bits(base
+ LDI_INT_CLR
, FRAME_END_INT_EN_OFST
,
352 drm_crtc_handle_vblank(crtc
);
358 static void ade_display_enable(struct ade_crtc
*acrtc
)
360 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
361 void __iomem
*base
= ctx
->base
;
362 u32 out_fmt
= acrtc
->out_format
;
364 /* enable output overlay compositor */
365 writel(ADE_ENABLE
, base
+ ADE_OVLYX_CTL(OUT_OVLY
));
366 ade_update_reload_bit(base
, OVLY_OFST
+ OUT_OVLY
, 0);
368 /* display source setting */
369 writel(DISP_SRC_OVLY2
, base
+ ADE_DISP_SRC_CFG
);
372 writel(ADE_ENABLE
, base
+ ADE_EN
);
374 writel(NORMAL_MODE
, base
+ LDI_WORK_MODE
);
375 writel((out_fmt
<< BPP_OFST
) | DATA_GATE_EN
| LDI_EN
,
378 writel(DSI_PCLK_ON
, base
+ LDI_HDMI_DSI_GT
);
382 static void ade_rdma_dump_regs(void __iomem
*base
, u32 ch
)
384 u32 reg_ctrl
, reg_addr
, reg_size
, reg_stride
, reg_space
, reg_en
;
387 reg_ctrl
= RD_CH_CTRL(ch
);
388 reg_addr
= RD_CH_ADDR(ch
);
389 reg_size
= RD_CH_SIZE(ch
);
390 reg_stride
= RD_CH_STRIDE(ch
);
391 reg_space
= RD_CH_SPACE(ch
);
392 reg_en
= RD_CH_EN(ch
);
394 val
= ade_read_reload_bit(base
, RDMA_OFST
+ ch
);
395 DRM_DEBUG_DRIVER("[rdma%d]: reload(%d)\n", ch
+ 1, val
);
396 val
= readl(base
+ reg_ctrl
);
397 DRM_DEBUG_DRIVER("[rdma%d]: reg_ctrl(0x%08x)\n", ch
+ 1, val
);
398 val
= readl(base
+ reg_addr
);
399 DRM_DEBUG_DRIVER("[rdma%d]: reg_addr(0x%08x)\n", ch
+ 1, val
);
400 val
= readl(base
+ reg_size
);
401 DRM_DEBUG_DRIVER("[rdma%d]: reg_size(0x%08x)\n", ch
+ 1, val
);
402 val
= readl(base
+ reg_stride
);
403 DRM_DEBUG_DRIVER("[rdma%d]: reg_stride(0x%08x)\n", ch
+ 1, val
);
404 val
= readl(base
+ reg_space
);
405 DRM_DEBUG_DRIVER("[rdma%d]: reg_space(0x%08x)\n", ch
+ 1, val
);
406 val
= readl(base
+ reg_en
);
407 DRM_DEBUG_DRIVER("[rdma%d]: reg_en(0x%08x)\n", ch
+ 1, val
);
410 static void ade_clip_dump_regs(void __iomem
*base
, u32 ch
)
414 val
= ade_read_reload_bit(base
, CLIP_OFST
+ ch
);
415 DRM_DEBUG_DRIVER("[clip%d]: reload(%d)\n", ch
+ 1, val
);
416 val
= readl(base
+ ADE_CLIP_DISABLE(ch
));
417 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_disable(0x%08x)\n", ch
+ 1, val
);
418 val
= readl(base
+ ADE_CLIP_SIZE0(ch
));
419 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size0(0x%08x)\n", ch
+ 1, val
);
420 val
= readl(base
+ ADE_CLIP_SIZE1(ch
));
421 DRM_DEBUG_DRIVER("[clip%d]: reg_clip_size1(0x%08x)\n", ch
+ 1, val
);
424 static void ade_compositor_routing_dump_regs(void __iomem
*base
, u32 ch
)
426 u8 ovly_ch
= 0; /* TODO: Only primary plane now */
429 val
= readl(base
+ ADE_OVLY_CH_XY0(ovly_ch
));
430 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy0(0x%08x)\n", ovly_ch
, val
);
431 val
= readl(base
+ ADE_OVLY_CH_XY1(ovly_ch
));
432 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_xy1(0x%08x)\n", ovly_ch
, val
);
433 val
= readl(base
+ ADE_OVLY_CH_CTL(ovly_ch
));
434 DRM_DEBUG_DRIVER("[overlay ch%d]: reg_ch_ctl(0x%08x)\n", ovly_ch
, val
);
437 static void ade_dump_overlay_compositor_regs(void __iomem
*base
, u32 comp
)
441 val
= ade_read_reload_bit(base
, OVLY_OFST
+ comp
);
442 DRM_DEBUG_DRIVER("[overlay%d]: reload(%d)\n", comp
+ 1, val
);
443 writel(ADE_ENABLE
, base
+ ADE_OVLYX_CTL(comp
));
444 DRM_DEBUG_DRIVER("[overlay%d]: reg_ctl(0x%08x)\n", comp
+ 1, val
);
445 val
= readl(base
+ ADE_OVLY_CTL
);
446 DRM_DEBUG_DRIVER("ovly_ctl(0x%08x)\n", val
);
449 static void ade_dump_regs(void __iomem
*base
)
453 /* dump channel regs */
454 for (i
= 0; i
< ADE_CH_NUM
; i
++) {
456 ade_rdma_dump_regs(base
, i
);
459 ade_clip_dump_regs(base
, i
);
461 /* dump compositor routing regs */
462 ade_compositor_routing_dump_regs(base
, i
);
465 /* dump overlay compositor regs */
466 ade_dump_overlay_compositor_regs(base
, OUT_OVLY
);
469 static void ade_dump_regs(void __iomem
*base
) { }
472 static void ade_crtc_enable(struct drm_crtc
*crtc
)
474 struct ade_crtc
*acrtc
= to_ade_crtc(crtc
);
475 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
481 if (!ctx
->power_on
) {
482 ret
= ade_power_up(ctx
);
487 ade_set_medianoc_qos(acrtc
);
488 ade_display_enable(acrtc
);
489 ade_dump_regs(ctx
->base
);
490 drm_crtc_vblank_on(crtc
);
491 acrtc
->enable
= true;
494 static void ade_crtc_disable(struct drm_crtc
*crtc
)
496 struct ade_crtc
*acrtc
= to_ade_crtc(crtc
);
497 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
502 drm_crtc_vblank_off(crtc
);
504 acrtc
->enable
= false;
507 static void ade_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
509 struct ade_crtc
*acrtc
= to_ade_crtc(crtc
);
510 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
511 struct drm_display_mode
*mode
= &crtc
->state
->mode
;
512 struct drm_display_mode
*adj_mode
= &crtc
->state
->adjusted_mode
;
515 (void)ade_power_up(ctx
);
516 ade_ldi_set_mode(acrtc
, mode
, adj_mode
);
519 static void ade_crtc_atomic_begin(struct drm_crtc
*crtc
,
520 struct drm_crtc_state
*old_state
)
522 struct ade_crtc
*acrtc
= to_ade_crtc(crtc
);
523 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
526 (void)ade_power_up(ctx
);
529 static void ade_crtc_atomic_flush(struct drm_crtc
*crtc
,
530 struct drm_crtc_state
*old_state
)
533 struct ade_crtc
*acrtc
= to_ade_crtc(crtc
);
534 struct ade_hw_ctx
*ctx
= acrtc
->ctx
;
535 struct drm_pending_vblank_event
*event
= crtc
->state
->event
;
536 void __iomem
*base
= ctx
->base
;
538 /* only crtc is enabled regs take effect */
541 /* flush ade registers */
542 writel(ADE_ENABLE
, base
+ ADE_EN
);
546 crtc
->state
->event
= NULL
;
548 spin_lock_irq(&crtc
->dev
->event_lock
);
549 if (drm_crtc_vblank_get(crtc
) == 0)
550 drm_crtc_arm_vblank_event(crtc
, event
);
552 drm_crtc_send_vblank_event(crtc
, event
);
553 spin_unlock_irq(&crtc
->dev
->event_lock
);
557 static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs
= {
558 .enable
= ade_crtc_enable
,
559 .disable
= ade_crtc_disable
,
560 .mode_set_nofb
= ade_crtc_mode_set_nofb
,
561 .atomic_begin
= ade_crtc_atomic_begin
,
562 .atomic_flush
= ade_crtc_atomic_flush
,
565 static const struct drm_crtc_funcs ade_crtc_funcs
= {
566 .destroy
= drm_crtc_cleanup
,
567 .set_config
= drm_atomic_helper_set_config
,
568 .page_flip
= drm_atomic_helper_page_flip
,
569 .reset
= drm_atomic_helper_crtc_reset
,
570 .set_property
= drm_atomic_helper_crtc_set_property
,
571 .atomic_duplicate_state
= drm_atomic_helper_crtc_duplicate_state
,
572 .atomic_destroy_state
= drm_atomic_helper_crtc_destroy_state
,
575 static int ade_crtc_init(struct drm_device
*dev
, struct drm_crtc
*crtc
,
576 struct drm_plane
*plane
)
578 struct kirin_drm_private
*priv
= dev
->dev_private
;
579 struct device_node
*port
;
582 /* set crtc port so that
583 * drm_of_find_possible_crtcs call works
585 port
= of_get_child_by_name(dev
->dev
->of_node
, "port");
587 DRM_ERROR("no port node found in %s\n",
588 dev
->dev
->of_node
->full_name
);
594 ret
= drm_crtc_init_with_planes(dev
, crtc
, plane
, NULL
,
595 &ade_crtc_funcs
, NULL
);
597 DRM_ERROR("failed to init crtc.\n");
601 drm_crtc_helper_add(crtc
, &ade_crtc_helper_funcs
);
602 priv
->crtc
[drm_crtc_index(crtc
)] = crtc
;
607 static void ade_rdma_set(void __iomem
*base
, struct drm_framebuffer
*fb
,
608 u32 ch
, u32 y
, u32 in_h
, u32 fmt
)
610 struct drm_gem_cma_object
*obj
= drm_fb_cma_get_gem_obj(fb
, 0);
612 u32 reg_ctrl
, reg_addr
, reg_size
, reg_stride
, reg_space
, reg_en
;
613 u32 stride
= fb
->pitches
[0];
614 u32 addr
= (u32
)obj
->paddr
+ y
* stride
;
616 DRM_DEBUG_DRIVER("rdma%d: (y=%d, height=%d), stride=%d, paddr=0x%x\n",
617 ch
+ 1, y
, in_h
, stride
, (u32
)obj
->paddr
);
618 format_name
= drm_get_format_name(fb
->pixel_format
);
619 DRM_DEBUG_DRIVER("addr=0x%x, fb:%dx%d, pixel_format=%d(%s)\n",
620 addr
, fb
->width
, fb
->height
, fmt
, format_name
);
624 reg_ctrl
= RD_CH_CTRL(ch
);
625 reg_addr
= RD_CH_ADDR(ch
);
626 reg_size
= RD_CH_SIZE(ch
);
627 reg_stride
= RD_CH_STRIDE(ch
);
628 reg_space
= RD_CH_SPACE(ch
);
629 reg_en
= RD_CH_EN(ch
);
634 writel((fmt
<< 16) & 0x1f0000, base
+ reg_ctrl
);
635 writel(addr
, base
+ reg_addr
);
636 writel((in_h
<< 16) | stride
, base
+ reg_size
);
637 writel(stride
, base
+ reg_stride
);
638 writel(in_h
* stride
, base
+ reg_space
);
639 writel(ADE_ENABLE
, base
+ reg_en
);
640 ade_update_reload_bit(base
, RDMA_OFST
+ ch
, 0);
643 static void ade_rdma_disable(void __iomem
*base
, u32 ch
)
648 reg_en
= RD_CH_EN(ch
);
649 writel(0, base
+ reg_en
);
650 ade_update_reload_bit(base
, RDMA_OFST
+ ch
, 1);
653 static void ade_clip_set(void __iomem
*base
, u32 ch
, u32 fb_w
, u32 x
,
661 * clip width, no need to clip height
663 if (fb_w
== in_w
) { /* bypass */
670 clip_right
= fb_w
- (x
+ in_w
) - 1;
673 DRM_DEBUG_DRIVER("clip%d: clip_left=%d, clip_right=%d\n",
674 ch
+ 1, clip_left
, clip_right
);
676 writel(disable_val
, base
+ ADE_CLIP_DISABLE(ch
));
677 writel((fb_w
- 1) << 16 | (in_h
- 1), base
+ ADE_CLIP_SIZE0(ch
));
678 writel(clip_left
<< 16 | clip_right
, base
+ ADE_CLIP_SIZE1(ch
));
679 ade_update_reload_bit(base
, CLIP_OFST
+ ch
, 0);
682 static void ade_clip_disable(void __iomem
*base
, u32 ch
)
684 writel(1, base
+ ADE_CLIP_DISABLE(ch
));
685 ade_update_reload_bit(base
, CLIP_OFST
+ ch
, 1);
688 static bool has_Alpha_channel(int format
)
701 static void ade_get_blending_params(u32 fmt
, u8 glb_alpha
, u8
*alp_mode
,
702 u8
*alp_sel
, u8
*under_alp_sel
)
704 bool has_alpha
= has_Alpha_channel(fmt
);
709 if (has_alpha
&& glb_alpha
< 255)
710 *alp_mode
= ADE_ALP_PIXEL_AND_GLB
;
712 *alp_mode
= ADE_ALP_PIXEL
;
714 *alp_mode
= ADE_ALP_GLOBAL
;
719 *alp_sel
= ADE_ALP_MUL_COEFF_3
; /* 1 */
720 *under_alp_sel
= ADE_ALP_MUL_COEFF_2
; /* 0 */
723 static void ade_compositor_routing_set(void __iomem
*base
, u8 ch
,
725 u32 in_w
, u32 in_h
, u32 fmt
)
727 u8 ovly_ch
= 0; /* TODO: This is the zpos, only one plane now */
729 u32 x1
= x0
+ in_w
- 1;
730 u32 y1
= y0
+ in_h
- 1;
736 ade_get_blending_params(fmt
, glb_alpha
, &alp_mode
, &alp_sel
,
739 /* overlay routing setting
741 writel(x0
<< 16 | y0
, base
+ ADE_OVLY_CH_XY0(ovly_ch
));
742 writel(x1
<< 16 | y1
, base
+ ADE_OVLY_CH_XY1(ovly_ch
));
743 val
= (ch
+ 1) << CH_SEL_OFST
| BIT(CH_EN_OFST
) |
744 alp_sel
<< CH_ALP_SEL_OFST
|
745 under_alp_sel
<< CH_UNDER_ALP_SEL_OFST
|
746 glb_alpha
<< CH_ALP_GBL_OFST
|
747 alp_mode
<< CH_ALP_MODE_OFST
;
748 writel(val
, base
+ ADE_OVLY_CH_CTL(ovly_ch
));
749 /* connect this plane/channel to overlay2 compositor */
750 ade_update_bits(base
+ ADE_OVLY_CTL
, CH_OVLY_SEL_OFST(ovly_ch
),
751 CH_OVLY_SEL_MASK
, CH_OVLY_SEL_VAL(OUT_OVLY
));
754 static void ade_compositor_routing_disable(void __iomem
*base
, u32 ch
)
756 u8 ovly_ch
= 0; /* TODO: Only primary plane now */
758 /* disable this plane/channel */
759 ade_update_bits(base
+ ADE_OVLY_CH_CTL(ovly_ch
), CH_EN_OFST
,
761 /* dis-connect this plane/channel of overlay2 compositor */
762 ade_update_bits(base
+ ADE_OVLY_CTL
, CH_OVLY_SEL_OFST(ovly_ch
),
763 CH_OVLY_SEL_MASK
, 0);
767 * Typicaly, a channel looks like: DMA-->clip-->scale-->ctrans-->compositor
769 static void ade_update_channel(struct ade_plane
*aplane
,
770 struct drm_framebuffer
*fb
, int crtc_x
,
771 int crtc_y
, unsigned int crtc_w
,
772 unsigned int crtc_h
, u32 src_x
,
773 u32 src_y
, u32 src_w
, u32 src_h
)
775 struct ade_hw_ctx
*ctx
= aplane
->ctx
;
776 void __iomem
*base
= ctx
->base
;
777 u32 fmt
= ade_get_format(fb
->pixel_format
);
782 DRM_DEBUG_DRIVER("channel%d: src:(%d, %d)-%dx%d, crtc:(%d, %d)-%dx%d",
783 ch
+ 1, src_x
, src_y
, src_w
, src_h
,
784 crtc_x
, crtc_y
, crtc_w
, crtc_h
);
789 ade_rdma_set(base
, fb
, ch
, src_y
, in_h
, fmt
);
791 /* 2) clip setting */
792 ade_clip_set(base
, ch
, fb
->width
, src_x
, in_w
, in_h
);
794 /* 3) TODO: scale setting for overlay planes */
796 /* 4) TODO: ctran/csc setting for overlay planes */
798 /* 5) compositor routing setting */
799 ade_compositor_routing_set(base
, ch
, crtc_x
, crtc_y
, in_w
, in_h
, fmt
);
802 static void ade_disable_channel(struct ade_plane
*aplane
)
804 struct ade_hw_ctx
*ctx
= aplane
->ctx
;
805 void __iomem
*base
= ctx
->base
;
808 DRM_DEBUG_DRIVER("disable channel%d\n", ch
+ 1);
810 /* disable read DMA */
811 ade_rdma_disable(base
, ch
);
814 ade_clip_disable(base
, ch
);
816 /* disable compositor routing */
817 ade_compositor_routing_disable(base
, ch
);
820 static int ade_plane_atomic_check(struct drm_plane
*plane
,
821 struct drm_plane_state
*state
)
823 struct drm_framebuffer
*fb
= state
->fb
;
824 struct drm_crtc
*crtc
= state
->crtc
;
825 struct drm_crtc_state
*crtc_state
;
826 u32 src_x
= state
->src_x
>> 16;
827 u32 src_y
= state
->src_y
>> 16;
828 u32 src_w
= state
->src_w
>> 16;
829 u32 src_h
= state
->src_h
>> 16;
830 int crtc_x
= state
->crtc_x
;
831 int crtc_y
= state
->crtc_y
;
832 u32 crtc_w
= state
->crtc_w
;
833 u32 crtc_h
= state
->crtc_h
;
839 fmt
= ade_get_format(fb
->pixel_format
);
840 if (fmt
== ADE_FORMAT_UNSUPPORT
)
843 crtc_state
= drm_atomic_get_crtc_state(state
->state
, crtc
);
844 if (IS_ERR(crtc_state
))
845 return PTR_ERR(crtc_state
);
847 if (src_w
!= crtc_w
|| src_h
!= crtc_h
) {
848 DRM_ERROR("Scale not support!!!\n");
852 if (src_x
+ src_w
> fb
->width
||
853 src_y
+ src_h
> fb
->height
)
856 if (crtc_x
< 0 || crtc_y
< 0)
859 if (crtc_x
+ crtc_w
> crtc_state
->adjusted_mode
.hdisplay
||
860 crtc_y
+ crtc_h
> crtc_state
->adjusted_mode
.vdisplay
)
866 static void ade_plane_atomic_update(struct drm_plane
*plane
,
867 struct drm_plane_state
*old_state
)
869 struct drm_plane_state
*state
= plane
->state
;
870 struct ade_plane
*aplane
= to_ade_plane(plane
);
872 ade_update_channel(aplane
, state
->fb
, state
->crtc_x
, state
->crtc_y
,
873 state
->crtc_w
, state
->crtc_h
,
874 state
->src_x
>> 16, state
->src_y
>> 16,
875 state
->src_w
>> 16, state
->src_h
>> 16);
878 static void ade_plane_atomic_disable(struct drm_plane
*plane
,
879 struct drm_plane_state
*old_state
)
881 struct ade_plane
*aplane
= to_ade_plane(plane
);
883 ade_disable_channel(aplane
);
886 static const struct drm_plane_helper_funcs ade_plane_helper_funcs
= {
887 .atomic_check
= ade_plane_atomic_check
,
888 .atomic_update
= ade_plane_atomic_update
,
889 .atomic_disable
= ade_plane_atomic_disable
,
892 static struct drm_plane_funcs ade_plane_funcs
= {
893 .update_plane
= drm_atomic_helper_update_plane
,
894 .disable_plane
= drm_atomic_helper_disable_plane
,
895 .set_property
= drm_atomic_helper_plane_set_property
,
896 .destroy
= drm_plane_cleanup
,
897 .reset
= drm_atomic_helper_plane_reset
,
898 .atomic_duplicate_state
= drm_atomic_helper_plane_duplicate_state
,
899 .atomic_destroy_state
= drm_atomic_helper_plane_destroy_state
,
902 static int ade_plane_init(struct drm_device
*dev
, struct ade_plane
*aplane
,
903 enum drm_plane_type type
)
910 fmts_cnt
= ade_get_channel_formats(aplane
->ch
, &fmts
);
914 ret
= drm_universal_plane_init(dev
, &aplane
->base
, 1, &ade_plane_funcs
,
915 fmts
, fmts_cnt
, type
, NULL
);
917 DRM_ERROR("fail to init plane, ch=%d\n", aplane
->ch
);
921 drm_plane_helper_add(&aplane
->base
, &ade_plane_helper_funcs
);
926 static int ade_dts_parse(struct platform_device
*pdev
, struct ade_hw_ctx
*ctx
)
928 struct resource
*res
;
929 struct device
*dev
= &pdev
->dev
;
930 struct device_node
*np
= pdev
->dev
.of_node
;
932 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
933 ctx
->base
= devm_ioremap_resource(dev
, res
);
934 if (IS_ERR(ctx
->base
)) {
935 DRM_ERROR("failed to remap ade io base\n");
936 return PTR_ERR(ctx
->base
);
939 ctx
->reset
= devm_reset_control_get(dev
, NULL
);
940 if (IS_ERR(ctx
->reset
))
941 return PTR_ERR(ctx
->reset
);
944 syscon_regmap_lookup_by_phandle(np
, "hisilicon,noc-syscon");
945 if (IS_ERR(ctx
->noc_regmap
)) {
946 DRM_ERROR("failed to get noc regmap\n");
947 return PTR_ERR(ctx
->noc_regmap
);
950 ctx
->irq
= platform_get_irq(pdev
, 0);
952 DRM_ERROR("failed to get irq\n");
956 ctx
->ade_core_clk
= devm_clk_get(dev
, "clk_ade_core");
957 if (IS_ERR(ctx
->ade_core_clk
)) {
958 DRM_ERROR("failed to parse clk ADE_CORE\n");
959 return PTR_ERR(ctx
->ade_core_clk
);
962 ctx
->media_noc_clk
= devm_clk_get(dev
, "clk_codec_jpeg");
963 if (IS_ERR(ctx
->media_noc_clk
)) {
964 DRM_ERROR("failed to parse clk CODEC_JPEG\n");
965 return PTR_ERR(ctx
->media_noc_clk
);
968 ctx
->ade_pix_clk
= devm_clk_get(dev
, "clk_ade_pix");
969 if (IS_ERR(ctx
->ade_pix_clk
)) {
970 DRM_ERROR("failed to parse clk ADE_PIX\n");
971 return PTR_ERR(ctx
->ade_pix_clk
);
977 static int ade_drm_init(struct drm_device
*dev
)
979 struct platform_device
*pdev
= dev
->platformdev
;
980 struct ade_data
*ade
;
981 struct ade_hw_ctx
*ctx
;
982 struct ade_crtc
*acrtc
;
983 struct ade_plane
*aplane
;
984 enum drm_plane_type type
;
988 ade
= devm_kzalloc(dev
->dev
, sizeof(*ade
), GFP_KERNEL
);
990 DRM_ERROR("failed to alloc ade_data\n");
993 platform_set_drvdata(pdev
, ade
);
998 acrtc
->out_format
= LDI_OUT_RGB_888
;
1000 ret
= ade_dts_parse(pdev
, ctx
);
1006 * TODO: Now only support primary plane, overlay planes
1009 for (i
= 0; i
< ADE_CH_NUM
; i
++) {
1010 aplane
= &ade
->aplane
[i
];
1013 type
= i
== PRIMARY_CH
? DRM_PLANE_TYPE_PRIMARY
:
1014 DRM_PLANE_TYPE_OVERLAY
;
1016 ret
= ade_plane_init(dev
, aplane
, type
);
1022 ret
= ade_crtc_init(dev
, &acrtc
->base
, &ade
->aplane
[PRIMARY_CH
].base
);
1026 /* vblank irq init */
1027 ret
= devm_request_irq(dev
->dev
, ctx
->irq
, ade_irq_handler
,
1028 IRQF_SHARED
, dev
->driver
->name
, acrtc
);
1031 dev
->driver
->get_vblank_counter
= drm_vblank_no_hw_counter
;
1032 dev
->driver
->enable_vblank
= ade_enable_vblank
;
1033 dev
->driver
->disable_vblank
= ade_disable_vblank
;
1038 static void ade_drm_cleanup(struct drm_device
*dev
)
1040 struct platform_device
*pdev
= dev
->platformdev
;
1041 struct ade_data
*ade
= platform_get_drvdata(pdev
);
1042 struct drm_crtc
*crtc
= &ade
->acrtc
.base
;
1044 drm_crtc_cleanup(crtc
);
1047 const struct kirin_dc_ops ade_dc_ops
= {
1048 .init
= ade_drm_init
,
1049 .cleanup
= ade_drm_cleanup