2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (i915_gem_obj_is_pinned(obj
))
105 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
107 switch (obj
->tiling_mode
) {
109 case I915_TILING_NONE
: return " ";
110 case I915_TILING_X
: return "X";
111 case I915_TILING_Y
: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
117 return i915_gem_obj_to_ggtt(obj
) ? "g" : " ";
121 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
123 struct i915_vma
*vma
;
126 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s",
129 get_tiling_flag(obj
),
130 get_global_flag(obj
),
131 obj
->base
.size
/ 1024,
132 obj
->base
.read_domains
,
133 obj
->base
.write_domain
,
134 i915_gem_request_get_seqno(obj
->last_read_req
),
135 i915_gem_request_get_seqno(obj
->last_write_req
),
136 i915_gem_request_get_seqno(obj
->last_fenced_req
),
137 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
138 obj
->dirty
? " dirty" : "",
139 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
141 seq_printf(m
, " (name: %d)", obj
->base
.name
);
142 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
143 if (vma
->pin_count
> 0)
146 seq_printf(m
, " (pinned x %d)", pin_count
);
147 if (obj
->pin_display
)
148 seq_printf(m
, " (display)");
149 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
150 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
151 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
152 if (!i915_is_ggtt(vma
->vm
))
156 seq_printf(m
, "gtt offset: %08lx, size: %08lx, type: %u)",
157 vma
->node
.start
, vma
->node
.size
,
158 vma
->ggtt_view
.type
);
161 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->last_read_req
!= NULL
)
172 seq_printf(m
, " (%s)",
173 i915_gem_request_get_ring(obj
->last_read_req
)->name
);
174 if (obj
->frontbuffer_bits
)
175 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
178 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
180 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
181 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
185 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
187 struct drm_info_node
*node
= m
->private;
188 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
189 struct list_head
*head
;
190 struct drm_device
*dev
= node
->minor
->dev
;
191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
193 struct i915_vma
*vma
;
194 size_t total_obj_size
, total_gtt_size
;
197 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
201 /* FIXME: the user of this interface might want more than just GGTT */
204 seq_puts(m
, "Active:\n");
205 head
= &vm
->active_list
;
208 seq_puts(m
, "Inactive:\n");
209 head
= &vm
->inactive_list
;
212 mutex_unlock(&dev
->struct_mutex
);
216 total_obj_size
= total_gtt_size
= count
= 0;
217 list_for_each_entry(vma
, head
, mm_list
) {
219 describe_obj(m
, vma
->obj
);
221 total_obj_size
+= vma
->obj
->base
.size
;
222 total_gtt_size
+= vma
->node
.size
;
225 mutex_unlock(&dev
->struct_mutex
);
227 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
228 count
, total_obj_size
, total_gtt_size
);
232 static int obj_rank_by_stolen(void *priv
,
233 struct list_head
*A
, struct list_head
*B
)
235 struct drm_i915_gem_object
*a
=
236 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
237 struct drm_i915_gem_object
*b
=
238 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
240 return a
->stolen
->start
- b
->stolen
->start
;
243 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
245 struct drm_info_node
*node
= m
->private;
246 struct drm_device
*dev
= node
->minor
->dev
;
247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
248 struct drm_i915_gem_object
*obj
;
249 size_t total_obj_size
, total_gtt_size
;
253 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
257 total_obj_size
= total_gtt_size
= count
= 0;
258 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
259 if (obj
->stolen
== NULL
)
262 list_add(&obj
->obj_exec_link
, &stolen
);
264 total_obj_size
+= obj
->base
.size
;
265 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
268 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
269 if (obj
->stolen
== NULL
)
272 list_add(&obj
->obj_exec_link
, &stolen
);
274 total_obj_size
+= obj
->base
.size
;
277 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
278 seq_puts(m
, "Stolen:\n");
279 while (!list_empty(&stolen
)) {
280 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
282 describe_obj(m
, obj
);
284 list_del_init(&obj
->obj_exec_link
);
286 mutex_unlock(&dev
->struct_mutex
);
288 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
289 count
, total_obj_size
, total_gtt_size
);
293 #define count_objects(list, member) do { \
294 list_for_each_entry(obj, list, member) { \
295 size += i915_gem_obj_ggtt_size(obj); \
297 if (obj->map_and_fenceable) { \
298 mappable_size += i915_gem_obj_ggtt_size(obj); \
305 struct drm_i915_file_private
*file_priv
;
307 size_t total
, unbound
;
308 size_t global
, shared
;
309 size_t active
, inactive
;
312 static int per_file_stats(int id
, void *ptr
, void *data
)
314 struct drm_i915_gem_object
*obj
= ptr
;
315 struct file_stats
*stats
= data
;
316 struct i915_vma
*vma
;
319 stats
->total
+= obj
->base
.size
;
321 if (obj
->base
.name
|| obj
->base
.dma_buf
)
322 stats
->shared
+= obj
->base
.size
;
324 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
325 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
326 struct i915_hw_ppgtt
*ppgtt
;
328 if (!drm_mm_node_allocated(&vma
->node
))
331 if (i915_is_ggtt(vma
->vm
)) {
332 stats
->global
+= obj
->base
.size
;
336 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
337 if (ppgtt
->file_priv
!= stats
->file_priv
)
340 if (obj
->active
) /* XXX per-vma statistic */
341 stats
->active
+= obj
->base
.size
;
343 stats
->inactive
+= obj
->base
.size
;
348 if (i915_gem_obj_ggtt_bound(obj
)) {
349 stats
->global
+= obj
->base
.size
;
351 stats
->active
+= obj
->base
.size
;
353 stats
->inactive
+= obj
->base
.size
;
358 if (!list_empty(&obj
->global_list
))
359 stats
->unbound
+= obj
->base
.size
;
364 #define print_file_stats(m, name, stats) \
365 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
375 static void print_batch_pool_stats(struct seq_file
*m
,
376 struct drm_i915_private
*dev_priv
)
378 struct drm_i915_gem_object
*obj
;
379 struct file_stats stats
;
381 memset(&stats
, 0, sizeof(stats
));
383 list_for_each_entry(obj
,
384 &dev_priv
->mm
.batch_pool
.cache_list
,
386 per_file_stats(0, obj
, &stats
);
388 print_file_stats(m
, "batch pool", stats
);
391 #define count_vmas(list, member) do { \
392 list_for_each_entry(vma, list, member) { \
393 size += i915_gem_obj_ggtt_size(vma->obj); \
395 if (vma->obj->map_and_fenceable) { \
396 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
402 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
404 struct drm_info_node
*node
= m
->private;
405 struct drm_device
*dev
= node
->minor
->dev
;
406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
407 u32 count
, mappable_count
, purgeable_count
;
408 size_t size
, mappable_size
, purgeable_size
;
409 struct drm_i915_gem_object
*obj
;
410 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
411 struct drm_file
*file
;
412 struct i915_vma
*vma
;
415 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
419 seq_printf(m
, "%u objects, %zu bytes\n",
420 dev_priv
->mm
.object_count
,
421 dev_priv
->mm
.object_memory
);
423 size
= count
= mappable_size
= mappable_count
= 0;
424 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
425 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
426 count
, mappable_count
, size
, mappable_size
);
428 size
= count
= mappable_size
= mappable_count
= 0;
429 count_vmas(&vm
->active_list
, mm_list
);
430 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
431 count
, mappable_count
, size
, mappable_size
);
433 size
= count
= mappable_size
= mappable_count
= 0;
434 count_vmas(&vm
->inactive_list
, mm_list
);
435 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
436 count
, mappable_count
, size
, mappable_size
);
438 size
= count
= purgeable_size
= purgeable_count
= 0;
439 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
440 size
+= obj
->base
.size
, ++count
;
441 if (obj
->madv
== I915_MADV_DONTNEED
)
442 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
444 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
446 size
= count
= mappable_size
= mappable_count
= 0;
447 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
448 if (obj
->fault_mappable
) {
449 size
+= i915_gem_obj_ggtt_size(obj
);
452 if (obj
->pin_mappable
) {
453 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
456 if (obj
->madv
== I915_MADV_DONTNEED
) {
457 purgeable_size
+= obj
->base
.size
;
461 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
462 purgeable_count
, purgeable_size
);
463 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
464 mappable_count
, mappable_size
);
465 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
468 seq_printf(m
, "%zu [%lu] gtt total\n",
469 dev_priv
->gtt
.base
.total
,
470 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
473 print_batch_pool_stats(m
, dev_priv
);
476 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
477 struct file_stats stats
;
478 struct task_struct
*task
;
480 memset(&stats
, 0, sizeof(stats
));
481 stats
.file_priv
= file
->driver_priv
;
482 spin_lock(&file
->table_lock
);
483 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
484 spin_unlock(&file
->table_lock
);
486 * Although we have a valid reference on file->pid, that does
487 * not guarantee that the task_struct who called get_pid() is
488 * still alive (e.g. get_pid(current) => fork() => exit()).
489 * Therefore, we need to protect this ->comm access using RCU.
492 task
= pid_task(file
->pid
, PIDTYPE_PID
);
493 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
497 mutex_unlock(&dev
->struct_mutex
);
502 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
504 struct drm_info_node
*node
= m
->private;
505 struct drm_device
*dev
= node
->minor
->dev
;
506 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
508 struct drm_i915_gem_object
*obj
;
509 size_t total_obj_size
, total_gtt_size
;
512 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
516 total_obj_size
= total_gtt_size
= count
= 0;
517 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
518 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
522 describe_obj(m
, obj
);
524 total_obj_size
+= obj
->base
.size
;
525 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
529 mutex_unlock(&dev
->struct_mutex
);
531 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
532 count
, total_obj_size
, total_gtt_size
);
537 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
539 struct drm_info_node
*node
= m
->private;
540 struct drm_device
*dev
= node
->minor
->dev
;
541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
542 struct intel_crtc
*crtc
;
545 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
549 for_each_intel_crtc(dev
, crtc
) {
550 const char pipe
= pipe_name(crtc
->pipe
);
551 const char plane
= plane_name(crtc
->plane
);
552 struct intel_unpin_work
*work
;
554 spin_lock_irq(&dev
->event_lock
);
555 work
= crtc
->unpin_work
;
557 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
562 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
563 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
566 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
569 if (work
->flip_queued_req
) {
570 struct intel_engine_cs
*ring
=
571 i915_gem_request_get_ring(work
->flip_queued_req
);
573 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
575 i915_gem_request_get_seqno(work
->flip_queued_req
),
576 dev_priv
->next_seqno
,
577 ring
->get_seqno(ring
, true),
578 i915_gem_request_completed(work
->flip_queued_req
, true));
580 seq_printf(m
, "Flip not associated with any ring\n");
581 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
582 work
->flip_queued_vblank
,
583 work
->flip_ready_vblank
,
584 drm_crtc_vblank_count(&crtc
->base
));
585 if (work
->enable_stall_check
)
586 seq_puts(m
, "Stall check enabled, ");
588 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
589 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
591 if (INTEL_INFO(dev
)->gen
>= 4)
592 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
594 addr
= I915_READ(DSPADDR(crtc
->plane
));
595 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
597 if (work
->pending_flip_obj
) {
598 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
599 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
602 spin_unlock_irq(&dev
->event_lock
);
605 mutex_unlock(&dev
->struct_mutex
);
610 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
612 struct drm_info_node
*node
= m
->private;
613 struct drm_device
*dev
= node
->minor
->dev
;
614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
615 struct drm_i915_gem_object
*obj
;
619 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
623 seq_puts(m
, "cache:\n");
624 list_for_each_entry(obj
,
625 &dev_priv
->mm
.batch_pool
.cache_list
,
628 describe_obj(m
, obj
);
633 seq_printf(m
, "total: %d\n", count
);
635 mutex_unlock(&dev
->struct_mutex
);
640 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
642 struct drm_info_node
*node
= m
->private;
643 struct drm_device
*dev
= node
->minor
->dev
;
644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
645 struct intel_engine_cs
*ring
;
646 struct drm_i915_gem_request
*gem_request
;
649 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
654 for_each_ring(ring
, dev_priv
, i
) {
655 if (list_empty(&ring
->request_list
))
658 seq_printf(m
, "%s requests:\n", ring
->name
);
659 list_for_each_entry(gem_request
,
662 seq_printf(m
, " %x @ %d\n",
664 (int) (jiffies
- gem_request
->emitted_jiffies
));
668 mutex_unlock(&dev
->struct_mutex
);
671 seq_puts(m
, "No requests\n");
676 static void i915_ring_seqno_info(struct seq_file
*m
,
677 struct intel_engine_cs
*ring
)
679 if (ring
->get_seqno
) {
680 seq_printf(m
, "Current sequence (%s): %x\n",
681 ring
->name
, ring
->get_seqno(ring
, false));
685 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
687 struct drm_info_node
*node
= m
->private;
688 struct drm_device
*dev
= node
->minor
->dev
;
689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
690 struct intel_engine_cs
*ring
;
693 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
696 intel_runtime_pm_get(dev_priv
);
698 for_each_ring(ring
, dev_priv
, i
)
699 i915_ring_seqno_info(m
, ring
);
701 intel_runtime_pm_put(dev_priv
);
702 mutex_unlock(&dev
->struct_mutex
);
708 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
710 struct drm_info_node
*node
= m
->private;
711 struct drm_device
*dev
= node
->minor
->dev
;
712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
713 struct intel_engine_cs
*ring
;
716 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
719 intel_runtime_pm_get(dev_priv
);
721 if (IS_CHERRYVIEW(dev
)) {
722 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
723 I915_READ(GEN8_MASTER_IRQ
));
725 seq_printf(m
, "Display IER:\t%08x\n",
727 seq_printf(m
, "Display IIR:\t%08x\n",
729 seq_printf(m
, "Display IIR_RW:\t%08x\n",
730 I915_READ(VLV_IIR_RW
));
731 seq_printf(m
, "Display IMR:\t%08x\n",
733 for_each_pipe(dev_priv
, pipe
)
734 seq_printf(m
, "Pipe %c stat:\t%08x\n",
736 I915_READ(PIPESTAT(pipe
)));
738 seq_printf(m
, "Port hotplug:\t%08x\n",
739 I915_READ(PORT_HOTPLUG_EN
));
740 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
741 I915_READ(VLV_DPFLIPSTAT
));
742 seq_printf(m
, "DPINVGTT:\t%08x\n",
743 I915_READ(DPINVGTT
));
745 for (i
= 0; i
< 4; i
++) {
746 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
747 i
, I915_READ(GEN8_GT_IMR(i
)));
748 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
749 i
, I915_READ(GEN8_GT_IIR(i
)));
750 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
751 i
, I915_READ(GEN8_GT_IER(i
)));
754 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
755 I915_READ(GEN8_PCU_IMR
));
756 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
757 I915_READ(GEN8_PCU_IIR
));
758 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
759 I915_READ(GEN8_PCU_IER
));
760 } else if (INTEL_INFO(dev
)->gen
>= 8) {
761 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
762 I915_READ(GEN8_MASTER_IRQ
));
764 for (i
= 0; i
< 4; i
++) {
765 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
766 i
, I915_READ(GEN8_GT_IMR(i
)));
767 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
768 i
, I915_READ(GEN8_GT_IIR(i
)));
769 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
770 i
, I915_READ(GEN8_GT_IER(i
)));
773 for_each_pipe(dev_priv
, pipe
) {
774 if (!intel_display_power_is_enabled(dev_priv
,
775 POWER_DOMAIN_PIPE(pipe
))) {
776 seq_printf(m
, "Pipe %c power disabled\n",
780 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
782 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
783 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
785 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
786 seq_printf(m
, "Pipe %c IER:\t%08x\n",
788 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
791 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
792 I915_READ(GEN8_DE_PORT_IMR
));
793 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
794 I915_READ(GEN8_DE_PORT_IIR
));
795 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
796 I915_READ(GEN8_DE_PORT_IER
));
798 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
799 I915_READ(GEN8_DE_MISC_IMR
));
800 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
801 I915_READ(GEN8_DE_MISC_IIR
));
802 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
803 I915_READ(GEN8_DE_MISC_IER
));
805 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
806 I915_READ(GEN8_PCU_IMR
));
807 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
808 I915_READ(GEN8_PCU_IIR
));
809 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
810 I915_READ(GEN8_PCU_IER
));
811 } else if (IS_VALLEYVIEW(dev
)) {
812 seq_printf(m
, "Display IER:\t%08x\n",
814 seq_printf(m
, "Display IIR:\t%08x\n",
816 seq_printf(m
, "Display IIR_RW:\t%08x\n",
817 I915_READ(VLV_IIR_RW
));
818 seq_printf(m
, "Display IMR:\t%08x\n",
820 for_each_pipe(dev_priv
, pipe
)
821 seq_printf(m
, "Pipe %c stat:\t%08x\n",
823 I915_READ(PIPESTAT(pipe
)));
825 seq_printf(m
, "Master IER:\t%08x\n",
826 I915_READ(VLV_MASTER_IER
));
828 seq_printf(m
, "Render IER:\t%08x\n",
830 seq_printf(m
, "Render IIR:\t%08x\n",
832 seq_printf(m
, "Render IMR:\t%08x\n",
835 seq_printf(m
, "PM IER:\t\t%08x\n",
836 I915_READ(GEN6_PMIER
));
837 seq_printf(m
, "PM IIR:\t\t%08x\n",
838 I915_READ(GEN6_PMIIR
));
839 seq_printf(m
, "PM IMR:\t\t%08x\n",
840 I915_READ(GEN6_PMIMR
));
842 seq_printf(m
, "Port hotplug:\t%08x\n",
843 I915_READ(PORT_HOTPLUG_EN
));
844 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
845 I915_READ(VLV_DPFLIPSTAT
));
846 seq_printf(m
, "DPINVGTT:\t%08x\n",
847 I915_READ(DPINVGTT
));
849 } else if (!HAS_PCH_SPLIT(dev
)) {
850 seq_printf(m
, "Interrupt enable: %08x\n",
852 seq_printf(m
, "Interrupt identity: %08x\n",
854 seq_printf(m
, "Interrupt mask: %08x\n",
856 for_each_pipe(dev_priv
, pipe
)
857 seq_printf(m
, "Pipe %c stat: %08x\n",
859 I915_READ(PIPESTAT(pipe
)));
861 seq_printf(m
, "North Display Interrupt enable: %08x\n",
863 seq_printf(m
, "North Display Interrupt identity: %08x\n",
865 seq_printf(m
, "North Display Interrupt mask: %08x\n",
867 seq_printf(m
, "South Display Interrupt enable: %08x\n",
869 seq_printf(m
, "South Display Interrupt identity: %08x\n",
871 seq_printf(m
, "South Display Interrupt mask: %08x\n",
873 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
875 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
877 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
880 for_each_ring(ring
, dev_priv
, i
) {
881 if (INTEL_INFO(dev
)->gen
>= 6) {
883 "Graphics Interrupt mask (%s): %08x\n",
884 ring
->name
, I915_READ_IMR(ring
));
886 i915_ring_seqno_info(m
, ring
);
888 intel_runtime_pm_put(dev_priv
);
889 mutex_unlock(&dev
->struct_mutex
);
894 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
896 struct drm_info_node
*node
= m
->private;
897 struct drm_device
*dev
= node
->minor
->dev
;
898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
901 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
905 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
906 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
907 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
908 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
910 seq_printf(m
, "Fence %d, pin count = %d, object = ",
911 i
, dev_priv
->fence_regs
[i
].pin_count
);
913 seq_puts(m
, "unused");
915 describe_obj(m
, obj
);
919 mutex_unlock(&dev
->struct_mutex
);
923 static int i915_hws_info(struct seq_file
*m
, void *data
)
925 struct drm_info_node
*node
= m
->private;
926 struct drm_device
*dev
= node
->minor
->dev
;
927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
928 struct intel_engine_cs
*ring
;
932 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
933 hws
= ring
->status_page
.page_addr
;
937 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
938 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
940 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
946 i915_error_state_write(struct file
*filp
,
947 const char __user
*ubuf
,
951 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
952 struct drm_device
*dev
= error_priv
->dev
;
955 DRM_DEBUG_DRIVER("Resetting error state\n");
957 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
961 i915_destroy_error_state(dev
);
962 mutex_unlock(&dev
->struct_mutex
);
967 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
969 struct drm_device
*dev
= inode
->i_private
;
970 struct i915_error_state_file_priv
*error_priv
;
972 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
976 error_priv
->dev
= dev
;
978 i915_error_state_get(dev
, error_priv
);
980 file
->private_data
= error_priv
;
985 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
987 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
989 i915_error_state_put(error_priv
);
995 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
996 size_t count
, loff_t
*pos
)
998 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
999 struct drm_i915_error_state_buf error_str
;
1001 ssize_t ret_count
= 0;
1004 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1008 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1012 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1019 *pos
= error_str
.start
+ ret_count
;
1021 i915_error_state_buf_release(&error_str
);
1022 return ret
?: ret_count
;
1025 static const struct file_operations i915_error_state_fops
= {
1026 .owner
= THIS_MODULE
,
1027 .open
= i915_error_state_open
,
1028 .read
= i915_error_state_read
,
1029 .write
= i915_error_state_write
,
1030 .llseek
= default_llseek
,
1031 .release
= i915_error_state_release
,
1035 i915_next_seqno_get(void *data
, u64
*val
)
1037 struct drm_device
*dev
= data
;
1038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1041 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1045 *val
= dev_priv
->next_seqno
;
1046 mutex_unlock(&dev
->struct_mutex
);
1052 i915_next_seqno_set(void *data
, u64 val
)
1054 struct drm_device
*dev
= data
;
1057 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1061 ret
= i915_gem_set_seqno(dev
, val
);
1062 mutex_unlock(&dev
->struct_mutex
);
1067 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1068 i915_next_seqno_get
, i915_next_seqno_set
,
1071 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1073 struct drm_info_node
*node
= m
->private;
1074 struct drm_device
*dev
= node
->minor
->dev
;
1075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1078 intel_runtime_pm_get(dev_priv
);
1080 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1083 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1084 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1086 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1087 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1088 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1090 seq_printf(m
, "Current P-state: %d\n",
1091 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1092 } else if (IS_GEN6(dev
) || (IS_GEN7(dev
) && !IS_VALLEYVIEW(dev
)) ||
1093 IS_BROADWELL(dev
)) {
1094 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1095 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1096 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1097 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1098 u32 rpstat
, cagf
, reqf
;
1099 u32 rpupei
, rpcurup
, rpprevup
;
1100 u32 rpdownei
, rpcurdown
, rpprevdown
;
1101 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1104 /* RPSTAT1 is in the GT power well */
1105 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1109 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1111 reqf
= I915_READ(GEN6_RPNSWREQ
);
1112 reqf
&= ~GEN6_TURBO_DISABLE
;
1113 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1117 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1119 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1120 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1121 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1123 rpstat
= I915_READ(GEN6_RPSTAT1
);
1124 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1125 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1126 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1127 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1128 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1129 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1130 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1131 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1133 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1134 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1136 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1137 mutex_unlock(&dev
->struct_mutex
);
1139 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1140 pm_ier
= I915_READ(GEN6_PMIER
);
1141 pm_imr
= I915_READ(GEN6_PMIMR
);
1142 pm_isr
= I915_READ(GEN6_PMISR
);
1143 pm_iir
= I915_READ(GEN6_PMIIR
);
1144 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1146 pm_ier
= I915_READ(GEN8_GT_IER(2));
1147 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1148 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1149 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1150 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1152 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1153 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1154 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1155 seq_printf(m
, "Render p-state ratio: %d\n",
1156 (gt_perf_status
& 0xff00) >> 8);
1157 seq_printf(m
, "Render p-state VID: %d\n",
1158 gt_perf_status
& 0xff);
1159 seq_printf(m
, "Render p-state limit: %d\n",
1160 rp_state_limits
& 0xff);
1161 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1162 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1163 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1164 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1165 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1166 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1167 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1168 GEN6_CURICONT_MASK
);
1169 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1170 GEN6_CURBSYTAVG_MASK
);
1171 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1172 GEN6_CURBSYTAVG_MASK
);
1173 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1175 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1176 GEN6_CURBSYTAVG_MASK
);
1177 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1178 GEN6_CURBSYTAVG_MASK
);
1180 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1181 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1182 intel_gpu_freq(dev_priv
, max_freq
));
1184 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1185 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1186 intel_gpu_freq(dev_priv
, max_freq
));
1188 max_freq
= rp_state_cap
& 0xff;
1189 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1190 intel_gpu_freq(dev_priv
, max_freq
));
1192 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1193 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1194 } else if (IS_VALLEYVIEW(dev
)) {
1197 mutex_lock(&dev_priv
->rps
.hw_lock
);
1198 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1199 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1200 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1202 seq_printf(m
, "max GPU freq: %d MHz\n",
1203 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1205 seq_printf(m
, "min GPU freq: %d MHz\n",
1206 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1209 "efficient (RPe) frequency: %d MHz\n",
1210 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1212 seq_printf(m
, "current GPU freq: %d MHz\n",
1213 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1214 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1216 seq_puts(m
, "no P-state info available\n");
1220 intel_runtime_pm_put(dev_priv
);
1224 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1226 struct drm_info_node
*node
= m
->private;
1227 struct drm_i915_private
*dev_priv
= to_i915(node
->minor
->dev
);
1228 struct intel_engine_cs
*ring
;
1231 if (!i915
.enable_hangcheck
) {
1232 seq_printf(m
, "Hangcheck disabled\n");
1236 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1237 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1238 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1241 seq_printf(m
, "Hangcheck inactive\n");
1243 for_each_ring(ring
, dev_priv
, i
) {
1244 seq_printf(m
, "%s:\n", ring
->name
);
1245 seq_printf(m
, "\tseqno = %x [current %x]\n",
1246 ring
->hangcheck
.seqno
, ring
->get_seqno(ring
, false));
1247 seq_printf(m
, "\taction = %d\n", ring
->hangcheck
.action
);
1248 seq_printf(m
, "\tscore = %d\n", ring
->hangcheck
.score
);
1249 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1250 (long long)ring
->hangcheck
.acthd
,
1251 (long long)intel_ring_get_active_head(ring
));
1252 seq_printf(m
, "\tmax ACTHD = 0x%08llx\n",
1253 (long long)ring
->hangcheck
.max_acthd
);
1259 static int ironlake_drpc_info(struct seq_file
*m
)
1261 struct drm_info_node
*node
= m
->private;
1262 struct drm_device
*dev
= node
->minor
->dev
;
1263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1264 u32 rgvmodectl
, rstdbyctl
;
1268 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1271 intel_runtime_pm_get(dev_priv
);
1273 rgvmodectl
= I915_READ(MEMMODECTL
);
1274 rstdbyctl
= I915_READ(RSTDBYCTL
);
1275 crstandvid
= I915_READ16(CRSTANDVID
);
1277 intel_runtime_pm_put(dev_priv
);
1278 mutex_unlock(&dev
->struct_mutex
);
1280 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1282 seq_printf(m
, "Boost freq: %d\n",
1283 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1284 MEMMODE_BOOST_FREQ_SHIFT
);
1285 seq_printf(m
, "HW control enabled: %s\n",
1286 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1287 seq_printf(m
, "SW control enabled: %s\n",
1288 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1289 seq_printf(m
, "Gated voltage change: %s\n",
1290 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1291 seq_printf(m
, "Starting frequency: P%d\n",
1292 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1293 seq_printf(m
, "Max P-state: P%d\n",
1294 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1295 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1296 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1297 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1298 seq_printf(m
, "Render standby enabled: %s\n",
1299 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1300 seq_puts(m
, "Current RS state: ");
1301 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1303 seq_puts(m
, "on\n");
1305 case RSX_STATUS_RC1
:
1306 seq_puts(m
, "RC1\n");
1308 case RSX_STATUS_RC1E
:
1309 seq_puts(m
, "RC1E\n");
1311 case RSX_STATUS_RS1
:
1312 seq_puts(m
, "RS1\n");
1314 case RSX_STATUS_RS2
:
1315 seq_puts(m
, "RS2 (RC6)\n");
1317 case RSX_STATUS_RS3
:
1318 seq_puts(m
, "RC3 (RC6+)\n");
1321 seq_puts(m
, "unknown\n");
1328 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1330 struct drm_info_node
*node
= m
->private;
1331 struct drm_device
*dev
= node
->minor
->dev
;
1332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1333 struct intel_uncore_forcewake_domain
*fw_domain
;
1336 spin_lock_irq(&dev_priv
->uncore
.lock
);
1337 for_each_fw_domain(fw_domain
, dev_priv
, i
) {
1338 seq_printf(m
, "%s.wake_count = %u\n",
1339 intel_uncore_forcewake_domain_to_str(i
),
1340 fw_domain
->wake_count
);
1342 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1347 static int vlv_drpc_info(struct seq_file
*m
)
1349 struct drm_info_node
*node
= m
->private;
1350 struct drm_device
*dev
= node
->minor
->dev
;
1351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1352 u32 rpmodectl1
, rcctl1
, pw_status
;
1354 intel_runtime_pm_get(dev_priv
);
1356 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1357 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1358 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1360 intel_runtime_pm_put(dev_priv
);
1362 seq_printf(m
, "Video Turbo Mode: %s\n",
1363 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1364 seq_printf(m
, "Turbo enabled: %s\n",
1365 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1366 seq_printf(m
, "HW control enabled: %s\n",
1367 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1368 seq_printf(m
, "SW control enabled: %s\n",
1369 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1370 GEN6_RP_MEDIA_SW_MODE
));
1371 seq_printf(m
, "RC6 Enabled: %s\n",
1372 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1373 GEN6_RC_CTL_EI_MODE(1))));
1374 seq_printf(m
, "Render Power Well: %s\n",
1375 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1376 seq_printf(m
, "Media Power Well: %s\n",
1377 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1379 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1380 I915_READ(VLV_GT_RENDER_RC6
));
1381 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1382 I915_READ(VLV_GT_MEDIA_RC6
));
1384 return i915_forcewake_domains(m
, NULL
);
1387 static int gen6_drpc_info(struct seq_file
*m
)
1389 struct drm_info_node
*node
= m
->private;
1390 struct drm_device
*dev
= node
->minor
->dev
;
1391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1392 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1393 unsigned forcewake_count
;
1396 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1399 intel_runtime_pm_get(dev_priv
);
1401 spin_lock_irq(&dev_priv
->uncore
.lock
);
1402 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1403 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1405 if (forcewake_count
) {
1406 seq_puts(m
, "RC information inaccurate because somebody "
1407 "holds a forcewake reference \n");
1409 /* NB: we cannot use forcewake, else we read the wrong values */
1410 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1412 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1415 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1416 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1418 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1419 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1420 mutex_unlock(&dev
->struct_mutex
);
1421 mutex_lock(&dev_priv
->rps
.hw_lock
);
1422 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1423 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1425 intel_runtime_pm_put(dev_priv
);
1427 seq_printf(m
, "Video Turbo Mode: %s\n",
1428 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1429 seq_printf(m
, "HW control enabled: %s\n",
1430 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1431 seq_printf(m
, "SW control enabled: %s\n",
1432 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1433 GEN6_RP_MEDIA_SW_MODE
));
1434 seq_printf(m
, "RC1e Enabled: %s\n",
1435 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1436 seq_printf(m
, "RC6 Enabled: %s\n",
1437 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1438 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1439 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1440 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1441 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1442 seq_puts(m
, "Current RC state: ");
1443 switch (gt_core_status
& GEN6_RCn_MASK
) {
1445 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1446 seq_puts(m
, "Core Power Down\n");
1448 seq_puts(m
, "on\n");
1451 seq_puts(m
, "RC3\n");
1454 seq_puts(m
, "RC6\n");
1457 seq_puts(m
, "RC7\n");
1460 seq_puts(m
, "Unknown\n");
1464 seq_printf(m
, "Core Power Down: %s\n",
1465 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1467 /* Not exactly sure what this is */
1468 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1469 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1470 seq_printf(m
, "RC6 residency since boot: %u\n",
1471 I915_READ(GEN6_GT_GFX_RC6
));
1472 seq_printf(m
, "RC6+ residency since boot: %u\n",
1473 I915_READ(GEN6_GT_GFX_RC6p
));
1474 seq_printf(m
, "RC6++ residency since boot: %u\n",
1475 I915_READ(GEN6_GT_GFX_RC6pp
));
1477 seq_printf(m
, "RC6 voltage: %dmV\n",
1478 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1479 seq_printf(m
, "RC6+ voltage: %dmV\n",
1480 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1481 seq_printf(m
, "RC6++ voltage: %dmV\n",
1482 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1486 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1488 struct drm_info_node
*node
= m
->private;
1489 struct drm_device
*dev
= node
->minor
->dev
;
1491 if (IS_VALLEYVIEW(dev
))
1492 return vlv_drpc_info(m
);
1493 else if (INTEL_INFO(dev
)->gen
>= 6)
1494 return gen6_drpc_info(m
);
1496 return ironlake_drpc_info(m
);
1499 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1501 struct drm_info_node
*node
= m
->private;
1502 struct drm_device
*dev
= node
->minor
->dev
;
1503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1505 if (!HAS_FBC(dev
)) {
1506 seq_puts(m
, "FBC unsupported on this chipset\n");
1510 intel_runtime_pm_get(dev_priv
);
1512 if (intel_fbc_enabled(dev
)) {
1513 seq_puts(m
, "FBC enabled\n");
1515 seq_puts(m
, "FBC disabled: ");
1516 switch (dev_priv
->fbc
.no_fbc_reason
) {
1518 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1520 case FBC_UNSUPPORTED
:
1521 seq_puts(m
, "unsupported by this chipset");
1524 seq_puts(m
, "no outputs");
1526 case FBC_STOLEN_TOO_SMALL
:
1527 seq_puts(m
, "not enough stolen memory");
1529 case FBC_UNSUPPORTED_MODE
:
1530 seq_puts(m
, "mode not supported");
1532 case FBC_MODE_TOO_LARGE
:
1533 seq_puts(m
, "mode too large");
1536 seq_puts(m
, "FBC unsupported on plane");
1539 seq_puts(m
, "scanout buffer not tiled");
1541 case FBC_MULTIPLE_PIPES
:
1542 seq_puts(m
, "multiple pipes are enabled");
1544 case FBC_MODULE_PARAM
:
1545 seq_puts(m
, "disabled per module param (default off)");
1547 case FBC_CHIP_DEFAULT
:
1548 seq_puts(m
, "disabled per chip default");
1551 seq_puts(m
, "unknown reason");
1556 intel_runtime_pm_put(dev_priv
);
1561 static int i915_fbc_fc_get(void *data
, u64
*val
)
1563 struct drm_device
*dev
= data
;
1564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1566 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1569 drm_modeset_lock_all(dev
);
1570 *val
= dev_priv
->fbc
.false_color
;
1571 drm_modeset_unlock_all(dev
);
1576 static int i915_fbc_fc_set(void *data
, u64 val
)
1578 struct drm_device
*dev
= data
;
1579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1582 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1585 drm_modeset_lock_all(dev
);
1587 reg
= I915_READ(ILK_DPFC_CONTROL
);
1588 dev_priv
->fbc
.false_color
= val
;
1590 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1591 (reg
| FBC_CTL_FALSE_COLOR
) :
1592 (reg
& ~FBC_CTL_FALSE_COLOR
));
1594 drm_modeset_unlock_all(dev
);
1598 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1599 i915_fbc_fc_get
, i915_fbc_fc_set
,
1602 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1604 struct drm_info_node
*node
= m
->private;
1605 struct drm_device
*dev
= node
->minor
->dev
;
1606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1608 if (!HAS_IPS(dev
)) {
1609 seq_puts(m
, "not supported\n");
1613 intel_runtime_pm_get(dev_priv
);
1615 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1616 yesno(i915
.enable_ips
));
1618 if (INTEL_INFO(dev
)->gen
>= 8) {
1619 seq_puts(m
, "Currently: unknown\n");
1621 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1622 seq_puts(m
, "Currently: enabled\n");
1624 seq_puts(m
, "Currently: disabled\n");
1627 intel_runtime_pm_put(dev_priv
);
1632 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1634 struct drm_info_node
*node
= m
->private;
1635 struct drm_device
*dev
= node
->minor
->dev
;
1636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1637 bool sr_enabled
= false;
1639 intel_runtime_pm_get(dev_priv
);
1641 if (HAS_PCH_SPLIT(dev
))
1642 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1643 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1644 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1645 else if (IS_I915GM(dev
))
1646 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1647 else if (IS_PINEVIEW(dev
))
1648 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1650 intel_runtime_pm_put(dev_priv
);
1652 seq_printf(m
, "self-refresh: %s\n",
1653 sr_enabled
? "enabled" : "disabled");
1658 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1660 struct drm_info_node
*node
= m
->private;
1661 struct drm_device
*dev
= node
->minor
->dev
;
1662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1663 unsigned long temp
, chipset
, gfx
;
1669 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1673 temp
= i915_mch_val(dev_priv
);
1674 chipset
= i915_chipset_val(dev_priv
);
1675 gfx
= i915_gfx_val(dev_priv
);
1676 mutex_unlock(&dev
->struct_mutex
);
1678 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1679 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1680 seq_printf(m
, "GFX power: %ld\n", gfx
);
1681 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1686 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1688 struct drm_info_node
*node
= m
->private;
1689 struct drm_device
*dev
= node
->minor
->dev
;
1690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1692 int gpu_freq
, ia_freq
;
1694 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1695 seq_puts(m
, "unsupported on this chipset\n");
1699 intel_runtime_pm_get(dev_priv
);
1701 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1703 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1707 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1709 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1710 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1713 sandybridge_pcode_read(dev_priv
,
1714 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1716 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1717 intel_gpu_freq(dev_priv
, gpu_freq
),
1718 ((ia_freq
>> 0) & 0xff) * 100,
1719 ((ia_freq
>> 8) & 0xff) * 100);
1722 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1725 intel_runtime_pm_put(dev_priv
);
1729 static int i915_opregion(struct seq_file
*m
, void *unused
)
1731 struct drm_info_node
*node
= m
->private;
1732 struct drm_device
*dev
= node
->minor
->dev
;
1733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1734 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1735 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1741 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1745 if (opregion
->header
) {
1746 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1747 seq_write(m
, data
, OPREGION_SIZE
);
1750 mutex_unlock(&dev
->struct_mutex
);
1757 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1759 struct drm_info_node
*node
= m
->private;
1760 struct drm_device
*dev
= node
->minor
->dev
;
1761 struct intel_fbdev
*ifbdev
= NULL
;
1762 struct intel_framebuffer
*fb
;
1764 #ifdef CONFIG_DRM_I915_FBDEV
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1767 ifbdev
= dev_priv
->fbdev
;
1768 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1770 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1774 fb
->base
.bits_per_pixel
,
1775 fb
->base
.modifier
[0],
1776 atomic_read(&fb
->base
.refcount
.refcount
));
1777 describe_obj(m
, fb
->obj
);
1781 mutex_lock(&dev
->mode_config
.fb_lock
);
1782 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1783 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1786 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1790 fb
->base
.bits_per_pixel
,
1791 fb
->base
.modifier
[0],
1792 atomic_read(&fb
->base
.refcount
.refcount
));
1793 describe_obj(m
, fb
->obj
);
1796 mutex_unlock(&dev
->mode_config
.fb_lock
);
1801 static void describe_ctx_ringbuf(struct seq_file
*m
,
1802 struct intel_ringbuffer
*ringbuf
)
1804 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1805 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1806 ringbuf
->last_retired_head
);
1809 static int i915_context_status(struct seq_file
*m
, void *unused
)
1811 struct drm_info_node
*node
= m
->private;
1812 struct drm_device
*dev
= node
->minor
->dev
;
1813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1814 struct intel_engine_cs
*ring
;
1815 struct intel_context
*ctx
;
1818 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1822 if (dev_priv
->ips
.pwrctx
) {
1823 seq_puts(m
, "power context ");
1824 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1828 if (dev_priv
->ips
.renderctx
) {
1829 seq_puts(m
, "render context ");
1830 describe_obj(m
, dev_priv
->ips
.renderctx
);
1834 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1835 if (!i915
.enable_execlists
&&
1836 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
1839 seq_puts(m
, "HW context ");
1840 describe_ctx(m
, ctx
);
1841 for_each_ring(ring
, dev_priv
, i
) {
1842 if (ring
->default_context
== ctx
)
1843 seq_printf(m
, "(default context %s) ",
1847 if (i915
.enable_execlists
) {
1849 for_each_ring(ring
, dev_priv
, i
) {
1850 struct drm_i915_gem_object
*ctx_obj
=
1851 ctx
->engine
[i
].state
;
1852 struct intel_ringbuffer
*ringbuf
=
1853 ctx
->engine
[i
].ringbuf
;
1855 seq_printf(m
, "%s: ", ring
->name
);
1857 describe_obj(m
, ctx_obj
);
1859 describe_ctx_ringbuf(m
, ringbuf
);
1863 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
1869 mutex_unlock(&dev
->struct_mutex
);
1874 static void i915_dump_lrc_obj(struct seq_file
*m
,
1875 struct intel_engine_cs
*ring
,
1876 struct drm_i915_gem_object
*ctx_obj
)
1879 uint32_t *reg_state
;
1881 unsigned long ggtt_offset
= 0;
1883 if (ctx_obj
== NULL
) {
1884 seq_printf(m
, "Context on %s with no gem object\n",
1889 seq_printf(m
, "CONTEXT: %s %u\n", ring
->name
,
1890 intel_execlists_ctx_id(ctx_obj
));
1892 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
1893 seq_puts(m
, "\tNot bound in GGTT\n");
1895 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
1897 if (i915_gem_object_get_pages(ctx_obj
)) {
1898 seq_puts(m
, "\tFailed to get pages for context object\n");
1902 page
= i915_gem_object_get_page(ctx_obj
, 1);
1903 if (!WARN_ON(page
== NULL
)) {
1904 reg_state
= kmap_atomic(page
);
1906 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
1907 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1908 ggtt_offset
+ 4096 + (j
* 4),
1909 reg_state
[j
], reg_state
[j
+ 1],
1910 reg_state
[j
+ 2], reg_state
[j
+ 3]);
1912 kunmap_atomic(reg_state
);
1918 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
1920 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1921 struct drm_device
*dev
= node
->minor
->dev
;
1922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1923 struct intel_engine_cs
*ring
;
1924 struct intel_context
*ctx
;
1927 if (!i915
.enable_execlists
) {
1928 seq_printf(m
, "Logical Ring Contexts are disabled\n");
1932 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1936 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1937 for_each_ring(ring
, dev_priv
, i
) {
1938 if (ring
->default_context
!= ctx
)
1939 i915_dump_lrc_obj(m
, ring
,
1940 ctx
->engine
[i
].state
);
1944 mutex_unlock(&dev
->struct_mutex
);
1949 static int i915_execlists(struct seq_file
*m
, void *data
)
1951 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
1952 struct drm_device
*dev
= node
->minor
->dev
;
1953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1954 struct intel_engine_cs
*ring
;
1960 struct list_head
*cursor
;
1964 if (!i915
.enable_execlists
) {
1965 seq_puts(m
, "Logical Ring Contexts are disabled\n");
1969 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1973 intel_runtime_pm_get(dev_priv
);
1975 for_each_ring(ring
, dev_priv
, ring_id
) {
1976 struct drm_i915_gem_request
*head_req
= NULL
;
1978 unsigned long flags
;
1980 seq_printf(m
, "%s\n", ring
->name
);
1982 status
= I915_READ(RING_EXECLIST_STATUS(ring
));
1983 ctx_id
= I915_READ(RING_EXECLIST_STATUS(ring
) + 4);
1984 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
1987 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(ring
));
1988 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
1990 read_pointer
= ring
->next_context_status_buffer
;
1991 write_pointer
= status_pointer
& 0x07;
1992 if (read_pointer
> write_pointer
)
1994 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1995 read_pointer
, write_pointer
);
1997 for (i
= 0; i
< 6; i
++) {
1998 status
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
);
1999 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF(ring
) + 8*i
+ 4);
2001 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2005 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2006 list_for_each(cursor
, &ring
->execlist_queue
)
2008 head_req
= list_first_entry_or_null(&ring
->execlist_queue
,
2009 struct drm_i915_gem_request
, execlist_link
);
2010 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2012 seq_printf(m
, "\t%d requests in queue\n", count
);
2014 struct drm_i915_gem_object
*ctx_obj
;
2016 ctx_obj
= head_req
->ctx
->engine
[ring_id
].state
;
2017 seq_printf(m
, "\tHead request id: %u\n",
2018 intel_execlists_ctx_id(ctx_obj
));
2019 seq_printf(m
, "\tHead request tail: %u\n",
2026 intel_runtime_pm_put(dev_priv
);
2027 mutex_unlock(&dev
->struct_mutex
);
2032 static const char *swizzle_string(unsigned swizzle
)
2035 case I915_BIT_6_SWIZZLE_NONE
:
2037 case I915_BIT_6_SWIZZLE_9
:
2039 case I915_BIT_6_SWIZZLE_9_10
:
2040 return "bit9/bit10";
2041 case I915_BIT_6_SWIZZLE_9_11
:
2042 return "bit9/bit11";
2043 case I915_BIT_6_SWIZZLE_9_10_11
:
2044 return "bit9/bit10/bit11";
2045 case I915_BIT_6_SWIZZLE_9_17
:
2046 return "bit9/bit17";
2047 case I915_BIT_6_SWIZZLE_9_10_17
:
2048 return "bit9/bit10/bit17";
2049 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2056 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2058 struct drm_info_node
*node
= m
->private;
2059 struct drm_device
*dev
= node
->minor
->dev
;
2060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2063 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2066 intel_runtime_pm_get(dev_priv
);
2068 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2069 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2070 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2071 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2073 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2074 seq_printf(m
, "DDC = 0x%08x\n",
2076 seq_printf(m
, "DDC2 = 0x%08x\n",
2078 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2079 I915_READ16(C0DRB3
));
2080 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2081 I915_READ16(C1DRB3
));
2082 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2083 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2084 I915_READ(MAD_DIMM_C0
));
2085 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2086 I915_READ(MAD_DIMM_C1
));
2087 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2088 I915_READ(MAD_DIMM_C2
));
2089 seq_printf(m
, "TILECTL = 0x%08x\n",
2090 I915_READ(TILECTL
));
2091 if (INTEL_INFO(dev
)->gen
>= 8)
2092 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2093 I915_READ(GAMTARBMODE
));
2095 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2096 I915_READ(ARB_MODE
));
2097 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2098 I915_READ(DISP_ARB_CTL
));
2101 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2102 seq_puts(m
, "L-shaped memory detected\n");
2104 intel_runtime_pm_put(dev_priv
);
2105 mutex_unlock(&dev
->struct_mutex
);
2110 static int per_file_ctx(int id
, void *ptr
, void *data
)
2112 struct intel_context
*ctx
= ptr
;
2113 struct seq_file
*m
= data
;
2114 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2117 seq_printf(m
, " no ppgtt for context %d\n",
2122 if (i915_gem_context_is_default(ctx
))
2123 seq_puts(m
, " default context:\n");
2125 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2126 ppgtt
->debug_dump(ppgtt
, m
);
2131 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2134 struct intel_engine_cs
*ring
;
2135 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2141 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
2142 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
2143 for_each_ring(ring
, dev_priv
, unused
) {
2144 seq_printf(m
, "%s\n", ring
->name
);
2145 for (i
= 0; i
< 4; i
++) {
2146 u32 offset
= 0x270 + i
* 8;
2147 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
2149 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
2150 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2155 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2158 struct intel_engine_cs
*ring
;
2159 struct drm_file
*file
;
2162 if (INTEL_INFO(dev
)->gen
== 6)
2163 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2165 for_each_ring(ring
, dev_priv
, i
) {
2166 seq_printf(m
, "%s\n", ring
->name
);
2167 if (INTEL_INFO(dev
)->gen
== 7)
2168 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
2169 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
2170 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
2171 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
2173 if (dev_priv
->mm
.aliasing_ppgtt
) {
2174 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2176 seq_puts(m
, "aliasing PPGTT:\n");
2177 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
2179 ppgtt
->debug_dump(ppgtt
, m
);
2182 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2183 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2185 seq_printf(m
, "proc: %s\n",
2186 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
2187 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
2189 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2192 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2194 struct drm_info_node
*node
= m
->private;
2195 struct drm_device
*dev
= node
->minor
->dev
;
2196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2198 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2201 intel_runtime_pm_get(dev_priv
);
2203 if (INTEL_INFO(dev
)->gen
>= 8)
2204 gen8_ppgtt_info(m
, dev
);
2205 else if (INTEL_INFO(dev
)->gen
>= 6)
2206 gen6_ppgtt_info(m
, dev
);
2208 intel_runtime_pm_put(dev_priv
);
2209 mutex_unlock(&dev
->struct_mutex
);
2214 static int i915_llc(struct seq_file
*m
, void *data
)
2216 struct drm_info_node
*node
= m
->private;
2217 struct drm_device
*dev
= node
->minor
->dev
;
2218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2220 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2221 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2222 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
2227 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2229 struct drm_info_node
*node
= m
->private;
2230 struct drm_device
*dev
= node
->minor
->dev
;
2231 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2235 bool enabled
= false;
2237 intel_runtime_pm_get(dev_priv
);
2239 mutex_lock(&dev_priv
->psr
.lock
);
2240 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2241 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2242 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2243 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2244 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2245 dev_priv
->psr
.busy_frontbuffer_bits
);
2246 seq_printf(m
, "Re-enable work scheduled: %s\n",
2247 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2251 enabled
= I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
2253 for_each_pipe(dev_priv
, pipe
) {
2254 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2255 VLV_EDP_PSR_CURR_STATE_MASK
;
2256 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2257 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2262 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2265 for_each_pipe(dev_priv
, pipe
) {
2266 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2267 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2268 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2272 seq_printf(m
, "Link standby: %s\n",
2273 yesno((bool)dev_priv
->psr
.link_standby
));
2275 /* CHV PSR has no kind of performance counter */
2276 if (HAS_PSR(dev
) && HAS_DDI(dev
)) {
2277 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
2278 EDP_PSR_PERF_CNT_MASK
;
2280 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2282 mutex_unlock(&dev_priv
->psr
.lock
);
2284 intel_runtime_pm_put(dev_priv
);
2288 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2290 struct drm_info_node
*node
= m
->private;
2291 struct drm_device
*dev
= node
->minor
->dev
;
2292 struct intel_encoder
*encoder
;
2293 struct intel_connector
*connector
;
2294 struct intel_dp
*intel_dp
= NULL
;
2298 drm_modeset_lock_all(dev
);
2299 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
2302 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2305 if (!connector
->base
.encoder
)
2308 encoder
= to_intel_encoder(connector
->base
.encoder
);
2309 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2312 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2314 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2318 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2319 crc
[0], crc
[1], crc
[2],
2320 crc
[3], crc
[4], crc
[5]);
2325 drm_modeset_unlock_all(dev
);
2329 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2331 struct drm_info_node
*node
= m
->private;
2332 struct drm_device
*dev
= node
->minor
->dev
;
2333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2337 if (INTEL_INFO(dev
)->gen
< 6)
2340 intel_runtime_pm_get(dev_priv
);
2342 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2343 power
= (power
& 0x1f00) >> 8;
2344 units
= 1000000 / (1 << power
); /* convert to uJ */
2345 power
= I915_READ(MCH_SECP_NRG_STTS
);
2348 intel_runtime_pm_put(dev_priv
);
2350 seq_printf(m
, "%llu", (long long unsigned)power
);
2355 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2357 struct drm_info_node
*node
= m
->private;
2358 struct drm_device
*dev
= node
->minor
->dev
;
2359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2361 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2362 seq_puts(m
, "not supported\n");
2366 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2367 seq_printf(m
, "IRQs disabled: %s\n",
2368 yesno(!intel_irqs_enabled(dev_priv
)));
2373 static const char *power_domain_str(enum intel_display_power_domain domain
)
2376 case POWER_DOMAIN_PIPE_A
:
2378 case POWER_DOMAIN_PIPE_B
:
2380 case POWER_DOMAIN_PIPE_C
:
2382 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2383 return "PIPE_A_PANEL_FITTER";
2384 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2385 return "PIPE_B_PANEL_FITTER";
2386 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2387 return "PIPE_C_PANEL_FITTER";
2388 case POWER_DOMAIN_TRANSCODER_A
:
2389 return "TRANSCODER_A";
2390 case POWER_DOMAIN_TRANSCODER_B
:
2391 return "TRANSCODER_B";
2392 case POWER_DOMAIN_TRANSCODER_C
:
2393 return "TRANSCODER_C";
2394 case POWER_DOMAIN_TRANSCODER_EDP
:
2395 return "TRANSCODER_EDP";
2396 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2397 return "PORT_DDI_A_2_LANES";
2398 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2399 return "PORT_DDI_A_4_LANES";
2400 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2401 return "PORT_DDI_B_2_LANES";
2402 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2403 return "PORT_DDI_B_4_LANES";
2404 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2405 return "PORT_DDI_C_2_LANES";
2406 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2407 return "PORT_DDI_C_4_LANES";
2408 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2409 return "PORT_DDI_D_2_LANES";
2410 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2411 return "PORT_DDI_D_4_LANES";
2412 case POWER_DOMAIN_PORT_DSI
:
2414 case POWER_DOMAIN_PORT_CRT
:
2416 case POWER_DOMAIN_PORT_OTHER
:
2417 return "PORT_OTHER";
2418 case POWER_DOMAIN_VGA
:
2420 case POWER_DOMAIN_AUDIO
:
2422 case POWER_DOMAIN_PLLS
:
2424 case POWER_DOMAIN_AUX_A
:
2426 case POWER_DOMAIN_AUX_B
:
2428 case POWER_DOMAIN_AUX_C
:
2430 case POWER_DOMAIN_AUX_D
:
2432 case POWER_DOMAIN_INIT
:
2435 MISSING_CASE(domain
);
2440 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2442 struct drm_info_node
*node
= m
->private;
2443 struct drm_device
*dev
= node
->minor
->dev
;
2444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2445 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2448 mutex_lock(&power_domains
->lock
);
2450 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2451 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2452 struct i915_power_well
*power_well
;
2453 enum intel_display_power_domain power_domain
;
2455 power_well
= &power_domains
->power_wells
[i
];
2456 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2459 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2461 if (!(BIT(power_domain
) & power_well
->domains
))
2464 seq_printf(m
, " %-23s %d\n",
2465 power_domain_str(power_domain
),
2466 power_domains
->domain_use_count
[power_domain
]);
2470 mutex_unlock(&power_domains
->lock
);
2475 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2476 struct drm_display_mode
*mode
)
2480 for (i
= 0; i
< tabs
; i
++)
2483 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2484 mode
->base
.id
, mode
->name
,
2485 mode
->vrefresh
, mode
->clock
,
2486 mode
->hdisplay
, mode
->hsync_start
,
2487 mode
->hsync_end
, mode
->htotal
,
2488 mode
->vdisplay
, mode
->vsync_start
,
2489 mode
->vsync_end
, mode
->vtotal
,
2490 mode
->type
, mode
->flags
);
2493 static void intel_encoder_info(struct seq_file
*m
,
2494 struct intel_crtc
*intel_crtc
,
2495 struct intel_encoder
*intel_encoder
)
2497 struct drm_info_node
*node
= m
->private;
2498 struct drm_device
*dev
= node
->minor
->dev
;
2499 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2500 struct intel_connector
*intel_connector
;
2501 struct drm_encoder
*encoder
;
2503 encoder
= &intel_encoder
->base
;
2504 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2505 encoder
->base
.id
, encoder
->name
);
2506 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2507 struct drm_connector
*connector
= &intel_connector
->base
;
2508 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2511 drm_get_connector_status_name(connector
->status
));
2512 if (connector
->status
== connector_status_connected
) {
2513 struct drm_display_mode
*mode
= &crtc
->mode
;
2514 seq_printf(m
, ", mode:\n");
2515 intel_seq_print_mode(m
, 2, mode
);
2522 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2524 struct drm_info_node
*node
= m
->private;
2525 struct drm_device
*dev
= node
->minor
->dev
;
2526 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2527 struct intel_encoder
*intel_encoder
;
2529 if (crtc
->primary
->fb
)
2530 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2531 crtc
->primary
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2532 crtc
->primary
->fb
->width
, crtc
->primary
->fb
->height
);
2534 seq_puts(m
, "\tprimary plane disabled\n");
2535 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2536 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2539 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2541 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2543 seq_printf(m
, "\tfixed mode:\n");
2544 intel_seq_print_mode(m
, 2, mode
);
2547 static void intel_dp_info(struct seq_file
*m
,
2548 struct intel_connector
*intel_connector
)
2550 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2551 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2553 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2554 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2556 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2557 intel_panel_info(m
, &intel_connector
->panel
);
2560 static void intel_hdmi_info(struct seq_file
*m
,
2561 struct intel_connector
*intel_connector
)
2563 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2564 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2566 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2570 static void intel_lvds_info(struct seq_file
*m
,
2571 struct intel_connector
*intel_connector
)
2573 intel_panel_info(m
, &intel_connector
->panel
);
2576 static void intel_connector_info(struct seq_file
*m
,
2577 struct drm_connector
*connector
)
2579 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2580 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2581 struct drm_display_mode
*mode
;
2583 seq_printf(m
, "connector %d: type %s, status: %s\n",
2584 connector
->base
.id
, connector
->name
,
2585 drm_get_connector_status_name(connector
->status
));
2586 if (connector
->status
== connector_status_connected
) {
2587 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2588 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2589 connector
->display_info
.width_mm
,
2590 connector
->display_info
.height_mm
);
2591 seq_printf(m
, "\tsubpixel order: %s\n",
2592 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2593 seq_printf(m
, "\tCEA rev: %d\n",
2594 connector
->display_info
.cea_rev
);
2596 if (intel_encoder
) {
2597 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2598 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2599 intel_dp_info(m
, intel_connector
);
2600 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2601 intel_hdmi_info(m
, intel_connector
);
2602 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2603 intel_lvds_info(m
, intel_connector
);
2606 seq_printf(m
, "\tmodes:\n");
2607 list_for_each_entry(mode
, &connector
->modes
, head
)
2608 intel_seq_print_mode(m
, 2, mode
);
2611 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2616 if (IS_845G(dev
) || IS_I865G(dev
))
2617 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2619 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2624 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2629 pos
= I915_READ(CURPOS(pipe
));
2631 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2632 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2635 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2636 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2639 return cursor_active(dev
, pipe
);
2642 static int i915_display_info(struct seq_file
*m
, void *unused
)
2644 struct drm_info_node
*node
= m
->private;
2645 struct drm_device
*dev
= node
->minor
->dev
;
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2647 struct intel_crtc
*crtc
;
2648 struct drm_connector
*connector
;
2650 intel_runtime_pm_get(dev_priv
);
2651 drm_modeset_lock_all(dev
);
2652 seq_printf(m
, "CRTC info\n");
2653 seq_printf(m
, "---------\n");
2654 for_each_intel_crtc(dev
, crtc
) {
2658 seq_printf(m
, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2659 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2660 yesno(crtc
->active
), crtc
->config
->pipe_src_w
,
2661 crtc
->config
->pipe_src_h
);
2663 intel_crtc_info(m
, crtc
);
2665 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2666 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2667 yesno(crtc
->cursor_base
),
2668 x
, y
, crtc
->cursor_width
, crtc
->cursor_height
,
2669 crtc
->cursor_addr
, yesno(active
));
2672 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
2673 yesno(!crtc
->cpu_fifo_underrun_disabled
),
2674 yesno(!crtc
->pch_fifo_underrun_disabled
));
2677 seq_printf(m
, "\n");
2678 seq_printf(m
, "Connector info\n");
2679 seq_printf(m
, "--------------\n");
2680 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2681 intel_connector_info(m
, connector
);
2683 drm_modeset_unlock_all(dev
);
2684 intel_runtime_pm_put(dev_priv
);
2689 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
2691 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2692 struct drm_device
*dev
= node
->minor
->dev
;
2693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2694 struct intel_engine_cs
*ring
;
2695 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
2698 if (!i915_semaphore_is_enabled(dev
)) {
2699 seq_puts(m
, "Semaphores are disabled\n");
2703 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2706 intel_runtime_pm_get(dev_priv
);
2708 if (IS_BROADWELL(dev
)) {
2712 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
2714 seqno
= (uint64_t *)kmap_atomic(page
);
2715 for_each_ring(ring
, dev_priv
, i
) {
2718 seq_printf(m
, "%s\n", ring
->name
);
2720 seq_puts(m
, " Last signal:");
2721 for (j
= 0; j
< num_rings
; j
++) {
2722 offset
= i
* I915_NUM_RINGS
+ j
;
2723 seq_printf(m
, "0x%08llx (0x%02llx) ",
2724 seqno
[offset
], offset
* 8);
2728 seq_puts(m
, " Last wait: ");
2729 for (j
= 0; j
< num_rings
; j
++) {
2730 offset
= i
+ (j
* I915_NUM_RINGS
);
2731 seq_printf(m
, "0x%08llx (0x%02llx) ",
2732 seqno
[offset
], offset
* 8);
2737 kunmap_atomic(seqno
);
2739 seq_puts(m
, " Last signal:");
2740 for_each_ring(ring
, dev_priv
, i
)
2741 for (j
= 0; j
< num_rings
; j
++)
2742 seq_printf(m
, "0x%08x\n",
2743 I915_READ(ring
->semaphore
.mbox
.signal
[j
]));
2747 seq_puts(m
, "\nSync seqno:\n");
2748 for_each_ring(ring
, dev_priv
, i
) {
2749 for (j
= 0; j
< num_rings
; j
++) {
2750 seq_printf(m
, " 0x%08x ", ring
->semaphore
.sync_seqno
[j
]);
2756 intel_runtime_pm_put(dev_priv
);
2757 mutex_unlock(&dev
->struct_mutex
);
2761 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
2763 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2764 struct drm_device
*dev
= node
->minor
->dev
;
2765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2768 drm_modeset_lock_all(dev
);
2769 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
2770 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
2772 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
2773 seq_printf(m
, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2774 pll
->config
.crtc_mask
, pll
->active
, yesno(pll
->on
));
2775 seq_printf(m
, " tracked hardware state:\n");
2776 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
2777 seq_printf(m
, " dpll_md: 0x%08x\n",
2778 pll
->config
.hw_state
.dpll_md
);
2779 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
2780 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
2781 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
2783 drm_modeset_unlock_all(dev
);
2788 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
2792 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2793 struct drm_device
*dev
= node
->minor
->dev
;
2794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2796 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2800 intel_runtime_pm_get(dev_priv
);
2802 seq_printf(m
, "Workarounds applied: %d\n", dev_priv
->workarounds
.count
);
2803 for (i
= 0; i
< dev_priv
->workarounds
.count
; ++i
) {
2804 u32 addr
, mask
, value
, read
;
2807 addr
= dev_priv
->workarounds
.reg
[i
].addr
;
2808 mask
= dev_priv
->workarounds
.reg
[i
].mask
;
2809 value
= dev_priv
->workarounds
.reg
[i
].value
;
2810 read
= I915_READ(addr
);
2811 ok
= (value
& mask
) == (read
& mask
);
2812 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2813 addr
, value
, mask
, read
, ok
? "OK" : "FAIL");
2816 intel_runtime_pm_put(dev_priv
);
2817 mutex_unlock(&dev
->struct_mutex
);
2822 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
2824 struct drm_info_node
*node
= m
->private;
2825 struct drm_device
*dev
= node
->minor
->dev
;
2826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2827 struct skl_ddb_allocation
*ddb
;
2828 struct skl_ddb_entry
*entry
;
2832 if (INTEL_INFO(dev
)->gen
< 9)
2835 drm_modeset_lock_all(dev
);
2837 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
2839 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2841 for_each_pipe(dev_priv
, pipe
) {
2842 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
2844 for_each_plane(pipe
, plane
) {
2845 entry
= &ddb
->plane
[pipe
][plane
];
2846 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
2847 entry
->start
, entry
->end
,
2848 skl_ddb_entry_size(entry
));
2851 entry
= &ddb
->cursor
[pipe
];
2852 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
2853 entry
->end
, skl_ddb_entry_size(entry
));
2856 drm_modeset_unlock_all(dev
);
2861 struct pipe_crc_info
{
2863 struct drm_device
*dev
;
2867 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
2869 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2870 struct drm_device
*dev
= node
->minor
->dev
;
2871 struct drm_encoder
*encoder
;
2872 struct intel_encoder
*intel_encoder
;
2873 struct intel_digital_port
*intel_dig_port
;
2874 drm_modeset_lock_all(dev
);
2875 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2876 intel_encoder
= to_intel_encoder(encoder
);
2877 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
2879 intel_dig_port
= enc_to_dig_port(encoder
);
2880 if (!intel_dig_port
->dp
.can_mst
)
2883 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
2885 drm_modeset_unlock_all(dev
);
2889 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2891 struct pipe_crc_info
*info
= inode
->i_private
;
2892 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2893 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2895 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2898 spin_lock_irq(&pipe_crc
->lock
);
2900 if (pipe_crc
->opened
) {
2901 spin_unlock_irq(&pipe_crc
->lock
);
2902 return -EBUSY
; /* already open */
2905 pipe_crc
->opened
= true;
2906 filep
->private_data
= inode
->i_private
;
2908 spin_unlock_irq(&pipe_crc
->lock
);
2913 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2915 struct pipe_crc_info
*info
= inode
->i_private
;
2916 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2917 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2919 spin_lock_irq(&pipe_crc
->lock
);
2920 pipe_crc
->opened
= false;
2921 spin_unlock_irq(&pipe_crc
->lock
);
2926 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2927 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2928 /* account for \'0' */
2929 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2931 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2933 assert_spin_locked(&pipe_crc
->lock
);
2934 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2935 INTEL_PIPE_CRC_ENTRIES_NR
);
2939 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2942 struct pipe_crc_info
*info
= filep
->private_data
;
2943 struct drm_device
*dev
= info
->dev
;
2944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2945 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2946 char buf
[PIPE_CRC_BUFFER_LEN
];
2951 * Don't allow user space to provide buffers not big enough to hold
2954 if (count
< PIPE_CRC_LINE_LEN
)
2957 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2960 /* nothing to read */
2961 spin_lock_irq(&pipe_crc
->lock
);
2962 while (pipe_crc_data_count(pipe_crc
) == 0) {
2965 if (filep
->f_flags
& O_NONBLOCK
) {
2966 spin_unlock_irq(&pipe_crc
->lock
);
2970 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2971 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2973 spin_unlock_irq(&pipe_crc
->lock
);
2978 /* We now have one or more entries to read */
2979 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
2982 while (n_entries
> 0) {
2983 struct intel_pipe_crc_entry
*entry
=
2984 &pipe_crc
->entries
[pipe_crc
->tail
];
2987 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2988 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
2991 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2992 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2994 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2995 "%8u %8x %8x %8x %8x %8x\n",
2996 entry
->frame
, entry
->crc
[0],
2997 entry
->crc
[1], entry
->crc
[2],
2998 entry
->crc
[3], entry
->crc
[4]);
3000 spin_unlock_irq(&pipe_crc
->lock
);
3002 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3003 if (ret
== PIPE_CRC_LINE_LEN
)
3006 user_buf
+= PIPE_CRC_LINE_LEN
;
3009 spin_lock_irq(&pipe_crc
->lock
);
3012 spin_unlock_irq(&pipe_crc
->lock
);
3017 static const struct file_operations i915_pipe_crc_fops
= {
3018 .owner
= THIS_MODULE
,
3019 .open
= i915_pipe_crc_open
,
3020 .read
= i915_pipe_crc_read
,
3021 .release
= i915_pipe_crc_release
,
3024 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3026 .name
= "i915_pipe_A_crc",
3030 .name
= "i915_pipe_B_crc",
3034 .name
= "i915_pipe_C_crc",
3039 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3042 struct drm_device
*dev
= minor
->dev
;
3044 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3047 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3048 &i915_pipe_crc_fops
);
3052 return drm_add_fake_info_node(minor
, ent
, info
);
3055 static const char * const pipe_crc_sources
[] = {
3068 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3070 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3071 return pipe_crc_sources
[source
];
3074 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3076 struct drm_device
*dev
= m
->private;
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3080 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3081 seq_printf(m
, "%c %s\n", pipe_name(i
),
3082 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3087 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3089 struct drm_device
*dev
= inode
->i_private
;
3091 return single_open(file
, display_crc_ctl_show
, dev
);
3094 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3097 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3098 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3101 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3102 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3104 case INTEL_PIPE_CRC_SOURCE_NONE
:
3114 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3115 enum intel_pipe_crc_source
*source
)
3117 struct intel_encoder
*encoder
;
3118 struct intel_crtc
*crtc
;
3119 struct intel_digital_port
*dig_port
;
3122 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3124 drm_modeset_lock_all(dev
);
3125 for_each_intel_encoder(dev
, encoder
) {
3126 if (!encoder
->base
.crtc
)
3129 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3131 if (crtc
->pipe
!= pipe
)
3134 switch (encoder
->type
) {
3135 case INTEL_OUTPUT_TVOUT
:
3136 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3138 case INTEL_OUTPUT_DISPLAYPORT
:
3139 case INTEL_OUTPUT_EDP
:
3140 dig_port
= enc_to_dig_port(&encoder
->base
);
3141 switch (dig_port
->port
) {
3143 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3146 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3149 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3152 WARN(1, "nonexisting DP port %c\n",
3153 port_name(dig_port
->port
));
3161 drm_modeset_unlock_all(dev
);
3166 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3168 enum intel_pipe_crc_source
*source
,
3171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3172 bool need_stable_symbols
= false;
3174 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3175 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3181 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3182 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3184 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3185 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3186 need_stable_symbols
= true;
3188 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3189 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3190 need_stable_symbols
= true;
3192 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3193 if (!IS_CHERRYVIEW(dev
))
3195 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3196 need_stable_symbols
= true;
3198 case INTEL_PIPE_CRC_SOURCE_NONE
:
3206 * When the pipe CRC tap point is after the transcoders we need
3207 * to tweak symbol-level features to produce a deterministic series of
3208 * symbols for a given frame. We need to reset those features only once
3209 * a frame (instead of every nth symbol):
3210 * - DC-balance: used to ensure a better clock recovery from the data
3212 * - DisplayPort scrambling: used for EMI reduction
3214 if (need_stable_symbols
) {
3215 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3217 tmp
|= DC_BALANCE_RESET_VLV
;
3220 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3223 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3226 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3231 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3237 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3239 enum intel_pipe_crc_source
*source
,
3242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3243 bool need_stable_symbols
= false;
3245 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3246 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3252 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3253 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3255 case INTEL_PIPE_CRC_SOURCE_TV
:
3256 if (!SUPPORTS_TV(dev
))
3258 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3260 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3263 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3264 need_stable_symbols
= true;
3266 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3269 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3270 need_stable_symbols
= true;
3272 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3275 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3276 need_stable_symbols
= true;
3278 case INTEL_PIPE_CRC_SOURCE_NONE
:
3286 * When the pipe CRC tap point is after the transcoders we need
3287 * to tweak symbol-level features to produce a deterministic series of
3288 * symbols for a given frame. We need to reset those features only once
3289 * a frame (instead of every nth symbol):
3290 * - DC-balance: used to ensure a better clock recovery from the data
3292 * - DisplayPort scrambling: used for EMI reduction
3294 if (need_stable_symbols
) {
3295 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3297 WARN_ON(!IS_G4X(dev
));
3299 I915_WRITE(PORT_DFT_I9XX
,
3300 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3303 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3305 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3307 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3313 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3317 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3321 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3324 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3327 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3332 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3333 tmp
&= ~DC_BALANCE_RESET_VLV
;
3334 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3338 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3342 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3345 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3347 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3348 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3350 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3351 I915_WRITE(PORT_DFT_I9XX
,
3352 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3356 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3359 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3360 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3363 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3364 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3366 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3367 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3369 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3370 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3372 case INTEL_PIPE_CRC_SOURCE_NONE
:
3382 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3385 struct intel_crtc
*crtc
=
3386 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3388 drm_modeset_lock_all(dev
);
3390 * If we use the eDP transcoder we need to make sure that we don't
3391 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3392 * relevant on hsw with pipe A when using the always-on power well
3395 if (crtc
->config
->cpu_transcoder
== TRANSCODER_EDP
&&
3396 !crtc
->config
->pch_pfit
.enabled
) {
3397 crtc
->config
->pch_pfit
.force_thru
= true;
3399 intel_display_power_get(dev_priv
,
3400 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3402 dev_priv
->display
.crtc_disable(&crtc
->base
);
3403 dev_priv
->display
.crtc_enable(&crtc
->base
);
3405 drm_modeset_unlock_all(dev
);
3408 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
)
3410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3411 struct intel_crtc
*crtc
=
3412 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3414 drm_modeset_lock_all(dev
);
3416 * If we use the eDP transcoder we need to make sure that we don't
3417 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3418 * relevant on hsw with pipe A when using the always-on power well
3421 if (crtc
->config
->pch_pfit
.force_thru
) {
3422 crtc
->config
->pch_pfit
.force_thru
= false;
3424 dev_priv
->display
.crtc_disable(&crtc
->base
);
3425 dev_priv
->display
.crtc_enable(&crtc
->base
);
3427 intel_display_power_put(dev_priv
,
3428 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A
));
3430 drm_modeset_unlock_all(dev
);
3433 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
3435 enum intel_pipe_crc_source
*source
,
3438 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3439 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
3442 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3443 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
3445 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3446 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
3448 case INTEL_PIPE_CRC_SOURCE_PF
:
3449 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3450 hsw_trans_edp_pipe_A_crc_wa(dev
);
3452 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
3454 case INTEL_PIPE_CRC_SOURCE_NONE
:
3464 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
3465 enum intel_pipe_crc_source source
)
3467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3468 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3469 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
3471 u32 val
= 0; /* shut up gcc */
3474 if (pipe_crc
->source
== source
)
3477 /* forbid changing the source without going back to 'none' */
3478 if (pipe_crc
->source
&& source
)
3481 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PIPE(pipe
))) {
3482 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3487 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
3488 else if (INTEL_INFO(dev
)->gen
< 5)
3489 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3490 else if (IS_VALLEYVIEW(dev
))
3491 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3492 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
3493 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
3495 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
3500 /* none -> real source transition */
3502 struct intel_pipe_crc_entry
*entries
;
3504 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3505 pipe_name(pipe
), pipe_crc_source_name(source
));
3507 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
3508 sizeof(pipe_crc
->entries
[0]),
3514 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3515 * enabled and disabled dynamically based on package C states,
3516 * user space can't make reliable use of the CRCs, so let's just
3517 * completely disable it.
3519 hsw_disable_ips(crtc
);
3521 spin_lock_irq(&pipe_crc
->lock
);
3522 kfree(pipe_crc
->entries
);
3523 pipe_crc
->entries
= entries
;
3526 spin_unlock_irq(&pipe_crc
->lock
);
3529 pipe_crc
->source
= source
;
3531 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
3532 POSTING_READ(PIPE_CRC_CTL(pipe
));
3534 /* real source -> none transition */
3535 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
3536 struct intel_pipe_crc_entry
*entries
;
3537 struct intel_crtc
*crtc
=
3538 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
3540 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3543 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
3545 intel_wait_for_vblank(dev
, pipe
);
3546 drm_modeset_unlock(&crtc
->base
.mutex
);
3548 spin_lock_irq(&pipe_crc
->lock
);
3549 entries
= pipe_crc
->entries
;
3550 pipe_crc
->entries
= NULL
;
3553 spin_unlock_irq(&pipe_crc
->lock
);
3558 g4x_undo_pipe_scramble_reset(dev
, pipe
);
3559 else if (IS_VALLEYVIEW(dev
))
3560 vlv_undo_pipe_scramble_reset(dev
, pipe
);
3561 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
3562 hsw_undo_trans_edp_pipe_A_crc_wa(dev
);
3564 hsw_enable_ips(crtc
);
3571 * Parse pipe CRC command strings:
3572 * command: wsp* object wsp+ name wsp+ source wsp*
3575 * source: (none | plane1 | plane2 | pf)
3576 * wsp: (#0x20 | #0x9 | #0xA)+
3579 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3580 * "pipe A none" -> Stop CRC
3582 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
3589 /* skip leading white space */
3590 buf
= skip_spaces(buf
);
3592 break; /* end of buffer */
3594 /* find end of word */
3595 for (end
= buf
; *end
&& !isspace(*end
); end
++)
3598 if (n_words
== max_words
) {
3599 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3601 return -EINVAL
; /* ran out of words[] before bytes */
3606 words
[n_words
++] = buf
;
3613 enum intel_pipe_crc_object
{
3614 PIPE_CRC_OBJECT_PIPE
,
3617 static const char * const pipe_crc_objects
[] = {
3622 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
3626 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
3627 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
3635 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
3637 const char name
= buf
[0];
3639 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3648 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3652 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3653 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3661 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3665 char *words
[N_WORDS
];
3667 enum intel_pipe_crc_object object
;
3668 enum intel_pipe_crc_source source
;
3670 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3671 if (n_words
!= N_WORDS
) {
3672 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3677 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3678 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3682 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3683 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3687 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3688 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3692 return pipe_crc_set_source(dev
, pipe
, source
);
3695 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3696 size_t len
, loff_t
*offp
)
3698 struct seq_file
*m
= file
->private_data
;
3699 struct drm_device
*dev
= m
->private;
3706 if (len
> PAGE_SIZE
- 1) {
3707 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3712 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3716 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3722 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3733 static const struct file_operations i915_display_crc_ctl_fops
= {
3734 .owner
= THIS_MODULE
,
3735 .open
= display_crc_ctl_open
,
3737 .llseek
= seq_lseek
,
3738 .release
= single_release
,
3739 .write
= display_crc_ctl_write
3742 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
3744 struct drm_device
*dev
= m
->private;
3745 int num_levels
= ilk_wm_max_level(dev
) + 1;
3748 drm_modeset_lock_all(dev
);
3750 for (level
= 0; level
< num_levels
; level
++) {
3751 unsigned int latency
= wm
[level
];
3754 * - WM1+ latency values in 0.5us units
3755 * - latencies are in us on gen9
3757 if (INTEL_INFO(dev
)->gen
>= 9)
3762 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3763 level
, wm
[level
], latency
/ 10, latency
% 10);
3766 drm_modeset_unlock_all(dev
);
3769 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3771 struct drm_device
*dev
= m
->private;
3772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3773 const uint16_t *latencies
;
3775 if (INTEL_INFO(dev
)->gen
>= 9)
3776 latencies
= dev_priv
->wm
.skl_latency
;
3778 latencies
= to_i915(dev
)->wm
.pri_latency
;
3780 wm_latency_show(m
, latencies
);
3785 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3787 struct drm_device
*dev
= m
->private;
3788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3789 const uint16_t *latencies
;
3791 if (INTEL_INFO(dev
)->gen
>= 9)
3792 latencies
= dev_priv
->wm
.skl_latency
;
3794 latencies
= to_i915(dev
)->wm
.spr_latency
;
3796 wm_latency_show(m
, latencies
);
3801 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3803 struct drm_device
*dev
= m
->private;
3804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3805 const uint16_t *latencies
;
3807 if (INTEL_INFO(dev
)->gen
>= 9)
3808 latencies
= dev_priv
->wm
.skl_latency
;
3810 latencies
= to_i915(dev
)->wm
.cur_latency
;
3812 wm_latency_show(m
, latencies
);
3817 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3819 struct drm_device
*dev
= inode
->i_private
;
3821 if (HAS_GMCH_DISPLAY(dev
))
3824 return single_open(file
, pri_wm_latency_show
, dev
);
3827 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3829 struct drm_device
*dev
= inode
->i_private
;
3831 if (HAS_GMCH_DISPLAY(dev
))
3834 return single_open(file
, spr_wm_latency_show
, dev
);
3837 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3839 struct drm_device
*dev
= inode
->i_private
;
3841 if (HAS_GMCH_DISPLAY(dev
))
3844 return single_open(file
, cur_wm_latency_show
, dev
);
3847 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3848 size_t len
, loff_t
*offp
, uint16_t wm
[8])
3850 struct seq_file
*m
= file
->private_data
;
3851 struct drm_device
*dev
= m
->private;
3852 uint16_t new[8] = { 0 };
3853 int num_levels
= ilk_wm_max_level(dev
) + 1;
3858 if (len
>= sizeof(tmp
))
3861 if (copy_from_user(tmp
, ubuf
, len
))
3866 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
3867 &new[0], &new[1], &new[2], &new[3],
3868 &new[4], &new[5], &new[6], &new[7]);
3869 if (ret
!= num_levels
)
3872 drm_modeset_lock_all(dev
);
3874 for (level
= 0; level
< num_levels
; level
++)
3875 wm
[level
] = new[level
];
3877 drm_modeset_unlock_all(dev
);
3883 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3884 size_t len
, loff_t
*offp
)
3886 struct seq_file
*m
= file
->private_data
;
3887 struct drm_device
*dev
= m
->private;
3888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3889 uint16_t *latencies
;
3891 if (INTEL_INFO(dev
)->gen
>= 9)
3892 latencies
= dev_priv
->wm
.skl_latency
;
3894 latencies
= to_i915(dev
)->wm
.pri_latency
;
3896 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3899 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3900 size_t len
, loff_t
*offp
)
3902 struct seq_file
*m
= file
->private_data
;
3903 struct drm_device
*dev
= m
->private;
3904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3905 uint16_t *latencies
;
3907 if (INTEL_INFO(dev
)->gen
>= 9)
3908 latencies
= dev_priv
->wm
.skl_latency
;
3910 latencies
= to_i915(dev
)->wm
.spr_latency
;
3912 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3915 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3916 size_t len
, loff_t
*offp
)
3918 struct seq_file
*m
= file
->private_data
;
3919 struct drm_device
*dev
= m
->private;
3920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3921 uint16_t *latencies
;
3923 if (INTEL_INFO(dev
)->gen
>= 9)
3924 latencies
= dev_priv
->wm
.skl_latency
;
3926 latencies
= to_i915(dev
)->wm
.cur_latency
;
3928 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
3931 static const struct file_operations i915_pri_wm_latency_fops
= {
3932 .owner
= THIS_MODULE
,
3933 .open
= pri_wm_latency_open
,
3935 .llseek
= seq_lseek
,
3936 .release
= single_release
,
3937 .write
= pri_wm_latency_write
3940 static const struct file_operations i915_spr_wm_latency_fops
= {
3941 .owner
= THIS_MODULE
,
3942 .open
= spr_wm_latency_open
,
3944 .llseek
= seq_lseek
,
3945 .release
= single_release
,
3946 .write
= spr_wm_latency_write
3949 static const struct file_operations i915_cur_wm_latency_fops
= {
3950 .owner
= THIS_MODULE
,
3951 .open
= cur_wm_latency_open
,
3953 .llseek
= seq_lseek
,
3954 .release
= single_release
,
3955 .write
= cur_wm_latency_write
3959 i915_wedged_get(void *data
, u64
*val
)
3961 struct drm_device
*dev
= data
;
3962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3964 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3970 i915_wedged_set(void *data
, u64 val
)
3972 struct drm_device
*dev
= data
;
3973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3976 * There is no safeguard against this debugfs entry colliding
3977 * with the hangcheck calling same i915_handle_error() in
3978 * parallel, causing an explosion. For now we assume that the
3979 * test harness is responsible enough not to inject gpu hangs
3980 * while it is writing to 'i915_wedged'
3983 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
3986 intel_runtime_pm_get(dev_priv
);
3988 i915_handle_error(dev
, val
,
3989 "Manually setting wedged to %llu", val
);
3991 intel_runtime_pm_put(dev_priv
);
3996 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3997 i915_wedged_get
, i915_wedged_set
,
4001 i915_ring_stop_get(void *data
, u64
*val
)
4003 struct drm_device
*dev
= data
;
4004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4006 *val
= dev_priv
->gpu_error
.stop_rings
;
4012 i915_ring_stop_set(void *data
, u64 val
)
4014 struct drm_device
*dev
= data
;
4015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4018 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4020 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4024 dev_priv
->gpu_error
.stop_rings
= val
;
4025 mutex_unlock(&dev
->struct_mutex
);
4030 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4031 i915_ring_stop_get
, i915_ring_stop_set
,
4035 i915_ring_missed_irq_get(void *data
, u64
*val
)
4037 struct drm_device
*dev
= data
;
4038 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4040 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4045 i915_ring_missed_irq_set(void *data
, u64 val
)
4047 struct drm_device
*dev
= data
;
4048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4051 /* Lock against concurrent debugfs callers */
4052 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4055 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4056 mutex_unlock(&dev
->struct_mutex
);
4061 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4062 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4066 i915_ring_test_irq_get(void *data
, u64
*val
)
4068 struct drm_device
*dev
= data
;
4069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4071 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4077 i915_ring_test_irq_set(void *data
, u64 val
)
4079 struct drm_device
*dev
= data
;
4080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4083 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4085 /* Lock against concurrent debugfs callers */
4086 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4090 dev_priv
->gpu_error
.test_irq_rings
= val
;
4091 mutex_unlock(&dev
->struct_mutex
);
4096 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4097 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4100 #define DROP_UNBOUND 0x1
4101 #define DROP_BOUND 0x2
4102 #define DROP_RETIRE 0x4
4103 #define DROP_ACTIVE 0x8
4104 #define DROP_ALL (DROP_UNBOUND | \
4109 i915_drop_caches_get(void *data
, u64
*val
)
4117 i915_drop_caches_set(void *data
, u64 val
)
4119 struct drm_device
*dev
= data
;
4120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4123 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4125 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4126 * on ioctls on -EAGAIN. */
4127 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4131 if (val
& DROP_ACTIVE
) {
4132 ret
= i915_gpu_idle(dev
);
4137 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4138 i915_gem_retire_requests(dev
);
4140 if (val
& DROP_BOUND
)
4141 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4143 if (val
& DROP_UNBOUND
)
4144 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4147 mutex_unlock(&dev
->struct_mutex
);
4152 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4153 i915_drop_caches_get
, i915_drop_caches_set
,
4157 i915_max_freq_get(void *data
, u64
*val
)
4159 struct drm_device
*dev
= data
;
4160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4163 if (INTEL_INFO(dev
)->gen
< 6)
4166 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4168 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4172 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4173 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4179 i915_max_freq_set(void *data
, u64 val
)
4181 struct drm_device
*dev
= data
;
4182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4183 u32 rp_state_cap
, hw_max
, hw_min
;
4186 if (INTEL_INFO(dev
)->gen
< 6)
4189 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4191 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4193 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4198 * Turbo will still be enabled, but won't go above the set value.
4200 if (IS_VALLEYVIEW(dev
)) {
4201 val
= intel_freq_opcode(dev_priv
, val
);
4203 hw_max
= dev_priv
->rps
.max_freq
;
4204 hw_min
= dev_priv
->rps
.min_freq
;
4206 val
= intel_freq_opcode(dev_priv
, val
);
4208 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4209 hw_max
= dev_priv
->rps
.max_freq
;
4210 hw_min
= (rp_state_cap
>> 16) & 0xff;
4213 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4214 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4218 dev_priv
->rps
.max_freq_softlimit
= val
;
4220 intel_set_rps(dev
, val
);
4222 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4227 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
4228 i915_max_freq_get
, i915_max_freq_set
,
4232 i915_min_freq_get(void *data
, u64
*val
)
4234 struct drm_device
*dev
= data
;
4235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4238 if (INTEL_INFO(dev
)->gen
< 6)
4241 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4243 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4247 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
4248 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4254 i915_min_freq_set(void *data
, u64 val
)
4256 struct drm_device
*dev
= data
;
4257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4258 u32 rp_state_cap
, hw_max
, hw_min
;
4261 if (INTEL_INFO(dev
)->gen
< 6)
4264 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4266 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
4268 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4273 * Turbo will still be enabled, but won't go below the set value.
4275 if (IS_VALLEYVIEW(dev
)) {
4276 val
= intel_freq_opcode(dev_priv
, val
);
4278 hw_max
= dev_priv
->rps
.max_freq
;
4279 hw_min
= dev_priv
->rps
.min_freq
;
4281 val
= intel_freq_opcode(dev_priv
, val
);
4283 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
4284 hw_max
= dev_priv
->rps
.max_freq
;
4285 hw_min
= (rp_state_cap
>> 16) & 0xff;
4288 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
4289 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4293 dev_priv
->rps
.min_freq_softlimit
= val
;
4295 intel_set_rps(dev
, val
);
4297 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4302 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
4303 i915_min_freq_get
, i915_min_freq_set
,
4307 i915_cache_sharing_get(void *data
, u64
*val
)
4309 struct drm_device
*dev
= data
;
4310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4314 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4317 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4320 intel_runtime_pm_get(dev_priv
);
4322 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4324 intel_runtime_pm_put(dev_priv
);
4325 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
4327 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
4333 i915_cache_sharing_set(void *data
, u64 val
)
4335 struct drm_device
*dev
= data
;
4336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4339 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
4345 intel_runtime_pm_get(dev_priv
);
4346 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
4348 /* Update the cache sharing policy here as well */
4349 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
4350 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
4351 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
4352 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
4354 intel_runtime_pm_put(dev_priv
);
4358 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
4359 i915_cache_sharing_get
, i915_cache_sharing_set
,
4362 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
4364 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
4365 struct drm_device
*dev
= node
->minor
->dev
;
4366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4367 unsigned int s_tot
= 0, ss_tot
= 0, ss_per
= 0, eu_tot
= 0, eu_per
= 0;
4369 if (INTEL_INFO(dev
)->gen
< 9)
4372 seq_puts(m
, "SSEU Device Info\n");
4373 seq_printf(m
, " Available Slice Total: %u\n",
4374 INTEL_INFO(dev
)->slice_total
);
4375 seq_printf(m
, " Available Subslice Total: %u\n",
4376 INTEL_INFO(dev
)->subslice_total
);
4377 seq_printf(m
, " Available Subslice Per Slice: %u\n",
4378 INTEL_INFO(dev
)->subslice_per_slice
);
4379 seq_printf(m
, " Available EU Total: %u\n",
4380 INTEL_INFO(dev
)->eu_total
);
4381 seq_printf(m
, " Available EU Per Subslice: %u\n",
4382 INTEL_INFO(dev
)->eu_per_subslice
);
4383 seq_printf(m
, " Has Slice Power Gating: %s\n",
4384 yesno(INTEL_INFO(dev
)->has_slice_pg
));
4385 seq_printf(m
, " Has Subslice Power Gating: %s\n",
4386 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
4387 seq_printf(m
, " Has EU Power Gating: %s\n",
4388 yesno(INTEL_INFO(dev
)->has_eu_pg
));
4390 seq_puts(m
, "SSEU Device Status\n");
4391 if (IS_SKYLAKE(dev
)) {
4392 const int s_max
= 3, ss_max
= 4;
4394 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
4396 s_reg
[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK
);
4397 s_reg
[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK
);
4398 s_reg
[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK
);
4399 eu_reg
[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK
);
4400 eu_reg
[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK
);
4401 eu_reg
[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK
);
4402 eu_reg
[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK
);
4403 eu_reg
[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK
);
4404 eu_reg
[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK
);
4405 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
4406 GEN9_PGCTL_SSA_EU19_ACK
|
4407 GEN9_PGCTL_SSA_EU210_ACK
|
4408 GEN9_PGCTL_SSA_EU311_ACK
;
4409 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
4410 GEN9_PGCTL_SSB_EU19_ACK
|
4411 GEN9_PGCTL_SSB_EU210_ACK
|
4412 GEN9_PGCTL_SSB_EU311_ACK
;
4414 for (s
= 0; s
< s_max
; s
++) {
4415 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
4416 /* skip disabled slice */
4420 ss_per
= INTEL_INFO(dev
)->subslice_per_slice
;
4422 for (ss
= 0; ss
< ss_max
; ss
++) {
4423 unsigned int eu_cnt
;
4425 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
4428 eu_per
= max(eu_per
, eu_cnt
);
4432 seq_printf(m
, " Enabled Slice Total: %u\n", s_tot
);
4433 seq_printf(m
, " Enabled Subslice Total: %u\n", ss_tot
);
4434 seq_printf(m
, " Enabled Subslice Per Slice: %u\n", ss_per
);
4435 seq_printf(m
, " Enabled EU Total: %u\n", eu_tot
);
4436 seq_printf(m
, " Enabled EU Per Subslice: %u\n", eu_per
);
4441 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
4443 struct drm_device
*dev
= inode
->i_private
;
4444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4446 if (INTEL_INFO(dev
)->gen
< 6)
4449 intel_runtime_pm_get(dev_priv
);
4450 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4455 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
4457 struct drm_device
*dev
= inode
->i_private
;
4458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4460 if (INTEL_INFO(dev
)->gen
< 6)
4463 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4464 intel_runtime_pm_put(dev_priv
);
4469 static const struct file_operations i915_forcewake_fops
= {
4470 .owner
= THIS_MODULE
,
4471 .open
= i915_forcewake_open
,
4472 .release
= i915_forcewake_release
,
4475 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
4477 struct drm_device
*dev
= minor
->dev
;
4480 ent
= debugfs_create_file("i915_forcewake_user",
4483 &i915_forcewake_fops
);
4487 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
4490 static int i915_debugfs_create(struct dentry
*root
,
4491 struct drm_minor
*minor
,
4493 const struct file_operations
*fops
)
4495 struct drm_device
*dev
= minor
->dev
;
4498 ent
= debugfs_create_file(name
,
4505 return drm_add_fake_info_node(minor
, ent
, fops
);
4508 static const struct drm_info_list i915_debugfs_list
[] = {
4509 {"i915_capabilities", i915_capabilities
, 0},
4510 {"i915_gem_objects", i915_gem_object_info
, 0},
4511 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
4512 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
4513 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
4514 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
4515 {"i915_gem_stolen", i915_gem_stolen_list_info
},
4516 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
4517 {"i915_gem_request", i915_gem_request_info
, 0},
4518 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
4519 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
4520 {"i915_gem_interrupt", i915_interrupt_info
, 0},
4521 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
4522 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
4523 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
4524 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
4525 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
4526 {"i915_frequency_info", i915_frequency_info
, 0},
4527 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
4528 {"i915_drpc_info", i915_drpc_info
, 0},
4529 {"i915_emon_status", i915_emon_status
, 0},
4530 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
4531 {"i915_fbc_status", i915_fbc_status
, 0},
4532 {"i915_ips_status", i915_ips_status
, 0},
4533 {"i915_sr_status", i915_sr_status
, 0},
4534 {"i915_opregion", i915_opregion
, 0},
4535 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
4536 {"i915_context_status", i915_context_status
, 0},
4537 {"i915_dump_lrc", i915_dump_lrc
, 0},
4538 {"i915_execlists", i915_execlists
, 0},
4539 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
4540 {"i915_swizzle_info", i915_swizzle_info
, 0},
4541 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
4542 {"i915_llc", i915_llc
, 0},
4543 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
4544 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
4545 {"i915_energy_uJ", i915_energy_uJ
, 0},
4546 {"i915_pc8_status", i915_pc8_status
, 0},
4547 {"i915_power_domain_info", i915_power_domain_info
, 0},
4548 {"i915_display_info", i915_display_info
, 0},
4549 {"i915_semaphore_status", i915_semaphore_status
, 0},
4550 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
4551 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
4552 {"i915_wa_registers", i915_wa_registers
, 0},
4553 {"i915_ddb_info", i915_ddb_info
, 0},
4554 {"i915_sseu_status", i915_sseu_status
, 0},
4556 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4558 static const struct i915_debugfs_files
{
4560 const struct file_operations
*fops
;
4561 } i915_debugfs_files
[] = {
4562 {"i915_wedged", &i915_wedged_fops
},
4563 {"i915_max_freq", &i915_max_freq_fops
},
4564 {"i915_min_freq", &i915_min_freq_fops
},
4565 {"i915_cache_sharing", &i915_cache_sharing_fops
},
4566 {"i915_ring_stop", &i915_ring_stop_fops
},
4567 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
4568 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
4569 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
4570 {"i915_error_state", &i915_error_state_fops
},
4571 {"i915_next_seqno", &i915_next_seqno_fops
},
4572 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
4573 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
4574 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
4575 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
4576 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
4579 void intel_display_crc_init(struct drm_device
*dev
)
4581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4584 for_each_pipe(dev_priv
, pipe
) {
4585 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4587 pipe_crc
->opened
= false;
4588 spin_lock_init(&pipe_crc
->lock
);
4589 init_waitqueue_head(&pipe_crc
->wq
);
4593 int i915_debugfs_init(struct drm_minor
*minor
)
4597 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
4601 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4602 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
4607 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4608 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
4609 i915_debugfs_files
[i
].name
,
4610 i915_debugfs_files
[i
].fops
);
4615 return drm_debugfs_create_files(i915_debugfs_list
,
4616 I915_DEBUGFS_ENTRIES
,
4617 minor
->debugfs_root
, minor
);
4620 void i915_debugfs_cleanup(struct drm_minor
*minor
)
4624 drm_debugfs_remove_files(i915_debugfs_list
,
4625 I915_DEBUGFS_ENTRIES
, minor
);
4627 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
4630 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
4631 struct drm_info_list
*info_list
=
4632 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
4634 drm_debugfs_remove_files(info_list
, 1, minor
);
4637 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
4638 struct drm_info_list
*info_list
=
4639 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
4641 drm_debugfs_remove_files(info_list
, 1, minor
);