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drm/i915: Kill dev_priv->irq_received
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
37 #include <drm/drmP.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
41 #include "i915_drv.h"
42
43 enum {
44 ACTIVE_LIST,
45 INACTIVE_LIST,
46 PINNED_LIST,
47 };
48
49 static const char *yesno(int v)
50 {
51 return v ? "yes" : "no";
52 }
53
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56 static int
57 drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60 {
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78 }
79
80 static int i915_capabilities(struct seq_file *m, void *data)
81 {
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91 #undef PRINT_FLAG
92 #undef SEP_SEMICOLON
93
94 return 0;
95 }
96
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
98 {
99 if (obj->user_pin_count > 0)
100 return "P";
101 else if (obj->pin_count > 0)
102 return "p";
103 else
104 return " ";
105 }
106
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
108 {
109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
115 }
116
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118 {
119 return obj->has_global_gtt_mapping ? "g" : " ";
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 struct i915_vma *vma;
126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
130 get_global_flag(obj),
131 obj->base.size / 1024,
132 obj->base.read_domains,
133 obj->base.write_domain,
134 obj->last_read_seqno,
135 obj->last_write_seqno,
136 obj->last_fenced_seqno,
137 i915_cache_level_str(obj->cache_level),
138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
142 if (obj->pin_count)
143 seq_printf(m, " (pinned x %d)", obj->pin_count);
144 if (obj->pin_display)
145 seq_printf(m, " (display)");
146 if (obj->fence_reg != I915_FENCE_REG_NONE)
147 seq_printf(m, " (fence: %d)", obj->fence_reg);
148 list_for_each_entry(vma, &obj->vma_list, vma_link) {
149 if (!i915_is_ggtt(vma->vm))
150 seq_puts(m, " (pp");
151 else
152 seq_puts(m, " (g");
153 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
154 vma->node.start, vma->node.size);
155 }
156 if (obj->stolen)
157 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
158 if (obj->pin_mappable || obj->fault_mappable) {
159 char s[3], *t = s;
160 if (obj->pin_mappable)
161 *t++ = 'p';
162 if (obj->fault_mappable)
163 *t++ = 'f';
164 *t = '\0';
165 seq_printf(m, " (%s mappable)", s);
166 }
167 if (obj->ring != NULL)
168 seq_printf(m, " (%s)", obj->ring->name);
169 }
170
171 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
172 {
173 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
174 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
175 seq_putc(m, ' ');
176 }
177
178 static int i915_gem_object_list_info(struct seq_file *m, void *data)
179 {
180 struct drm_info_node *node = (struct drm_info_node *) m->private;
181 uintptr_t list = (uintptr_t) node->info_ent->data;
182 struct list_head *head;
183 struct drm_device *dev = node->minor->dev;
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 struct i915_address_space *vm = &dev_priv->gtt.base;
186 struct i915_vma *vma;
187 size_t total_obj_size, total_gtt_size;
188 int count, ret;
189
190 ret = mutex_lock_interruptible(&dev->struct_mutex);
191 if (ret)
192 return ret;
193
194 /* FIXME: the user of this interface might want more than just GGTT */
195 switch (list) {
196 case ACTIVE_LIST:
197 seq_puts(m, "Active:\n");
198 head = &vm->active_list;
199 break;
200 case INACTIVE_LIST:
201 seq_puts(m, "Inactive:\n");
202 head = &vm->inactive_list;
203 break;
204 default:
205 mutex_unlock(&dev->struct_mutex);
206 return -EINVAL;
207 }
208
209 total_obj_size = total_gtt_size = count = 0;
210 list_for_each_entry(vma, head, mm_list) {
211 seq_printf(m, " ");
212 describe_obj(m, vma->obj);
213 seq_printf(m, "\n");
214 total_obj_size += vma->obj->base.size;
215 total_gtt_size += vma->node.size;
216 count++;
217 }
218 mutex_unlock(&dev->struct_mutex);
219
220 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
221 count, total_obj_size, total_gtt_size);
222 return 0;
223 }
224
225 static int obj_rank_by_stolen(void *priv,
226 struct list_head *A, struct list_head *B)
227 {
228 struct drm_i915_gem_object *a =
229 container_of(A, struct drm_i915_gem_object, obj_exec_link);
230 struct drm_i915_gem_object *b =
231 container_of(B, struct drm_i915_gem_object, obj_exec_link);
232
233 return a->stolen->start - b->stolen->start;
234 }
235
236 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
237 {
238 struct drm_info_node *node = (struct drm_info_node *) m->private;
239 struct drm_device *dev = node->minor->dev;
240 struct drm_i915_private *dev_priv = dev->dev_private;
241 struct drm_i915_gem_object *obj;
242 size_t total_obj_size, total_gtt_size;
243 LIST_HEAD(stolen);
244 int count, ret;
245
246 ret = mutex_lock_interruptible(&dev->struct_mutex);
247 if (ret)
248 return ret;
249
250 total_obj_size = total_gtt_size = count = 0;
251 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
252 if (obj->stolen == NULL)
253 continue;
254
255 list_add(&obj->obj_exec_link, &stolen);
256
257 total_obj_size += obj->base.size;
258 total_gtt_size += i915_gem_obj_ggtt_size(obj);
259 count++;
260 }
261 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
262 if (obj->stolen == NULL)
263 continue;
264
265 list_add(&obj->obj_exec_link, &stolen);
266
267 total_obj_size += obj->base.size;
268 count++;
269 }
270 list_sort(NULL, &stolen, obj_rank_by_stolen);
271 seq_puts(m, "Stolen:\n");
272 while (!list_empty(&stolen)) {
273 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
274 seq_puts(m, " ");
275 describe_obj(m, obj);
276 seq_putc(m, '\n');
277 list_del_init(&obj->obj_exec_link);
278 }
279 mutex_unlock(&dev->struct_mutex);
280
281 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
282 count, total_obj_size, total_gtt_size);
283 return 0;
284 }
285
286 #define count_objects(list, member) do { \
287 list_for_each_entry(obj, list, member) { \
288 size += i915_gem_obj_ggtt_size(obj); \
289 ++count; \
290 if (obj->map_and_fenceable) { \
291 mappable_size += i915_gem_obj_ggtt_size(obj); \
292 ++mappable_count; \
293 } \
294 } \
295 } while (0)
296
297 struct file_stats {
298 int count;
299 size_t total, active, inactive, unbound;
300 };
301
302 static int per_file_stats(int id, void *ptr, void *data)
303 {
304 struct drm_i915_gem_object *obj = ptr;
305 struct file_stats *stats = data;
306
307 stats->count++;
308 stats->total += obj->base.size;
309
310 if (i915_gem_obj_ggtt_bound(obj)) {
311 if (!list_empty(&obj->ring_list))
312 stats->active += obj->base.size;
313 else
314 stats->inactive += obj->base.size;
315 } else {
316 if (!list_empty(&obj->global_list))
317 stats->unbound += obj->base.size;
318 }
319
320 return 0;
321 }
322
323 #define count_vmas(list, member) do { \
324 list_for_each_entry(vma, list, member) { \
325 size += i915_gem_obj_ggtt_size(vma->obj); \
326 ++count; \
327 if (vma->obj->map_and_fenceable) { \
328 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
329 ++mappable_count; \
330 } \
331 } \
332 } while (0)
333
334 static int i915_gem_object_info(struct seq_file *m, void* data)
335 {
336 struct drm_info_node *node = (struct drm_info_node *) m->private;
337 struct drm_device *dev = node->minor->dev;
338 struct drm_i915_private *dev_priv = dev->dev_private;
339 u32 count, mappable_count, purgeable_count;
340 size_t size, mappable_size, purgeable_size;
341 struct drm_i915_gem_object *obj;
342 struct i915_address_space *vm = &dev_priv->gtt.base;
343 struct drm_file *file;
344 struct i915_vma *vma;
345 int ret;
346
347 ret = mutex_lock_interruptible(&dev->struct_mutex);
348 if (ret)
349 return ret;
350
351 seq_printf(m, "%u objects, %zu bytes\n",
352 dev_priv->mm.object_count,
353 dev_priv->mm.object_memory);
354
355 size = count = mappable_size = mappable_count = 0;
356 count_objects(&dev_priv->mm.bound_list, global_list);
357 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
358 count, mappable_count, size, mappable_size);
359
360 size = count = mappable_size = mappable_count = 0;
361 count_vmas(&vm->active_list, mm_list);
362 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
363 count, mappable_count, size, mappable_size);
364
365 size = count = mappable_size = mappable_count = 0;
366 count_vmas(&vm->inactive_list, mm_list);
367 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
368 count, mappable_count, size, mappable_size);
369
370 size = count = purgeable_size = purgeable_count = 0;
371 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
372 size += obj->base.size, ++count;
373 if (obj->madv == I915_MADV_DONTNEED)
374 purgeable_size += obj->base.size, ++purgeable_count;
375 }
376 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
377
378 size = count = mappable_size = mappable_count = 0;
379 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
380 if (obj->fault_mappable) {
381 size += i915_gem_obj_ggtt_size(obj);
382 ++count;
383 }
384 if (obj->pin_mappable) {
385 mappable_size += i915_gem_obj_ggtt_size(obj);
386 ++mappable_count;
387 }
388 if (obj->madv == I915_MADV_DONTNEED) {
389 purgeable_size += obj->base.size;
390 ++purgeable_count;
391 }
392 }
393 seq_printf(m, "%u purgeable objects, %zu bytes\n",
394 purgeable_count, purgeable_size);
395 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
396 mappable_count, mappable_size);
397 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
398 count, size);
399
400 seq_printf(m, "%zu [%lu] gtt total\n",
401 dev_priv->gtt.base.total,
402 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
403
404 seq_putc(m, '\n');
405 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
406 struct file_stats stats;
407 struct task_struct *task;
408
409 memset(&stats, 0, sizeof(stats));
410 idr_for_each(&file->object_idr, per_file_stats, &stats);
411 /*
412 * Although we have a valid reference on file->pid, that does
413 * not guarantee that the task_struct who called get_pid() is
414 * still alive (e.g. get_pid(current) => fork() => exit()).
415 * Therefore, we need to protect this ->comm access using RCU.
416 */
417 rcu_read_lock();
418 task = pid_task(file->pid, PIDTYPE_PID);
419 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
420 task ? task->comm : "<unknown>",
421 stats.count,
422 stats.total,
423 stats.active,
424 stats.inactive,
425 stats.unbound);
426 rcu_read_unlock();
427 }
428
429 mutex_unlock(&dev->struct_mutex);
430
431 return 0;
432 }
433
434 static int i915_gem_gtt_info(struct seq_file *m, void *data)
435 {
436 struct drm_info_node *node = (struct drm_info_node *) m->private;
437 struct drm_device *dev = node->minor->dev;
438 uintptr_t list = (uintptr_t) node->info_ent->data;
439 struct drm_i915_private *dev_priv = dev->dev_private;
440 struct drm_i915_gem_object *obj;
441 size_t total_obj_size, total_gtt_size;
442 int count, ret;
443
444 ret = mutex_lock_interruptible(&dev->struct_mutex);
445 if (ret)
446 return ret;
447
448 total_obj_size = total_gtt_size = count = 0;
449 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
450 if (list == PINNED_LIST && obj->pin_count == 0)
451 continue;
452
453 seq_puts(m, " ");
454 describe_obj(m, obj);
455 seq_putc(m, '\n');
456 total_obj_size += obj->base.size;
457 total_gtt_size += i915_gem_obj_ggtt_size(obj);
458 count++;
459 }
460
461 mutex_unlock(&dev->struct_mutex);
462
463 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
464 count, total_obj_size, total_gtt_size);
465
466 return 0;
467 }
468
469 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
470 {
471 struct drm_info_node *node = (struct drm_info_node *) m->private;
472 struct drm_device *dev = node->minor->dev;
473 unsigned long flags;
474 struct intel_crtc *crtc;
475
476 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
477 const char pipe = pipe_name(crtc->pipe);
478 const char plane = plane_name(crtc->plane);
479 struct intel_unpin_work *work;
480
481 spin_lock_irqsave(&dev->event_lock, flags);
482 work = crtc->unpin_work;
483 if (work == NULL) {
484 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
485 pipe, plane);
486 } else {
487 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
488 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
489 pipe, plane);
490 } else {
491 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
492 pipe, plane);
493 }
494 if (work->enable_stall_check)
495 seq_puts(m, "Stall check enabled, ");
496 else
497 seq_puts(m, "Stall check waiting for page flip ioctl, ");
498 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
499
500 if (work->old_fb_obj) {
501 struct drm_i915_gem_object *obj = work->old_fb_obj;
502 if (obj)
503 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
504 i915_gem_obj_ggtt_offset(obj));
505 }
506 if (work->pending_flip_obj) {
507 struct drm_i915_gem_object *obj = work->pending_flip_obj;
508 if (obj)
509 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
510 i915_gem_obj_ggtt_offset(obj));
511 }
512 }
513 spin_unlock_irqrestore(&dev->event_lock, flags);
514 }
515
516 return 0;
517 }
518
519 static int i915_gem_request_info(struct seq_file *m, void *data)
520 {
521 struct drm_info_node *node = (struct drm_info_node *) m->private;
522 struct drm_device *dev = node->minor->dev;
523 drm_i915_private_t *dev_priv = dev->dev_private;
524 struct intel_ring_buffer *ring;
525 struct drm_i915_gem_request *gem_request;
526 int ret, count, i;
527
528 ret = mutex_lock_interruptible(&dev->struct_mutex);
529 if (ret)
530 return ret;
531
532 count = 0;
533 for_each_ring(ring, dev_priv, i) {
534 if (list_empty(&ring->request_list))
535 continue;
536
537 seq_printf(m, "%s requests:\n", ring->name);
538 list_for_each_entry(gem_request,
539 &ring->request_list,
540 list) {
541 seq_printf(m, " %d @ %d\n",
542 gem_request->seqno,
543 (int) (jiffies - gem_request->emitted_jiffies));
544 }
545 count++;
546 }
547 mutex_unlock(&dev->struct_mutex);
548
549 if (count == 0)
550 seq_puts(m, "No requests\n");
551
552 return 0;
553 }
554
555 static void i915_ring_seqno_info(struct seq_file *m,
556 struct intel_ring_buffer *ring)
557 {
558 if (ring->get_seqno) {
559 seq_printf(m, "Current sequence (%s): %u\n",
560 ring->name, ring->get_seqno(ring, false));
561 }
562 }
563
564 static int i915_gem_seqno_info(struct seq_file *m, void *data)
565 {
566 struct drm_info_node *node = (struct drm_info_node *) m->private;
567 struct drm_device *dev = node->minor->dev;
568 drm_i915_private_t *dev_priv = dev->dev_private;
569 struct intel_ring_buffer *ring;
570 int ret, i;
571
572 ret = mutex_lock_interruptible(&dev->struct_mutex);
573 if (ret)
574 return ret;
575 intel_runtime_pm_get(dev_priv);
576
577 for_each_ring(ring, dev_priv, i)
578 i915_ring_seqno_info(m, ring);
579
580 intel_runtime_pm_put(dev_priv);
581 mutex_unlock(&dev->struct_mutex);
582
583 return 0;
584 }
585
586
587 static int i915_interrupt_info(struct seq_file *m, void *data)
588 {
589 struct drm_info_node *node = (struct drm_info_node *) m->private;
590 struct drm_device *dev = node->minor->dev;
591 drm_i915_private_t *dev_priv = dev->dev_private;
592 struct intel_ring_buffer *ring;
593 int ret, i, pipe;
594
595 ret = mutex_lock_interruptible(&dev->struct_mutex);
596 if (ret)
597 return ret;
598 intel_runtime_pm_get(dev_priv);
599
600 if (INTEL_INFO(dev)->gen >= 8) {
601 int i;
602 seq_printf(m, "Master Interrupt Control:\t%08x\n",
603 I915_READ(GEN8_MASTER_IRQ));
604
605 for (i = 0; i < 4; i++) {
606 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
607 i, I915_READ(GEN8_GT_IMR(i)));
608 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
609 i, I915_READ(GEN8_GT_IIR(i)));
610 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
611 i, I915_READ(GEN8_GT_IER(i)));
612 }
613
614 for_each_pipe(i) {
615 seq_printf(m, "Pipe %c IMR:\t%08x\n",
616 pipe_name(i),
617 I915_READ(GEN8_DE_PIPE_IMR(i)));
618 seq_printf(m, "Pipe %c IIR:\t%08x\n",
619 pipe_name(i),
620 I915_READ(GEN8_DE_PIPE_IIR(i)));
621 seq_printf(m, "Pipe %c IER:\t%08x\n",
622 pipe_name(i),
623 I915_READ(GEN8_DE_PIPE_IER(i)));
624 }
625
626 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
627 I915_READ(GEN8_DE_PORT_IMR));
628 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
629 I915_READ(GEN8_DE_PORT_IIR));
630 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
631 I915_READ(GEN8_DE_PORT_IER));
632
633 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
634 I915_READ(GEN8_DE_MISC_IMR));
635 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
636 I915_READ(GEN8_DE_MISC_IIR));
637 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
638 I915_READ(GEN8_DE_MISC_IER));
639
640 seq_printf(m, "PCU interrupt mask:\t%08x\n",
641 I915_READ(GEN8_PCU_IMR));
642 seq_printf(m, "PCU interrupt identity:\t%08x\n",
643 I915_READ(GEN8_PCU_IIR));
644 seq_printf(m, "PCU interrupt enable:\t%08x\n",
645 I915_READ(GEN8_PCU_IER));
646 } else if (IS_VALLEYVIEW(dev)) {
647 seq_printf(m, "Display IER:\t%08x\n",
648 I915_READ(VLV_IER));
649 seq_printf(m, "Display IIR:\t%08x\n",
650 I915_READ(VLV_IIR));
651 seq_printf(m, "Display IIR_RW:\t%08x\n",
652 I915_READ(VLV_IIR_RW));
653 seq_printf(m, "Display IMR:\t%08x\n",
654 I915_READ(VLV_IMR));
655 for_each_pipe(pipe)
656 seq_printf(m, "Pipe %c stat:\t%08x\n",
657 pipe_name(pipe),
658 I915_READ(PIPESTAT(pipe)));
659
660 seq_printf(m, "Master IER:\t%08x\n",
661 I915_READ(VLV_MASTER_IER));
662
663 seq_printf(m, "Render IER:\t%08x\n",
664 I915_READ(GTIER));
665 seq_printf(m, "Render IIR:\t%08x\n",
666 I915_READ(GTIIR));
667 seq_printf(m, "Render IMR:\t%08x\n",
668 I915_READ(GTIMR));
669
670 seq_printf(m, "PM IER:\t\t%08x\n",
671 I915_READ(GEN6_PMIER));
672 seq_printf(m, "PM IIR:\t\t%08x\n",
673 I915_READ(GEN6_PMIIR));
674 seq_printf(m, "PM IMR:\t\t%08x\n",
675 I915_READ(GEN6_PMIMR));
676
677 seq_printf(m, "Port hotplug:\t%08x\n",
678 I915_READ(PORT_HOTPLUG_EN));
679 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
680 I915_READ(VLV_DPFLIPSTAT));
681 seq_printf(m, "DPINVGTT:\t%08x\n",
682 I915_READ(DPINVGTT));
683
684 } else if (!HAS_PCH_SPLIT(dev)) {
685 seq_printf(m, "Interrupt enable: %08x\n",
686 I915_READ(IER));
687 seq_printf(m, "Interrupt identity: %08x\n",
688 I915_READ(IIR));
689 seq_printf(m, "Interrupt mask: %08x\n",
690 I915_READ(IMR));
691 for_each_pipe(pipe)
692 seq_printf(m, "Pipe %c stat: %08x\n",
693 pipe_name(pipe),
694 I915_READ(PIPESTAT(pipe)));
695 } else {
696 seq_printf(m, "North Display Interrupt enable: %08x\n",
697 I915_READ(DEIER));
698 seq_printf(m, "North Display Interrupt identity: %08x\n",
699 I915_READ(DEIIR));
700 seq_printf(m, "North Display Interrupt mask: %08x\n",
701 I915_READ(DEIMR));
702 seq_printf(m, "South Display Interrupt enable: %08x\n",
703 I915_READ(SDEIER));
704 seq_printf(m, "South Display Interrupt identity: %08x\n",
705 I915_READ(SDEIIR));
706 seq_printf(m, "South Display Interrupt mask: %08x\n",
707 I915_READ(SDEIMR));
708 seq_printf(m, "Graphics Interrupt enable: %08x\n",
709 I915_READ(GTIER));
710 seq_printf(m, "Graphics Interrupt identity: %08x\n",
711 I915_READ(GTIIR));
712 seq_printf(m, "Graphics Interrupt mask: %08x\n",
713 I915_READ(GTIMR));
714 }
715 for_each_ring(ring, dev_priv, i) {
716 if (INTEL_INFO(dev)->gen >= 6) {
717 seq_printf(m,
718 "Graphics Interrupt mask (%s): %08x\n",
719 ring->name, I915_READ_IMR(ring));
720 }
721 i915_ring_seqno_info(m, ring);
722 }
723 intel_runtime_pm_put(dev_priv);
724 mutex_unlock(&dev->struct_mutex);
725
726 return 0;
727 }
728
729 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
730 {
731 struct drm_info_node *node = (struct drm_info_node *) m->private;
732 struct drm_device *dev = node->minor->dev;
733 drm_i915_private_t *dev_priv = dev->dev_private;
734 int i, ret;
735
736 ret = mutex_lock_interruptible(&dev->struct_mutex);
737 if (ret)
738 return ret;
739
740 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
741 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
742 for (i = 0; i < dev_priv->num_fence_regs; i++) {
743 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
744
745 seq_printf(m, "Fence %d, pin count = %d, object = ",
746 i, dev_priv->fence_regs[i].pin_count);
747 if (obj == NULL)
748 seq_puts(m, "unused");
749 else
750 describe_obj(m, obj);
751 seq_putc(m, '\n');
752 }
753
754 mutex_unlock(&dev->struct_mutex);
755 return 0;
756 }
757
758 static int i915_hws_info(struct seq_file *m, void *data)
759 {
760 struct drm_info_node *node = (struct drm_info_node *) m->private;
761 struct drm_device *dev = node->minor->dev;
762 drm_i915_private_t *dev_priv = dev->dev_private;
763 struct intel_ring_buffer *ring;
764 const u32 *hws;
765 int i;
766
767 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
768 hws = ring->status_page.page_addr;
769 if (hws == NULL)
770 return 0;
771
772 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
773 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
774 i * 4,
775 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
776 }
777 return 0;
778 }
779
780 static ssize_t
781 i915_error_state_write(struct file *filp,
782 const char __user *ubuf,
783 size_t cnt,
784 loff_t *ppos)
785 {
786 struct i915_error_state_file_priv *error_priv = filp->private_data;
787 struct drm_device *dev = error_priv->dev;
788 int ret;
789
790 DRM_DEBUG_DRIVER("Resetting error state\n");
791
792 ret = mutex_lock_interruptible(&dev->struct_mutex);
793 if (ret)
794 return ret;
795
796 i915_destroy_error_state(dev);
797 mutex_unlock(&dev->struct_mutex);
798
799 return cnt;
800 }
801
802 static int i915_error_state_open(struct inode *inode, struct file *file)
803 {
804 struct drm_device *dev = inode->i_private;
805 struct i915_error_state_file_priv *error_priv;
806
807 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
808 if (!error_priv)
809 return -ENOMEM;
810
811 error_priv->dev = dev;
812
813 i915_error_state_get(dev, error_priv);
814
815 file->private_data = error_priv;
816
817 return 0;
818 }
819
820 static int i915_error_state_release(struct inode *inode, struct file *file)
821 {
822 struct i915_error_state_file_priv *error_priv = file->private_data;
823
824 i915_error_state_put(error_priv);
825 kfree(error_priv);
826
827 return 0;
828 }
829
830 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
831 size_t count, loff_t *pos)
832 {
833 struct i915_error_state_file_priv *error_priv = file->private_data;
834 struct drm_i915_error_state_buf error_str;
835 loff_t tmp_pos = 0;
836 ssize_t ret_count = 0;
837 int ret;
838
839 ret = i915_error_state_buf_init(&error_str, count, *pos);
840 if (ret)
841 return ret;
842
843 ret = i915_error_state_to_str(&error_str, error_priv);
844 if (ret)
845 goto out;
846
847 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
848 error_str.buf,
849 error_str.bytes);
850
851 if (ret_count < 0)
852 ret = ret_count;
853 else
854 *pos = error_str.start + ret_count;
855 out:
856 i915_error_state_buf_release(&error_str);
857 return ret ?: ret_count;
858 }
859
860 static const struct file_operations i915_error_state_fops = {
861 .owner = THIS_MODULE,
862 .open = i915_error_state_open,
863 .read = i915_error_state_read,
864 .write = i915_error_state_write,
865 .llseek = default_llseek,
866 .release = i915_error_state_release,
867 };
868
869 static int
870 i915_next_seqno_get(void *data, u64 *val)
871 {
872 struct drm_device *dev = data;
873 drm_i915_private_t *dev_priv = dev->dev_private;
874 int ret;
875
876 ret = mutex_lock_interruptible(&dev->struct_mutex);
877 if (ret)
878 return ret;
879
880 *val = dev_priv->next_seqno;
881 mutex_unlock(&dev->struct_mutex);
882
883 return 0;
884 }
885
886 static int
887 i915_next_seqno_set(void *data, u64 val)
888 {
889 struct drm_device *dev = data;
890 int ret;
891
892 ret = mutex_lock_interruptible(&dev->struct_mutex);
893 if (ret)
894 return ret;
895
896 ret = i915_gem_set_seqno(dev, val);
897 mutex_unlock(&dev->struct_mutex);
898
899 return ret;
900 }
901
902 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
903 i915_next_seqno_get, i915_next_seqno_set,
904 "0x%llx\n");
905
906 static int i915_rstdby_delays(struct seq_file *m, void *unused)
907 {
908 struct drm_info_node *node = (struct drm_info_node *) m->private;
909 struct drm_device *dev = node->minor->dev;
910 drm_i915_private_t *dev_priv = dev->dev_private;
911 u16 crstanddelay;
912 int ret;
913
914 ret = mutex_lock_interruptible(&dev->struct_mutex);
915 if (ret)
916 return ret;
917 intel_runtime_pm_get(dev_priv);
918
919 crstanddelay = I915_READ16(CRSTANDVID);
920
921 intel_runtime_pm_put(dev_priv);
922 mutex_unlock(&dev->struct_mutex);
923
924 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
925
926 return 0;
927 }
928
929 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
930 {
931 struct drm_info_node *node = (struct drm_info_node *) m->private;
932 struct drm_device *dev = node->minor->dev;
933 drm_i915_private_t *dev_priv = dev->dev_private;
934 int ret = 0;
935
936 intel_runtime_pm_get(dev_priv);
937
938 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
939
940 if (IS_GEN5(dev)) {
941 u16 rgvswctl = I915_READ16(MEMSWCTL);
942 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
943
944 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
945 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
946 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
947 MEMSTAT_VID_SHIFT);
948 seq_printf(m, "Current P-state: %d\n",
949 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
950 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
951 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
952 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
953 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
954 u32 rpstat, cagf, reqf;
955 u32 rpupei, rpcurup, rpprevup;
956 u32 rpdownei, rpcurdown, rpprevdown;
957 int max_freq;
958
959 /* RPSTAT1 is in the GT power well */
960 ret = mutex_lock_interruptible(&dev->struct_mutex);
961 if (ret)
962 goto out;
963
964 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
965
966 reqf = I915_READ(GEN6_RPNSWREQ);
967 reqf &= ~GEN6_TURBO_DISABLE;
968 if (IS_HASWELL(dev))
969 reqf >>= 24;
970 else
971 reqf >>= 25;
972 reqf *= GT_FREQUENCY_MULTIPLIER;
973
974 rpstat = I915_READ(GEN6_RPSTAT1);
975 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
976 rpcurup = I915_READ(GEN6_RP_CUR_UP);
977 rpprevup = I915_READ(GEN6_RP_PREV_UP);
978 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
979 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
980 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
981 if (IS_HASWELL(dev))
982 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
983 else
984 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
985 cagf *= GT_FREQUENCY_MULTIPLIER;
986
987 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
988 mutex_unlock(&dev->struct_mutex);
989
990 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
991 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
992 seq_printf(m, "Render p-state ratio: %d\n",
993 (gt_perf_status & 0xff00) >> 8);
994 seq_printf(m, "Render p-state VID: %d\n",
995 gt_perf_status & 0xff);
996 seq_printf(m, "Render p-state limit: %d\n",
997 rp_state_limits & 0xff);
998 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
999 seq_printf(m, "CAGF: %dMHz\n", cagf);
1000 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1001 GEN6_CURICONT_MASK);
1002 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1003 GEN6_CURBSYTAVG_MASK);
1004 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1005 GEN6_CURBSYTAVG_MASK);
1006 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1007 GEN6_CURIAVG_MASK);
1008 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1009 GEN6_CURBSYTAVG_MASK);
1010 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1011 GEN6_CURBSYTAVG_MASK);
1012
1013 max_freq = (rp_state_cap & 0xff0000) >> 16;
1014 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1015 max_freq * GT_FREQUENCY_MULTIPLIER);
1016
1017 max_freq = (rp_state_cap & 0xff00) >> 8;
1018 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1019 max_freq * GT_FREQUENCY_MULTIPLIER);
1020
1021 max_freq = rp_state_cap & 0xff;
1022 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1023 max_freq * GT_FREQUENCY_MULTIPLIER);
1024
1025 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1026 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1027 } else if (IS_VALLEYVIEW(dev)) {
1028 u32 freq_sts, val;
1029
1030 mutex_lock(&dev_priv->rps.hw_lock);
1031 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1032 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1033 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1034
1035 val = valleyview_rps_max_freq(dev_priv);
1036 seq_printf(m, "max GPU freq: %d MHz\n",
1037 vlv_gpu_freq(dev_priv, val));
1038
1039 val = valleyview_rps_min_freq(dev_priv);
1040 seq_printf(m, "min GPU freq: %d MHz\n",
1041 vlv_gpu_freq(dev_priv, val));
1042
1043 seq_printf(m, "current GPU freq: %d MHz\n",
1044 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1045 mutex_unlock(&dev_priv->rps.hw_lock);
1046 } else {
1047 seq_puts(m, "no P-state info available\n");
1048 }
1049
1050 out:
1051 intel_runtime_pm_put(dev_priv);
1052 return ret;
1053 }
1054
1055 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1056 {
1057 struct drm_info_node *node = (struct drm_info_node *) m->private;
1058 struct drm_device *dev = node->minor->dev;
1059 drm_i915_private_t *dev_priv = dev->dev_private;
1060 u32 delayfreq;
1061 int ret, i;
1062
1063 ret = mutex_lock_interruptible(&dev->struct_mutex);
1064 if (ret)
1065 return ret;
1066 intel_runtime_pm_get(dev_priv);
1067
1068 for (i = 0; i < 16; i++) {
1069 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1070 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1071 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1072 }
1073
1074 intel_runtime_pm_put(dev_priv);
1075
1076 mutex_unlock(&dev->struct_mutex);
1077
1078 return 0;
1079 }
1080
1081 static inline int MAP_TO_MV(int map)
1082 {
1083 return 1250 - (map * 25);
1084 }
1085
1086 static int i915_inttoext_table(struct seq_file *m, void *unused)
1087 {
1088 struct drm_info_node *node = (struct drm_info_node *) m->private;
1089 struct drm_device *dev = node->minor->dev;
1090 drm_i915_private_t *dev_priv = dev->dev_private;
1091 u32 inttoext;
1092 int ret, i;
1093
1094 ret = mutex_lock_interruptible(&dev->struct_mutex);
1095 if (ret)
1096 return ret;
1097 intel_runtime_pm_get(dev_priv);
1098
1099 for (i = 1; i <= 32; i++) {
1100 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1101 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1102 }
1103
1104 intel_runtime_pm_put(dev_priv);
1105 mutex_unlock(&dev->struct_mutex);
1106
1107 return 0;
1108 }
1109
1110 static int ironlake_drpc_info(struct seq_file *m)
1111 {
1112 struct drm_info_node *node = (struct drm_info_node *) m->private;
1113 struct drm_device *dev = node->minor->dev;
1114 drm_i915_private_t *dev_priv = dev->dev_private;
1115 u32 rgvmodectl, rstdbyctl;
1116 u16 crstandvid;
1117 int ret;
1118
1119 ret = mutex_lock_interruptible(&dev->struct_mutex);
1120 if (ret)
1121 return ret;
1122 intel_runtime_pm_get(dev_priv);
1123
1124 rgvmodectl = I915_READ(MEMMODECTL);
1125 rstdbyctl = I915_READ(RSTDBYCTL);
1126 crstandvid = I915_READ16(CRSTANDVID);
1127
1128 intel_runtime_pm_put(dev_priv);
1129 mutex_unlock(&dev->struct_mutex);
1130
1131 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1132 "yes" : "no");
1133 seq_printf(m, "Boost freq: %d\n",
1134 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1135 MEMMODE_BOOST_FREQ_SHIFT);
1136 seq_printf(m, "HW control enabled: %s\n",
1137 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1138 seq_printf(m, "SW control enabled: %s\n",
1139 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1140 seq_printf(m, "Gated voltage change: %s\n",
1141 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1142 seq_printf(m, "Starting frequency: P%d\n",
1143 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1144 seq_printf(m, "Max P-state: P%d\n",
1145 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1146 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1147 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1148 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1149 seq_printf(m, "Render standby enabled: %s\n",
1150 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1151 seq_puts(m, "Current RS state: ");
1152 switch (rstdbyctl & RSX_STATUS_MASK) {
1153 case RSX_STATUS_ON:
1154 seq_puts(m, "on\n");
1155 break;
1156 case RSX_STATUS_RC1:
1157 seq_puts(m, "RC1\n");
1158 break;
1159 case RSX_STATUS_RC1E:
1160 seq_puts(m, "RC1E\n");
1161 break;
1162 case RSX_STATUS_RS1:
1163 seq_puts(m, "RS1\n");
1164 break;
1165 case RSX_STATUS_RS2:
1166 seq_puts(m, "RS2 (RC6)\n");
1167 break;
1168 case RSX_STATUS_RS3:
1169 seq_puts(m, "RC3 (RC6+)\n");
1170 break;
1171 default:
1172 seq_puts(m, "unknown\n");
1173 break;
1174 }
1175
1176 return 0;
1177 }
1178
1179 static int vlv_drpc_info(struct seq_file *m)
1180 {
1181
1182 struct drm_info_node *node = (struct drm_info_node *) m->private;
1183 struct drm_device *dev = node->minor->dev;
1184 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 rpmodectl1, rcctl1;
1186 unsigned fw_rendercount = 0, fw_mediacount = 0;
1187
1188 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1189 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1190
1191 seq_printf(m, "Video Turbo Mode: %s\n",
1192 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1193 seq_printf(m, "Turbo enabled: %s\n",
1194 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1195 seq_printf(m, "HW control enabled: %s\n",
1196 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1197 seq_printf(m, "SW control enabled: %s\n",
1198 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1199 GEN6_RP_MEDIA_SW_MODE));
1200 seq_printf(m, "RC6 Enabled: %s\n",
1201 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1202 GEN6_RC_CTL_EI_MODE(1))));
1203 seq_printf(m, "Render Power Well: %s\n",
1204 (I915_READ(VLV_GTLC_PW_STATUS) &
1205 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1206 seq_printf(m, "Media Power Well: %s\n",
1207 (I915_READ(VLV_GTLC_PW_STATUS) &
1208 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1209
1210 spin_lock_irq(&dev_priv->uncore.lock);
1211 fw_rendercount = dev_priv->uncore.fw_rendercount;
1212 fw_mediacount = dev_priv->uncore.fw_mediacount;
1213 spin_unlock_irq(&dev_priv->uncore.lock);
1214
1215 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1216 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1217
1218
1219 return 0;
1220 }
1221
1222
1223 static int gen6_drpc_info(struct seq_file *m)
1224 {
1225
1226 struct drm_info_node *node = (struct drm_info_node *) m->private;
1227 struct drm_device *dev = node->minor->dev;
1228 struct drm_i915_private *dev_priv = dev->dev_private;
1229 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1230 unsigned forcewake_count;
1231 int count = 0, ret;
1232
1233 ret = mutex_lock_interruptible(&dev->struct_mutex);
1234 if (ret)
1235 return ret;
1236 intel_runtime_pm_get(dev_priv);
1237
1238 spin_lock_irq(&dev_priv->uncore.lock);
1239 forcewake_count = dev_priv->uncore.forcewake_count;
1240 spin_unlock_irq(&dev_priv->uncore.lock);
1241
1242 if (forcewake_count) {
1243 seq_puts(m, "RC information inaccurate because somebody "
1244 "holds a forcewake reference \n");
1245 } else {
1246 /* NB: we cannot use forcewake, else we read the wrong values */
1247 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1248 udelay(10);
1249 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1250 }
1251
1252 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1253 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1254
1255 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1256 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1257 mutex_unlock(&dev->struct_mutex);
1258 mutex_lock(&dev_priv->rps.hw_lock);
1259 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1260 mutex_unlock(&dev_priv->rps.hw_lock);
1261
1262 intel_runtime_pm_put(dev_priv);
1263
1264 seq_printf(m, "Video Turbo Mode: %s\n",
1265 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1266 seq_printf(m, "HW control enabled: %s\n",
1267 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1268 seq_printf(m, "SW control enabled: %s\n",
1269 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1270 GEN6_RP_MEDIA_SW_MODE));
1271 seq_printf(m, "RC1e Enabled: %s\n",
1272 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1273 seq_printf(m, "RC6 Enabled: %s\n",
1274 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1275 seq_printf(m, "Deep RC6 Enabled: %s\n",
1276 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1277 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1278 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1279 seq_puts(m, "Current RC state: ");
1280 switch (gt_core_status & GEN6_RCn_MASK) {
1281 case GEN6_RC0:
1282 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1283 seq_puts(m, "Core Power Down\n");
1284 else
1285 seq_puts(m, "on\n");
1286 break;
1287 case GEN6_RC3:
1288 seq_puts(m, "RC3\n");
1289 break;
1290 case GEN6_RC6:
1291 seq_puts(m, "RC6\n");
1292 break;
1293 case GEN6_RC7:
1294 seq_puts(m, "RC7\n");
1295 break;
1296 default:
1297 seq_puts(m, "Unknown\n");
1298 break;
1299 }
1300
1301 seq_printf(m, "Core Power Down: %s\n",
1302 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1303
1304 /* Not exactly sure what this is */
1305 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1306 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1307 seq_printf(m, "RC6 residency since boot: %u\n",
1308 I915_READ(GEN6_GT_GFX_RC6));
1309 seq_printf(m, "RC6+ residency since boot: %u\n",
1310 I915_READ(GEN6_GT_GFX_RC6p));
1311 seq_printf(m, "RC6++ residency since boot: %u\n",
1312 I915_READ(GEN6_GT_GFX_RC6pp));
1313
1314 seq_printf(m, "RC6 voltage: %dmV\n",
1315 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1316 seq_printf(m, "RC6+ voltage: %dmV\n",
1317 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1318 seq_printf(m, "RC6++ voltage: %dmV\n",
1319 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1320 return 0;
1321 }
1322
1323 static int i915_drpc_info(struct seq_file *m, void *unused)
1324 {
1325 struct drm_info_node *node = (struct drm_info_node *) m->private;
1326 struct drm_device *dev = node->minor->dev;
1327
1328 if (IS_VALLEYVIEW(dev))
1329 return vlv_drpc_info(m);
1330 else if (IS_GEN6(dev) || IS_GEN7(dev))
1331 return gen6_drpc_info(m);
1332 else
1333 return ironlake_drpc_info(m);
1334 }
1335
1336 static int i915_fbc_status(struct seq_file *m, void *unused)
1337 {
1338 struct drm_info_node *node = (struct drm_info_node *) m->private;
1339 struct drm_device *dev = node->minor->dev;
1340 drm_i915_private_t *dev_priv = dev->dev_private;
1341
1342 if (!HAS_FBC(dev)) {
1343 seq_puts(m, "FBC unsupported on this chipset\n");
1344 return 0;
1345 }
1346
1347 if (intel_fbc_enabled(dev)) {
1348 seq_puts(m, "FBC enabled\n");
1349 } else {
1350 seq_puts(m, "FBC disabled: ");
1351 switch (dev_priv->fbc.no_fbc_reason) {
1352 case FBC_OK:
1353 seq_puts(m, "FBC actived, but currently disabled in hardware");
1354 break;
1355 case FBC_UNSUPPORTED:
1356 seq_puts(m, "unsupported by this chipset");
1357 break;
1358 case FBC_NO_OUTPUT:
1359 seq_puts(m, "no outputs");
1360 break;
1361 case FBC_STOLEN_TOO_SMALL:
1362 seq_puts(m, "not enough stolen memory");
1363 break;
1364 case FBC_UNSUPPORTED_MODE:
1365 seq_puts(m, "mode not supported");
1366 break;
1367 case FBC_MODE_TOO_LARGE:
1368 seq_puts(m, "mode too large");
1369 break;
1370 case FBC_BAD_PLANE:
1371 seq_puts(m, "FBC unsupported on plane");
1372 break;
1373 case FBC_NOT_TILED:
1374 seq_puts(m, "scanout buffer not tiled");
1375 break;
1376 case FBC_MULTIPLE_PIPES:
1377 seq_puts(m, "multiple pipes are enabled");
1378 break;
1379 case FBC_MODULE_PARAM:
1380 seq_puts(m, "disabled per module param (default off)");
1381 break;
1382 case FBC_CHIP_DEFAULT:
1383 seq_puts(m, "disabled per chip default");
1384 break;
1385 default:
1386 seq_puts(m, "unknown reason");
1387 }
1388 seq_putc(m, '\n');
1389 }
1390 return 0;
1391 }
1392
1393 static int i915_ips_status(struct seq_file *m, void *unused)
1394 {
1395 struct drm_info_node *node = (struct drm_info_node *) m->private;
1396 struct drm_device *dev = node->minor->dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398
1399 if (!HAS_IPS(dev)) {
1400 seq_puts(m, "not supported\n");
1401 return 0;
1402 }
1403
1404 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1405 seq_puts(m, "enabled\n");
1406 else
1407 seq_puts(m, "disabled\n");
1408
1409 return 0;
1410 }
1411
1412 static int i915_sr_status(struct seq_file *m, void *unused)
1413 {
1414 struct drm_info_node *node = (struct drm_info_node *) m->private;
1415 struct drm_device *dev = node->minor->dev;
1416 drm_i915_private_t *dev_priv = dev->dev_private;
1417 bool sr_enabled = false;
1418
1419 if (HAS_PCH_SPLIT(dev))
1420 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1421 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1422 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1423 else if (IS_I915GM(dev))
1424 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1425 else if (IS_PINEVIEW(dev))
1426 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1427
1428 seq_printf(m, "self-refresh: %s\n",
1429 sr_enabled ? "enabled" : "disabled");
1430
1431 return 0;
1432 }
1433
1434 static int i915_emon_status(struct seq_file *m, void *unused)
1435 {
1436 struct drm_info_node *node = (struct drm_info_node *) m->private;
1437 struct drm_device *dev = node->minor->dev;
1438 drm_i915_private_t *dev_priv = dev->dev_private;
1439 unsigned long temp, chipset, gfx;
1440 int ret;
1441
1442 if (!IS_GEN5(dev))
1443 return -ENODEV;
1444
1445 ret = mutex_lock_interruptible(&dev->struct_mutex);
1446 if (ret)
1447 return ret;
1448
1449 temp = i915_mch_val(dev_priv);
1450 chipset = i915_chipset_val(dev_priv);
1451 gfx = i915_gfx_val(dev_priv);
1452 mutex_unlock(&dev->struct_mutex);
1453
1454 seq_printf(m, "GMCH temp: %ld\n", temp);
1455 seq_printf(m, "Chipset power: %ld\n", chipset);
1456 seq_printf(m, "GFX power: %ld\n", gfx);
1457 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1458
1459 return 0;
1460 }
1461
1462 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1463 {
1464 struct drm_info_node *node = (struct drm_info_node *) m->private;
1465 struct drm_device *dev = node->minor->dev;
1466 drm_i915_private_t *dev_priv = dev->dev_private;
1467 int ret;
1468 int gpu_freq, ia_freq;
1469
1470 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1471 seq_puts(m, "unsupported on this chipset\n");
1472 return 0;
1473 }
1474
1475 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1476
1477 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1478 if (ret)
1479 return ret;
1480 intel_runtime_pm_get(dev_priv);
1481
1482 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1483
1484 for (gpu_freq = dev_priv->rps.min_delay;
1485 gpu_freq <= dev_priv->rps.max_delay;
1486 gpu_freq++) {
1487 ia_freq = gpu_freq;
1488 sandybridge_pcode_read(dev_priv,
1489 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1490 &ia_freq);
1491 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1492 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1493 ((ia_freq >> 0) & 0xff) * 100,
1494 ((ia_freq >> 8) & 0xff) * 100);
1495 }
1496
1497 intel_runtime_pm_put(dev_priv);
1498 mutex_unlock(&dev_priv->rps.hw_lock);
1499
1500 return 0;
1501 }
1502
1503 static int i915_gfxec(struct seq_file *m, void *unused)
1504 {
1505 struct drm_info_node *node = (struct drm_info_node *) m->private;
1506 struct drm_device *dev = node->minor->dev;
1507 drm_i915_private_t *dev_priv = dev->dev_private;
1508 int ret;
1509
1510 ret = mutex_lock_interruptible(&dev->struct_mutex);
1511 if (ret)
1512 return ret;
1513 intel_runtime_pm_get(dev_priv);
1514
1515 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1516 intel_runtime_pm_put(dev_priv);
1517
1518 mutex_unlock(&dev->struct_mutex);
1519
1520 return 0;
1521 }
1522
1523 static int i915_opregion(struct seq_file *m, void *unused)
1524 {
1525 struct drm_info_node *node = (struct drm_info_node *) m->private;
1526 struct drm_device *dev = node->minor->dev;
1527 drm_i915_private_t *dev_priv = dev->dev_private;
1528 struct intel_opregion *opregion = &dev_priv->opregion;
1529 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1530 int ret;
1531
1532 if (data == NULL)
1533 return -ENOMEM;
1534
1535 ret = mutex_lock_interruptible(&dev->struct_mutex);
1536 if (ret)
1537 goto out;
1538
1539 if (opregion->header) {
1540 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1541 seq_write(m, data, OPREGION_SIZE);
1542 }
1543
1544 mutex_unlock(&dev->struct_mutex);
1545
1546 out:
1547 kfree(data);
1548 return 0;
1549 }
1550
1551 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1552 {
1553 struct drm_info_node *node = (struct drm_info_node *) m->private;
1554 struct drm_device *dev = node->minor->dev;
1555 struct intel_fbdev *ifbdev = NULL;
1556 struct intel_framebuffer *fb;
1557
1558 #ifdef CONFIG_DRM_I915_FBDEV
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1561 if (ret)
1562 return ret;
1563
1564 ifbdev = dev_priv->fbdev;
1565 fb = to_intel_framebuffer(ifbdev->helper.fb);
1566
1567 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1568 fb->base.width,
1569 fb->base.height,
1570 fb->base.depth,
1571 fb->base.bits_per_pixel,
1572 atomic_read(&fb->base.refcount.refcount));
1573 describe_obj(m, fb->obj);
1574 seq_putc(m, '\n');
1575 mutex_unlock(&dev->mode_config.mutex);
1576 #endif
1577
1578 mutex_lock(&dev->mode_config.fb_lock);
1579 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1580 if (ifbdev && &fb->base == ifbdev->helper.fb)
1581 continue;
1582
1583 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1584 fb->base.width,
1585 fb->base.height,
1586 fb->base.depth,
1587 fb->base.bits_per_pixel,
1588 atomic_read(&fb->base.refcount.refcount));
1589 describe_obj(m, fb->obj);
1590 seq_putc(m, '\n');
1591 }
1592 mutex_unlock(&dev->mode_config.fb_lock);
1593
1594 return 0;
1595 }
1596
1597 static int i915_context_status(struct seq_file *m, void *unused)
1598 {
1599 struct drm_info_node *node = (struct drm_info_node *) m->private;
1600 struct drm_device *dev = node->minor->dev;
1601 drm_i915_private_t *dev_priv = dev->dev_private;
1602 struct intel_ring_buffer *ring;
1603 struct i915_hw_context *ctx;
1604 int ret, i;
1605
1606 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1607 if (ret)
1608 return ret;
1609
1610 if (dev_priv->ips.pwrctx) {
1611 seq_puts(m, "power context ");
1612 describe_obj(m, dev_priv->ips.pwrctx);
1613 seq_putc(m, '\n');
1614 }
1615
1616 if (dev_priv->ips.renderctx) {
1617 seq_puts(m, "render context ");
1618 describe_obj(m, dev_priv->ips.renderctx);
1619 seq_putc(m, '\n');
1620 }
1621
1622 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1623 seq_puts(m, "HW context ");
1624 describe_ctx(m, ctx);
1625 for_each_ring(ring, dev_priv, i)
1626 if (ring->default_context == ctx)
1627 seq_printf(m, "(default context %s) ", ring->name);
1628
1629 describe_obj(m, ctx->obj);
1630 seq_putc(m, '\n');
1631 }
1632
1633 mutex_unlock(&dev->mode_config.mutex);
1634
1635 return 0;
1636 }
1637
1638 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1639 {
1640 struct drm_info_node *node = (struct drm_info_node *) m->private;
1641 struct drm_device *dev = node->minor->dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1644
1645 spin_lock_irq(&dev_priv->uncore.lock);
1646 if (IS_VALLEYVIEW(dev)) {
1647 fw_rendercount = dev_priv->uncore.fw_rendercount;
1648 fw_mediacount = dev_priv->uncore.fw_mediacount;
1649 } else
1650 forcewake_count = dev_priv->uncore.forcewake_count;
1651 spin_unlock_irq(&dev_priv->uncore.lock);
1652
1653 if (IS_VALLEYVIEW(dev)) {
1654 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1655 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1656 } else
1657 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1658
1659 return 0;
1660 }
1661
1662 static const char *swizzle_string(unsigned swizzle)
1663 {
1664 switch (swizzle) {
1665 case I915_BIT_6_SWIZZLE_NONE:
1666 return "none";
1667 case I915_BIT_6_SWIZZLE_9:
1668 return "bit9";
1669 case I915_BIT_6_SWIZZLE_9_10:
1670 return "bit9/bit10";
1671 case I915_BIT_6_SWIZZLE_9_11:
1672 return "bit9/bit11";
1673 case I915_BIT_6_SWIZZLE_9_10_11:
1674 return "bit9/bit10/bit11";
1675 case I915_BIT_6_SWIZZLE_9_17:
1676 return "bit9/bit17";
1677 case I915_BIT_6_SWIZZLE_9_10_17:
1678 return "bit9/bit10/bit17";
1679 case I915_BIT_6_SWIZZLE_UNKNOWN:
1680 return "unknown";
1681 }
1682
1683 return "bug";
1684 }
1685
1686 static int i915_swizzle_info(struct seq_file *m, void *data)
1687 {
1688 struct drm_info_node *node = (struct drm_info_node *) m->private;
1689 struct drm_device *dev = node->minor->dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int ret;
1692
1693 ret = mutex_lock_interruptible(&dev->struct_mutex);
1694 if (ret)
1695 return ret;
1696 intel_runtime_pm_get(dev_priv);
1697
1698 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1699 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1700 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1701 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1702
1703 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1704 seq_printf(m, "DDC = 0x%08x\n",
1705 I915_READ(DCC));
1706 seq_printf(m, "C0DRB3 = 0x%04x\n",
1707 I915_READ16(C0DRB3));
1708 seq_printf(m, "C1DRB3 = 0x%04x\n",
1709 I915_READ16(C1DRB3));
1710 } else if (INTEL_INFO(dev)->gen >= 6) {
1711 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1712 I915_READ(MAD_DIMM_C0));
1713 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1714 I915_READ(MAD_DIMM_C1));
1715 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1716 I915_READ(MAD_DIMM_C2));
1717 seq_printf(m, "TILECTL = 0x%08x\n",
1718 I915_READ(TILECTL));
1719 if (IS_GEN8(dev))
1720 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1721 I915_READ(GAMTARBMODE));
1722 else
1723 seq_printf(m, "ARB_MODE = 0x%08x\n",
1724 I915_READ(ARB_MODE));
1725 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1726 I915_READ(DISP_ARB_CTL));
1727 }
1728 intel_runtime_pm_put(dev_priv);
1729 mutex_unlock(&dev->struct_mutex);
1730
1731 return 0;
1732 }
1733
1734 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1735 {
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 struct intel_ring_buffer *ring;
1738 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1739 int unused, i;
1740
1741 if (!ppgtt)
1742 return;
1743
1744 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1745 seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
1746 for_each_ring(ring, dev_priv, unused) {
1747 seq_printf(m, "%s\n", ring->name);
1748 for (i = 0; i < 4; i++) {
1749 u32 offset = 0x270 + i * 8;
1750 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1751 pdp <<= 32;
1752 pdp |= I915_READ(ring->mmio_base + offset);
1753 for (i = 0; i < 4; i++)
1754 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1755 }
1756 }
1757 }
1758
1759 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1760 {
1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762 struct intel_ring_buffer *ring;
1763 int i;
1764
1765 if (INTEL_INFO(dev)->gen == 6)
1766 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1767
1768 for_each_ring(ring, dev_priv, i) {
1769 seq_printf(m, "%s\n", ring->name);
1770 if (INTEL_INFO(dev)->gen == 7)
1771 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1772 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1773 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1774 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1775 }
1776 if (dev_priv->mm.aliasing_ppgtt) {
1777 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1778
1779 seq_puts(m, "aliasing PPGTT:\n");
1780 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1781 }
1782 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1783 }
1784
1785 static int i915_ppgtt_info(struct seq_file *m, void *data)
1786 {
1787 struct drm_info_node *node = (struct drm_info_node *) m->private;
1788 struct drm_device *dev = node->minor->dev;
1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790
1791 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1792 if (ret)
1793 return ret;
1794 intel_runtime_pm_get(dev_priv);
1795
1796 if (INTEL_INFO(dev)->gen >= 8)
1797 gen8_ppgtt_info(m, dev);
1798 else if (INTEL_INFO(dev)->gen >= 6)
1799 gen6_ppgtt_info(m, dev);
1800
1801 intel_runtime_pm_put(dev_priv);
1802 mutex_unlock(&dev->struct_mutex);
1803
1804 return 0;
1805 }
1806
1807 static int i915_dpio_info(struct seq_file *m, void *data)
1808 {
1809 struct drm_info_node *node = (struct drm_info_node *) m->private;
1810 struct drm_device *dev = node->minor->dev;
1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 int ret;
1813
1814
1815 if (!IS_VALLEYVIEW(dev)) {
1816 seq_puts(m, "unsupported\n");
1817 return 0;
1818 }
1819
1820 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1821 if (ret)
1822 return ret;
1823
1824 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1825
1826 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1827 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1828 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1829 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1830
1831 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1832 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1833 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1834 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1835
1836 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1837 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1838 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1839 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1840
1841 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1842 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1843 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1844 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1845
1846 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1847 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1848
1849 mutex_unlock(&dev_priv->dpio_lock);
1850
1851 return 0;
1852 }
1853
1854 static int i915_llc(struct seq_file *m, void *data)
1855 {
1856 struct drm_info_node *node = (struct drm_info_node *) m->private;
1857 struct drm_device *dev = node->minor->dev;
1858 struct drm_i915_private *dev_priv = dev->dev_private;
1859
1860 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1861 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1862 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1863
1864 return 0;
1865 }
1866
1867 static int i915_edp_psr_status(struct seq_file *m, void *data)
1868 {
1869 struct drm_info_node *node = m->private;
1870 struct drm_device *dev = node->minor->dev;
1871 struct drm_i915_private *dev_priv = dev->dev_private;
1872 u32 psrperf = 0;
1873 bool enabled = false;
1874
1875 intel_runtime_pm_get(dev_priv);
1876
1877 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1878 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1879
1880 enabled = HAS_PSR(dev) &&
1881 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1882 seq_printf(m, "Enabled: %s\n", yesno(enabled));
1883
1884 if (HAS_PSR(dev))
1885 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1886 EDP_PSR_PERF_CNT_MASK;
1887 seq_printf(m, "Performance_Counter: %u\n", psrperf);
1888
1889 intel_runtime_pm_put(dev_priv);
1890 return 0;
1891 }
1892
1893 static int i915_energy_uJ(struct seq_file *m, void *data)
1894 {
1895 struct drm_info_node *node = m->private;
1896 struct drm_device *dev = node->minor->dev;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 u64 power;
1899 u32 units;
1900
1901 if (INTEL_INFO(dev)->gen < 6)
1902 return -ENODEV;
1903
1904 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1905 power = (power & 0x1f00) >> 8;
1906 units = 1000000 / (1 << power); /* convert to uJ */
1907 power = I915_READ(MCH_SECP_NRG_STTS);
1908 power *= units;
1909
1910 seq_printf(m, "%llu", (long long unsigned)power);
1911
1912 return 0;
1913 }
1914
1915 static int i915_pc8_status(struct seq_file *m, void *unused)
1916 {
1917 struct drm_info_node *node = (struct drm_info_node *) m->private;
1918 struct drm_device *dev = node->minor->dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920
1921 if (!IS_HASWELL(dev)) {
1922 seq_puts(m, "not supported\n");
1923 return 0;
1924 }
1925
1926 mutex_lock(&dev_priv->pc8.lock);
1927 seq_printf(m, "Requirements met: %s\n",
1928 yesno(dev_priv->pc8.requirements_met));
1929 seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
1930 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
1931 seq_printf(m, "IRQs disabled: %s\n",
1932 yesno(dev_priv->pc8.irqs_disabled));
1933 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
1934 mutex_unlock(&dev_priv->pc8.lock);
1935
1936 return 0;
1937 }
1938
1939 static const char *power_domain_str(enum intel_display_power_domain domain)
1940 {
1941 switch (domain) {
1942 case POWER_DOMAIN_PIPE_A:
1943 return "PIPE_A";
1944 case POWER_DOMAIN_PIPE_B:
1945 return "PIPE_B";
1946 case POWER_DOMAIN_PIPE_C:
1947 return "PIPE_C";
1948 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1949 return "PIPE_A_PANEL_FITTER";
1950 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1951 return "PIPE_B_PANEL_FITTER";
1952 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1953 return "PIPE_C_PANEL_FITTER";
1954 case POWER_DOMAIN_TRANSCODER_A:
1955 return "TRANSCODER_A";
1956 case POWER_DOMAIN_TRANSCODER_B:
1957 return "TRANSCODER_B";
1958 case POWER_DOMAIN_TRANSCODER_C:
1959 return "TRANSCODER_C";
1960 case POWER_DOMAIN_TRANSCODER_EDP:
1961 return "TRANSCODER_EDP";
1962 case POWER_DOMAIN_VGA:
1963 return "VGA";
1964 case POWER_DOMAIN_AUDIO:
1965 return "AUDIO";
1966 case POWER_DOMAIN_INIT:
1967 return "INIT";
1968 default:
1969 WARN_ON(1);
1970 return "?";
1971 }
1972 }
1973
1974 static int i915_power_domain_info(struct seq_file *m, void *unused)
1975 {
1976 struct drm_info_node *node = (struct drm_info_node *) m->private;
1977 struct drm_device *dev = node->minor->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1980 int i;
1981
1982 mutex_lock(&power_domains->lock);
1983
1984 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
1985 for (i = 0; i < power_domains->power_well_count; i++) {
1986 struct i915_power_well *power_well;
1987 enum intel_display_power_domain power_domain;
1988
1989 power_well = &power_domains->power_wells[i];
1990 seq_printf(m, "%-25s %d\n", power_well->name,
1991 power_well->count);
1992
1993 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
1994 power_domain++) {
1995 if (!(BIT(power_domain) & power_well->domains))
1996 continue;
1997
1998 seq_printf(m, " %-23s %d\n",
1999 power_domain_str(power_domain),
2000 power_domains->domain_use_count[power_domain]);
2001 }
2002 }
2003
2004 mutex_unlock(&power_domains->lock);
2005
2006 return 0;
2007 }
2008
2009 struct pipe_crc_info {
2010 const char *name;
2011 struct drm_device *dev;
2012 enum pipe pipe;
2013 };
2014
2015 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2016 {
2017 struct pipe_crc_info *info = inode->i_private;
2018 struct drm_i915_private *dev_priv = info->dev->dev_private;
2019 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2020
2021 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2022 return -ENODEV;
2023
2024 spin_lock_irq(&pipe_crc->lock);
2025
2026 if (pipe_crc->opened) {
2027 spin_unlock_irq(&pipe_crc->lock);
2028 return -EBUSY; /* already open */
2029 }
2030
2031 pipe_crc->opened = true;
2032 filep->private_data = inode->i_private;
2033
2034 spin_unlock_irq(&pipe_crc->lock);
2035
2036 return 0;
2037 }
2038
2039 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2040 {
2041 struct pipe_crc_info *info = inode->i_private;
2042 struct drm_i915_private *dev_priv = info->dev->dev_private;
2043 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2044
2045 spin_lock_irq(&pipe_crc->lock);
2046 pipe_crc->opened = false;
2047 spin_unlock_irq(&pipe_crc->lock);
2048
2049 return 0;
2050 }
2051
2052 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2053 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2054 /* account for \'0' */
2055 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2056
2057 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2058 {
2059 assert_spin_locked(&pipe_crc->lock);
2060 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2061 INTEL_PIPE_CRC_ENTRIES_NR);
2062 }
2063
2064 static ssize_t
2065 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2066 loff_t *pos)
2067 {
2068 struct pipe_crc_info *info = filep->private_data;
2069 struct drm_device *dev = info->dev;
2070 struct drm_i915_private *dev_priv = dev->dev_private;
2071 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2072 char buf[PIPE_CRC_BUFFER_LEN];
2073 int head, tail, n_entries, n;
2074 ssize_t bytes_read;
2075
2076 /*
2077 * Don't allow user space to provide buffers not big enough to hold
2078 * a line of data.
2079 */
2080 if (count < PIPE_CRC_LINE_LEN)
2081 return -EINVAL;
2082
2083 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2084 return 0;
2085
2086 /* nothing to read */
2087 spin_lock_irq(&pipe_crc->lock);
2088 while (pipe_crc_data_count(pipe_crc) == 0) {
2089 int ret;
2090
2091 if (filep->f_flags & O_NONBLOCK) {
2092 spin_unlock_irq(&pipe_crc->lock);
2093 return -EAGAIN;
2094 }
2095
2096 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2097 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2098 if (ret) {
2099 spin_unlock_irq(&pipe_crc->lock);
2100 return ret;
2101 }
2102 }
2103
2104 /* We now have one or more entries to read */
2105 head = pipe_crc->head;
2106 tail = pipe_crc->tail;
2107 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2108 count / PIPE_CRC_LINE_LEN);
2109 spin_unlock_irq(&pipe_crc->lock);
2110
2111 bytes_read = 0;
2112 n = 0;
2113 do {
2114 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2115 int ret;
2116
2117 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2118 "%8u %8x %8x %8x %8x %8x\n",
2119 entry->frame, entry->crc[0],
2120 entry->crc[1], entry->crc[2],
2121 entry->crc[3], entry->crc[4]);
2122
2123 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2124 buf, PIPE_CRC_LINE_LEN);
2125 if (ret == PIPE_CRC_LINE_LEN)
2126 return -EFAULT;
2127
2128 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2129 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2130 n++;
2131 } while (--n_entries);
2132
2133 spin_lock_irq(&pipe_crc->lock);
2134 pipe_crc->tail = tail;
2135 spin_unlock_irq(&pipe_crc->lock);
2136
2137 return bytes_read;
2138 }
2139
2140 static const struct file_operations i915_pipe_crc_fops = {
2141 .owner = THIS_MODULE,
2142 .open = i915_pipe_crc_open,
2143 .read = i915_pipe_crc_read,
2144 .release = i915_pipe_crc_release,
2145 };
2146
2147 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2148 {
2149 .name = "i915_pipe_A_crc",
2150 .pipe = PIPE_A,
2151 },
2152 {
2153 .name = "i915_pipe_B_crc",
2154 .pipe = PIPE_B,
2155 },
2156 {
2157 .name = "i915_pipe_C_crc",
2158 .pipe = PIPE_C,
2159 },
2160 };
2161
2162 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2163 enum pipe pipe)
2164 {
2165 struct drm_device *dev = minor->dev;
2166 struct dentry *ent;
2167 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2168
2169 info->dev = dev;
2170 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2171 &i915_pipe_crc_fops);
2172 if (!ent)
2173 return -ENOMEM;
2174
2175 return drm_add_fake_info_node(minor, ent, info);
2176 }
2177
2178 static const char * const pipe_crc_sources[] = {
2179 "none",
2180 "plane1",
2181 "plane2",
2182 "pf",
2183 "pipe",
2184 "TV",
2185 "DP-B",
2186 "DP-C",
2187 "DP-D",
2188 "auto",
2189 };
2190
2191 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2192 {
2193 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2194 return pipe_crc_sources[source];
2195 }
2196
2197 static int display_crc_ctl_show(struct seq_file *m, void *data)
2198 {
2199 struct drm_device *dev = m->private;
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 int i;
2202
2203 for (i = 0; i < I915_MAX_PIPES; i++)
2204 seq_printf(m, "%c %s\n", pipe_name(i),
2205 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2206
2207 return 0;
2208 }
2209
2210 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2211 {
2212 struct drm_device *dev = inode->i_private;
2213
2214 return single_open(file, display_crc_ctl_show, dev);
2215 }
2216
2217 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2218 uint32_t *val)
2219 {
2220 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2221 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2222
2223 switch (*source) {
2224 case INTEL_PIPE_CRC_SOURCE_PIPE:
2225 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2226 break;
2227 case INTEL_PIPE_CRC_SOURCE_NONE:
2228 *val = 0;
2229 break;
2230 default:
2231 return -EINVAL;
2232 }
2233
2234 return 0;
2235 }
2236
2237 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2238 enum intel_pipe_crc_source *source)
2239 {
2240 struct intel_encoder *encoder;
2241 struct intel_crtc *crtc;
2242 struct intel_digital_port *dig_port;
2243 int ret = 0;
2244
2245 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2246
2247 mutex_lock(&dev->mode_config.mutex);
2248 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2249 base.head) {
2250 if (!encoder->base.crtc)
2251 continue;
2252
2253 crtc = to_intel_crtc(encoder->base.crtc);
2254
2255 if (crtc->pipe != pipe)
2256 continue;
2257
2258 switch (encoder->type) {
2259 case INTEL_OUTPUT_TVOUT:
2260 *source = INTEL_PIPE_CRC_SOURCE_TV;
2261 break;
2262 case INTEL_OUTPUT_DISPLAYPORT:
2263 case INTEL_OUTPUT_EDP:
2264 dig_port = enc_to_dig_port(&encoder->base);
2265 switch (dig_port->port) {
2266 case PORT_B:
2267 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2268 break;
2269 case PORT_C:
2270 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2271 break;
2272 case PORT_D:
2273 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2274 break;
2275 default:
2276 WARN(1, "nonexisting DP port %c\n",
2277 port_name(dig_port->port));
2278 break;
2279 }
2280 break;
2281 }
2282 }
2283 mutex_unlock(&dev->mode_config.mutex);
2284
2285 return ret;
2286 }
2287
2288 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2289 enum pipe pipe,
2290 enum intel_pipe_crc_source *source,
2291 uint32_t *val)
2292 {
2293 struct drm_i915_private *dev_priv = dev->dev_private;
2294 bool need_stable_symbols = false;
2295
2296 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2297 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2298 if (ret)
2299 return ret;
2300 }
2301
2302 switch (*source) {
2303 case INTEL_PIPE_CRC_SOURCE_PIPE:
2304 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2305 break;
2306 case INTEL_PIPE_CRC_SOURCE_DP_B:
2307 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2308 need_stable_symbols = true;
2309 break;
2310 case INTEL_PIPE_CRC_SOURCE_DP_C:
2311 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2312 need_stable_symbols = true;
2313 break;
2314 case INTEL_PIPE_CRC_SOURCE_NONE:
2315 *val = 0;
2316 break;
2317 default:
2318 return -EINVAL;
2319 }
2320
2321 /*
2322 * When the pipe CRC tap point is after the transcoders we need
2323 * to tweak symbol-level features to produce a deterministic series of
2324 * symbols for a given frame. We need to reset those features only once
2325 * a frame (instead of every nth symbol):
2326 * - DC-balance: used to ensure a better clock recovery from the data
2327 * link (SDVO)
2328 * - DisplayPort scrambling: used for EMI reduction
2329 */
2330 if (need_stable_symbols) {
2331 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2332
2333 WARN_ON(!IS_G4X(dev));
2334
2335 tmp |= DC_BALANCE_RESET_VLV;
2336 if (pipe == PIPE_A)
2337 tmp |= PIPE_A_SCRAMBLE_RESET;
2338 else
2339 tmp |= PIPE_B_SCRAMBLE_RESET;
2340
2341 I915_WRITE(PORT_DFT2_G4X, tmp);
2342 }
2343
2344 return 0;
2345 }
2346
2347 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2348 enum pipe pipe,
2349 enum intel_pipe_crc_source *source,
2350 uint32_t *val)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 bool need_stable_symbols = false;
2354
2355 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2356 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2357 if (ret)
2358 return ret;
2359 }
2360
2361 switch (*source) {
2362 case INTEL_PIPE_CRC_SOURCE_PIPE:
2363 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2364 break;
2365 case INTEL_PIPE_CRC_SOURCE_TV:
2366 if (!SUPPORTS_TV(dev))
2367 return -EINVAL;
2368 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2369 break;
2370 case INTEL_PIPE_CRC_SOURCE_DP_B:
2371 if (!IS_G4X(dev))
2372 return -EINVAL;
2373 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2374 need_stable_symbols = true;
2375 break;
2376 case INTEL_PIPE_CRC_SOURCE_DP_C:
2377 if (!IS_G4X(dev))
2378 return -EINVAL;
2379 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2380 need_stable_symbols = true;
2381 break;
2382 case INTEL_PIPE_CRC_SOURCE_DP_D:
2383 if (!IS_G4X(dev))
2384 return -EINVAL;
2385 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2386 need_stable_symbols = true;
2387 break;
2388 case INTEL_PIPE_CRC_SOURCE_NONE:
2389 *val = 0;
2390 break;
2391 default:
2392 return -EINVAL;
2393 }
2394
2395 /*
2396 * When the pipe CRC tap point is after the transcoders we need
2397 * to tweak symbol-level features to produce a deterministic series of
2398 * symbols for a given frame. We need to reset those features only once
2399 * a frame (instead of every nth symbol):
2400 * - DC-balance: used to ensure a better clock recovery from the data
2401 * link (SDVO)
2402 * - DisplayPort scrambling: used for EMI reduction
2403 */
2404 if (need_stable_symbols) {
2405 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2406
2407 WARN_ON(!IS_G4X(dev));
2408
2409 I915_WRITE(PORT_DFT_I9XX,
2410 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2411
2412 if (pipe == PIPE_A)
2413 tmp |= PIPE_A_SCRAMBLE_RESET;
2414 else
2415 tmp |= PIPE_B_SCRAMBLE_RESET;
2416
2417 I915_WRITE(PORT_DFT2_G4X, tmp);
2418 }
2419
2420 return 0;
2421 }
2422
2423 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2424 enum pipe pipe)
2425 {
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2428
2429 if (pipe == PIPE_A)
2430 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2431 else
2432 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2433 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2434 tmp &= ~DC_BALANCE_RESET_VLV;
2435 I915_WRITE(PORT_DFT2_G4X, tmp);
2436
2437 }
2438
2439 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2440 enum pipe pipe)
2441 {
2442 struct drm_i915_private *dev_priv = dev->dev_private;
2443 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2444
2445 if (pipe == PIPE_A)
2446 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2447 else
2448 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2449 I915_WRITE(PORT_DFT2_G4X, tmp);
2450
2451 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2452 I915_WRITE(PORT_DFT_I9XX,
2453 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2454 }
2455 }
2456
2457 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2458 uint32_t *val)
2459 {
2460 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2461 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2462
2463 switch (*source) {
2464 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2465 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2466 break;
2467 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2468 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2469 break;
2470 case INTEL_PIPE_CRC_SOURCE_PIPE:
2471 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2472 break;
2473 case INTEL_PIPE_CRC_SOURCE_NONE:
2474 *val = 0;
2475 break;
2476 default:
2477 return -EINVAL;
2478 }
2479
2480 return 0;
2481 }
2482
2483 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2484 uint32_t *val)
2485 {
2486 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2487 *source = INTEL_PIPE_CRC_SOURCE_PF;
2488
2489 switch (*source) {
2490 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2491 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2492 break;
2493 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2494 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2495 break;
2496 case INTEL_PIPE_CRC_SOURCE_PF:
2497 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2498 break;
2499 case INTEL_PIPE_CRC_SOURCE_NONE:
2500 *val = 0;
2501 break;
2502 default:
2503 return -EINVAL;
2504 }
2505
2506 return 0;
2507 }
2508
2509 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2510 enum intel_pipe_crc_source source)
2511 {
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2514 u32 val = 0; /* shut up gcc */
2515 int ret;
2516
2517 if (pipe_crc->source == source)
2518 return 0;
2519
2520 /* forbid changing the source without going back to 'none' */
2521 if (pipe_crc->source && source)
2522 return -EINVAL;
2523
2524 if (IS_GEN2(dev))
2525 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2526 else if (INTEL_INFO(dev)->gen < 5)
2527 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2528 else if (IS_VALLEYVIEW(dev))
2529 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2530 else if (IS_GEN5(dev) || IS_GEN6(dev))
2531 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2532 else
2533 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2534
2535 if (ret != 0)
2536 return ret;
2537
2538 /* none -> real source transition */
2539 if (source) {
2540 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2541 pipe_name(pipe), pipe_crc_source_name(source));
2542
2543 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2544 INTEL_PIPE_CRC_ENTRIES_NR,
2545 GFP_KERNEL);
2546 if (!pipe_crc->entries)
2547 return -ENOMEM;
2548
2549 spin_lock_irq(&pipe_crc->lock);
2550 pipe_crc->head = 0;
2551 pipe_crc->tail = 0;
2552 spin_unlock_irq(&pipe_crc->lock);
2553 }
2554
2555 pipe_crc->source = source;
2556
2557 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2558 POSTING_READ(PIPE_CRC_CTL(pipe));
2559
2560 /* real source -> none transition */
2561 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2562 struct intel_pipe_crc_entry *entries;
2563
2564 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2565 pipe_name(pipe));
2566
2567 intel_wait_for_vblank(dev, pipe);
2568
2569 spin_lock_irq(&pipe_crc->lock);
2570 entries = pipe_crc->entries;
2571 pipe_crc->entries = NULL;
2572 spin_unlock_irq(&pipe_crc->lock);
2573
2574 kfree(entries);
2575
2576 if (IS_G4X(dev))
2577 g4x_undo_pipe_scramble_reset(dev, pipe);
2578 else if (IS_VALLEYVIEW(dev))
2579 vlv_undo_pipe_scramble_reset(dev, pipe);
2580 }
2581
2582 return 0;
2583 }
2584
2585 /*
2586 * Parse pipe CRC command strings:
2587 * command: wsp* object wsp+ name wsp+ source wsp*
2588 * object: 'pipe'
2589 * name: (A | B | C)
2590 * source: (none | plane1 | plane2 | pf)
2591 * wsp: (#0x20 | #0x9 | #0xA)+
2592 *
2593 * eg.:
2594 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2595 * "pipe A none" -> Stop CRC
2596 */
2597 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2598 {
2599 int n_words = 0;
2600
2601 while (*buf) {
2602 char *end;
2603
2604 /* skip leading white space */
2605 buf = skip_spaces(buf);
2606 if (!*buf)
2607 break; /* end of buffer */
2608
2609 /* find end of word */
2610 for (end = buf; *end && !isspace(*end); end++)
2611 ;
2612
2613 if (n_words == max_words) {
2614 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2615 max_words);
2616 return -EINVAL; /* ran out of words[] before bytes */
2617 }
2618
2619 if (*end)
2620 *end++ = '\0';
2621 words[n_words++] = buf;
2622 buf = end;
2623 }
2624
2625 return n_words;
2626 }
2627
2628 enum intel_pipe_crc_object {
2629 PIPE_CRC_OBJECT_PIPE,
2630 };
2631
2632 static const char * const pipe_crc_objects[] = {
2633 "pipe",
2634 };
2635
2636 static int
2637 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
2638 {
2639 int i;
2640
2641 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2642 if (!strcmp(buf, pipe_crc_objects[i])) {
2643 *o = i;
2644 return 0;
2645 }
2646
2647 return -EINVAL;
2648 }
2649
2650 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
2651 {
2652 const char name = buf[0];
2653
2654 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2655 return -EINVAL;
2656
2657 *pipe = name - 'A';
2658
2659 return 0;
2660 }
2661
2662 static int
2663 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
2664 {
2665 int i;
2666
2667 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2668 if (!strcmp(buf, pipe_crc_sources[i])) {
2669 *s = i;
2670 return 0;
2671 }
2672
2673 return -EINVAL;
2674 }
2675
2676 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
2677 {
2678 #define N_WORDS 3
2679 int n_words;
2680 char *words[N_WORDS];
2681 enum pipe pipe;
2682 enum intel_pipe_crc_object object;
2683 enum intel_pipe_crc_source source;
2684
2685 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
2686 if (n_words != N_WORDS) {
2687 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2688 N_WORDS);
2689 return -EINVAL;
2690 }
2691
2692 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
2693 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
2694 return -EINVAL;
2695 }
2696
2697 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
2698 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2699 return -EINVAL;
2700 }
2701
2702 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
2703 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
2704 return -EINVAL;
2705 }
2706
2707 return pipe_crc_set_source(dev, pipe, source);
2708 }
2709
2710 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2711 size_t len, loff_t *offp)
2712 {
2713 struct seq_file *m = file->private_data;
2714 struct drm_device *dev = m->private;
2715 char *tmpbuf;
2716 int ret;
2717
2718 if (len == 0)
2719 return 0;
2720
2721 if (len > PAGE_SIZE - 1) {
2722 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2723 PAGE_SIZE);
2724 return -E2BIG;
2725 }
2726
2727 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2728 if (!tmpbuf)
2729 return -ENOMEM;
2730
2731 if (copy_from_user(tmpbuf, ubuf, len)) {
2732 ret = -EFAULT;
2733 goto out;
2734 }
2735 tmpbuf[len] = '\0';
2736
2737 ret = display_crc_ctl_parse(dev, tmpbuf, len);
2738
2739 out:
2740 kfree(tmpbuf);
2741 if (ret < 0)
2742 return ret;
2743
2744 *offp += len;
2745 return len;
2746 }
2747
2748 static const struct file_operations i915_display_crc_ctl_fops = {
2749 .owner = THIS_MODULE,
2750 .open = display_crc_ctl_open,
2751 .read = seq_read,
2752 .llseek = seq_lseek,
2753 .release = single_release,
2754 .write = display_crc_ctl_write
2755 };
2756
2757 static int
2758 i915_wedged_get(void *data, u64 *val)
2759 {
2760 struct drm_device *dev = data;
2761 drm_i915_private_t *dev_priv = dev->dev_private;
2762
2763 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
2764
2765 return 0;
2766 }
2767
2768 static int
2769 i915_wedged_set(void *data, u64 val)
2770 {
2771 struct drm_device *dev = data;
2772
2773 DRM_INFO("Manually setting wedged to %llu\n", val);
2774 i915_handle_error(dev, val);
2775
2776 return 0;
2777 }
2778
2779 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
2780 i915_wedged_get, i915_wedged_set,
2781 "%llu\n");
2782
2783 static int
2784 i915_ring_stop_get(void *data, u64 *val)
2785 {
2786 struct drm_device *dev = data;
2787 drm_i915_private_t *dev_priv = dev->dev_private;
2788
2789 *val = dev_priv->gpu_error.stop_rings;
2790
2791 return 0;
2792 }
2793
2794 static int
2795 i915_ring_stop_set(void *data, u64 val)
2796 {
2797 struct drm_device *dev = data;
2798 struct drm_i915_private *dev_priv = dev->dev_private;
2799 int ret;
2800
2801 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
2802
2803 ret = mutex_lock_interruptible(&dev->struct_mutex);
2804 if (ret)
2805 return ret;
2806
2807 dev_priv->gpu_error.stop_rings = val;
2808 mutex_unlock(&dev->struct_mutex);
2809
2810 return 0;
2811 }
2812
2813 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
2814 i915_ring_stop_get, i915_ring_stop_set,
2815 "0x%08llx\n");
2816
2817 static int
2818 i915_ring_missed_irq_get(void *data, u64 *val)
2819 {
2820 struct drm_device *dev = data;
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822
2823 *val = dev_priv->gpu_error.missed_irq_rings;
2824 return 0;
2825 }
2826
2827 static int
2828 i915_ring_missed_irq_set(void *data, u64 val)
2829 {
2830 struct drm_device *dev = data;
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 int ret;
2833
2834 /* Lock against concurrent debugfs callers */
2835 ret = mutex_lock_interruptible(&dev->struct_mutex);
2836 if (ret)
2837 return ret;
2838 dev_priv->gpu_error.missed_irq_rings = val;
2839 mutex_unlock(&dev->struct_mutex);
2840
2841 return 0;
2842 }
2843
2844 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
2845 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
2846 "0x%08llx\n");
2847
2848 static int
2849 i915_ring_test_irq_get(void *data, u64 *val)
2850 {
2851 struct drm_device *dev = data;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853
2854 *val = dev_priv->gpu_error.test_irq_rings;
2855
2856 return 0;
2857 }
2858
2859 static int
2860 i915_ring_test_irq_set(void *data, u64 val)
2861 {
2862 struct drm_device *dev = data;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 int ret;
2865
2866 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
2867
2868 /* Lock against concurrent debugfs callers */
2869 ret = mutex_lock_interruptible(&dev->struct_mutex);
2870 if (ret)
2871 return ret;
2872
2873 dev_priv->gpu_error.test_irq_rings = val;
2874 mutex_unlock(&dev->struct_mutex);
2875
2876 return 0;
2877 }
2878
2879 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
2880 i915_ring_test_irq_get, i915_ring_test_irq_set,
2881 "0x%08llx\n");
2882
2883 #define DROP_UNBOUND 0x1
2884 #define DROP_BOUND 0x2
2885 #define DROP_RETIRE 0x4
2886 #define DROP_ACTIVE 0x8
2887 #define DROP_ALL (DROP_UNBOUND | \
2888 DROP_BOUND | \
2889 DROP_RETIRE | \
2890 DROP_ACTIVE)
2891 static int
2892 i915_drop_caches_get(void *data, u64 *val)
2893 {
2894 *val = DROP_ALL;
2895
2896 return 0;
2897 }
2898
2899 static int
2900 i915_drop_caches_set(void *data, u64 val)
2901 {
2902 struct drm_device *dev = data;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct drm_i915_gem_object *obj, *next;
2905 struct i915_address_space *vm;
2906 struct i915_vma *vma, *x;
2907 int ret;
2908
2909 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
2910
2911 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2912 * on ioctls on -EAGAIN. */
2913 ret = mutex_lock_interruptible(&dev->struct_mutex);
2914 if (ret)
2915 return ret;
2916
2917 if (val & DROP_ACTIVE) {
2918 ret = i915_gpu_idle(dev);
2919 if (ret)
2920 goto unlock;
2921 }
2922
2923 if (val & (DROP_RETIRE | DROP_ACTIVE))
2924 i915_gem_retire_requests(dev);
2925
2926 if (val & DROP_BOUND) {
2927 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2928 list_for_each_entry_safe(vma, x, &vm->inactive_list,
2929 mm_list) {
2930 if (vma->obj->pin_count)
2931 continue;
2932
2933 ret = i915_vma_unbind(vma);
2934 if (ret)
2935 goto unlock;
2936 }
2937 }
2938 }
2939
2940 if (val & DROP_UNBOUND) {
2941 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
2942 global_list)
2943 if (obj->pages_pin_count == 0) {
2944 ret = i915_gem_object_put_pages(obj);
2945 if (ret)
2946 goto unlock;
2947 }
2948 }
2949
2950 unlock:
2951 mutex_unlock(&dev->struct_mutex);
2952
2953 return ret;
2954 }
2955
2956 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
2957 i915_drop_caches_get, i915_drop_caches_set,
2958 "0x%08llx\n");
2959
2960 static int
2961 i915_max_freq_get(void *data, u64 *val)
2962 {
2963 struct drm_device *dev = data;
2964 drm_i915_private_t *dev_priv = dev->dev_private;
2965 int ret;
2966
2967 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2968 return -ENODEV;
2969
2970 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2971
2972 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2973 if (ret)
2974 return ret;
2975
2976 if (IS_VALLEYVIEW(dev))
2977 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
2978 else
2979 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2980 mutex_unlock(&dev_priv->rps.hw_lock);
2981
2982 return 0;
2983 }
2984
2985 static int
2986 i915_max_freq_set(void *data, u64 val)
2987 {
2988 struct drm_device *dev = data;
2989 struct drm_i915_private *dev_priv = dev->dev_private;
2990 int ret;
2991
2992 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
2993 return -ENODEV;
2994
2995 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
2996
2997 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
2998
2999 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3000 if (ret)
3001 return ret;
3002
3003 /*
3004 * Turbo will still be enabled, but won't go above the set value.
3005 */
3006 if (IS_VALLEYVIEW(dev)) {
3007 val = vlv_freq_opcode(dev_priv, val);
3008 dev_priv->rps.max_delay = val;
3009 valleyview_set_rps(dev, val);
3010 } else {
3011 do_div(val, GT_FREQUENCY_MULTIPLIER);
3012 dev_priv->rps.max_delay = val;
3013 gen6_set_rps(dev, val);
3014 }
3015
3016 mutex_unlock(&dev_priv->rps.hw_lock);
3017
3018 return 0;
3019 }
3020
3021 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3022 i915_max_freq_get, i915_max_freq_set,
3023 "%llu\n");
3024
3025 static int
3026 i915_min_freq_get(void *data, u64 *val)
3027 {
3028 struct drm_device *dev = data;
3029 drm_i915_private_t *dev_priv = dev->dev_private;
3030 int ret;
3031
3032 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3033 return -ENODEV;
3034
3035 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3036
3037 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3038 if (ret)
3039 return ret;
3040
3041 if (IS_VALLEYVIEW(dev))
3042 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
3043 else
3044 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
3045 mutex_unlock(&dev_priv->rps.hw_lock);
3046
3047 return 0;
3048 }
3049
3050 static int
3051 i915_min_freq_set(void *data, u64 val)
3052 {
3053 struct drm_device *dev = data;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 int ret;
3056
3057 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3058 return -ENODEV;
3059
3060 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3061
3062 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3063
3064 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3065 if (ret)
3066 return ret;
3067
3068 /*
3069 * Turbo will still be enabled, but won't go below the set value.
3070 */
3071 if (IS_VALLEYVIEW(dev)) {
3072 val = vlv_freq_opcode(dev_priv, val);
3073 dev_priv->rps.min_delay = val;
3074 valleyview_set_rps(dev, val);
3075 } else {
3076 do_div(val, GT_FREQUENCY_MULTIPLIER);
3077 dev_priv->rps.min_delay = val;
3078 gen6_set_rps(dev, val);
3079 }
3080 mutex_unlock(&dev_priv->rps.hw_lock);
3081
3082 return 0;
3083 }
3084
3085 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3086 i915_min_freq_get, i915_min_freq_set,
3087 "%llu\n");
3088
3089 static int
3090 i915_cache_sharing_get(void *data, u64 *val)
3091 {
3092 struct drm_device *dev = data;
3093 drm_i915_private_t *dev_priv = dev->dev_private;
3094 u32 snpcr;
3095 int ret;
3096
3097 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3098 return -ENODEV;
3099
3100 ret = mutex_lock_interruptible(&dev->struct_mutex);
3101 if (ret)
3102 return ret;
3103 intel_runtime_pm_get(dev_priv);
3104
3105 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3106
3107 intel_runtime_pm_put(dev_priv);
3108 mutex_unlock(&dev_priv->dev->struct_mutex);
3109
3110 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3111
3112 return 0;
3113 }
3114
3115 static int
3116 i915_cache_sharing_set(void *data, u64 val)
3117 {
3118 struct drm_device *dev = data;
3119 struct drm_i915_private *dev_priv = dev->dev_private;
3120 u32 snpcr;
3121
3122 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3123 return -ENODEV;
3124
3125 if (val > 3)
3126 return -EINVAL;
3127
3128 intel_runtime_pm_get(dev_priv);
3129 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3130
3131 /* Update the cache sharing policy here as well */
3132 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3133 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3134 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3135 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3136
3137 intel_runtime_pm_put(dev_priv);
3138 return 0;
3139 }
3140
3141 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3142 i915_cache_sharing_get, i915_cache_sharing_set,
3143 "%llu\n");
3144
3145 static int i915_forcewake_open(struct inode *inode, struct file *file)
3146 {
3147 struct drm_device *dev = inode->i_private;
3148 struct drm_i915_private *dev_priv = dev->dev_private;
3149
3150 if (INTEL_INFO(dev)->gen < 6)
3151 return 0;
3152
3153 intel_runtime_pm_get(dev_priv);
3154 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3155
3156 return 0;
3157 }
3158
3159 static int i915_forcewake_release(struct inode *inode, struct file *file)
3160 {
3161 struct drm_device *dev = inode->i_private;
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163
3164 if (INTEL_INFO(dev)->gen < 6)
3165 return 0;
3166
3167 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3168 intel_runtime_pm_put(dev_priv);
3169
3170 return 0;
3171 }
3172
3173 static const struct file_operations i915_forcewake_fops = {
3174 .owner = THIS_MODULE,
3175 .open = i915_forcewake_open,
3176 .release = i915_forcewake_release,
3177 };
3178
3179 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3180 {
3181 struct drm_device *dev = minor->dev;
3182 struct dentry *ent;
3183
3184 ent = debugfs_create_file("i915_forcewake_user",
3185 S_IRUSR,
3186 root, dev,
3187 &i915_forcewake_fops);
3188 if (!ent)
3189 return -ENOMEM;
3190
3191 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3192 }
3193
3194 static int i915_debugfs_create(struct dentry *root,
3195 struct drm_minor *minor,
3196 const char *name,
3197 const struct file_operations *fops)
3198 {
3199 struct drm_device *dev = minor->dev;
3200 struct dentry *ent;
3201
3202 ent = debugfs_create_file(name,
3203 S_IRUGO | S_IWUSR,
3204 root, dev,
3205 fops);
3206 if (!ent)
3207 return -ENOMEM;
3208
3209 return drm_add_fake_info_node(minor, ent, fops);
3210 }
3211
3212 static const struct drm_info_list i915_debugfs_list[] = {
3213 {"i915_capabilities", i915_capabilities, 0},
3214 {"i915_gem_objects", i915_gem_object_info, 0},
3215 {"i915_gem_gtt", i915_gem_gtt_info, 0},
3216 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3217 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3218 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3219 {"i915_gem_stolen", i915_gem_stolen_list_info },
3220 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3221 {"i915_gem_request", i915_gem_request_info, 0},
3222 {"i915_gem_seqno", i915_gem_seqno_info, 0},
3223 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3224 {"i915_gem_interrupt", i915_interrupt_info, 0},
3225 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3226 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3227 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3228 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3229 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3230 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3231 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3232 {"i915_inttoext_table", i915_inttoext_table, 0},
3233 {"i915_drpc_info", i915_drpc_info, 0},
3234 {"i915_emon_status", i915_emon_status, 0},
3235 {"i915_ring_freq_table", i915_ring_freq_table, 0},
3236 {"i915_gfxec", i915_gfxec, 0},
3237 {"i915_fbc_status", i915_fbc_status, 0},
3238 {"i915_ips_status", i915_ips_status, 0},
3239 {"i915_sr_status", i915_sr_status, 0},
3240 {"i915_opregion", i915_opregion, 0},
3241 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3242 {"i915_context_status", i915_context_status, 0},
3243 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3244 {"i915_swizzle_info", i915_swizzle_info, 0},
3245 {"i915_ppgtt_info", i915_ppgtt_info, 0},
3246 {"i915_dpio", i915_dpio_info, 0},
3247 {"i915_llc", i915_llc, 0},
3248 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3249 {"i915_energy_uJ", i915_energy_uJ, 0},
3250 {"i915_pc8_status", i915_pc8_status, 0},
3251 {"i915_power_domain_info", i915_power_domain_info, 0},
3252 };
3253 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3254
3255 static const struct i915_debugfs_files {
3256 const char *name;
3257 const struct file_operations *fops;
3258 } i915_debugfs_files[] = {
3259 {"i915_wedged", &i915_wedged_fops},
3260 {"i915_max_freq", &i915_max_freq_fops},
3261 {"i915_min_freq", &i915_min_freq_fops},
3262 {"i915_cache_sharing", &i915_cache_sharing_fops},
3263 {"i915_ring_stop", &i915_ring_stop_fops},
3264 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3265 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3266 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3267 {"i915_error_state", &i915_error_state_fops},
3268 {"i915_next_seqno", &i915_next_seqno_fops},
3269 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3270 };
3271
3272 void intel_display_crc_init(struct drm_device *dev)
3273 {
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 enum pipe pipe;
3276
3277 for_each_pipe(pipe) {
3278 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3279
3280 pipe_crc->opened = false;
3281 spin_lock_init(&pipe_crc->lock);
3282 init_waitqueue_head(&pipe_crc->wq);
3283 }
3284 }
3285
3286 int i915_debugfs_init(struct drm_minor *minor)
3287 {
3288 int ret, i;
3289
3290 ret = i915_forcewake_create(minor->debugfs_root, minor);
3291 if (ret)
3292 return ret;
3293
3294 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3295 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3296 if (ret)
3297 return ret;
3298 }
3299
3300 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3301 ret = i915_debugfs_create(minor->debugfs_root, minor,
3302 i915_debugfs_files[i].name,
3303 i915_debugfs_files[i].fops);
3304 if (ret)
3305 return ret;
3306 }
3307
3308 return drm_debugfs_create_files(i915_debugfs_list,
3309 I915_DEBUGFS_ENTRIES,
3310 minor->debugfs_root, minor);
3311 }
3312
3313 void i915_debugfs_cleanup(struct drm_minor *minor)
3314 {
3315 int i;
3316
3317 drm_debugfs_remove_files(i915_debugfs_list,
3318 I915_DEBUGFS_ENTRIES, minor);
3319
3320 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3321 1, minor);
3322
3323 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3324 struct drm_info_list *info_list =
3325 (struct drm_info_list *)&i915_pipe_crc_data[i];
3326
3327 drm_debugfs_remove_files(info_list, 1, minor);
3328 }
3329
3330 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3331 struct drm_info_list *info_list =
3332 (struct drm_info_list *) i915_debugfs_files[i].fops;
3333
3334 drm_debugfs_remove_files(info_list, 1, minor);
3335 }
3336 }
Linux kernel - Deliverables
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