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ae73288a9699cbb7c02915680e656fced951842c
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29 #include <linux/seq_file.h>
30 #include <linux/debugfs.h>
31 #include <linux/slab.h>
32 #include <linux/export.h>
33 #include "drmP.h"
34 #include "drm.h"
35 #include "intel_drv.h"
36 #include "intel_ringbuffer.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39
40 #define DRM_I915_RING_DEBUG 1
41
42
43 #if defined(CONFIG_DEBUG_FS)
44
45 enum {
46 ACTIVE_LIST,
47 FLUSHING_LIST,
48 INACTIVE_LIST,
49 PINNED_LIST,
50 DEFERRED_FREE_LIST,
51 };
52
53 static const char *yesno(int v)
54 {
55 return v ? "yes" : "no";
56 }
57
58 static int i915_capabilities(struct seq_file *m, void *data)
59 {
60 struct drm_info_node *node = (struct drm_info_node *) m->private;
61 struct drm_device *dev = node->minor->dev;
62 const struct intel_device_info *info = INTEL_INFO(dev);
63
64 seq_printf(m, "gen: %d\n", info->gen);
65 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
66 #define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
67 B(is_mobile);
68 B(is_i85x);
69 B(is_i915g);
70 B(is_i945gm);
71 B(is_g33);
72 B(need_gfx_hws);
73 B(is_g4x);
74 B(is_pineview);
75 B(is_broadwater);
76 B(is_crestline);
77 B(has_fbc);
78 B(has_pipe_cxsr);
79 B(has_hotplug);
80 B(cursor_needs_physical);
81 B(has_overlay);
82 B(overlay_needs_physical);
83 B(supports_tv);
84 B(has_bsd_ring);
85 B(has_blt_ring);
86 B(has_llc);
87 #undef B
88
89 return 0;
90 }
91
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
93 {
94 if (obj->user_pin_count > 0)
95 return "P";
96 else if (obj->pin_count > 0)
97 return "p";
98 else
99 return " ";
100 }
101
102 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
103 {
104 switch (obj->tiling_mode) {
105 default:
106 case I915_TILING_NONE: return " ";
107 case I915_TILING_X: return "X";
108 case I915_TILING_Y: return "Y";
109 }
110 }
111
112 static const char *cache_level_str(int type)
113 {
114 switch (type) {
115 case I915_CACHE_NONE: return " uncached";
116 case I915_CACHE_LLC: return " snooped (LLC)";
117 case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
118 default: return "";
119 }
120 }
121
122 static void
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124 {
125 seq_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
126 &obj->base,
127 get_pin_flag(obj),
128 get_tiling_flag(obj),
129 obj->base.size / 1024,
130 obj->base.read_domains,
131 obj->base.write_domain,
132 obj->last_rendering_seqno,
133 obj->last_fenced_seqno,
134 cache_level_str(obj->cache_level),
135 obj->dirty ? " dirty" : "",
136 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
137 if (obj->base.name)
138 seq_printf(m, " (name: %d)", obj->base.name);
139 if (obj->fence_reg != I915_FENCE_REG_NONE)
140 seq_printf(m, " (fence: %d)", obj->fence_reg);
141 if (obj->gtt_space != NULL)
142 seq_printf(m, " (gtt offset: %08x, size: %08x)",
143 obj->gtt_offset, (unsigned int)obj->gtt_space->size);
144 if (obj->pin_mappable || obj->fault_mappable) {
145 char s[3], *t = s;
146 if (obj->pin_mappable)
147 *t++ = 'p';
148 if (obj->fault_mappable)
149 *t++ = 'f';
150 *t = '\0';
151 seq_printf(m, " (%s mappable)", s);
152 }
153 if (obj->ring != NULL)
154 seq_printf(m, " (%s)", obj->ring->name);
155 }
156
157 static int i915_gem_object_list_info(struct seq_file *m, void *data)
158 {
159 struct drm_info_node *node = (struct drm_info_node *) m->private;
160 uintptr_t list = (uintptr_t) node->info_ent->data;
161 struct list_head *head;
162 struct drm_device *dev = node->minor->dev;
163 drm_i915_private_t *dev_priv = dev->dev_private;
164 struct drm_i915_gem_object *obj;
165 size_t total_obj_size, total_gtt_size;
166 int count, ret;
167
168 ret = mutex_lock_interruptible(&dev->struct_mutex);
169 if (ret)
170 return ret;
171
172 switch (list) {
173 case ACTIVE_LIST:
174 seq_printf(m, "Active:\n");
175 head = &dev_priv->mm.active_list;
176 break;
177 case INACTIVE_LIST:
178 seq_printf(m, "Inactive:\n");
179 head = &dev_priv->mm.inactive_list;
180 break;
181 case PINNED_LIST:
182 seq_printf(m, "Pinned:\n");
183 head = &dev_priv->mm.pinned_list;
184 break;
185 case FLUSHING_LIST:
186 seq_printf(m, "Flushing:\n");
187 head = &dev_priv->mm.flushing_list;
188 break;
189 case DEFERRED_FREE_LIST:
190 seq_printf(m, "Deferred free:\n");
191 head = &dev_priv->mm.deferred_free_list;
192 break;
193 default:
194 mutex_unlock(&dev->struct_mutex);
195 return -EINVAL;
196 }
197
198 total_obj_size = total_gtt_size = count = 0;
199 list_for_each_entry(obj, head, mm_list) {
200 seq_printf(m, " ");
201 describe_obj(m, obj);
202 seq_printf(m, "\n");
203 total_obj_size += obj->base.size;
204 total_gtt_size += obj->gtt_space->size;
205 count++;
206 }
207 mutex_unlock(&dev->struct_mutex);
208
209 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
210 count, total_obj_size, total_gtt_size);
211 return 0;
212 }
213
214 #define count_objects(list, member) do { \
215 list_for_each_entry(obj, list, member) { \
216 size += obj->gtt_space->size; \
217 ++count; \
218 if (obj->map_and_fenceable) { \
219 mappable_size += obj->gtt_space->size; \
220 ++mappable_count; \
221 } \
222 } \
223 } while (0)
224
225 static int i915_gem_object_info(struct seq_file *m, void* data)
226 {
227 struct drm_info_node *node = (struct drm_info_node *) m->private;
228 struct drm_device *dev = node->minor->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 u32 count, mappable_count;
231 size_t size, mappable_size;
232 struct drm_i915_gem_object *obj;
233 int ret;
234
235 ret = mutex_lock_interruptible(&dev->struct_mutex);
236 if (ret)
237 return ret;
238
239 seq_printf(m, "%u objects, %zu bytes\n",
240 dev_priv->mm.object_count,
241 dev_priv->mm.object_memory);
242
243 size = count = mappable_size = mappable_count = 0;
244 count_objects(&dev_priv->mm.gtt_list, gtt_list);
245 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
246 count, mappable_count, size, mappable_size);
247
248 size = count = mappable_size = mappable_count = 0;
249 count_objects(&dev_priv->mm.active_list, mm_list);
250 count_objects(&dev_priv->mm.flushing_list, mm_list);
251 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
252 count, mappable_count, size, mappable_size);
253
254 size = count = mappable_size = mappable_count = 0;
255 count_objects(&dev_priv->mm.pinned_list, mm_list);
256 seq_printf(m, " %u [%u] pinned objects, %zu [%zu] bytes\n",
257 count, mappable_count, size, mappable_size);
258
259 size = count = mappable_size = mappable_count = 0;
260 count_objects(&dev_priv->mm.inactive_list, mm_list);
261 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
262 count, mappable_count, size, mappable_size);
263
264 size = count = mappable_size = mappable_count = 0;
265 count_objects(&dev_priv->mm.deferred_free_list, mm_list);
266 seq_printf(m, " %u [%u] freed objects, %zu [%zu] bytes\n",
267 count, mappable_count, size, mappable_size);
268
269 size = count = mappable_size = mappable_count = 0;
270 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
271 if (obj->fault_mappable) {
272 size += obj->gtt_space->size;
273 ++count;
274 }
275 if (obj->pin_mappable) {
276 mappable_size += obj->gtt_space->size;
277 ++mappable_count;
278 }
279 }
280 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
281 mappable_count, mappable_size);
282 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
283 count, size);
284
285 seq_printf(m, "%zu [%zu] gtt total\n",
286 dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
287
288 mutex_unlock(&dev->struct_mutex);
289
290 return 0;
291 }
292
293 static int i915_gem_gtt_info(struct seq_file *m, void* data)
294 {
295 struct drm_info_node *node = (struct drm_info_node *) m->private;
296 struct drm_device *dev = node->minor->dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 struct drm_i915_gem_object *obj;
299 size_t total_obj_size, total_gtt_size;
300 int count, ret;
301
302 ret = mutex_lock_interruptible(&dev->struct_mutex);
303 if (ret)
304 return ret;
305
306 total_obj_size = total_gtt_size = count = 0;
307 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
308 seq_printf(m, " ");
309 describe_obj(m, obj);
310 seq_printf(m, "\n");
311 total_obj_size += obj->base.size;
312 total_gtt_size += obj->gtt_space->size;
313 count++;
314 }
315
316 mutex_unlock(&dev->struct_mutex);
317
318 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
319 count, total_obj_size, total_gtt_size);
320
321 return 0;
322 }
323
324
325 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
326 {
327 struct drm_info_node *node = (struct drm_info_node *) m->private;
328 struct drm_device *dev = node->minor->dev;
329 unsigned long flags;
330 struct intel_crtc *crtc;
331
332 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
333 const char pipe = pipe_name(crtc->pipe);
334 const char plane = plane_name(crtc->plane);
335 struct intel_unpin_work *work;
336
337 spin_lock_irqsave(&dev->event_lock, flags);
338 work = crtc->unpin_work;
339 if (work == NULL) {
340 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
341 pipe, plane);
342 } else {
343 if (!work->pending) {
344 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
345 pipe, plane);
346 } else {
347 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
348 pipe, plane);
349 }
350 if (work->enable_stall_check)
351 seq_printf(m, "Stall check enabled, ");
352 else
353 seq_printf(m, "Stall check waiting for page flip ioctl, ");
354 seq_printf(m, "%d prepares\n", work->pending);
355
356 if (work->old_fb_obj) {
357 struct drm_i915_gem_object *obj = work->old_fb_obj;
358 if (obj)
359 seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
360 }
361 if (work->pending_flip_obj) {
362 struct drm_i915_gem_object *obj = work->pending_flip_obj;
363 if (obj)
364 seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
365 }
366 }
367 spin_unlock_irqrestore(&dev->event_lock, flags);
368 }
369
370 return 0;
371 }
372
373 static int i915_gem_request_info(struct seq_file *m, void *data)
374 {
375 struct drm_info_node *node = (struct drm_info_node *) m->private;
376 struct drm_device *dev = node->minor->dev;
377 drm_i915_private_t *dev_priv = dev->dev_private;
378 struct drm_i915_gem_request *gem_request;
379 int ret, count;
380
381 ret = mutex_lock_interruptible(&dev->struct_mutex);
382 if (ret)
383 return ret;
384
385 count = 0;
386 if (!list_empty(&dev_priv->ring[RCS].request_list)) {
387 seq_printf(m, "Render requests:\n");
388 list_for_each_entry(gem_request,
389 &dev_priv->ring[RCS].request_list,
390 list) {
391 seq_printf(m, " %d @ %d\n",
392 gem_request->seqno,
393 (int) (jiffies - gem_request->emitted_jiffies));
394 }
395 count++;
396 }
397 if (!list_empty(&dev_priv->ring[VCS].request_list)) {
398 seq_printf(m, "BSD requests:\n");
399 list_for_each_entry(gem_request,
400 &dev_priv->ring[VCS].request_list,
401 list) {
402 seq_printf(m, " %d @ %d\n",
403 gem_request->seqno,
404 (int) (jiffies - gem_request->emitted_jiffies));
405 }
406 count++;
407 }
408 if (!list_empty(&dev_priv->ring[BCS].request_list)) {
409 seq_printf(m, "BLT requests:\n");
410 list_for_each_entry(gem_request,
411 &dev_priv->ring[BCS].request_list,
412 list) {
413 seq_printf(m, " %d @ %d\n",
414 gem_request->seqno,
415 (int) (jiffies - gem_request->emitted_jiffies));
416 }
417 count++;
418 }
419 mutex_unlock(&dev->struct_mutex);
420
421 if (count == 0)
422 seq_printf(m, "No requests\n");
423
424 return 0;
425 }
426
427 static void i915_ring_seqno_info(struct seq_file *m,
428 struct intel_ring_buffer *ring)
429 {
430 if (ring->get_seqno) {
431 seq_printf(m, "Current sequence (%s): %d\n",
432 ring->name, ring->get_seqno(ring));
433 seq_printf(m, "Waiter sequence (%s): %d\n",
434 ring->name, ring->waiting_seqno);
435 seq_printf(m, "IRQ sequence (%s): %d\n",
436 ring->name, ring->irq_seqno);
437 }
438 }
439
440 static int i915_gem_seqno_info(struct seq_file *m, void *data)
441 {
442 struct drm_info_node *node = (struct drm_info_node *) m->private;
443 struct drm_device *dev = node->minor->dev;
444 drm_i915_private_t *dev_priv = dev->dev_private;
445 int ret, i;
446
447 ret = mutex_lock_interruptible(&dev->struct_mutex);
448 if (ret)
449 return ret;
450
451 for (i = 0; i < I915_NUM_RINGS; i++)
452 i915_ring_seqno_info(m, &dev_priv->ring[i]);
453
454 mutex_unlock(&dev->struct_mutex);
455
456 return 0;
457 }
458
459
460 static int i915_interrupt_info(struct seq_file *m, void *data)
461 {
462 struct drm_info_node *node = (struct drm_info_node *) m->private;
463 struct drm_device *dev = node->minor->dev;
464 drm_i915_private_t *dev_priv = dev->dev_private;
465 int ret, i, pipe;
466
467 ret = mutex_lock_interruptible(&dev->struct_mutex);
468 if (ret)
469 return ret;
470
471 if (!HAS_PCH_SPLIT(dev)) {
472 seq_printf(m, "Interrupt enable: %08x\n",
473 I915_READ(IER));
474 seq_printf(m, "Interrupt identity: %08x\n",
475 I915_READ(IIR));
476 seq_printf(m, "Interrupt mask: %08x\n",
477 I915_READ(IMR));
478 for_each_pipe(pipe)
479 seq_printf(m, "Pipe %c stat: %08x\n",
480 pipe_name(pipe),
481 I915_READ(PIPESTAT(pipe)));
482 } else {
483 seq_printf(m, "North Display Interrupt enable: %08x\n",
484 I915_READ(DEIER));
485 seq_printf(m, "North Display Interrupt identity: %08x\n",
486 I915_READ(DEIIR));
487 seq_printf(m, "North Display Interrupt mask: %08x\n",
488 I915_READ(DEIMR));
489 seq_printf(m, "South Display Interrupt enable: %08x\n",
490 I915_READ(SDEIER));
491 seq_printf(m, "South Display Interrupt identity: %08x\n",
492 I915_READ(SDEIIR));
493 seq_printf(m, "South Display Interrupt mask: %08x\n",
494 I915_READ(SDEIMR));
495 seq_printf(m, "Graphics Interrupt enable: %08x\n",
496 I915_READ(GTIER));
497 seq_printf(m, "Graphics Interrupt identity: %08x\n",
498 I915_READ(GTIIR));
499 seq_printf(m, "Graphics Interrupt mask: %08x\n",
500 I915_READ(GTIMR));
501 }
502 seq_printf(m, "Interrupts received: %d\n",
503 atomic_read(&dev_priv->irq_received));
504 for (i = 0; i < I915_NUM_RINGS; i++) {
505 if (IS_GEN6(dev) || IS_GEN7(dev)) {
506 seq_printf(m, "Graphics Interrupt mask (%s): %08x\n",
507 dev_priv->ring[i].name,
508 I915_READ_IMR(&dev_priv->ring[i]));
509 }
510 i915_ring_seqno_info(m, &dev_priv->ring[i]);
511 }
512 mutex_unlock(&dev->struct_mutex);
513
514 return 0;
515 }
516
517 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
518 {
519 struct drm_info_node *node = (struct drm_info_node *) m->private;
520 struct drm_device *dev = node->minor->dev;
521 drm_i915_private_t *dev_priv = dev->dev_private;
522 int i, ret;
523
524 ret = mutex_lock_interruptible(&dev->struct_mutex);
525 if (ret)
526 return ret;
527
528 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
529 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
530 for (i = 0; i < dev_priv->num_fence_regs; i++) {
531 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
532
533 seq_printf(m, "Fenced object[%2d] = ", i);
534 if (obj == NULL)
535 seq_printf(m, "unused");
536 else
537 describe_obj(m, obj);
538 seq_printf(m, "\n");
539 }
540
541 mutex_unlock(&dev->struct_mutex);
542 return 0;
543 }
544
545 static int i915_hws_info(struct seq_file *m, void *data)
546 {
547 struct drm_info_node *node = (struct drm_info_node *) m->private;
548 struct drm_device *dev = node->minor->dev;
549 drm_i915_private_t *dev_priv = dev->dev_private;
550 struct intel_ring_buffer *ring;
551 const volatile u32 __iomem *hws;
552 int i;
553
554 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
555 hws = (volatile u32 __iomem *)ring->status_page.page_addr;
556 if (hws == NULL)
557 return 0;
558
559 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
560 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
561 i * 4,
562 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
563 }
564 return 0;
565 }
566
567 static int i915_ringbuffer_data(struct seq_file *m, void *data)
568 {
569 struct drm_info_node *node = (struct drm_info_node *) m->private;
570 struct drm_device *dev = node->minor->dev;
571 drm_i915_private_t *dev_priv = dev->dev_private;
572 struct intel_ring_buffer *ring;
573 int ret;
574
575 ret = mutex_lock_interruptible(&dev->struct_mutex);
576 if (ret)
577 return ret;
578
579 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
580 if (!ring->obj) {
581 seq_printf(m, "No ringbuffer setup\n");
582 } else {
583 const u8 __iomem *virt = ring->virtual_start;
584 uint32_t off;
585
586 for (off = 0; off < ring->size; off += 4) {
587 uint32_t *ptr = (uint32_t *)(virt + off);
588 seq_printf(m, "%08x : %08x\n", off, *ptr);
589 }
590 }
591 mutex_unlock(&dev->struct_mutex);
592
593 return 0;
594 }
595
596 static int i915_ringbuffer_info(struct seq_file *m, void *data)
597 {
598 struct drm_info_node *node = (struct drm_info_node *) m->private;
599 struct drm_device *dev = node->minor->dev;
600 drm_i915_private_t *dev_priv = dev->dev_private;
601 struct intel_ring_buffer *ring;
602 int ret;
603
604 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
605 if (ring->size == 0)
606 return 0;
607
608 ret = mutex_lock_interruptible(&dev->struct_mutex);
609 if (ret)
610 return ret;
611
612 seq_printf(m, "Ring %s:\n", ring->name);
613 seq_printf(m, " Head : %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
614 seq_printf(m, " Tail : %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
615 seq_printf(m, " Size : %08x\n", ring->size);
616 seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring));
617 seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring));
618 if (IS_GEN6(dev) || IS_GEN7(dev)) {
619 seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring));
620 seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring));
621 }
622 seq_printf(m, " Control : %08x\n", I915_READ_CTL(ring));
623 seq_printf(m, " Start : %08x\n", I915_READ_START(ring));
624
625 mutex_unlock(&dev->struct_mutex);
626
627 return 0;
628 }
629
630 static const char *ring_str(int ring)
631 {
632 switch (ring) {
633 case RCS: return "render";
634 case VCS: return "bsd";
635 case BCS: return "blt";
636 default: return "";
637 }
638 }
639
640 static const char *pin_flag(int pinned)
641 {
642 if (pinned > 0)
643 return " P";
644 else if (pinned < 0)
645 return " p";
646 else
647 return "";
648 }
649
650 static const char *tiling_flag(int tiling)
651 {
652 switch (tiling) {
653 default:
654 case I915_TILING_NONE: return "";
655 case I915_TILING_X: return " X";
656 case I915_TILING_Y: return " Y";
657 }
658 }
659
660 static const char *dirty_flag(int dirty)
661 {
662 return dirty ? " dirty" : "";
663 }
664
665 static const char *purgeable_flag(int purgeable)
666 {
667 return purgeable ? " purgeable" : "";
668 }
669
670 static void print_error_buffers(struct seq_file *m,
671 const char *name,
672 struct drm_i915_error_buffer *err,
673 int count)
674 {
675 seq_printf(m, "%s [%d]:\n", name, count);
676
677 while (count--) {
678 seq_printf(m, " %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
679 err->gtt_offset,
680 err->size,
681 err->read_domains,
682 err->write_domain,
683 err->seqno,
684 pin_flag(err->pinned),
685 tiling_flag(err->tiling),
686 dirty_flag(err->dirty),
687 purgeable_flag(err->purgeable),
688 err->ring != -1 ? " " : "",
689 ring_str(err->ring),
690 cache_level_str(err->cache_level));
691
692 if (err->name)
693 seq_printf(m, " (name: %d)", err->name);
694 if (err->fence_reg != I915_FENCE_REG_NONE)
695 seq_printf(m, " (fence: %d)", err->fence_reg);
696
697 seq_printf(m, "\n");
698 err++;
699 }
700 }
701
702 static void i915_ring_error_state(struct seq_file *m,
703 struct drm_device *dev,
704 struct drm_i915_error_state *error,
705 unsigned ring)
706 {
707 seq_printf(m, "%s command stream:\n", ring_str(ring));
708 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
709 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
710 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
711 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
712 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
713 seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone[ring]);
714 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
715 seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
716 seq_printf(m, " BBADDR: 0x%08llx\n", error->bbaddr);
717 }
718 if (INTEL_INFO(dev)->gen >= 4)
719 seq_printf(m, " INSTPS: 0x%08x\n", error->instps[ring]);
720 seq_printf(m, " INSTPM: 0x%08x\n", error->instpm[ring]);
721 if (INTEL_INFO(dev)->gen >= 6) {
722 seq_printf(m, " FADDR: 0x%08x\n", error->faddr[ring]);
723 seq_printf(m, " FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
724 seq_printf(m, " SYNC_0: 0x%08x\n",
725 error->semaphore_mboxes[ring][0]);
726 seq_printf(m, " SYNC_1: 0x%08x\n",
727 error->semaphore_mboxes[ring][1]);
728 }
729 seq_printf(m, " seqno: 0x%08x\n", error->seqno[ring]);
730 seq_printf(m, " ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
731 seq_printf(m, " ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
732 }
733
734 static int i915_error_state(struct seq_file *m, void *unused)
735 {
736 struct drm_info_node *node = (struct drm_info_node *) m->private;
737 struct drm_device *dev = node->minor->dev;
738 drm_i915_private_t *dev_priv = dev->dev_private;
739 struct drm_i915_error_state *error;
740 unsigned long flags;
741 int i, page, offset, elt;
742
743 spin_lock_irqsave(&dev_priv->error_lock, flags);
744 if (!dev_priv->first_error) {
745 seq_printf(m, "no error state collected\n");
746 goto out;
747 }
748
749 error = dev_priv->first_error;
750
751 seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
752 error->time.tv_usec);
753 seq_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
754 seq_printf(m, "EIR: 0x%08x\n", error->eir);
755 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
756
757 for (i = 0; i < dev_priv->num_fence_regs; i++)
758 seq_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
759
760 if (INTEL_INFO(dev)->gen >= 6) {
761 seq_printf(m, "ERROR: 0x%08x\n", error->error);
762 seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
763 }
764
765 i915_ring_error_state(m, dev, error, RCS);
766 if (HAS_BLT(dev))
767 i915_ring_error_state(m, dev, error, BCS);
768 if (HAS_BSD(dev))
769 i915_ring_error_state(m, dev, error, VCS);
770
771 if (error->active_bo)
772 print_error_buffers(m, "Active",
773 error->active_bo,
774 error->active_bo_count);
775
776 if (error->pinned_bo)
777 print_error_buffers(m, "Pinned",
778 error->pinned_bo,
779 error->pinned_bo_count);
780
781 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) {
782 if (error->batchbuffer[i]) {
783 struct drm_i915_error_object *obj = error->batchbuffer[i];
784
785 seq_printf(m, "%s --- gtt_offset = 0x%08x\n",
786 dev_priv->ring[i].name,
787 obj->gtt_offset);
788 offset = 0;
789 for (page = 0; page < obj->page_count; page++) {
790 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
791 seq_printf(m, "%08x : %08x\n", offset, obj->pages[page][elt]);
792 offset += 4;
793 }
794 }
795 }
796 }
797
798 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) {
799 if (error->ringbuffer[i]) {
800 struct drm_i915_error_object *obj = error->ringbuffer[i];
801 seq_printf(m, "%s --- ringbuffer = 0x%08x\n",
802 dev_priv->ring[i].name,
803 obj->gtt_offset);
804 offset = 0;
805 for (page = 0; page < obj->page_count; page++) {
806 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
807 seq_printf(m, "%08x : %08x\n",
808 offset,
809 obj->pages[page][elt]);
810 offset += 4;
811 }
812 }
813 }
814 }
815
816 if (error->overlay)
817 intel_overlay_print_error_state(m, error->overlay);
818
819 if (error->display)
820 intel_display_print_error_state(m, dev, error->display);
821
822 out:
823 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
824
825 return 0;
826 }
827
828 static int i915_rstdby_delays(struct seq_file *m, void *unused)
829 {
830 struct drm_info_node *node = (struct drm_info_node *) m->private;
831 struct drm_device *dev = node->minor->dev;
832 drm_i915_private_t *dev_priv = dev->dev_private;
833 u16 crstanddelay;
834 int ret;
835
836 ret = mutex_lock_interruptible(&dev->struct_mutex);
837 if (ret)
838 return ret;
839
840 crstanddelay = I915_READ16(CRSTANDVID);
841
842 mutex_unlock(&dev->struct_mutex);
843
844 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
845
846 return 0;
847 }
848
849 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
850 {
851 struct drm_info_node *node = (struct drm_info_node *) m->private;
852 struct drm_device *dev = node->minor->dev;
853 drm_i915_private_t *dev_priv = dev->dev_private;
854 int ret;
855
856 if (IS_GEN5(dev)) {
857 u16 rgvswctl = I915_READ16(MEMSWCTL);
858 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
859
860 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
861 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
862 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
863 MEMSTAT_VID_SHIFT);
864 seq_printf(m, "Current P-state: %d\n",
865 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
866 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
867 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
868 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
869 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
870 u32 rpstat;
871 u32 rpupei, rpcurup, rpprevup;
872 u32 rpdownei, rpcurdown, rpprevdown;
873 int max_freq;
874
875 /* RPSTAT1 is in the GT power well */
876 ret = mutex_lock_interruptible(&dev->struct_mutex);
877 if (ret)
878 return ret;
879
880 gen6_gt_force_wake_get(dev_priv);
881
882 rpstat = I915_READ(GEN6_RPSTAT1);
883 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
884 rpcurup = I915_READ(GEN6_RP_CUR_UP);
885 rpprevup = I915_READ(GEN6_RP_PREV_UP);
886 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
887 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
888 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
889
890 gen6_gt_force_wake_put(dev_priv);
891 mutex_unlock(&dev->struct_mutex);
892
893 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
894 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
895 seq_printf(m, "Render p-state ratio: %d\n",
896 (gt_perf_status & 0xff00) >> 8);
897 seq_printf(m, "Render p-state VID: %d\n",
898 gt_perf_status & 0xff);
899 seq_printf(m, "Render p-state limit: %d\n",
900 rp_state_limits & 0xff);
901 seq_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
902 GEN6_CAGF_SHIFT) * 50);
903 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
904 GEN6_CURICONT_MASK);
905 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
906 GEN6_CURBSYTAVG_MASK);
907 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
908 GEN6_CURBSYTAVG_MASK);
909 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
910 GEN6_CURIAVG_MASK);
911 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
912 GEN6_CURBSYTAVG_MASK);
913 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
914 GEN6_CURBSYTAVG_MASK);
915
916 max_freq = (rp_state_cap & 0xff0000) >> 16;
917 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
918 max_freq * 50);
919
920 max_freq = (rp_state_cap & 0xff00) >> 8;
921 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
922 max_freq * 50);
923
924 max_freq = rp_state_cap & 0xff;
925 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
926 max_freq * 50);
927 } else {
928 seq_printf(m, "no P-state info available\n");
929 }
930
931 return 0;
932 }
933
934 static int i915_delayfreq_table(struct seq_file *m, void *unused)
935 {
936 struct drm_info_node *node = (struct drm_info_node *) m->private;
937 struct drm_device *dev = node->minor->dev;
938 drm_i915_private_t *dev_priv = dev->dev_private;
939 u32 delayfreq;
940 int ret, i;
941
942 ret = mutex_lock_interruptible(&dev->struct_mutex);
943 if (ret)
944 return ret;
945
946 for (i = 0; i < 16; i++) {
947 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
948 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
949 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
950 }
951
952 mutex_unlock(&dev->struct_mutex);
953
954 return 0;
955 }
956
957 static inline int MAP_TO_MV(int map)
958 {
959 return 1250 - (map * 25);
960 }
961
962 static int i915_inttoext_table(struct seq_file *m, void *unused)
963 {
964 struct drm_info_node *node = (struct drm_info_node *) m->private;
965 struct drm_device *dev = node->minor->dev;
966 drm_i915_private_t *dev_priv = dev->dev_private;
967 u32 inttoext;
968 int ret, i;
969
970 ret = mutex_lock_interruptible(&dev->struct_mutex);
971 if (ret)
972 return ret;
973
974 for (i = 1; i <= 32; i++) {
975 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
976 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
977 }
978
979 mutex_unlock(&dev->struct_mutex);
980
981 return 0;
982 }
983
984 static int ironlake_drpc_info(struct seq_file *m)
985 {
986 struct drm_info_node *node = (struct drm_info_node *) m->private;
987 struct drm_device *dev = node->minor->dev;
988 drm_i915_private_t *dev_priv = dev->dev_private;
989 u32 rgvmodectl, rstdbyctl;
990 u16 crstandvid;
991 int ret;
992
993 ret = mutex_lock_interruptible(&dev->struct_mutex);
994 if (ret)
995 return ret;
996
997 rgvmodectl = I915_READ(MEMMODECTL);
998 rstdbyctl = I915_READ(RSTDBYCTL);
999 crstandvid = I915_READ16(CRSTANDVID);
1000
1001 mutex_unlock(&dev->struct_mutex);
1002
1003 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1004 "yes" : "no");
1005 seq_printf(m, "Boost freq: %d\n",
1006 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1007 MEMMODE_BOOST_FREQ_SHIFT);
1008 seq_printf(m, "HW control enabled: %s\n",
1009 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1010 seq_printf(m, "SW control enabled: %s\n",
1011 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1012 seq_printf(m, "Gated voltage change: %s\n",
1013 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1014 seq_printf(m, "Starting frequency: P%d\n",
1015 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1016 seq_printf(m, "Max P-state: P%d\n",
1017 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1018 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1019 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1020 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1021 seq_printf(m, "Render standby enabled: %s\n",
1022 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1023 seq_printf(m, "Current RS state: ");
1024 switch (rstdbyctl & RSX_STATUS_MASK) {
1025 case RSX_STATUS_ON:
1026 seq_printf(m, "on\n");
1027 break;
1028 case RSX_STATUS_RC1:
1029 seq_printf(m, "RC1\n");
1030 break;
1031 case RSX_STATUS_RC1E:
1032 seq_printf(m, "RC1E\n");
1033 break;
1034 case RSX_STATUS_RS1:
1035 seq_printf(m, "RS1\n");
1036 break;
1037 case RSX_STATUS_RS2:
1038 seq_printf(m, "RS2 (RC6)\n");
1039 break;
1040 case RSX_STATUS_RS3:
1041 seq_printf(m, "RC3 (RC6+)\n");
1042 break;
1043 default:
1044 seq_printf(m, "unknown\n");
1045 break;
1046 }
1047
1048 return 0;
1049 }
1050
1051 static int gen6_drpc_info(struct seq_file *m)
1052 {
1053
1054 struct drm_info_node *node = (struct drm_info_node *) m->private;
1055 struct drm_device *dev = node->minor->dev;
1056 struct drm_i915_private *dev_priv = dev->dev_private;
1057 u32 rpmodectl1, gt_core_status, rcctl1;
1058 unsigned forcewake_count;
1059 int count=0, ret;
1060
1061
1062 ret = mutex_lock_interruptible(&dev->struct_mutex);
1063 if (ret)
1064 return ret;
1065
1066 spin_lock_irq(&dev_priv->gt_lock);
1067 forcewake_count = dev_priv->forcewake_count;
1068 spin_unlock_irq(&dev_priv->gt_lock);
1069
1070 if (forcewake_count) {
1071 seq_printf(m, "RC information inaccurate because somebody "
1072 "holds a forcewake reference \n");
1073 } else {
1074 /* NB: we cannot use forcewake, else we read the wrong values */
1075 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1076 udelay(10);
1077 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1078 }
1079
1080 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1081 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1082
1083 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1084 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1085 mutex_unlock(&dev->struct_mutex);
1086
1087 seq_printf(m, "Video Turbo Mode: %s\n",
1088 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1089 seq_printf(m, "HW control enabled: %s\n",
1090 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1091 seq_printf(m, "SW control enabled: %s\n",
1092 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1093 GEN6_RP_MEDIA_SW_MODE));
1094 seq_printf(m, "RC1e Enabled: %s\n",
1095 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1096 seq_printf(m, "RC6 Enabled: %s\n",
1097 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1098 seq_printf(m, "Deep RC6 Enabled: %s\n",
1099 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1100 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1101 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1102 seq_printf(m, "Current RC state: ");
1103 switch (gt_core_status & GEN6_RCn_MASK) {
1104 case GEN6_RC0:
1105 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1106 seq_printf(m, "Core Power Down\n");
1107 else
1108 seq_printf(m, "on\n");
1109 break;
1110 case GEN6_RC3:
1111 seq_printf(m, "RC3\n");
1112 break;
1113 case GEN6_RC6:
1114 seq_printf(m, "RC6\n");
1115 break;
1116 case GEN6_RC7:
1117 seq_printf(m, "RC7\n");
1118 break;
1119 default:
1120 seq_printf(m, "Unknown\n");
1121 break;
1122 }
1123
1124 seq_printf(m, "Core Power Down: %s\n",
1125 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1126 return 0;
1127 }
1128
1129 static int i915_drpc_info(struct seq_file *m, void *unused)
1130 {
1131 struct drm_info_node *node = (struct drm_info_node *) m->private;
1132 struct drm_device *dev = node->minor->dev;
1133
1134 if (IS_GEN6(dev) || IS_GEN7(dev))
1135 return gen6_drpc_info(m);
1136 else
1137 return ironlake_drpc_info(m);
1138 }
1139
1140 static int i915_fbc_status(struct seq_file *m, void *unused)
1141 {
1142 struct drm_info_node *node = (struct drm_info_node *) m->private;
1143 struct drm_device *dev = node->minor->dev;
1144 drm_i915_private_t *dev_priv = dev->dev_private;
1145
1146 if (!I915_HAS_FBC(dev)) {
1147 seq_printf(m, "FBC unsupported on this chipset\n");
1148 return 0;
1149 }
1150
1151 if (intel_fbc_enabled(dev)) {
1152 seq_printf(m, "FBC enabled\n");
1153 } else {
1154 seq_printf(m, "FBC disabled: ");
1155 switch (dev_priv->no_fbc_reason) {
1156 case FBC_NO_OUTPUT:
1157 seq_printf(m, "no outputs");
1158 break;
1159 case FBC_STOLEN_TOO_SMALL:
1160 seq_printf(m, "not enough stolen memory");
1161 break;
1162 case FBC_UNSUPPORTED_MODE:
1163 seq_printf(m, "mode not supported");
1164 break;
1165 case FBC_MODE_TOO_LARGE:
1166 seq_printf(m, "mode too large");
1167 break;
1168 case FBC_BAD_PLANE:
1169 seq_printf(m, "FBC unsupported on plane");
1170 break;
1171 case FBC_NOT_TILED:
1172 seq_printf(m, "scanout buffer not tiled");
1173 break;
1174 case FBC_MULTIPLE_PIPES:
1175 seq_printf(m, "multiple pipes are enabled");
1176 break;
1177 case FBC_MODULE_PARAM:
1178 seq_printf(m, "disabled per module param (default off)");
1179 break;
1180 default:
1181 seq_printf(m, "unknown reason");
1182 }
1183 seq_printf(m, "\n");
1184 }
1185 return 0;
1186 }
1187
1188 static int i915_sr_status(struct seq_file *m, void *unused)
1189 {
1190 struct drm_info_node *node = (struct drm_info_node *) m->private;
1191 struct drm_device *dev = node->minor->dev;
1192 drm_i915_private_t *dev_priv = dev->dev_private;
1193 bool sr_enabled = false;
1194
1195 if (HAS_PCH_SPLIT(dev))
1196 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1197 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1198 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1199 else if (IS_I915GM(dev))
1200 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1201 else if (IS_PINEVIEW(dev))
1202 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1203
1204 seq_printf(m, "self-refresh: %s\n",
1205 sr_enabled ? "enabled" : "disabled");
1206
1207 return 0;
1208 }
1209
1210 static int i915_emon_status(struct seq_file *m, void *unused)
1211 {
1212 struct drm_info_node *node = (struct drm_info_node *) m->private;
1213 struct drm_device *dev = node->minor->dev;
1214 drm_i915_private_t *dev_priv = dev->dev_private;
1215 unsigned long temp, chipset, gfx;
1216 int ret;
1217
1218 ret = mutex_lock_interruptible(&dev->struct_mutex);
1219 if (ret)
1220 return ret;
1221
1222 temp = i915_mch_val(dev_priv);
1223 chipset = i915_chipset_val(dev_priv);
1224 gfx = i915_gfx_val(dev_priv);
1225 mutex_unlock(&dev->struct_mutex);
1226
1227 seq_printf(m, "GMCH temp: %ld\n", temp);
1228 seq_printf(m, "Chipset power: %ld\n", chipset);
1229 seq_printf(m, "GFX power: %ld\n", gfx);
1230 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1231
1232 return 0;
1233 }
1234
1235 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1236 {
1237 struct drm_info_node *node = (struct drm_info_node *) m->private;
1238 struct drm_device *dev = node->minor->dev;
1239 drm_i915_private_t *dev_priv = dev->dev_private;
1240 int ret;
1241 int gpu_freq, ia_freq;
1242
1243 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1244 seq_printf(m, "unsupported on this chipset\n");
1245 return 0;
1246 }
1247
1248 ret = mutex_lock_interruptible(&dev->struct_mutex);
1249 if (ret)
1250 return ret;
1251
1252 seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1253
1254 for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1255 gpu_freq++) {
1256 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1257 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1258 GEN6_PCODE_READ_MIN_FREQ_TABLE);
1259 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
1260 GEN6_PCODE_READY) == 0, 10)) {
1261 DRM_ERROR("pcode read of freq table timed out\n");
1262 continue;
1263 }
1264 ia_freq = I915_READ(GEN6_PCODE_DATA);
1265 seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1266 }
1267
1268 mutex_unlock(&dev->struct_mutex);
1269
1270 return 0;
1271 }
1272
1273 static int i915_gfxec(struct seq_file *m, void *unused)
1274 {
1275 struct drm_info_node *node = (struct drm_info_node *) m->private;
1276 struct drm_device *dev = node->minor->dev;
1277 drm_i915_private_t *dev_priv = dev->dev_private;
1278 int ret;
1279
1280 ret = mutex_lock_interruptible(&dev->struct_mutex);
1281 if (ret)
1282 return ret;
1283
1284 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1285
1286 mutex_unlock(&dev->struct_mutex);
1287
1288 return 0;
1289 }
1290
1291 static int i915_opregion(struct seq_file *m, void *unused)
1292 {
1293 struct drm_info_node *node = (struct drm_info_node *) m->private;
1294 struct drm_device *dev = node->minor->dev;
1295 drm_i915_private_t *dev_priv = dev->dev_private;
1296 struct intel_opregion *opregion = &dev_priv->opregion;
1297 int ret;
1298
1299 ret = mutex_lock_interruptible(&dev->struct_mutex);
1300 if (ret)
1301 return ret;
1302
1303 if (opregion->header)
1304 seq_write(m, opregion->header, OPREGION_SIZE);
1305
1306 mutex_unlock(&dev->struct_mutex);
1307
1308 return 0;
1309 }
1310
1311 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1312 {
1313 struct drm_info_node *node = (struct drm_info_node *) m->private;
1314 struct drm_device *dev = node->minor->dev;
1315 drm_i915_private_t *dev_priv = dev->dev_private;
1316 struct intel_fbdev *ifbdev;
1317 struct intel_framebuffer *fb;
1318 int ret;
1319
1320 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1321 if (ret)
1322 return ret;
1323
1324 ifbdev = dev_priv->fbdev;
1325 fb = to_intel_framebuffer(ifbdev->helper.fb);
1326
1327 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1328 fb->base.width,
1329 fb->base.height,
1330 fb->base.depth,
1331 fb->base.bits_per_pixel);
1332 describe_obj(m, fb->obj);
1333 seq_printf(m, "\n");
1334
1335 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1336 if (&fb->base == ifbdev->helper.fb)
1337 continue;
1338
1339 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1340 fb->base.width,
1341 fb->base.height,
1342 fb->base.depth,
1343 fb->base.bits_per_pixel);
1344 describe_obj(m, fb->obj);
1345 seq_printf(m, "\n");
1346 }
1347
1348 mutex_unlock(&dev->mode_config.mutex);
1349
1350 return 0;
1351 }
1352
1353 static int i915_context_status(struct seq_file *m, void *unused)
1354 {
1355 struct drm_info_node *node = (struct drm_info_node *) m->private;
1356 struct drm_device *dev = node->minor->dev;
1357 drm_i915_private_t *dev_priv = dev->dev_private;
1358 int ret;
1359
1360 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1361 if (ret)
1362 return ret;
1363
1364 if (dev_priv->pwrctx) {
1365 seq_printf(m, "power context ");
1366 describe_obj(m, dev_priv->pwrctx);
1367 seq_printf(m, "\n");
1368 }
1369
1370 if (dev_priv->renderctx) {
1371 seq_printf(m, "render context ");
1372 describe_obj(m, dev_priv->renderctx);
1373 seq_printf(m, "\n");
1374 }
1375
1376 mutex_unlock(&dev->mode_config.mutex);
1377
1378 return 0;
1379 }
1380
1381 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1382 {
1383 struct drm_info_node *node = (struct drm_info_node *) m->private;
1384 struct drm_device *dev = node->minor->dev;
1385 struct drm_i915_private *dev_priv = dev->dev_private;
1386 unsigned forcewake_count;
1387
1388 spin_lock_irq(&dev_priv->gt_lock);
1389 forcewake_count = dev_priv->forcewake_count;
1390 spin_unlock_irq(&dev_priv->gt_lock);
1391
1392 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1393
1394 return 0;
1395 }
1396
1397 static const char *swizzle_string(unsigned swizzle)
1398 {
1399 switch(swizzle) {
1400 case I915_BIT_6_SWIZZLE_NONE:
1401 return "none";
1402 case I915_BIT_6_SWIZZLE_9:
1403 return "bit9";
1404 case I915_BIT_6_SWIZZLE_9_10:
1405 return "bit9/bit10";
1406 case I915_BIT_6_SWIZZLE_9_11:
1407 return "bit9/bit11";
1408 case I915_BIT_6_SWIZZLE_9_10_11:
1409 return "bit9/bit10/bit11";
1410 case I915_BIT_6_SWIZZLE_9_17:
1411 return "bit9/bit17";
1412 case I915_BIT_6_SWIZZLE_9_10_17:
1413 return "bit9/bit10/bit17";
1414 case I915_BIT_6_SWIZZLE_UNKNOWN:
1415 return "unkown";
1416 }
1417
1418 return "bug";
1419 }
1420
1421 static int i915_swizzle_info(struct seq_file *m, void *data)
1422 {
1423 struct drm_info_node *node = (struct drm_info_node *) m->private;
1424 struct drm_device *dev = node->minor->dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426
1427 mutex_lock(&dev->struct_mutex);
1428 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1429 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1430 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1431 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1432
1433 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1434 seq_printf(m, "DDC = 0x%08x\n",
1435 I915_READ(DCC));
1436 seq_printf(m, "C0DRB3 = 0x%04x\n",
1437 I915_READ16(C0DRB3));
1438 seq_printf(m, "C1DRB3 = 0x%04x\n",
1439 I915_READ16(C1DRB3));
1440 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1441 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1442 I915_READ(MAD_DIMM_C0));
1443 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1444 I915_READ(MAD_DIMM_C1));
1445 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1446 I915_READ(MAD_DIMM_C2));
1447 seq_printf(m, "TILECTL = 0x%08x\n",
1448 I915_READ(TILECTL));
1449 seq_printf(m, "ARB_MODE = 0x%08x\n",
1450 I915_READ(ARB_MODE));
1451 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1452 I915_READ(DISP_ARB_CTL));
1453 }
1454 mutex_unlock(&dev->struct_mutex);
1455
1456 return 0;
1457 }
1458
1459 static int i915_ppgtt_info(struct seq_file *m, void *data)
1460 {
1461 struct drm_info_node *node = (struct drm_info_node *) m->private;
1462 struct drm_device *dev = node->minor->dev;
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464 struct intel_ring_buffer *ring;
1465 int i, ret;
1466
1467
1468 ret = mutex_lock_interruptible(&dev->struct_mutex);
1469 if (ret)
1470 return ret;
1471 if (INTEL_INFO(dev)->gen == 6)
1472 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1473
1474 for (i = 0; i < I915_NUM_RINGS; i++) {
1475 ring = &dev_priv->ring[i];
1476
1477 seq_printf(m, "%s\n", ring->name);
1478 if (INTEL_INFO(dev)->gen == 7)
1479 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1480 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1481 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1482 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1483 }
1484 if (dev_priv->mm.aliasing_ppgtt) {
1485 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1486
1487 seq_printf(m, "aliasing PPGTT:\n");
1488 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1489 }
1490 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1491 mutex_unlock(&dev->struct_mutex);
1492
1493 return 0;
1494 }
1495
1496 static int
1497 i915_debugfs_common_open(struct inode *inode,
1498 struct file *filp)
1499 {
1500 filp->private_data = inode->i_private;
1501 return 0;
1502 }
1503
1504 static ssize_t
1505 i915_wedged_read(struct file *filp,
1506 char __user *ubuf,
1507 size_t max,
1508 loff_t *ppos)
1509 {
1510 struct drm_device *dev = filp->private_data;
1511 drm_i915_private_t *dev_priv = dev->dev_private;
1512 char buf[80];
1513 int len;
1514
1515 len = snprintf(buf, sizeof(buf),
1516 "wedged : %d\n",
1517 atomic_read(&dev_priv->mm.wedged));
1518
1519 if (len > sizeof(buf))
1520 len = sizeof(buf);
1521
1522 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1523 }
1524
1525 static ssize_t
1526 i915_wedged_write(struct file *filp,
1527 const char __user *ubuf,
1528 size_t cnt,
1529 loff_t *ppos)
1530 {
1531 struct drm_device *dev = filp->private_data;
1532 char buf[20];
1533 int val = 1;
1534
1535 if (cnt > 0) {
1536 if (cnt > sizeof(buf) - 1)
1537 return -EINVAL;
1538
1539 if (copy_from_user(buf, ubuf, cnt))
1540 return -EFAULT;
1541 buf[cnt] = 0;
1542
1543 val = simple_strtoul(buf, NULL, 0);
1544 }
1545
1546 DRM_INFO("Manually setting wedged to %d\n", val);
1547 i915_handle_error(dev, val);
1548
1549 return cnt;
1550 }
1551
1552 static const struct file_operations i915_wedged_fops = {
1553 .owner = THIS_MODULE,
1554 .open = i915_debugfs_common_open,
1555 .read = i915_wedged_read,
1556 .write = i915_wedged_write,
1557 .llseek = default_llseek,
1558 };
1559
1560 static ssize_t
1561 i915_max_freq_read(struct file *filp,
1562 char __user *ubuf,
1563 size_t max,
1564 loff_t *ppos)
1565 {
1566 struct drm_device *dev = filp->private_data;
1567 drm_i915_private_t *dev_priv = dev->dev_private;
1568 char buf[80];
1569 int len;
1570
1571 len = snprintf(buf, sizeof(buf),
1572 "max freq: %d\n", dev_priv->max_delay * 50);
1573
1574 if (len > sizeof(buf))
1575 len = sizeof(buf);
1576
1577 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1578 }
1579
1580 static ssize_t
1581 i915_max_freq_write(struct file *filp,
1582 const char __user *ubuf,
1583 size_t cnt,
1584 loff_t *ppos)
1585 {
1586 struct drm_device *dev = filp->private_data;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 char buf[20];
1589 int val = 1;
1590
1591 if (cnt > 0) {
1592 if (cnt > sizeof(buf) - 1)
1593 return -EINVAL;
1594
1595 if (copy_from_user(buf, ubuf, cnt))
1596 return -EFAULT;
1597 buf[cnt] = 0;
1598
1599 val = simple_strtoul(buf, NULL, 0);
1600 }
1601
1602 DRM_DEBUG_DRIVER("Manually setting max freq to %d\n", val);
1603
1604 /*
1605 * Turbo will still be enabled, but won't go above the set value.
1606 */
1607 dev_priv->max_delay = val / 50;
1608
1609 gen6_set_rps(dev, val / 50);
1610
1611 return cnt;
1612 }
1613
1614 static const struct file_operations i915_max_freq_fops = {
1615 .owner = THIS_MODULE,
1616 .open = i915_debugfs_common_open,
1617 .read = i915_max_freq_read,
1618 .write = i915_max_freq_write,
1619 .llseek = default_llseek,
1620 };
1621
1622 static ssize_t
1623 i915_cache_sharing_read(struct file *filp,
1624 char __user *ubuf,
1625 size_t max,
1626 loff_t *ppos)
1627 {
1628 struct drm_device *dev = filp->private_data;
1629 drm_i915_private_t *dev_priv = dev->dev_private;
1630 char buf[80];
1631 u32 snpcr;
1632 int len;
1633
1634 mutex_lock(&dev_priv->dev->struct_mutex);
1635 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1636 mutex_unlock(&dev_priv->dev->struct_mutex);
1637
1638 len = snprintf(buf, sizeof(buf),
1639 "%d\n", (snpcr & GEN6_MBC_SNPCR_MASK) >>
1640 GEN6_MBC_SNPCR_SHIFT);
1641
1642 if (len > sizeof(buf))
1643 len = sizeof(buf);
1644
1645 return simple_read_from_buffer(ubuf, max, ppos, buf, len);
1646 }
1647
1648 static ssize_t
1649 i915_cache_sharing_write(struct file *filp,
1650 const char __user *ubuf,
1651 size_t cnt,
1652 loff_t *ppos)
1653 {
1654 struct drm_device *dev = filp->private_data;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 char buf[20];
1657 u32 snpcr;
1658 int val = 1;
1659
1660 if (cnt > 0) {
1661 if (cnt > sizeof(buf) - 1)
1662 return -EINVAL;
1663
1664 if (copy_from_user(buf, ubuf, cnt))
1665 return -EFAULT;
1666 buf[cnt] = 0;
1667
1668 val = simple_strtoul(buf, NULL, 0);
1669 }
1670
1671 if (val < 0 || val > 3)
1672 return -EINVAL;
1673
1674 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %d\n", val);
1675
1676 /* Update the cache sharing policy here as well */
1677 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1678 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1679 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
1680 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1681
1682 return cnt;
1683 }
1684
1685 static const struct file_operations i915_cache_sharing_fops = {
1686 .owner = THIS_MODULE,
1687 .open = i915_debugfs_common_open,
1688 .read = i915_cache_sharing_read,
1689 .write = i915_cache_sharing_write,
1690 .llseek = default_llseek,
1691 };
1692
1693 /* As the drm_debugfs_init() routines are called before dev->dev_private is
1694 * allocated we need to hook into the minor for release. */
1695 static int
1696 drm_add_fake_info_node(struct drm_minor *minor,
1697 struct dentry *ent,
1698 const void *key)
1699 {
1700 struct drm_info_node *node;
1701
1702 node = kmalloc(sizeof(struct drm_info_node), GFP_KERNEL);
1703 if (node == NULL) {
1704 debugfs_remove(ent);
1705 return -ENOMEM;
1706 }
1707
1708 node->minor = minor;
1709 node->dent = ent;
1710 node->info_ent = (void *) key;
1711
1712 mutex_lock(&minor->debugfs_lock);
1713 list_add(&node->list, &minor->debugfs_list);
1714 mutex_unlock(&minor->debugfs_lock);
1715
1716 return 0;
1717 }
1718
1719 static int i915_forcewake_open(struct inode *inode, struct file *file)
1720 {
1721 struct drm_device *dev = inode->i_private;
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 int ret;
1724
1725 if (INTEL_INFO(dev)->gen < 6)
1726 return 0;
1727
1728 ret = mutex_lock_interruptible(&dev->struct_mutex);
1729 if (ret)
1730 return ret;
1731 gen6_gt_force_wake_get(dev_priv);
1732 mutex_unlock(&dev->struct_mutex);
1733
1734 return 0;
1735 }
1736
1737 int i915_forcewake_release(struct inode *inode, struct file *file)
1738 {
1739 struct drm_device *dev = inode->i_private;
1740 struct drm_i915_private *dev_priv = dev->dev_private;
1741
1742 if (INTEL_INFO(dev)->gen < 6)
1743 return 0;
1744
1745 /*
1746 * It's bad that we can potentially hang userspace if struct_mutex gets
1747 * forever stuck. However, if we cannot acquire this lock it means that
1748 * almost certainly the driver has hung, is not unload-able. Therefore
1749 * hanging here is probably a minor inconvenience not to be seen my
1750 * almost every user.
1751 */
1752 mutex_lock(&dev->struct_mutex);
1753 gen6_gt_force_wake_put(dev_priv);
1754 mutex_unlock(&dev->struct_mutex);
1755
1756 return 0;
1757 }
1758
1759 static const struct file_operations i915_forcewake_fops = {
1760 .owner = THIS_MODULE,
1761 .open = i915_forcewake_open,
1762 .release = i915_forcewake_release,
1763 };
1764
1765 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
1766 {
1767 struct drm_device *dev = minor->dev;
1768 struct dentry *ent;
1769
1770 ent = debugfs_create_file("i915_forcewake_user",
1771 S_IRUSR,
1772 root, dev,
1773 &i915_forcewake_fops);
1774 if (IS_ERR(ent))
1775 return PTR_ERR(ent);
1776
1777 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
1778 }
1779
1780 static int i915_debugfs_create(struct dentry *root,
1781 struct drm_minor *minor,
1782 const char *name,
1783 const struct file_operations *fops)
1784 {
1785 struct drm_device *dev = minor->dev;
1786 struct dentry *ent;
1787
1788 ent = debugfs_create_file(name,
1789 S_IRUGO | S_IWUSR,
1790 root, dev,
1791 fops);
1792 if (IS_ERR(ent))
1793 return PTR_ERR(ent);
1794
1795 return drm_add_fake_info_node(minor, ent, fops);
1796 }
1797
1798 static struct drm_info_list i915_debugfs_list[] = {
1799 {"i915_capabilities", i915_capabilities, 0},
1800 {"i915_gem_objects", i915_gem_object_info, 0},
1801 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1802 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
1803 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
1804 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
1805 {"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
1806 {"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
1807 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1808 {"i915_gem_request", i915_gem_request_info, 0},
1809 {"i915_gem_seqno", i915_gem_seqno_info, 0},
1810 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1811 {"i915_gem_interrupt", i915_interrupt_info, 0},
1812 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1813 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1814 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1815 {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1816 {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1817 {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1818 {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1819 {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1820 {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1821 {"i915_error_state", i915_error_state, 0},
1822 {"i915_rstdby_delays", i915_rstdby_delays, 0},
1823 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1824 {"i915_delayfreq_table", i915_delayfreq_table, 0},
1825 {"i915_inttoext_table", i915_inttoext_table, 0},
1826 {"i915_drpc_info", i915_drpc_info, 0},
1827 {"i915_emon_status", i915_emon_status, 0},
1828 {"i915_ring_freq_table", i915_ring_freq_table, 0},
1829 {"i915_gfxec", i915_gfxec, 0},
1830 {"i915_fbc_status", i915_fbc_status, 0},
1831 {"i915_sr_status", i915_sr_status, 0},
1832 {"i915_opregion", i915_opregion, 0},
1833 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1834 {"i915_context_status", i915_context_status, 0},
1835 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
1836 {"i915_swizzle_info", i915_swizzle_info, 0},
1837 {"i915_ppgtt_info", i915_ppgtt_info, 0},
1838 };
1839 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1840
1841 int i915_debugfs_init(struct drm_minor *minor)
1842 {
1843 int ret;
1844
1845 ret = i915_debugfs_create(minor->debugfs_root, minor,
1846 "i915_wedged",
1847 &i915_wedged_fops);
1848 if (ret)
1849 return ret;
1850
1851 ret = i915_forcewake_create(minor->debugfs_root, minor);
1852 if (ret)
1853 return ret;
1854
1855 ret = i915_debugfs_create(minor->debugfs_root, minor,
1856 "i915_max_freq",
1857 &i915_max_freq_fops);
1858 if (ret)
1859 return ret;
1860
1861 ret = i915_debugfs_create(minor->debugfs_root, minor,
1862 "i915_cache_sharing",
1863 &i915_cache_sharing_fops);
1864 if (ret)
1865 return ret;
1866
1867 return drm_debugfs_create_files(i915_debugfs_list,
1868 I915_DEBUGFS_ENTRIES,
1869 minor->debugfs_root, minor);
1870 }
1871
1872 void i915_debugfs_cleanup(struct drm_minor *minor)
1873 {
1874 drm_debugfs_remove_files(i915_debugfs_list,
1875 I915_DEBUGFS_ENTRIES, minor);
1876 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
1877 1, minor);
1878 drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1879 1, minor);
1880 drm_debugfs_remove_files((struct drm_info_list *) &i915_max_freq_fops,
1881 1, minor);
1882 drm_debugfs_remove_files((struct drm_info_list *) &i915_cache_sharing_fops,
1883 1, minor);
1884 }
1885
1886 #endif /* CONFIG_DEBUG_FS */
Linux kernel - Deliverables
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