2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
43 #if defined(CONFIG_DEBUG_FS)
51 static const char *yesno(int v
)
53 return v
? "yes" : "no";
56 /* As the drm_debugfs_init() routines are called before dev->dev_private is
57 * allocated we need to hook into the minor for release. */
59 drm_add_fake_info_node(struct drm_minor
*minor
,
63 struct drm_info_node
*node
;
65 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
73 node
->info_ent
= (void *) key
;
75 mutex_lock(&minor
->debugfs_lock
);
76 list_add(&node
->list
, &minor
->debugfs_list
);
77 mutex_unlock(&minor
->debugfs_lock
);
82 static int i915_capabilities(struct seq_file
*m
, void *data
)
84 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
85 struct drm_device
*dev
= node
->minor
->dev
;
86 const struct intel_device_info
*info
= INTEL_INFO(dev
);
88 seq_printf(m
, "gen: %d\n", info
->gen
);
89 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
90 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
91 #define SEP_SEMICOLON ;
92 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
99 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
101 if (obj
->user_pin_count
> 0)
103 else if (obj
->pin_count
> 0)
109 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
111 switch (obj
->tiling_mode
) {
113 case I915_TILING_NONE
: return " ";
114 case I915_TILING_X
: return "X";
115 case I915_TILING_Y
: return "Y";
119 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
121 return obj
->has_global_gtt_mapping
? "g" : " ";
125 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
127 struct i915_vma
*vma
;
128 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj
),
132 get_global_flag(obj
),
133 obj
->base
.size
/ 1024,
134 obj
->base
.read_domains
,
135 obj
->base
.write_domain
,
136 obj
->last_read_seqno
,
137 obj
->last_write_seqno
,
138 obj
->last_fenced_seqno
,
139 i915_cache_level_str(obj
->cache_level
),
140 obj
->dirty
? " dirty" : "",
141 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
143 seq_printf(m
, " (name: %d)", obj
->base
.name
);
145 seq_printf(m
, " (pinned x %d)", obj
->pin_count
);
146 if (obj
->pin_display
)
147 seq_printf(m
, " (display)");
148 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
149 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
150 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
151 if (!i915_is_ggtt(vma
->vm
))
155 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
156 vma
->node
.start
, vma
->node
.size
);
159 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
160 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
162 if (obj
->pin_mappable
)
164 if (obj
->fault_mappable
)
167 seq_printf(m
, " (%s mappable)", s
);
169 if (obj
->ring
!= NULL
)
170 seq_printf(m
, " (%s)", obj
->ring
->name
);
173 static void describe_ctx(struct seq_file
*m
, struct i915_hw_context
*ctx
)
175 seq_putc(m
, ctx
->is_initialized
? 'I' : 'i');
176 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
180 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
182 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
183 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
184 struct list_head
*head
;
185 struct drm_device
*dev
= node
->minor
->dev
;
186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
187 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
188 struct i915_vma
*vma
;
189 size_t total_obj_size
, total_gtt_size
;
192 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
196 /* FIXME: the user of this interface might want more than just GGTT */
199 seq_puts(m
, "Active:\n");
200 head
= &vm
->active_list
;
203 seq_puts(m
, "Inactive:\n");
204 head
= &vm
->inactive_list
;
207 mutex_unlock(&dev
->struct_mutex
);
211 total_obj_size
= total_gtt_size
= count
= 0;
212 list_for_each_entry(vma
, head
, mm_list
) {
214 describe_obj(m
, vma
->obj
);
216 total_obj_size
+= vma
->obj
->base
.size
;
217 total_gtt_size
+= vma
->node
.size
;
220 mutex_unlock(&dev
->struct_mutex
);
222 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
223 count
, total_obj_size
, total_gtt_size
);
227 static int obj_rank_by_stolen(void *priv
,
228 struct list_head
*A
, struct list_head
*B
)
230 struct drm_i915_gem_object
*a
=
231 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
232 struct drm_i915_gem_object
*b
=
233 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
235 return a
->stolen
->start
- b
->stolen
->start
;
238 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
240 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
241 struct drm_device
*dev
= node
->minor
->dev
;
242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
243 struct drm_i915_gem_object
*obj
;
244 size_t total_obj_size
, total_gtt_size
;
248 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
252 total_obj_size
= total_gtt_size
= count
= 0;
253 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
254 if (obj
->stolen
== NULL
)
257 list_add(&obj
->obj_exec_link
, &stolen
);
259 total_obj_size
+= obj
->base
.size
;
260 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
263 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
264 if (obj
->stolen
== NULL
)
267 list_add(&obj
->obj_exec_link
, &stolen
);
269 total_obj_size
+= obj
->base
.size
;
272 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
273 seq_puts(m
, "Stolen:\n");
274 while (!list_empty(&stolen
)) {
275 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
277 describe_obj(m
, obj
);
279 list_del_init(&obj
->obj_exec_link
);
281 mutex_unlock(&dev
->struct_mutex
);
283 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
284 count
, total_obj_size
, total_gtt_size
);
288 #define count_objects(list, member) do { \
289 list_for_each_entry(obj, list, member) { \
290 size += i915_gem_obj_ggtt_size(obj); \
292 if (obj->map_and_fenceable) { \
293 mappable_size += i915_gem_obj_ggtt_size(obj); \
301 size_t total
, active
, inactive
, unbound
;
304 static int per_file_stats(int id
, void *ptr
, void *data
)
306 struct drm_i915_gem_object
*obj
= ptr
;
307 struct file_stats
*stats
= data
;
310 stats
->total
+= obj
->base
.size
;
312 if (i915_gem_obj_ggtt_bound(obj
)) {
313 if (!list_empty(&obj
->ring_list
))
314 stats
->active
+= obj
->base
.size
;
316 stats
->inactive
+= obj
->base
.size
;
318 if (!list_empty(&obj
->global_list
))
319 stats
->unbound
+= obj
->base
.size
;
325 #define count_vmas(list, member) do { \
326 list_for_each_entry(vma, list, member) { \
327 size += i915_gem_obj_ggtt_size(vma->obj); \
329 if (vma->obj->map_and_fenceable) { \
330 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
336 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
338 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
339 struct drm_device
*dev
= node
->minor
->dev
;
340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
341 u32 count
, mappable_count
, purgeable_count
;
342 size_t size
, mappable_size
, purgeable_size
;
343 struct drm_i915_gem_object
*obj
;
344 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
345 struct drm_file
*file
;
346 struct i915_vma
*vma
;
349 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
353 seq_printf(m
, "%u objects, %zu bytes\n",
354 dev_priv
->mm
.object_count
,
355 dev_priv
->mm
.object_memory
);
357 size
= count
= mappable_size
= mappable_count
= 0;
358 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
359 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
360 count
, mappable_count
, size
, mappable_size
);
362 size
= count
= mappable_size
= mappable_count
= 0;
363 count_vmas(&vm
->active_list
, mm_list
);
364 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
365 count
, mappable_count
, size
, mappable_size
);
367 size
= count
= mappable_size
= mappable_count
= 0;
368 count_vmas(&vm
->inactive_list
, mm_list
);
369 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
370 count
, mappable_count
, size
, mappable_size
);
372 size
= count
= purgeable_size
= purgeable_count
= 0;
373 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
374 size
+= obj
->base
.size
, ++count
;
375 if (obj
->madv
== I915_MADV_DONTNEED
)
376 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
378 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
380 size
= count
= mappable_size
= mappable_count
= 0;
381 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
382 if (obj
->fault_mappable
) {
383 size
+= i915_gem_obj_ggtt_size(obj
);
386 if (obj
->pin_mappable
) {
387 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
390 if (obj
->madv
== I915_MADV_DONTNEED
) {
391 purgeable_size
+= obj
->base
.size
;
395 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
396 purgeable_count
, purgeable_size
);
397 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
398 mappable_count
, mappable_size
);
399 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
402 seq_printf(m
, "%zu [%lu] gtt total\n",
403 dev_priv
->gtt
.base
.total
,
404 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
407 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
408 struct file_stats stats
;
410 memset(&stats
, 0, sizeof(stats
));
411 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
412 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
413 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
,
421 mutex_unlock(&dev
->struct_mutex
);
426 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
428 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
429 struct drm_device
*dev
= node
->minor
->dev
;
430 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
432 struct drm_i915_gem_object
*obj
;
433 size_t total_obj_size
, total_gtt_size
;
436 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
440 total_obj_size
= total_gtt_size
= count
= 0;
441 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
442 if (list
== PINNED_LIST
&& obj
->pin_count
== 0)
446 describe_obj(m
, obj
);
448 total_obj_size
+= obj
->base
.size
;
449 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
453 mutex_unlock(&dev
->struct_mutex
);
455 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
456 count
, total_obj_size
, total_gtt_size
);
461 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
463 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
464 struct drm_device
*dev
= node
->minor
->dev
;
466 struct intel_crtc
*crtc
;
468 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
469 const char pipe
= pipe_name(crtc
->pipe
);
470 const char plane
= plane_name(crtc
->plane
);
471 struct intel_unpin_work
*work
;
473 spin_lock_irqsave(&dev
->event_lock
, flags
);
474 work
= crtc
->unpin_work
;
476 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
479 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
480 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
483 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
486 if (work
->enable_stall_check
)
487 seq_puts(m
, "Stall check enabled, ");
489 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
490 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
492 if (work
->old_fb_obj
) {
493 struct drm_i915_gem_object
*obj
= work
->old_fb_obj
;
495 seq_printf(m
, "Old framebuffer gtt_offset 0x%08lx\n",
496 i915_gem_obj_ggtt_offset(obj
));
498 if (work
->pending_flip_obj
) {
499 struct drm_i915_gem_object
*obj
= work
->pending_flip_obj
;
501 seq_printf(m
, "New framebuffer gtt_offset 0x%08lx\n",
502 i915_gem_obj_ggtt_offset(obj
));
505 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
511 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
513 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
514 struct drm_device
*dev
= node
->minor
->dev
;
515 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
516 struct intel_ring_buffer
*ring
;
517 struct drm_i915_gem_request
*gem_request
;
520 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
525 for_each_ring(ring
, dev_priv
, i
) {
526 if (list_empty(&ring
->request_list
))
529 seq_printf(m
, "%s requests:\n", ring
->name
);
530 list_for_each_entry(gem_request
,
533 seq_printf(m
, " %d @ %d\n",
535 (int) (jiffies
- gem_request
->emitted_jiffies
));
539 mutex_unlock(&dev
->struct_mutex
);
542 seq_puts(m
, "No requests\n");
547 static void i915_ring_seqno_info(struct seq_file
*m
,
548 struct intel_ring_buffer
*ring
)
550 if (ring
->get_seqno
) {
551 seq_printf(m
, "Current sequence (%s): %u\n",
552 ring
->name
, ring
->get_seqno(ring
, false));
556 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
558 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
559 struct drm_device
*dev
= node
->minor
->dev
;
560 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
561 struct intel_ring_buffer
*ring
;
564 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
568 for_each_ring(ring
, dev_priv
, i
)
569 i915_ring_seqno_info(m
, ring
);
571 mutex_unlock(&dev
->struct_mutex
);
577 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
579 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
580 struct drm_device
*dev
= node
->minor
->dev
;
581 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
582 struct intel_ring_buffer
*ring
;
585 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
589 if (IS_VALLEYVIEW(dev
)) {
590 seq_printf(m
, "Display IER:\t%08x\n",
592 seq_printf(m
, "Display IIR:\t%08x\n",
594 seq_printf(m
, "Display IIR_RW:\t%08x\n",
595 I915_READ(VLV_IIR_RW
));
596 seq_printf(m
, "Display IMR:\t%08x\n",
599 seq_printf(m
, "Pipe %c stat:\t%08x\n",
601 I915_READ(PIPESTAT(pipe
)));
603 seq_printf(m
, "Master IER:\t%08x\n",
604 I915_READ(VLV_MASTER_IER
));
606 seq_printf(m
, "Render IER:\t%08x\n",
608 seq_printf(m
, "Render IIR:\t%08x\n",
610 seq_printf(m
, "Render IMR:\t%08x\n",
613 seq_printf(m
, "PM IER:\t\t%08x\n",
614 I915_READ(GEN6_PMIER
));
615 seq_printf(m
, "PM IIR:\t\t%08x\n",
616 I915_READ(GEN6_PMIIR
));
617 seq_printf(m
, "PM IMR:\t\t%08x\n",
618 I915_READ(GEN6_PMIMR
));
620 seq_printf(m
, "Port hotplug:\t%08x\n",
621 I915_READ(PORT_HOTPLUG_EN
));
622 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
623 I915_READ(VLV_DPFLIPSTAT
));
624 seq_printf(m
, "DPINVGTT:\t%08x\n",
625 I915_READ(DPINVGTT
));
627 } else if (!HAS_PCH_SPLIT(dev
)) {
628 seq_printf(m
, "Interrupt enable: %08x\n",
630 seq_printf(m
, "Interrupt identity: %08x\n",
632 seq_printf(m
, "Interrupt mask: %08x\n",
635 seq_printf(m
, "Pipe %c stat: %08x\n",
637 I915_READ(PIPESTAT(pipe
)));
639 seq_printf(m
, "North Display Interrupt enable: %08x\n",
641 seq_printf(m
, "North Display Interrupt identity: %08x\n",
643 seq_printf(m
, "North Display Interrupt mask: %08x\n",
645 seq_printf(m
, "South Display Interrupt enable: %08x\n",
647 seq_printf(m
, "South Display Interrupt identity: %08x\n",
649 seq_printf(m
, "South Display Interrupt mask: %08x\n",
651 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
653 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
655 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
658 seq_printf(m
, "Interrupts received: %d\n",
659 atomic_read(&dev_priv
->irq_received
));
660 for_each_ring(ring
, dev_priv
, i
) {
661 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
663 "Graphics Interrupt mask (%s): %08x\n",
664 ring
->name
, I915_READ_IMR(ring
));
666 i915_ring_seqno_info(m
, ring
);
668 mutex_unlock(&dev
->struct_mutex
);
673 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
675 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
676 struct drm_device
*dev
= node
->minor
->dev
;
677 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
680 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
684 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
685 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
686 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
687 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
689 seq_printf(m
, "Fence %d, pin count = %d, object = ",
690 i
, dev_priv
->fence_regs
[i
].pin_count
);
692 seq_puts(m
, "unused");
694 describe_obj(m
, obj
);
698 mutex_unlock(&dev
->struct_mutex
);
702 static int i915_hws_info(struct seq_file
*m
, void *data
)
704 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
705 struct drm_device
*dev
= node
->minor
->dev
;
706 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
707 struct intel_ring_buffer
*ring
;
711 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
712 hws
= ring
->status_page
.page_addr
;
716 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
717 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
719 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
725 i915_error_state_write(struct file
*filp
,
726 const char __user
*ubuf
,
730 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
731 struct drm_device
*dev
= error_priv
->dev
;
734 DRM_DEBUG_DRIVER("Resetting error state\n");
736 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
740 i915_destroy_error_state(dev
);
741 mutex_unlock(&dev
->struct_mutex
);
746 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
748 struct drm_device
*dev
= inode
->i_private
;
749 struct i915_error_state_file_priv
*error_priv
;
751 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
755 error_priv
->dev
= dev
;
757 i915_error_state_get(dev
, error_priv
);
759 file
->private_data
= error_priv
;
764 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
766 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
768 i915_error_state_put(error_priv
);
774 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
775 size_t count
, loff_t
*pos
)
777 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
778 struct drm_i915_error_state_buf error_str
;
780 ssize_t ret_count
= 0;
783 ret
= i915_error_state_buf_init(&error_str
, count
, *pos
);
787 ret
= i915_error_state_to_str(&error_str
, error_priv
);
791 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
798 *pos
= error_str
.start
+ ret_count
;
800 i915_error_state_buf_release(&error_str
);
801 return ret
?: ret_count
;
804 static const struct file_operations i915_error_state_fops
= {
805 .owner
= THIS_MODULE
,
806 .open
= i915_error_state_open
,
807 .read
= i915_error_state_read
,
808 .write
= i915_error_state_write
,
809 .llseek
= default_llseek
,
810 .release
= i915_error_state_release
,
814 i915_next_seqno_get(void *data
, u64
*val
)
816 struct drm_device
*dev
= data
;
817 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
820 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
824 *val
= dev_priv
->next_seqno
;
825 mutex_unlock(&dev
->struct_mutex
);
831 i915_next_seqno_set(void *data
, u64 val
)
833 struct drm_device
*dev
= data
;
836 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
840 ret
= i915_gem_set_seqno(dev
, val
);
841 mutex_unlock(&dev
->struct_mutex
);
846 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
847 i915_next_seqno_get
, i915_next_seqno_set
,
850 static int i915_rstdby_delays(struct seq_file
*m
, void *unused
)
852 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
853 struct drm_device
*dev
= node
->minor
->dev
;
854 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
858 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
862 crstanddelay
= I915_READ16(CRSTANDVID
);
864 mutex_unlock(&dev
->struct_mutex
);
866 seq_printf(m
, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay
>> 8) & 0x3f, (crstanddelay
& 0x3f));
871 static int i915_cur_delayinfo(struct seq_file
*m
, void *unused
)
873 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
874 struct drm_device
*dev
= node
->minor
->dev
;
875 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
878 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
881 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
882 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
884 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
885 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
886 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
888 seq_printf(m
, "Current P-state: %d\n",
889 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
890 } else if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
891 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
892 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
893 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
894 u32 rpstat
, cagf
, reqf
;
895 u32 rpupei
, rpcurup
, rpprevup
;
896 u32 rpdownei
, rpcurdown
, rpprevdown
;
899 /* RPSTAT1 is in the GT power well */
900 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
904 gen6_gt_force_wake_get(dev_priv
);
906 reqf
= I915_READ(GEN6_RPNSWREQ
);
907 reqf
&= ~GEN6_TURBO_DISABLE
;
912 reqf
*= GT_FREQUENCY_MULTIPLIER
;
914 rpstat
= I915_READ(GEN6_RPSTAT1
);
915 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
916 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
917 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
918 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
919 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
920 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
922 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
924 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
925 cagf
*= GT_FREQUENCY_MULTIPLIER
;
927 gen6_gt_force_wake_put(dev_priv
);
928 mutex_unlock(&dev
->struct_mutex
);
930 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
931 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
932 seq_printf(m
, "Render p-state ratio: %d\n",
933 (gt_perf_status
& 0xff00) >> 8);
934 seq_printf(m
, "Render p-state VID: %d\n",
935 gt_perf_status
& 0xff);
936 seq_printf(m
, "Render p-state limit: %d\n",
937 rp_state_limits
& 0xff);
938 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
939 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
940 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
942 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
943 GEN6_CURBSYTAVG_MASK
);
944 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
945 GEN6_CURBSYTAVG_MASK
);
946 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
948 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
949 GEN6_CURBSYTAVG_MASK
);
950 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
951 GEN6_CURBSYTAVG_MASK
);
953 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
954 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
955 max_freq
* GT_FREQUENCY_MULTIPLIER
);
957 max_freq
= (rp_state_cap
& 0xff00) >> 8;
958 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
959 max_freq
* GT_FREQUENCY_MULTIPLIER
);
961 max_freq
= rp_state_cap
& 0xff;
962 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
963 max_freq
* GT_FREQUENCY_MULTIPLIER
);
965 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
966 dev_priv
->rps
.hw_max
* GT_FREQUENCY_MULTIPLIER
);
967 } else if (IS_VALLEYVIEW(dev
)) {
970 mutex_lock(&dev_priv
->rps
.hw_lock
);
971 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
972 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
973 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
975 val
= vlv_punit_read(dev_priv
, PUNIT_FUSE_BUS1
);
976 seq_printf(m
, "max GPU freq: %d MHz\n",
977 vlv_gpu_freq(dev_priv
->mem_freq
, val
));
979 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
);
980 seq_printf(m
, "min GPU freq: %d MHz\n",
981 vlv_gpu_freq(dev_priv
->mem_freq
, val
));
983 seq_printf(m
, "current GPU freq: %d MHz\n",
984 vlv_gpu_freq(dev_priv
->mem_freq
,
985 (freq_sts
>> 8) & 0xff));
986 mutex_unlock(&dev_priv
->rps
.hw_lock
);
988 seq_puts(m
, "no P-state info available\n");
994 static int i915_delayfreq_table(struct seq_file
*m
, void *unused
)
996 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
997 struct drm_device
*dev
= node
->minor
->dev
;
998 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1002 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1006 for (i
= 0; i
< 16; i
++) {
1007 delayfreq
= I915_READ(PXVFREQ_BASE
+ i
* 4);
1008 seq_printf(m
, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i
, delayfreq
,
1009 (delayfreq
& PXVFREQ_PX_MASK
) >> PXVFREQ_PX_SHIFT
);
1012 mutex_unlock(&dev
->struct_mutex
);
1017 static inline int MAP_TO_MV(int map
)
1019 return 1250 - (map
* 25);
1022 static int i915_inttoext_table(struct seq_file
*m
, void *unused
)
1024 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1025 struct drm_device
*dev
= node
->minor
->dev
;
1026 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1030 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1034 for (i
= 1; i
<= 32; i
++) {
1035 inttoext
= I915_READ(INTTOEXT_BASE_ILK
+ i
* 4);
1036 seq_printf(m
, "INTTOEXT%02d: 0x%08x\n", i
, inttoext
);
1039 mutex_unlock(&dev
->struct_mutex
);
1044 static int ironlake_drpc_info(struct seq_file
*m
)
1046 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1047 struct drm_device
*dev
= node
->minor
->dev
;
1048 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1049 u32 rgvmodectl
, rstdbyctl
;
1053 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1057 rgvmodectl
= I915_READ(MEMMODECTL
);
1058 rstdbyctl
= I915_READ(RSTDBYCTL
);
1059 crstandvid
= I915_READ16(CRSTANDVID
);
1061 mutex_unlock(&dev
->struct_mutex
);
1063 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1065 seq_printf(m
, "Boost freq: %d\n",
1066 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1067 MEMMODE_BOOST_FREQ_SHIFT
);
1068 seq_printf(m
, "HW control enabled: %s\n",
1069 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1070 seq_printf(m
, "SW control enabled: %s\n",
1071 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1072 seq_printf(m
, "Gated voltage change: %s\n",
1073 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1074 seq_printf(m
, "Starting frequency: P%d\n",
1075 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1076 seq_printf(m
, "Max P-state: P%d\n",
1077 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1078 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1079 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1080 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1081 seq_printf(m
, "Render standby enabled: %s\n",
1082 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1083 seq_puts(m
, "Current RS state: ");
1084 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1086 seq_puts(m
, "on\n");
1088 case RSX_STATUS_RC1
:
1089 seq_puts(m
, "RC1\n");
1091 case RSX_STATUS_RC1E
:
1092 seq_puts(m
, "RC1E\n");
1094 case RSX_STATUS_RS1
:
1095 seq_puts(m
, "RS1\n");
1097 case RSX_STATUS_RS2
:
1098 seq_puts(m
, "RS2 (RC6)\n");
1100 case RSX_STATUS_RS3
:
1101 seq_puts(m
, "RC3 (RC6+)\n");
1104 seq_puts(m
, "unknown\n");
1111 static int gen6_drpc_info(struct seq_file
*m
)
1114 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1115 struct drm_device
*dev
= node
->minor
->dev
;
1116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1117 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1118 unsigned forcewake_count
;
1121 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1125 spin_lock_irq(&dev_priv
->uncore
.lock
);
1126 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1127 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1129 if (forcewake_count
) {
1130 seq_puts(m
, "RC information inaccurate because somebody "
1131 "holds a forcewake reference \n");
1133 /* NB: we cannot use forcewake, else we read the wrong values */
1134 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1136 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1139 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1140 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1142 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1143 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1144 mutex_unlock(&dev
->struct_mutex
);
1145 mutex_lock(&dev_priv
->rps
.hw_lock
);
1146 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1147 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1149 seq_printf(m
, "Video Turbo Mode: %s\n",
1150 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1151 seq_printf(m
, "HW control enabled: %s\n",
1152 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1153 seq_printf(m
, "SW control enabled: %s\n",
1154 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1155 GEN6_RP_MEDIA_SW_MODE
));
1156 seq_printf(m
, "RC1e Enabled: %s\n",
1157 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1158 seq_printf(m
, "RC6 Enabled: %s\n",
1159 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1160 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1161 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1162 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1163 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1164 seq_puts(m
, "Current RC state: ");
1165 switch (gt_core_status
& GEN6_RCn_MASK
) {
1167 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1168 seq_puts(m
, "Core Power Down\n");
1170 seq_puts(m
, "on\n");
1173 seq_puts(m
, "RC3\n");
1176 seq_puts(m
, "RC6\n");
1179 seq_puts(m
, "RC7\n");
1182 seq_puts(m
, "Unknown\n");
1186 seq_printf(m
, "Core Power Down: %s\n",
1187 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1189 /* Not exactly sure what this is */
1190 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1191 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1192 seq_printf(m
, "RC6 residency since boot: %u\n",
1193 I915_READ(GEN6_GT_GFX_RC6
));
1194 seq_printf(m
, "RC6+ residency since boot: %u\n",
1195 I915_READ(GEN6_GT_GFX_RC6p
));
1196 seq_printf(m
, "RC6++ residency since boot: %u\n",
1197 I915_READ(GEN6_GT_GFX_RC6pp
));
1199 seq_printf(m
, "RC6 voltage: %dmV\n",
1200 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1201 seq_printf(m
, "RC6+ voltage: %dmV\n",
1202 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1203 seq_printf(m
, "RC6++ voltage: %dmV\n",
1204 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1208 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1210 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1211 struct drm_device
*dev
= node
->minor
->dev
;
1213 if (IS_GEN6(dev
) || IS_GEN7(dev
))
1214 return gen6_drpc_info(m
);
1216 return ironlake_drpc_info(m
);
1219 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1221 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1222 struct drm_device
*dev
= node
->minor
->dev
;
1223 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1225 if (!I915_HAS_FBC(dev
)) {
1226 seq_puts(m
, "FBC unsupported on this chipset\n");
1230 if (intel_fbc_enabled(dev
)) {
1231 seq_puts(m
, "FBC enabled\n");
1233 seq_puts(m
, "FBC disabled: ");
1234 switch (dev_priv
->fbc
.no_fbc_reason
) {
1236 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1238 case FBC_UNSUPPORTED
:
1239 seq_puts(m
, "unsupported by this chipset");
1242 seq_puts(m
, "no outputs");
1244 case FBC_STOLEN_TOO_SMALL
:
1245 seq_puts(m
, "not enough stolen memory");
1247 case FBC_UNSUPPORTED_MODE
:
1248 seq_puts(m
, "mode not supported");
1250 case FBC_MODE_TOO_LARGE
:
1251 seq_puts(m
, "mode too large");
1254 seq_puts(m
, "FBC unsupported on plane");
1257 seq_puts(m
, "scanout buffer not tiled");
1259 case FBC_MULTIPLE_PIPES
:
1260 seq_puts(m
, "multiple pipes are enabled");
1262 case FBC_MODULE_PARAM
:
1263 seq_puts(m
, "disabled per module param (default off)");
1265 case FBC_CHIP_DEFAULT
:
1266 seq_puts(m
, "disabled per chip default");
1269 seq_puts(m
, "unknown reason");
1276 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1278 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1279 struct drm_device
*dev
= node
->minor
->dev
;
1280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1282 if (!HAS_IPS(dev
)) {
1283 seq_puts(m
, "not supported\n");
1287 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1288 seq_puts(m
, "enabled\n");
1290 seq_puts(m
, "disabled\n");
1295 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1297 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1298 struct drm_device
*dev
= node
->minor
->dev
;
1299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1300 bool sr_enabled
= false;
1302 if (HAS_PCH_SPLIT(dev
))
1303 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1304 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1305 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1306 else if (IS_I915GM(dev
))
1307 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1308 else if (IS_PINEVIEW(dev
))
1309 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1311 seq_printf(m
, "self-refresh: %s\n",
1312 sr_enabled
? "enabled" : "disabled");
1317 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1319 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1320 struct drm_device
*dev
= node
->minor
->dev
;
1321 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1322 unsigned long temp
, chipset
, gfx
;
1328 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1332 temp
= i915_mch_val(dev_priv
);
1333 chipset
= i915_chipset_val(dev_priv
);
1334 gfx
= i915_gfx_val(dev_priv
);
1335 mutex_unlock(&dev
->struct_mutex
);
1337 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1338 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1339 seq_printf(m
, "GFX power: %ld\n", gfx
);
1340 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1345 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1347 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1348 struct drm_device
*dev
= node
->minor
->dev
;
1349 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1351 int gpu_freq
, ia_freq
;
1353 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1354 seq_puts(m
, "unsupported on this chipset\n");
1358 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1360 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1364 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1366 for (gpu_freq
= dev_priv
->rps
.min_delay
;
1367 gpu_freq
<= dev_priv
->rps
.max_delay
;
1370 sandybridge_pcode_read(dev_priv
,
1371 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1373 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1374 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1375 ((ia_freq
>> 0) & 0xff) * 100,
1376 ((ia_freq
>> 8) & 0xff) * 100);
1379 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1384 static int i915_gfxec(struct seq_file
*m
, void *unused
)
1386 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1387 struct drm_device
*dev
= node
->minor
->dev
;
1388 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1391 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1395 seq_printf(m
, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1397 mutex_unlock(&dev
->struct_mutex
);
1402 static int i915_opregion(struct seq_file
*m
, void *unused
)
1404 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1405 struct drm_device
*dev
= node
->minor
->dev
;
1406 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1407 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1408 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1414 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1418 if (opregion
->header
) {
1419 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1420 seq_write(m
, data
, OPREGION_SIZE
);
1423 mutex_unlock(&dev
->struct_mutex
);
1430 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1432 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1433 struct drm_device
*dev
= node
->minor
->dev
;
1434 struct intel_fbdev
*ifbdev
= NULL
;
1435 struct intel_framebuffer
*fb
;
1437 #ifdef CONFIG_DRM_I915_FBDEV
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1439 int ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1443 ifbdev
= dev_priv
->fbdev
;
1444 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1446 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1450 fb
->base
.bits_per_pixel
,
1451 atomic_read(&fb
->base
.refcount
.refcount
));
1452 describe_obj(m
, fb
->obj
);
1454 mutex_unlock(&dev
->mode_config
.mutex
);
1457 mutex_lock(&dev
->mode_config
.fb_lock
);
1458 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1459 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1462 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1466 fb
->base
.bits_per_pixel
,
1467 atomic_read(&fb
->base
.refcount
.refcount
));
1468 describe_obj(m
, fb
->obj
);
1471 mutex_unlock(&dev
->mode_config
.fb_lock
);
1476 static int i915_context_status(struct seq_file
*m
, void *unused
)
1478 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1479 struct drm_device
*dev
= node
->minor
->dev
;
1480 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1481 struct intel_ring_buffer
*ring
;
1482 struct i915_hw_context
*ctx
;
1485 ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1489 if (dev_priv
->ips
.pwrctx
) {
1490 seq_puts(m
, "power context ");
1491 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1495 if (dev_priv
->ips
.renderctx
) {
1496 seq_puts(m
, "render context ");
1497 describe_obj(m
, dev_priv
->ips
.renderctx
);
1501 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1502 seq_puts(m
, "HW context ");
1503 describe_ctx(m
, ctx
);
1504 for_each_ring(ring
, dev_priv
, i
)
1505 if (ring
->default_context
== ctx
)
1506 seq_printf(m
, "(default context %s) ", ring
->name
);
1508 describe_obj(m
, ctx
->obj
);
1512 mutex_unlock(&dev
->mode_config
.mutex
);
1517 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1519 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1520 struct drm_device
*dev
= node
->minor
->dev
;
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1522 unsigned forcewake_count
;
1524 spin_lock_irq(&dev_priv
->uncore
.lock
);
1525 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1526 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1528 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1533 static const char *swizzle_string(unsigned swizzle
)
1536 case I915_BIT_6_SWIZZLE_NONE
:
1538 case I915_BIT_6_SWIZZLE_9
:
1540 case I915_BIT_6_SWIZZLE_9_10
:
1541 return "bit9/bit10";
1542 case I915_BIT_6_SWIZZLE_9_11
:
1543 return "bit9/bit11";
1544 case I915_BIT_6_SWIZZLE_9_10_11
:
1545 return "bit9/bit10/bit11";
1546 case I915_BIT_6_SWIZZLE_9_17
:
1547 return "bit9/bit17";
1548 case I915_BIT_6_SWIZZLE_9_10_17
:
1549 return "bit9/bit10/bit17";
1550 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1557 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1559 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1560 struct drm_device
*dev
= node
->minor
->dev
;
1561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1564 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1568 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1569 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1570 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1571 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1573 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
1574 seq_printf(m
, "DDC = 0x%08x\n",
1576 seq_printf(m
, "C0DRB3 = 0x%04x\n",
1577 I915_READ16(C0DRB3
));
1578 seq_printf(m
, "C1DRB3 = 0x%04x\n",
1579 I915_READ16(C1DRB3
));
1580 } else if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1581 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
1582 I915_READ(MAD_DIMM_C0
));
1583 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
1584 I915_READ(MAD_DIMM_C1
));
1585 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
1586 I915_READ(MAD_DIMM_C2
));
1587 seq_printf(m
, "TILECTL = 0x%08x\n",
1588 I915_READ(TILECTL
));
1589 seq_printf(m
, "ARB_MODE = 0x%08x\n",
1590 I915_READ(ARB_MODE
));
1591 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
1592 I915_READ(DISP_ARB_CTL
));
1594 mutex_unlock(&dev
->struct_mutex
);
1599 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
1601 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1602 struct drm_device
*dev
= node
->minor
->dev
;
1603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1604 struct intel_ring_buffer
*ring
;
1608 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1611 if (INTEL_INFO(dev
)->gen
== 6)
1612 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
1614 for_each_ring(ring
, dev_priv
, i
) {
1615 seq_printf(m
, "%s\n", ring
->name
);
1616 if (INTEL_INFO(dev
)->gen
== 7)
1617 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
1618 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
1619 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
1620 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
1622 if (dev_priv
->mm
.aliasing_ppgtt
) {
1623 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1625 seq_puts(m
, "aliasing PPGTT:\n");
1626 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
1628 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
1629 mutex_unlock(&dev
->struct_mutex
);
1634 static int i915_dpio_info(struct seq_file
*m
, void *data
)
1636 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1637 struct drm_device
*dev
= node
->minor
->dev
;
1638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1642 if (!IS_VALLEYVIEW(dev
)) {
1643 seq_puts(m
, "unsupported\n");
1647 ret
= mutex_lock_interruptible(&dev_priv
->dpio_lock
);
1651 seq_printf(m
, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL
));
1653 seq_printf(m
, "DPIO_DIV_A: 0x%08x\n",
1654 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_DIV_A
));
1655 seq_printf(m
, "DPIO_DIV_B: 0x%08x\n",
1656 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_DIV_B
));
1658 seq_printf(m
, "DPIO_REFSFR_A: 0x%08x\n",
1659 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_REFSFR_A
));
1660 seq_printf(m
, "DPIO_REFSFR_B: 0x%08x\n",
1661 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_REFSFR_B
));
1663 seq_printf(m
, "DPIO_CORE_CLK_A: 0x%08x\n",
1664 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_CORE_CLK_A
));
1665 seq_printf(m
, "DPIO_CORE_CLK_B: 0x%08x\n",
1666 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_CORE_CLK_B
));
1668 seq_printf(m
, "DPIO_LPF_COEFF_A: 0x%08x\n",
1669 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_LPF_COEFF_A
));
1670 seq_printf(m
, "DPIO_LPF_COEFF_B: 0x%08x\n",
1671 vlv_dpio_read(dev_priv
, PIPE_A
, _DPIO_LPF_COEFF_B
));
1673 seq_printf(m
, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1674 vlv_dpio_read(dev_priv
, PIPE_A
, DPIO_FASTCLK_DISABLE
));
1676 mutex_unlock(&dev_priv
->dpio_lock
);
1681 static int i915_llc(struct seq_file
*m
, void *data
)
1683 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1684 struct drm_device
*dev
= node
->minor
->dev
;
1685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1687 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1688 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
1689 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
1694 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
1696 struct drm_info_node
*node
= m
->private;
1697 struct drm_device
*dev
= node
->minor
->dev
;
1698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1700 bool enabled
= false;
1702 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
1703 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
1705 enabled
= HAS_PSR(dev
) &&
1706 I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1707 seq_printf(m
, "Enabled: %s\n", yesno(enabled
));
1710 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
1711 EDP_PSR_PERF_CNT_MASK
;
1712 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
1717 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
1719 struct drm_info_node
*node
= m
->private;
1720 struct drm_device
*dev
= node
->minor
->dev
;
1721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1725 if (INTEL_INFO(dev
)->gen
< 6)
1728 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
1729 power
= (power
& 0x1f00) >> 8;
1730 units
= 1000000 / (1 << power
); /* convert to uJ */
1731 power
= I915_READ(MCH_SECP_NRG_STTS
);
1734 seq_printf(m
, "%llu", (long long unsigned)power
);
1739 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
1741 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1742 struct drm_device
*dev
= node
->minor
->dev
;
1743 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1745 if (!IS_HASWELL(dev
)) {
1746 seq_puts(m
, "not supported\n");
1750 mutex_lock(&dev_priv
->pc8
.lock
);
1751 seq_printf(m
, "Requirements met: %s\n",
1752 yesno(dev_priv
->pc8
.requirements_met
));
1753 seq_printf(m
, "GPU idle: %s\n", yesno(dev_priv
->pc8
.gpu_idle
));
1754 seq_printf(m
, "Disable count: %d\n", dev_priv
->pc8
.disable_count
);
1755 seq_printf(m
, "IRQs disabled: %s\n",
1756 yesno(dev_priv
->pc8
.irqs_disabled
));
1757 seq_printf(m
, "Enabled: %s\n", yesno(dev_priv
->pc8
.enabled
));
1758 mutex_unlock(&dev_priv
->pc8
.lock
);
1763 struct pipe_crc_info
{
1765 struct drm_device
*dev
;
1769 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
1771 struct pipe_crc_info
*info
= inode
->i_private
;
1772 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
1773 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
1775 if (!atomic_dec_and_test(&pipe_crc
->available
)) {
1776 atomic_inc(&pipe_crc
->available
);
1777 return -EBUSY
; /* already open */
1780 filep
->private_data
= inode
->i_private
;
1785 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
1787 struct pipe_crc_info
*info
= inode
->i_private
;
1788 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
1789 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
1791 atomic_inc(&pipe_crc
->available
); /* release the device */
1796 /* (6 fields, 8 chars each, space separated (5) + '\n') */
1797 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
1798 /* account for \'0' */
1799 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
1801 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
1805 head
= atomic_read(&pipe_crc
->head
);
1806 tail
= atomic_read(&pipe_crc
->tail
);
1808 return CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
);
1812 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
1815 struct pipe_crc_info
*info
= filep
->private_data
;
1816 struct drm_device
*dev
= info
->dev
;
1817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1818 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
1819 char buf
[PIPE_CRC_BUFFER_LEN
];
1820 int head
, tail
, n_entries
, n
;
1824 * Don't allow user space to provide buffers not big enough to hold
1827 if (count
< PIPE_CRC_LINE_LEN
)
1830 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
1833 /* nothing to read */
1834 while (pipe_crc_data_count(pipe_crc
) == 0) {
1835 if (filep
->f_flags
& O_NONBLOCK
)
1838 if (wait_event_interruptible(pipe_crc
->wq
,
1839 pipe_crc_data_count(pipe_crc
)))
1840 return -ERESTARTSYS
;
1843 /* We now have one or more entries to read */
1844 head
= atomic_read(&pipe_crc
->head
);
1845 tail
= atomic_read(&pipe_crc
->tail
);
1846 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
1847 count
/ PIPE_CRC_LINE_LEN
);
1851 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
1854 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
1855 "%8u %8x %8x %8x %8x %8x\n",
1856 entry
->frame
, entry
->crc
[0],
1857 entry
->crc
[1], entry
->crc
[2],
1858 entry
->crc
[3], entry
->crc
[4]);
1860 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
1861 buf
, PIPE_CRC_LINE_LEN
);
1862 if (ret
== PIPE_CRC_LINE_LEN
)
1865 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
1866 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
1867 atomic_set(&pipe_crc
->tail
, tail
);
1869 } while (--n_entries
);
1874 static const struct file_operations i915_pipe_crc_fops
= {
1875 .owner
= THIS_MODULE
,
1876 .open
= i915_pipe_crc_open
,
1877 .read
= i915_pipe_crc_read
,
1878 .release
= i915_pipe_crc_release
,
1881 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
1883 .name
= "i915_pipe_A_crc",
1887 .name
= "i915_pipe_B_crc",
1891 .name
= "i915_pipe_C_crc",
1896 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
1899 struct drm_device
*dev
= minor
->dev
;
1901 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
1904 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
1905 &i915_pipe_crc_fops
);
1907 return PTR_ERR(ent
);
1909 return drm_add_fake_info_node(minor
, ent
, info
);
1912 static const char * const pipe_crc_sources
[] = {
1920 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
1922 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
1923 return pipe_crc_sources
[source
];
1926 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
1928 struct drm_device
*dev
= m
->private;
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1932 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
1933 seq_printf(m
, "%c %s\n", pipe_name(i
),
1934 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
1939 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
1941 struct drm_device
*dev
= inode
->i_private
;
1943 return single_open(file
, display_crc_ctl_show
, dev
);
1946 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source source
,
1950 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
1951 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
1953 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
1954 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
1956 case INTEL_PIPE_CRC_SOURCE_PF
:
1958 case INTEL_PIPE_CRC_SOURCE_PIPE
:
1959 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
1969 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source source
,
1973 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
1974 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
1976 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
1977 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
1979 case INTEL_PIPE_CRC_SOURCE_PF
:
1980 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
1982 case INTEL_PIPE_CRC_SOURCE_PIPE
:
1992 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
1993 enum intel_pipe_crc_source source
)
1995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1996 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
2000 if (!(IS_IVYBRIDGE(dev
) || IS_GEN5(dev
) || IS_GEN6(dev
)))
2003 if (pipe_crc
->source
== source
)
2006 /* forbid changing the source without going back to 'none' */
2007 if (pipe_crc
->source
&& source
)
2010 if (IS_GEN5(dev
) || IS_GEN6(dev
))
2011 ret
= ilk_pipe_crc_ctl_reg(source
, &val
);
2013 ret
= ivb_pipe_crc_ctl_reg(source
, &val
);
2018 /* none -> real source transition */
2020 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2021 pipe_name(pipe
), pipe_crc_source_name(source
));
2023 pipe_crc
->entries
= kzalloc(sizeof(*pipe_crc
->entries
) *
2024 INTEL_PIPE_CRC_ENTRIES_NR
,
2026 if (!pipe_crc
->entries
)
2029 atomic_set(&pipe_crc
->head
, 0);
2030 atomic_set(&pipe_crc
->tail
, 0);
2033 pipe_crc
->source
= source
;
2035 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
2036 POSTING_READ(PIPE_CRC_CTL(pipe
));
2038 /* real source -> none transition */
2039 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
2040 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2043 kfree(pipe_crc
->entries
);
2044 pipe_crc
->entries
= NULL
;
2051 * Parse pipe CRC command strings:
2052 * command: wsp* object wsp+ name wsp+ source wsp*
2055 * source: (none | plane1 | plane2 | pf)
2056 * wsp: (#0x20 | #0x9 | #0xA)+
2059 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2060 * "pipe A none" -> Stop CRC
2062 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
2069 /* skip leading white space */
2070 buf
= skip_spaces(buf
);
2072 break; /* end of buffer */
2074 /* find end of word */
2075 for (end
= buf
; *end
&& !isspace(*end
); end
++)
2078 if (n_words
== max_words
) {
2079 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2081 return -EINVAL
; /* ran out of words[] before bytes */
2086 words
[n_words
++] = buf
;
2093 enum intel_pipe_crc_object
{
2094 PIPE_CRC_OBJECT_PIPE
,
2097 static const char * const pipe_crc_objects
[] = {
2102 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
2106 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
2107 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
2115 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
2117 const char name
= buf
[0];
2119 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
2128 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
2132 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
2133 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
2141 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
2145 char *words
[N_WORDS
];
2147 enum intel_pipe_crc_object object
;
2148 enum intel_pipe_crc_source source
;
2150 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
2151 if (n_words
!= N_WORDS
) {
2152 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2157 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
2158 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
2162 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
2163 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
2167 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
2168 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
2172 return pipe_crc_set_source(dev
, pipe
, source
);
2175 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
2176 size_t len
, loff_t
*offp
)
2178 struct seq_file
*m
= file
->private_data
;
2179 struct drm_device
*dev
= m
->private;
2186 if (len
> PAGE_SIZE
- 1) {
2187 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2192 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
2196 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
2202 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
2213 static const struct file_operations i915_display_crc_ctl_fops
= {
2214 .owner
= THIS_MODULE
,
2215 .open
= display_crc_ctl_open
,
2217 .llseek
= seq_lseek
,
2218 .release
= single_release
,
2219 .write
= display_crc_ctl_write
2223 i915_wedged_get(void *data
, u64
*val
)
2225 struct drm_device
*dev
= data
;
2226 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2228 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2234 i915_wedged_set(void *data
, u64 val
)
2236 struct drm_device
*dev
= data
;
2238 DRM_INFO("Manually setting wedged to %llu\n", val
);
2239 i915_handle_error(dev
, val
);
2244 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
2245 i915_wedged_get
, i915_wedged_set
,
2249 i915_ring_stop_get(void *data
, u64
*val
)
2251 struct drm_device
*dev
= data
;
2252 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2254 *val
= dev_priv
->gpu_error
.stop_rings
;
2260 i915_ring_stop_set(void *data
, u64 val
)
2262 struct drm_device
*dev
= data
;
2263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2266 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
2268 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2272 dev_priv
->gpu_error
.stop_rings
= val
;
2273 mutex_unlock(&dev
->struct_mutex
);
2278 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
2279 i915_ring_stop_get
, i915_ring_stop_set
,
2283 i915_ring_missed_irq_get(void *data
, u64
*val
)
2285 struct drm_device
*dev
= data
;
2286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2288 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
2293 i915_ring_missed_irq_set(void *data
, u64 val
)
2295 struct drm_device
*dev
= data
;
2296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2299 /* Lock against concurrent debugfs callers */
2300 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2303 dev_priv
->gpu_error
.missed_irq_rings
= val
;
2304 mutex_unlock(&dev
->struct_mutex
);
2309 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
2310 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
2314 i915_ring_test_irq_get(void *data
, u64
*val
)
2316 struct drm_device
*dev
= data
;
2317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2319 *val
= dev_priv
->gpu_error
.test_irq_rings
;
2325 i915_ring_test_irq_set(void *data
, u64 val
)
2327 struct drm_device
*dev
= data
;
2328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2331 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
2333 /* Lock against concurrent debugfs callers */
2334 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2338 dev_priv
->gpu_error
.test_irq_rings
= val
;
2339 mutex_unlock(&dev
->struct_mutex
);
2344 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
2345 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
2348 #define DROP_UNBOUND 0x1
2349 #define DROP_BOUND 0x2
2350 #define DROP_RETIRE 0x4
2351 #define DROP_ACTIVE 0x8
2352 #define DROP_ALL (DROP_UNBOUND | \
2357 i915_drop_caches_get(void *data
, u64
*val
)
2365 i915_drop_caches_set(void *data
, u64 val
)
2367 struct drm_device
*dev
= data
;
2368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2369 struct drm_i915_gem_object
*obj
, *next
;
2370 struct i915_address_space
*vm
;
2371 struct i915_vma
*vma
, *x
;
2374 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val
);
2376 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2377 * on ioctls on -EAGAIN. */
2378 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2382 if (val
& DROP_ACTIVE
) {
2383 ret
= i915_gpu_idle(dev
);
2388 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
2389 i915_gem_retire_requests(dev
);
2391 if (val
& DROP_BOUND
) {
2392 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2393 list_for_each_entry_safe(vma
, x
, &vm
->inactive_list
,
2395 if (vma
->obj
->pin_count
)
2398 ret
= i915_vma_unbind(vma
);
2405 if (val
& DROP_UNBOUND
) {
2406 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
2408 if (obj
->pages_pin_count
== 0) {
2409 ret
= i915_gem_object_put_pages(obj
);
2416 mutex_unlock(&dev
->struct_mutex
);
2421 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
2422 i915_drop_caches_get
, i915_drop_caches_set
,
2426 i915_max_freq_get(void *data
, u64
*val
)
2428 struct drm_device
*dev
= data
;
2429 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2432 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
2435 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
2437 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
2441 if (IS_VALLEYVIEW(dev
))
2442 *val
= vlv_gpu_freq(dev_priv
->mem_freq
,
2443 dev_priv
->rps
.max_delay
);
2445 *val
= dev_priv
->rps
.max_delay
* GT_FREQUENCY_MULTIPLIER
;
2446 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2452 i915_max_freq_set(void *data
, u64 val
)
2454 struct drm_device
*dev
= data
;
2455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2458 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
2461 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
2463 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
2465 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
2470 * Turbo will still be enabled, but won't go above the set value.
2472 if (IS_VALLEYVIEW(dev
)) {
2473 val
= vlv_freq_opcode(dev_priv
->mem_freq
, val
);
2474 dev_priv
->rps
.max_delay
= val
;
2475 gen6_set_rps(dev
, val
);
2477 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
2478 dev_priv
->rps
.max_delay
= val
;
2479 gen6_set_rps(dev
, val
);
2482 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2487 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
2488 i915_max_freq_get
, i915_max_freq_set
,
2492 i915_min_freq_get(void *data
, u64
*val
)
2494 struct drm_device
*dev
= data
;
2495 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2498 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
2501 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
2503 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
2507 if (IS_VALLEYVIEW(dev
))
2508 *val
= vlv_gpu_freq(dev_priv
->mem_freq
,
2509 dev_priv
->rps
.min_delay
);
2511 *val
= dev_priv
->rps
.min_delay
* GT_FREQUENCY_MULTIPLIER
;
2512 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2518 i915_min_freq_set(void *data
, u64 val
)
2520 struct drm_device
*dev
= data
;
2521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2524 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
2527 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
2529 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
2531 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
2536 * Turbo will still be enabled, but won't go below the set value.
2538 if (IS_VALLEYVIEW(dev
)) {
2539 val
= vlv_freq_opcode(dev_priv
->mem_freq
, val
);
2540 dev_priv
->rps
.min_delay
= val
;
2541 valleyview_set_rps(dev
, val
);
2543 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
2544 dev_priv
->rps
.min_delay
= val
;
2545 gen6_set_rps(dev
, val
);
2547 mutex_unlock(&dev_priv
->rps
.hw_lock
);
2552 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
2553 i915_min_freq_get
, i915_min_freq_set
,
2557 i915_cache_sharing_get(void *data
, u64
*val
)
2559 struct drm_device
*dev
= data
;
2560 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2564 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
2567 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2571 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
2572 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
2574 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
2580 i915_cache_sharing_set(void *data
, u64 val
)
2582 struct drm_device
*dev
= data
;
2583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2586 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
2592 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
2594 /* Update the cache sharing policy here as well */
2595 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
2596 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
2597 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
2598 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
2603 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
2604 i915_cache_sharing_get
, i915_cache_sharing_set
,
2607 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
2609 struct drm_device
*dev
= inode
->i_private
;
2610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2612 if (INTEL_INFO(dev
)->gen
< 6)
2615 gen6_gt_force_wake_get(dev_priv
);
2620 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
2622 struct drm_device
*dev
= inode
->i_private
;
2623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2625 if (INTEL_INFO(dev
)->gen
< 6)
2628 gen6_gt_force_wake_put(dev_priv
);
2633 static const struct file_operations i915_forcewake_fops
= {
2634 .owner
= THIS_MODULE
,
2635 .open
= i915_forcewake_open
,
2636 .release
= i915_forcewake_release
,
2639 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
2641 struct drm_device
*dev
= minor
->dev
;
2644 ent
= debugfs_create_file("i915_forcewake_user",
2647 &i915_forcewake_fops
);
2649 return PTR_ERR(ent
);
2651 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
2654 static int i915_debugfs_create(struct dentry
*root
,
2655 struct drm_minor
*minor
,
2657 const struct file_operations
*fops
)
2659 struct drm_device
*dev
= minor
->dev
;
2662 ent
= debugfs_create_file(name
,
2667 return PTR_ERR(ent
);
2669 return drm_add_fake_info_node(minor
, ent
, fops
);
2672 static struct drm_info_list i915_debugfs_list
[] = {
2673 {"i915_capabilities", i915_capabilities
, 0},
2674 {"i915_gem_objects", i915_gem_object_info
, 0},
2675 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
2676 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
2677 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
2678 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
2679 {"i915_gem_stolen", i915_gem_stolen_list_info
},
2680 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
2681 {"i915_gem_request", i915_gem_request_info
, 0},
2682 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
2683 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
2684 {"i915_gem_interrupt", i915_interrupt_info
, 0},
2685 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
2686 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
2687 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
2688 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
2689 {"i915_rstdby_delays", i915_rstdby_delays
, 0},
2690 {"i915_cur_delayinfo", i915_cur_delayinfo
, 0},
2691 {"i915_delayfreq_table", i915_delayfreq_table
, 0},
2692 {"i915_inttoext_table", i915_inttoext_table
, 0},
2693 {"i915_drpc_info", i915_drpc_info
, 0},
2694 {"i915_emon_status", i915_emon_status
, 0},
2695 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
2696 {"i915_gfxec", i915_gfxec
, 0},
2697 {"i915_fbc_status", i915_fbc_status
, 0},
2698 {"i915_ips_status", i915_ips_status
, 0},
2699 {"i915_sr_status", i915_sr_status
, 0},
2700 {"i915_opregion", i915_opregion
, 0},
2701 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
2702 {"i915_context_status", i915_context_status
, 0},
2703 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
2704 {"i915_swizzle_info", i915_swizzle_info
, 0},
2705 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
2706 {"i915_dpio", i915_dpio_info
, 0},
2707 {"i915_llc", i915_llc
, 0},
2708 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
2709 {"i915_energy_uJ", i915_energy_uJ
, 0},
2710 {"i915_pc8_status", i915_pc8_status
, 0},
2712 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2714 static struct i915_debugfs_files
{
2716 const struct file_operations
*fops
;
2717 } i915_debugfs_files
[] = {
2718 {"i915_wedged", &i915_wedged_fops
},
2719 {"i915_max_freq", &i915_max_freq_fops
},
2720 {"i915_min_freq", &i915_min_freq_fops
},
2721 {"i915_cache_sharing", &i915_cache_sharing_fops
},
2722 {"i915_ring_stop", &i915_ring_stop_fops
},
2723 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
2724 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
2725 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
2726 {"i915_error_state", &i915_error_state_fops
},
2727 {"i915_next_seqno", &i915_next_seqno_fops
},
2728 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
2731 void intel_display_crc_init(struct drm_device
*dev
)
2733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2736 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
2737 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[i
];
2739 atomic_set(&pipe_crc
->available
, 1);
2740 init_waitqueue_head(&pipe_crc
->wq
);
2744 int i915_debugfs_init(struct drm_minor
*minor
)
2748 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
2752 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
2753 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
2758 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
2759 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
2760 i915_debugfs_files
[i
].name
,
2761 i915_debugfs_files
[i
].fops
);
2766 return drm_debugfs_create_files(i915_debugfs_list
,
2767 I915_DEBUGFS_ENTRIES
,
2768 minor
->debugfs_root
, minor
);
2771 void i915_debugfs_cleanup(struct drm_minor
*minor
)
2773 struct drm_device
*dev
= minor
->dev
;
2776 drm_debugfs_remove_files(i915_debugfs_list
,
2777 I915_DEBUGFS_ENTRIES
, minor
);
2779 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
2782 for (i
= 0; i
< INTEL_INFO(dev
)->num_pipes
; i
++) {
2783 struct drm_info_list
*info_list
=
2784 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
2786 drm_debugfs_remove_files(info_list
, 1, minor
);
2789 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
2790 struct drm_info_list
*info_list
=
2791 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
2793 drm_debugfs_remove_files(info_list
, 1, minor
);
2797 #endif /* CONFIG_DEBUG_FS */