2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor
*minor
,
56 struct drm_info_node
*node
;
58 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
66 node
->info_ent
= (void *) key
;
68 mutex_lock(&minor
->debugfs_lock
);
69 list_add(&node
->list
, &minor
->debugfs_list
);
70 mutex_unlock(&minor
->debugfs_lock
);
75 static int i915_capabilities(struct seq_file
*m
, void *data
)
77 struct drm_info_node
*node
= m
->private;
78 struct drm_device
*dev
= node
->minor
->dev
;
79 const struct intel_device_info
*info
= INTEL_INFO(dev
);
81 seq_printf(m
, "gen: %d\n", info
->gen
);
82 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
92 static const char get_active_flag(struct drm_i915_gem_object
*obj
)
94 return obj
->active
? '*' : ' ';
97 static const char get_pin_flag(struct drm_i915_gem_object
*obj
)
99 return obj
->pin_display
? 'p' : ' ';
102 static const char get_tiling_flag(struct drm_i915_gem_object
*obj
)
104 switch (obj
->tiling_mode
) {
106 case I915_TILING_NONE
: return ' ';
107 case I915_TILING_X
: return 'X';
108 case I915_TILING_Y
: return 'Y';
112 static inline const char get_global_flag(struct drm_i915_gem_object
*obj
)
114 return i915_gem_obj_to_ggtt(obj
) ? 'g' : ' ';
117 static inline const char get_pin_mapped_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->mapping
? 'M' : ' ';
122 static u64
i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
127 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
128 if (vma
->is_ggtt
&& drm_mm_node_allocated(&vma
->node
))
129 size
+= vma
->node
.size
;
136 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
138 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
139 struct intel_engine_cs
*engine
;
140 struct i915_vma
*vma
;
142 enum intel_engine_id id
;
144 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
146 seq_printf(m
, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
148 get_active_flag(obj
),
150 get_tiling_flag(obj
),
151 get_global_flag(obj
),
152 get_pin_mapped_flag(obj
),
153 obj
->base
.size
/ 1024,
154 obj
->base
.read_domains
,
155 obj
->base
.write_domain
);
156 for_each_engine_id(engine
, dev_priv
, id
)
158 i915_gem_request_get_seqno(obj
->last_read_req
[id
]));
159 seq_printf(m
, "] %x %x%s%s%s",
160 i915_gem_request_get_seqno(obj
->last_write_req
),
161 i915_gem_request_get_seqno(obj
->last_fenced_req
),
162 i915_cache_level_str(to_i915(obj
->base
.dev
), obj
->cache_level
),
163 obj
->dirty
? " dirty" : "",
164 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
166 seq_printf(m
, " (name: %d)", obj
->base
.name
);
167 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
168 if (vma
->pin_count
> 0)
171 seq_printf(m
, " (pinned x %d)", pin_count
);
172 if (obj
->pin_display
)
173 seq_printf(m
, " (display)");
174 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
175 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
176 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
177 seq_printf(m
, " (%sgtt offset: %08llx, size: %08llx",
178 vma
->is_ggtt
? "g" : "pp",
179 vma
->node
.start
, vma
->node
.size
);
181 seq_printf(m
, ", type: %u", vma
->ggtt_view
.type
);
185 seq_printf(m
, " (stolen: %08llx)", obj
->stolen
->start
);
186 if (obj
->pin_display
|| obj
->fault_mappable
) {
188 if (obj
->pin_display
)
190 if (obj
->fault_mappable
)
193 seq_printf(m
, " (%s mappable)", s
);
195 if (obj
->last_write_req
!= NULL
)
196 seq_printf(m
, " (%s)",
197 i915_gem_request_get_engine(obj
->last_write_req
)->name
);
198 if (obj
->frontbuffer_bits
)
199 seq_printf(m
, " (frontbuffer: 0x%03x)", obj
->frontbuffer_bits
);
202 static void describe_ctx(struct seq_file
*m
, struct intel_context
*ctx
)
204 seq_putc(m
, ctx
->legacy_hw_ctx
.initialized
? 'I' : 'i');
205 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
209 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
211 struct drm_info_node
*node
= m
->private;
212 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
213 struct list_head
*head
;
214 struct drm_device
*dev
= node
->minor
->dev
;
215 struct drm_i915_private
*dev_priv
= to_i915(dev
);
216 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
217 struct i915_vma
*vma
;
218 u64 total_obj_size
, total_gtt_size
;
221 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
225 /* FIXME: the user of this interface might want more than just GGTT */
228 seq_puts(m
, "Active:\n");
229 head
= &ggtt
->base
.active_list
;
232 seq_puts(m
, "Inactive:\n");
233 head
= &ggtt
->base
.inactive_list
;
236 mutex_unlock(&dev
->struct_mutex
);
240 total_obj_size
= total_gtt_size
= count
= 0;
241 list_for_each_entry(vma
, head
, vm_link
) {
243 describe_obj(m
, vma
->obj
);
245 total_obj_size
+= vma
->obj
->base
.size
;
246 total_gtt_size
+= vma
->node
.size
;
249 mutex_unlock(&dev
->struct_mutex
);
251 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
252 count
, total_obj_size
, total_gtt_size
);
256 static int obj_rank_by_stolen(void *priv
,
257 struct list_head
*A
, struct list_head
*B
)
259 struct drm_i915_gem_object
*a
=
260 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
261 struct drm_i915_gem_object
*b
=
262 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
264 if (a
->stolen
->start
< b
->stolen
->start
)
266 if (a
->stolen
->start
> b
->stolen
->start
)
271 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
273 struct drm_info_node
*node
= m
->private;
274 struct drm_device
*dev
= node
->minor
->dev
;
275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
276 struct drm_i915_gem_object
*obj
;
277 u64 total_obj_size
, total_gtt_size
;
281 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
285 total_obj_size
= total_gtt_size
= count
= 0;
286 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
287 if (obj
->stolen
== NULL
)
290 list_add(&obj
->obj_exec_link
, &stolen
);
292 total_obj_size
+= obj
->base
.size
;
293 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
296 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
297 if (obj
->stolen
== NULL
)
300 list_add(&obj
->obj_exec_link
, &stolen
);
302 total_obj_size
+= obj
->base
.size
;
305 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
306 seq_puts(m
, "Stolen:\n");
307 while (!list_empty(&stolen
)) {
308 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
310 describe_obj(m
, obj
);
312 list_del_init(&obj
->obj_exec_link
);
314 mutex_unlock(&dev
->struct_mutex
);
316 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
317 count
, total_obj_size
, total_gtt_size
);
321 #define count_objects(list, member) do { \
322 list_for_each_entry(obj, list, member) { \
323 size += i915_gem_obj_total_ggtt_size(obj); \
325 if (obj->map_and_fenceable) { \
326 mappable_size += i915_gem_obj_ggtt_size(obj); \
333 struct drm_i915_file_private
*file_priv
;
337 u64 active
, inactive
;
340 static int per_file_stats(int id
, void *ptr
, void *data
)
342 struct drm_i915_gem_object
*obj
= ptr
;
343 struct file_stats
*stats
= data
;
344 struct i915_vma
*vma
;
347 stats
->total
+= obj
->base
.size
;
349 if (obj
->base
.name
|| obj
->base
.dma_buf
)
350 stats
->shared
+= obj
->base
.size
;
352 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
353 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
354 struct i915_hw_ppgtt
*ppgtt
;
356 if (!drm_mm_node_allocated(&vma
->node
))
360 stats
->global
+= obj
->base
.size
;
364 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
365 if (ppgtt
->file_priv
!= stats
->file_priv
)
368 if (obj
->active
) /* XXX per-vma statistic */
369 stats
->active
+= obj
->base
.size
;
371 stats
->inactive
+= obj
->base
.size
;
376 if (i915_gem_obj_ggtt_bound(obj
)) {
377 stats
->global
+= obj
->base
.size
;
379 stats
->active
+= obj
->base
.size
;
381 stats
->inactive
+= obj
->base
.size
;
386 if (!list_empty(&obj
->global_list
))
387 stats
->unbound
+= obj
->base
.size
;
392 #define print_file_stats(m, name, stats) do { \
394 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
405 static void print_batch_pool_stats(struct seq_file
*m
,
406 struct drm_i915_private
*dev_priv
)
408 struct drm_i915_gem_object
*obj
;
409 struct file_stats stats
;
410 struct intel_engine_cs
*engine
;
413 memset(&stats
, 0, sizeof(stats
));
415 for_each_engine(engine
, dev_priv
) {
416 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
417 list_for_each_entry(obj
,
418 &engine
->batch_pool
.cache_list
[j
],
420 per_file_stats(0, obj
, &stats
);
424 print_file_stats(m
, "[k]batch pool", stats
);
427 #define count_vmas(list, member) do { \
428 list_for_each_entry(vma, list, member) { \
429 size += i915_gem_obj_total_ggtt_size(vma->obj); \
431 if (vma->obj->map_and_fenceable) { \
432 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
438 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
440 struct drm_info_node
*node
= m
->private;
441 struct drm_device
*dev
= node
->minor
->dev
;
442 struct drm_i915_private
*dev_priv
= to_i915(dev
);
443 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
444 u32 count
, mappable_count
, purgeable_count
;
445 u64 size
, mappable_size
, purgeable_size
;
446 unsigned long pin_mapped_count
= 0, pin_mapped_purgeable_count
= 0;
447 u64 pin_mapped_size
= 0, pin_mapped_purgeable_size
= 0;
448 struct drm_i915_gem_object
*obj
;
449 struct drm_file
*file
;
450 struct i915_vma
*vma
;
453 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
457 seq_printf(m
, "%u objects, %zu bytes\n",
458 dev_priv
->mm
.object_count
,
459 dev_priv
->mm
.object_memory
);
461 size
= count
= mappable_size
= mappable_count
= 0;
462 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
463 seq_printf(m
, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
464 count
, mappable_count
, size
, mappable_size
);
466 size
= count
= mappable_size
= mappable_count
= 0;
467 count_vmas(&ggtt
->base
.active_list
, vm_link
);
468 seq_printf(m
, " %u [%u] active objects, %llu [%llu] bytes\n",
469 count
, mappable_count
, size
, mappable_size
);
471 size
= count
= mappable_size
= mappable_count
= 0;
472 count_vmas(&ggtt
->base
.inactive_list
, vm_link
);
473 seq_printf(m
, " %u [%u] inactive objects, %llu [%llu] bytes\n",
474 count
, mappable_count
, size
, mappable_size
);
476 size
= count
= purgeable_size
= purgeable_count
= 0;
477 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
478 size
+= obj
->base
.size
, ++count
;
479 if (obj
->madv
== I915_MADV_DONTNEED
)
480 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
483 pin_mapped_size
+= obj
->base
.size
;
484 if (obj
->pages_pin_count
== 0) {
485 pin_mapped_purgeable_count
++;
486 pin_mapped_purgeable_size
+= obj
->base
.size
;
490 seq_printf(m
, "%u unbound objects, %llu bytes\n", count
, size
);
492 size
= count
= mappable_size
= mappable_count
= 0;
493 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
494 if (obj
->fault_mappable
) {
495 size
+= i915_gem_obj_ggtt_size(obj
);
498 if (obj
->pin_display
) {
499 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
502 if (obj
->madv
== I915_MADV_DONTNEED
) {
503 purgeable_size
+= obj
->base
.size
;
508 pin_mapped_size
+= obj
->base
.size
;
509 if (obj
->pages_pin_count
== 0) {
510 pin_mapped_purgeable_count
++;
511 pin_mapped_purgeable_size
+= obj
->base
.size
;
515 seq_printf(m
, "%u purgeable objects, %llu bytes\n",
516 purgeable_count
, purgeable_size
);
517 seq_printf(m
, "%u pinned mappable objects, %llu bytes\n",
518 mappable_count
, mappable_size
);
519 seq_printf(m
, "%u fault mappable objects, %llu bytes\n",
522 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
523 pin_mapped_count
, pin_mapped_purgeable_count
,
524 pin_mapped_size
, pin_mapped_purgeable_size
);
526 seq_printf(m
, "%llu [%llu] gtt total\n",
527 ggtt
->base
.total
, ggtt
->mappable_end
- ggtt
->base
.start
);
530 print_batch_pool_stats(m
, dev_priv
);
532 mutex_unlock(&dev
->struct_mutex
);
534 mutex_lock(&dev
->filelist_mutex
);
535 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
536 struct file_stats stats
;
537 struct task_struct
*task
;
539 memset(&stats
, 0, sizeof(stats
));
540 stats
.file_priv
= file
->driver_priv
;
541 spin_lock(&file
->table_lock
);
542 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
543 spin_unlock(&file
->table_lock
);
545 * Although we have a valid reference on file->pid, that does
546 * not guarantee that the task_struct who called get_pid() is
547 * still alive (e.g. get_pid(current) => fork() => exit()).
548 * Therefore, we need to protect this ->comm access using RCU.
551 task
= pid_task(file
->pid
, PIDTYPE_PID
);
552 print_file_stats(m
, task
? task
->comm
: "<unknown>", stats
);
555 mutex_unlock(&dev
->filelist_mutex
);
560 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
562 struct drm_info_node
*node
= m
->private;
563 struct drm_device
*dev
= node
->minor
->dev
;
564 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 struct drm_i915_gem_object
*obj
;
567 u64 total_obj_size
, total_gtt_size
;
570 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
574 total_obj_size
= total_gtt_size
= count
= 0;
575 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
576 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
580 describe_obj(m
, obj
);
582 total_obj_size
+= obj
->base
.size
;
583 total_gtt_size
+= i915_gem_obj_total_ggtt_size(obj
);
587 mutex_unlock(&dev
->struct_mutex
);
589 seq_printf(m
, "Total %d objects, %llu bytes, %llu GTT size\n",
590 count
, total_obj_size
, total_gtt_size
);
595 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
597 struct drm_info_node
*node
= m
->private;
598 struct drm_device
*dev
= node
->minor
->dev
;
599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
600 struct intel_crtc
*crtc
;
603 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
607 for_each_intel_crtc(dev
, crtc
) {
608 const char pipe
= pipe_name(crtc
->pipe
);
609 const char plane
= plane_name(crtc
->plane
);
610 struct intel_unpin_work
*work
;
612 spin_lock_irq(&dev
->event_lock
);
613 work
= crtc
->unpin_work
;
615 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
620 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
621 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
624 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
627 if (work
->flip_queued_req
) {
628 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(work
->flip_queued_req
);
630 seq_printf(m
, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
632 i915_gem_request_get_seqno(work
->flip_queued_req
),
633 dev_priv
->next_seqno
,
634 engine
->get_seqno(engine
),
635 i915_gem_request_completed(work
->flip_queued_req
, true));
637 seq_printf(m
, "Flip not associated with any ring\n");
638 seq_printf(m
, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
639 work
->flip_queued_vblank
,
640 work
->flip_ready_vblank
,
641 drm_crtc_vblank_count(&crtc
->base
));
642 if (work
->enable_stall_check
)
643 seq_puts(m
, "Stall check enabled, ");
645 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
646 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
648 if (INTEL_INFO(dev
)->gen
>= 4)
649 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(crtc
->plane
)));
651 addr
= I915_READ(DSPADDR(crtc
->plane
));
652 seq_printf(m
, "Current scanout address 0x%08x\n", addr
);
654 if (work
->pending_flip_obj
) {
655 seq_printf(m
, "New framebuffer address 0x%08lx\n", (long)work
->gtt_offset
);
656 seq_printf(m
, "MMIO update completed? %d\n", addr
== work
->gtt_offset
);
659 spin_unlock_irq(&dev
->event_lock
);
662 mutex_unlock(&dev
->struct_mutex
);
667 static int i915_gem_batch_pool_info(struct seq_file
*m
, void *data
)
669 struct drm_info_node
*node
= m
->private;
670 struct drm_device
*dev
= node
->minor
->dev
;
671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
672 struct drm_i915_gem_object
*obj
;
673 struct intel_engine_cs
*engine
;
677 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
681 for_each_engine(engine
, dev_priv
) {
682 for (j
= 0; j
< ARRAY_SIZE(engine
->batch_pool
.cache_list
); j
++) {
686 list_for_each_entry(obj
,
687 &engine
->batch_pool
.cache_list
[j
],
690 seq_printf(m
, "%s cache[%d]: %d objects\n",
691 engine
->name
, j
, count
);
693 list_for_each_entry(obj
,
694 &engine
->batch_pool
.cache_list
[j
],
697 describe_obj(m
, obj
);
705 seq_printf(m
, "total: %d\n", total
);
707 mutex_unlock(&dev
->struct_mutex
);
712 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
714 struct drm_info_node
*node
= m
->private;
715 struct drm_device
*dev
= node
->minor
->dev
;
716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
717 struct intel_engine_cs
*engine
;
718 struct drm_i915_gem_request
*req
;
721 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
726 for_each_engine(engine
, dev_priv
) {
730 list_for_each_entry(req
, &engine
->request_list
, list
)
735 seq_printf(m
, "%s requests: %d\n", engine
->name
, count
);
736 list_for_each_entry(req
, &engine
->request_list
, list
) {
737 struct task_struct
*task
;
742 task
= pid_task(req
->pid
, PIDTYPE_PID
);
743 seq_printf(m
, " %x @ %d: %s [%d]\n",
745 (int) (jiffies
- req
->emitted_jiffies
),
746 task
? task
->comm
: "<unknown>",
747 task
? task
->pid
: -1);
753 mutex_unlock(&dev
->struct_mutex
);
756 seq_puts(m
, "No requests\n");
761 static void i915_ring_seqno_info(struct seq_file
*m
,
762 struct intel_engine_cs
*engine
)
764 seq_printf(m
, "Current sequence (%s): %x\n",
765 engine
->name
, engine
->get_seqno(engine
));
766 seq_printf(m
, "Current user interrupts (%s): %x\n",
767 engine
->name
, READ_ONCE(engine
->user_interrupts
));
770 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
772 struct drm_info_node
*node
= m
->private;
773 struct drm_device
*dev
= node
->minor
->dev
;
774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
775 struct intel_engine_cs
*engine
;
778 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
781 intel_runtime_pm_get(dev_priv
);
783 for_each_engine(engine
, dev_priv
)
784 i915_ring_seqno_info(m
, engine
);
786 intel_runtime_pm_put(dev_priv
);
787 mutex_unlock(&dev
->struct_mutex
);
793 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
795 struct drm_info_node
*node
= m
->private;
796 struct drm_device
*dev
= node
->minor
->dev
;
797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
798 struct intel_engine_cs
*engine
;
801 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
804 intel_runtime_pm_get(dev_priv
);
806 if (IS_CHERRYVIEW(dev
)) {
807 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
808 I915_READ(GEN8_MASTER_IRQ
));
810 seq_printf(m
, "Display IER:\t%08x\n",
812 seq_printf(m
, "Display IIR:\t%08x\n",
814 seq_printf(m
, "Display IIR_RW:\t%08x\n",
815 I915_READ(VLV_IIR_RW
));
816 seq_printf(m
, "Display IMR:\t%08x\n",
818 for_each_pipe(dev_priv
, pipe
)
819 seq_printf(m
, "Pipe %c stat:\t%08x\n",
821 I915_READ(PIPESTAT(pipe
)));
823 seq_printf(m
, "Port hotplug:\t%08x\n",
824 I915_READ(PORT_HOTPLUG_EN
));
825 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
826 I915_READ(VLV_DPFLIPSTAT
));
827 seq_printf(m
, "DPINVGTT:\t%08x\n",
828 I915_READ(DPINVGTT
));
830 for (i
= 0; i
< 4; i
++) {
831 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
832 i
, I915_READ(GEN8_GT_IMR(i
)));
833 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
834 i
, I915_READ(GEN8_GT_IIR(i
)));
835 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
836 i
, I915_READ(GEN8_GT_IER(i
)));
839 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
840 I915_READ(GEN8_PCU_IMR
));
841 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
842 I915_READ(GEN8_PCU_IIR
));
843 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
844 I915_READ(GEN8_PCU_IER
));
845 } else if (INTEL_INFO(dev
)->gen
>= 8) {
846 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
847 I915_READ(GEN8_MASTER_IRQ
));
849 for (i
= 0; i
< 4; i
++) {
850 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
851 i
, I915_READ(GEN8_GT_IMR(i
)));
852 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
853 i
, I915_READ(GEN8_GT_IIR(i
)));
854 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
855 i
, I915_READ(GEN8_GT_IER(i
)));
858 for_each_pipe(dev_priv
, pipe
) {
859 enum intel_display_power_domain power_domain
;
861 power_domain
= POWER_DOMAIN_PIPE(pipe
);
862 if (!intel_display_power_get_if_enabled(dev_priv
,
864 seq_printf(m
, "Pipe %c power disabled\n",
868 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
870 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
871 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
873 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
874 seq_printf(m
, "Pipe %c IER:\t%08x\n",
876 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
878 intel_display_power_put(dev_priv
, power_domain
);
881 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
882 I915_READ(GEN8_DE_PORT_IMR
));
883 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
884 I915_READ(GEN8_DE_PORT_IIR
));
885 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
886 I915_READ(GEN8_DE_PORT_IER
));
888 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
889 I915_READ(GEN8_DE_MISC_IMR
));
890 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
891 I915_READ(GEN8_DE_MISC_IIR
));
892 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
893 I915_READ(GEN8_DE_MISC_IER
));
895 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
896 I915_READ(GEN8_PCU_IMR
));
897 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
898 I915_READ(GEN8_PCU_IIR
));
899 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
900 I915_READ(GEN8_PCU_IER
));
901 } else if (IS_VALLEYVIEW(dev
)) {
902 seq_printf(m
, "Display IER:\t%08x\n",
904 seq_printf(m
, "Display IIR:\t%08x\n",
906 seq_printf(m
, "Display IIR_RW:\t%08x\n",
907 I915_READ(VLV_IIR_RW
));
908 seq_printf(m
, "Display IMR:\t%08x\n",
910 for_each_pipe(dev_priv
, pipe
)
911 seq_printf(m
, "Pipe %c stat:\t%08x\n",
913 I915_READ(PIPESTAT(pipe
)));
915 seq_printf(m
, "Master IER:\t%08x\n",
916 I915_READ(VLV_MASTER_IER
));
918 seq_printf(m
, "Render IER:\t%08x\n",
920 seq_printf(m
, "Render IIR:\t%08x\n",
922 seq_printf(m
, "Render IMR:\t%08x\n",
925 seq_printf(m
, "PM IER:\t\t%08x\n",
926 I915_READ(GEN6_PMIER
));
927 seq_printf(m
, "PM IIR:\t\t%08x\n",
928 I915_READ(GEN6_PMIIR
));
929 seq_printf(m
, "PM IMR:\t\t%08x\n",
930 I915_READ(GEN6_PMIMR
));
932 seq_printf(m
, "Port hotplug:\t%08x\n",
933 I915_READ(PORT_HOTPLUG_EN
));
934 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
935 I915_READ(VLV_DPFLIPSTAT
));
936 seq_printf(m
, "DPINVGTT:\t%08x\n",
937 I915_READ(DPINVGTT
));
939 } else if (!HAS_PCH_SPLIT(dev
)) {
940 seq_printf(m
, "Interrupt enable: %08x\n",
942 seq_printf(m
, "Interrupt identity: %08x\n",
944 seq_printf(m
, "Interrupt mask: %08x\n",
946 for_each_pipe(dev_priv
, pipe
)
947 seq_printf(m
, "Pipe %c stat: %08x\n",
949 I915_READ(PIPESTAT(pipe
)));
951 seq_printf(m
, "North Display Interrupt enable: %08x\n",
953 seq_printf(m
, "North Display Interrupt identity: %08x\n",
955 seq_printf(m
, "North Display Interrupt mask: %08x\n",
957 seq_printf(m
, "South Display Interrupt enable: %08x\n",
959 seq_printf(m
, "South Display Interrupt identity: %08x\n",
961 seq_printf(m
, "South Display Interrupt mask: %08x\n",
963 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
965 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
967 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
970 for_each_engine(engine
, dev_priv
) {
971 if (INTEL_INFO(dev
)->gen
>= 6) {
973 "Graphics Interrupt mask (%s): %08x\n",
974 engine
->name
, I915_READ_IMR(engine
));
976 i915_ring_seqno_info(m
, engine
);
978 intel_runtime_pm_put(dev_priv
);
979 mutex_unlock(&dev
->struct_mutex
);
984 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
986 struct drm_info_node
*node
= m
->private;
987 struct drm_device
*dev
= node
->minor
->dev
;
988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
991 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
995 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
996 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
997 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
999 seq_printf(m
, "Fence %d, pin count = %d, object = ",
1000 i
, dev_priv
->fence_regs
[i
].pin_count
);
1002 seq_puts(m
, "unused");
1004 describe_obj(m
, obj
);
1008 mutex_unlock(&dev
->struct_mutex
);
1012 static int i915_hws_info(struct seq_file
*m
, void *data
)
1014 struct drm_info_node
*node
= m
->private;
1015 struct drm_device
*dev
= node
->minor
->dev
;
1016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1017 struct intel_engine_cs
*engine
;
1021 engine
= &dev_priv
->engine
[(uintptr_t)node
->info_ent
->data
];
1022 hws
= engine
->status_page
.page_addr
;
1026 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
1027 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1029 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
1035 i915_error_state_write(struct file
*filp
,
1036 const char __user
*ubuf
,
1040 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
1041 struct drm_device
*dev
= error_priv
->dev
;
1044 DRM_DEBUG_DRIVER("Resetting error state\n");
1046 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1050 i915_destroy_error_state(dev
);
1051 mutex_unlock(&dev
->struct_mutex
);
1056 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
1058 struct drm_device
*dev
= inode
->i_private
;
1059 struct i915_error_state_file_priv
*error_priv
;
1061 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
1065 error_priv
->dev
= dev
;
1067 i915_error_state_get(dev
, error_priv
);
1069 file
->private_data
= error_priv
;
1074 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
1076 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1078 i915_error_state_put(error_priv
);
1084 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
1085 size_t count
, loff_t
*pos
)
1087 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
1088 struct drm_i915_error_state_buf error_str
;
1090 ssize_t ret_count
= 0;
1093 ret
= i915_error_state_buf_init(&error_str
, to_i915(error_priv
->dev
), count
, *pos
);
1097 ret
= i915_error_state_to_str(&error_str
, error_priv
);
1101 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
1108 *pos
= error_str
.start
+ ret_count
;
1110 i915_error_state_buf_release(&error_str
);
1111 return ret
?: ret_count
;
1114 static const struct file_operations i915_error_state_fops
= {
1115 .owner
= THIS_MODULE
,
1116 .open
= i915_error_state_open
,
1117 .read
= i915_error_state_read
,
1118 .write
= i915_error_state_write
,
1119 .llseek
= default_llseek
,
1120 .release
= i915_error_state_release
,
1124 i915_next_seqno_get(void *data
, u64
*val
)
1126 struct drm_device
*dev
= data
;
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1130 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1134 *val
= dev_priv
->next_seqno
;
1135 mutex_unlock(&dev
->struct_mutex
);
1141 i915_next_seqno_set(void *data
, u64 val
)
1143 struct drm_device
*dev
= data
;
1146 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1150 ret
= i915_gem_set_seqno(dev
, val
);
1151 mutex_unlock(&dev
->struct_mutex
);
1156 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
1157 i915_next_seqno_get
, i915_next_seqno_set
,
1160 static int i915_frequency_info(struct seq_file
*m
, void *unused
)
1162 struct drm_info_node
*node
= m
->private;
1163 struct drm_device
*dev
= node
->minor
->dev
;
1164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1167 intel_runtime_pm_get(dev_priv
);
1169 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1172 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
1173 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
1175 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
1176 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
1177 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
1179 seq_printf(m
, "Current P-state: %d\n",
1180 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
1181 } else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
)) {
1184 mutex_lock(&dev_priv
->rps
.hw_lock
);
1185 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1186 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1187 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1189 seq_printf(m
, "actual GPU freq: %d MHz\n",
1190 intel_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1192 seq_printf(m
, "current GPU freq: %d MHz\n",
1193 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1195 seq_printf(m
, "max GPU freq: %d MHz\n",
1196 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1198 seq_printf(m
, "min GPU freq: %d MHz\n",
1199 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1201 seq_printf(m
, "idle GPU freq: %d MHz\n",
1202 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1205 "efficient (RPe) frequency: %d MHz\n",
1206 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1207 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1208 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1209 u32 rp_state_limits
;
1212 u32 rpmodectl
, rpinclimit
, rpdeclimit
;
1213 u32 rpstat
, cagf
, reqf
;
1214 u32 rpupei
, rpcurup
, rpprevup
;
1215 u32 rpdownei
, rpcurdown
, rpprevdown
;
1216 u32 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
;
1219 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
1220 if (IS_BROXTON(dev
)) {
1221 rp_state_cap
= I915_READ(BXT_RP_STATE_CAP
);
1222 gt_perf_status
= I915_READ(BXT_GT_PERF_STATUS
);
1224 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
1225 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
1228 /* RPSTAT1 is in the GT power well */
1229 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1233 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
1235 reqf
= I915_READ(GEN6_RPNSWREQ
);
1239 reqf
&= ~GEN6_TURBO_DISABLE
;
1240 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1245 reqf
= intel_gpu_freq(dev_priv
, reqf
);
1247 rpmodectl
= I915_READ(GEN6_RP_CONTROL
);
1248 rpinclimit
= I915_READ(GEN6_RP_UP_THRESHOLD
);
1249 rpdeclimit
= I915_READ(GEN6_RP_DOWN_THRESHOLD
);
1251 rpstat
= I915_READ(GEN6_RPSTAT1
);
1252 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
) & GEN6_CURICONT_MASK
;
1253 rpcurup
= I915_READ(GEN6_RP_CUR_UP
) & GEN6_CURBSYTAVG_MASK
;
1254 rpprevup
= I915_READ(GEN6_RP_PREV_UP
) & GEN6_CURBSYTAVG_MASK
;
1255 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
) & GEN6_CURIAVG_MASK
;
1256 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1257 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
) & GEN6_CURBSYTAVG_MASK
;
1259 cagf
= (rpstat
& GEN9_CAGF_MASK
) >> GEN9_CAGF_SHIFT
;
1260 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1261 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1263 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1264 cagf
= intel_gpu_freq(dev_priv
, cagf
);
1266 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
1267 mutex_unlock(&dev
->struct_mutex
);
1269 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
1270 pm_ier
= I915_READ(GEN6_PMIER
);
1271 pm_imr
= I915_READ(GEN6_PMIMR
);
1272 pm_isr
= I915_READ(GEN6_PMISR
);
1273 pm_iir
= I915_READ(GEN6_PMIIR
);
1274 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1276 pm_ier
= I915_READ(GEN8_GT_IER(2));
1277 pm_imr
= I915_READ(GEN8_GT_IMR(2));
1278 pm_isr
= I915_READ(GEN8_GT_ISR(2));
1279 pm_iir
= I915_READ(GEN8_GT_IIR(2));
1280 pm_mask
= I915_READ(GEN6_PMINTRMSK
);
1282 seq_printf(m
, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1283 pm_ier
, pm_imr
, pm_isr
, pm_iir
, pm_mask
);
1284 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1285 seq_printf(m
, "Render p-state ratio: %d\n",
1286 (gt_perf_status
& (IS_GEN9(dev
) ? 0x1ff00 : 0xff00)) >> 8);
1287 seq_printf(m
, "Render p-state VID: %d\n",
1288 gt_perf_status
& 0xff);
1289 seq_printf(m
, "Render p-state limit: %d\n",
1290 rp_state_limits
& 0xff);
1291 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1292 seq_printf(m
, "RPMODECTL: 0x%08x\n", rpmodectl
);
1293 seq_printf(m
, "RPINCLIMIT: 0x%08x\n", rpinclimit
);
1294 seq_printf(m
, "RPDECLIMIT: 0x%08x\n", rpdeclimit
);
1295 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1296 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1297 seq_printf(m
, "RP CUR UP EI: %d (%dus)\n",
1298 rpupei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpupei
));
1299 seq_printf(m
, "RP CUR UP: %d (%dus)\n",
1300 rpcurup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurup
));
1301 seq_printf(m
, "RP PREV UP: %d (%dus)\n",
1302 rpprevup
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevup
));
1303 seq_printf(m
, "Up threshold: %d%%\n",
1304 dev_priv
->rps
.up_threshold
);
1306 seq_printf(m
, "RP CUR DOWN EI: %d (%dus)\n",
1307 rpdownei
, GT_PM_INTERVAL_TO_US(dev_priv
, rpdownei
));
1308 seq_printf(m
, "RP CUR DOWN: %d (%dus)\n",
1309 rpcurdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpcurdown
));
1310 seq_printf(m
, "RP PREV DOWN: %d (%dus)\n",
1311 rpprevdown
, GT_PM_INTERVAL_TO_US(dev_priv
, rpprevdown
));
1312 seq_printf(m
, "Down threshold: %d%%\n",
1313 dev_priv
->rps
.down_threshold
);
1315 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 0 :
1316 rp_state_cap
>> 16) & 0xff;
1317 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1318 GEN9_FREQ_SCALER
: 1);
1319 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1320 intel_gpu_freq(dev_priv
, max_freq
));
1322 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1323 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1324 GEN9_FREQ_SCALER
: 1);
1325 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1326 intel_gpu_freq(dev_priv
, max_freq
));
1328 max_freq
= (IS_BROXTON(dev
) ? rp_state_cap
>> 16 :
1329 rp_state_cap
>> 0) & 0xff;
1330 max_freq
*= (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1331 GEN9_FREQ_SCALER
: 1);
1332 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1333 intel_gpu_freq(dev_priv
, max_freq
));
1334 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1335 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1337 seq_printf(m
, "Current freq: %d MHz\n",
1338 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
));
1339 seq_printf(m
, "Actual freq: %d MHz\n", cagf
);
1340 seq_printf(m
, "Idle freq: %d MHz\n",
1341 intel_gpu_freq(dev_priv
, dev_priv
->rps
.idle_freq
));
1342 seq_printf(m
, "Min freq: %d MHz\n",
1343 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
));
1344 seq_printf(m
, "Max freq: %d MHz\n",
1345 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
1347 "efficient (RPe) frequency: %d MHz\n",
1348 intel_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
));
1350 seq_puts(m
, "no P-state info available\n");
1353 seq_printf(m
, "Current CD clock frequency: %d kHz\n", dev_priv
->cdclk_freq
);
1354 seq_printf(m
, "Max CD clock frequency: %d kHz\n", dev_priv
->max_cdclk_freq
);
1355 seq_printf(m
, "Max pixel clock frequency: %d kHz\n", dev_priv
->max_dotclk_freq
);
1358 intel_runtime_pm_put(dev_priv
);
1362 static int i915_hangcheck_info(struct seq_file
*m
, void *unused
)
1364 struct drm_info_node
*node
= m
->private;
1365 struct drm_device
*dev
= node
->minor
->dev
;
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1367 struct intel_engine_cs
*engine
;
1368 u64 acthd
[I915_NUM_ENGINES
];
1369 u32 seqno
[I915_NUM_ENGINES
];
1370 u32 instdone
[I915_NUM_INSTDONE_REG
];
1371 enum intel_engine_id id
;
1374 if (!i915
.enable_hangcheck
) {
1375 seq_printf(m
, "Hangcheck disabled\n");
1379 intel_runtime_pm_get(dev_priv
);
1381 for_each_engine_id(engine
, dev_priv
, id
) {
1382 acthd
[id
] = intel_ring_get_active_head(engine
);
1383 seqno
[id
] = engine
->get_seqno(engine
);
1386 i915_get_extra_instdone(dev
, instdone
);
1388 intel_runtime_pm_put(dev_priv
);
1390 if (delayed_work_pending(&dev_priv
->gpu_error
.hangcheck_work
)) {
1391 seq_printf(m
, "Hangcheck active, fires in %dms\n",
1392 jiffies_to_msecs(dev_priv
->gpu_error
.hangcheck_work
.timer
.expires
-
1395 seq_printf(m
, "Hangcheck inactive\n");
1397 for_each_engine_id(engine
, dev_priv
, id
) {
1398 seq_printf(m
, "%s:\n", engine
->name
);
1399 seq_printf(m
, "\tseqno = %x [current %x, last %x]\n",
1400 engine
->hangcheck
.seqno
,
1402 engine
->last_submitted_seqno
);
1403 seq_printf(m
, "\tuser interrupts = %x [current %x]\n",
1404 engine
->hangcheck
.user_interrupts
,
1405 READ_ONCE(engine
->user_interrupts
));
1406 seq_printf(m
, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1407 (long long)engine
->hangcheck
.acthd
,
1408 (long long)acthd
[id
]);
1409 seq_printf(m
, "\tscore = %d\n", engine
->hangcheck
.score
);
1410 seq_printf(m
, "\taction = %d\n", engine
->hangcheck
.action
);
1412 if (engine
->id
== RCS
) {
1413 seq_puts(m
, "\tinstdone read =");
1415 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1416 seq_printf(m
, " 0x%08x", instdone
[j
]);
1418 seq_puts(m
, "\n\tinstdone accu =");
1420 for (j
= 0; j
< I915_NUM_INSTDONE_REG
; j
++)
1421 seq_printf(m
, " 0x%08x",
1422 engine
->hangcheck
.instdone
[j
]);
1431 static int ironlake_drpc_info(struct seq_file
*m
)
1433 struct drm_info_node
*node
= m
->private;
1434 struct drm_device
*dev
= node
->minor
->dev
;
1435 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1436 u32 rgvmodectl
, rstdbyctl
;
1440 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1443 intel_runtime_pm_get(dev_priv
);
1445 rgvmodectl
= I915_READ(MEMMODECTL
);
1446 rstdbyctl
= I915_READ(RSTDBYCTL
);
1447 crstandvid
= I915_READ16(CRSTANDVID
);
1449 intel_runtime_pm_put(dev_priv
);
1450 mutex_unlock(&dev
->struct_mutex
);
1452 seq_printf(m
, "HD boost: %s\n", yesno(rgvmodectl
& MEMMODE_BOOST_EN
));
1453 seq_printf(m
, "Boost freq: %d\n",
1454 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1455 MEMMODE_BOOST_FREQ_SHIFT
);
1456 seq_printf(m
, "HW control enabled: %s\n",
1457 yesno(rgvmodectl
& MEMMODE_HWIDLE_EN
));
1458 seq_printf(m
, "SW control enabled: %s\n",
1459 yesno(rgvmodectl
& MEMMODE_SWMODE_EN
));
1460 seq_printf(m
, "Gated voltage change: %s\n",
1461 yesno(rgvmodectl
& MEMMODE_RCLK_GATE
));
1462 seq_printf(m
, "Starting frequency: P%d\n",
1463 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1464 seq_printf(m
, "Max P-state: P%d\n",
1465 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1466 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1467 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1468 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1469 seq_printf(m
, "Render standby enabled: %s\n",
1470 yesno(!(rstdbyctl
& RCX_SW_EXIT
)));
1471 seq_puts(m
, "Current RS state: ");
1472 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1474 seq_puts(m
, "on\n");
1476 case RSX_STATUS_RC1
:
1477 seq_puts(m
, "RC1\n");
1479 case RSX_STATUS_RC1E
:
1480 seq_puts(m
, "RC1E\n");
1482 case RSX_STATUS_RS1
:
1483 seq_puts(m
, "RS1\n");
1485 case RSX_STATUS_RS2
:
1486 seq_puts(m
, "RS2 (RC6)\n");
1488 case RSX_STATUS_RS3
:
1489 seq_puts(m
, "RC3 (RC6+)\n");
1492 seq_puts(m
, "unknown\n");
1499 static int i915_forcewake_domains(struct seq_file
*m
, void *data
)
1501 struct drm_info_node
*node
= m
->private;
1502 struct drm_device
*dev
= node
->minor
->dev
;
1503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1504 struct intel_uncore_forcewake_domain
*fw_domain
;
1506 spin_lock_irq(&dev_priv
->uncore
.lock
);
1507 for_each_fw_domain(fw_domain
, dev_priv
) {
1508 seq_printf(m
, "%s.wake_count = %u\n",
1509 intel_uncore_forcewake_domain_to_str(fw_domain
->id
),
1510 fw_domain
->wake_count
);
1512 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1517 static int vlv_drpc_info(struct seq_file
*m
)
1519 struct drm_info_node
*node
= m
->private;
1520 struct drm_device
*dev
= node
->minor
->dev
;
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1522 u32 rpmodectl1
, rcctl1
, pw_status
;
1524 intel_runtime_pm_get(dev_priv
);
1526 pw_status
= I915_READ(VLV_GTLC_PW_STATUS
);
1527 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1528 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1530 intel_runtime_pm_put(dev_priv
);
1532 seq_printf(m
, "Video Turbo Mode: %s\n",
1533 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1534 seq_printf(m
, "Turbo enabled: %s\n",
1535 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1536 seq_printf(m
, "HW control enabled: %s\n",
1537 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1538 seq_printf(m
, "SW control enabled: %s\n",
1539 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1540 GEN6_RP_MEDIA_SW_MODE
));
1541 seq_printf(m
, "RC6 Enabled: %s\n",
1542 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1543 GEN6_RC_CTL_EI_MODE(1))));
1544 seq_printf(m
, "Render Power Well: %s\n",
1545 (pw_status
& VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1546 seq_printf(m
, "Media Power Well: %s\n",
1547 (pw_status
& VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1549 seq_printf(m
, "Render RC6 residency since boot: %u\n",
1550 I915_READ(VLV_GT_RENDER_RC6
));
1551 seq_printf(m
, "Media RC6 residency since boot: %u\n",
1552 I915_READ(VLV_GT_MEDIA_RC6
));
1554 return i915_forcewake_domains(m
, NULL
);
1557 static int gen6_drpc_info(struct seq_file
*m
)
1559 struct drm_info_node
*node
= m
->private;
1560 struct drm_device
*dev
= node
->minor
->dev
;
1561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1562 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1563 unsigned forcewake_count
;
1566 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1569 intel_runtime_pm_get(dev_priv
);
1571 spin_lock_irq(&dev_priv
->uncore
.lock
);
1572 forcewake_count
= dev_priv
->uncore
.fw_domain
[FW_DOMAIN_ID_RENDER
].wake_count
;
1573 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1575 if (forcewake_count
) {
1576 seq_puts(m
, "RC information inaccurate because somebody "
1577 "holds a forcewake reference \n");
1579 /* NB: we cannot use forcewake, else we read the wrong values */
1580 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1582 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1585 gt_core_status
= I915_READ_FW(GEN6_GT_CORE_STATUS
);
1586 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1588 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1589 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1590 mutex_unlock(&dev
->struct_mutex
);
1591 mutex_lock(&dev_priv
->rps
.hw_lock
);
1592 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1593 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1595 intel_runtime_pm_put(dev_priv
);
1597 seq_printf(m
, "Video Turbo Mode: %s\n",
1598 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1599 seq_printf(m
, "HW control enabled: %s\n",
1600 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1601 seq_printf(m
, "SW control enabled: %s\n",
1602 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1603 GEN6_RP_MEDIA_SW_MODE
));
1604 seq_printf(m
, "RC1e Enabled: %s\n",
1605 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1606 seq_printf(m
, "RC6 Enabled: %s\n",
1607 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1608 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1609 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1610 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1611 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1612 seq_puts(m
, "Current RC state: ");
1613 switch (gt_core_status
& GEN6_RCn_MASK
) {
1615 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1616 seq_puts(m
, "Core Power Down\n");
1618 seq_puts(m
, "on\n");
1621 seq_puts(m
, "RC3\n");
1624 seq_puts(m
, "RC6\n");
1627 seq_puts(m
, "RC7\n");
1630 seq_puts(m
, "Unknown\n");
1634 seq_printf(m
, "Core Power Down: %s\n",
1635 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1637 /* Not exactly sure what this is */
1638 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1639 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1640 seq_printf(m
, "RC6 residency since boot: %u\n",
1641 I915_READ(GEN6_GT_GFX_RC6
));
1642 seq_printf(m
, "RC6+ residency since boot: %u\n",
1643 I915_READ(GEN6_GT_GFX_RC6p
));
1644 seq_printf(m
, "RC6++ residency since boot: %u\n",
1645 I915_READ(GEN6_GT_GFX_RC6pp
));
1647 seq_printf(m
, "RC6 voltage: %dmV\n",
1648 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1649 seq_printf(m
, "RC6+ voltage: %dmV\n",
1650 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1651 seq_printf(m
, "RC6++ voltage: %dmV\n",
1652 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1656 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1658 struct drm_info_node
*node
= m
->private;
1659 struct drm_device
*dev
= node
->minor
->dev
;
1661 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1662 return vlv_drpc_info(m
);
1663 else if (INTEL_INFO(dev
)->gen
>= 6)
1664 return gen6_drpc_info(m
);
1666 return ironlake_drpc_info(m
);
1669 static int i915_frontbuffer_tracking(struct seq_file
*m
, void *unused
)
1671 struct drm_info_node
*node
= m
->private;
1672 struct drm_device
*dev
= node
->minor
->dev
;
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1675 seq_printf(m
, "FB tracking busy bits: 0x%08x\n",
1676 dev_priv
->fb_tracking
.busy_bits
);
1678 seq_printf(m
, "FB tracking flip bits: 0x%08x\n",
1679 dev_priv
->fb_tracking
.flip_bits
);
1684 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1686 struct drm_info_node
*node
= m
->private;
1687 struct drm_device
*dev
= node
->minor
->dev
;
1688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1690 if (!HAS_FBC(dev
)) {
1691 seq_puts(m
, "FBC unsupported on this chipset\n");
1695 intel_runtime_pm_get(dev_priv
);
1696 mutex_lock(&dev_priv
->fbc
.lock
);
1698 if (intel_fbc_is_active(dev_priv
))
1699 seq_puts(m
, "FBC enabled\n");
1701 seq_printf(m
, "FBC disabled: %s\n",
1702 dev_priv
->fbc
.no_fbc_reason
);
1704 if (INTEL_INFO(dev_priv
)->gen
>= 7)
1705 seq_printf(m
, "Compressing: %s\n",
1706 yesno(I915_READ(FBC_STATUS2
) &
1707 FBC_COMPRESSION_MASK
));
1709 mutex_unlock(&dev_priv
->fbc
.lock
);
1710 intel_runtime_pm_put(dev_priv
);
1715 static int i915_fbc_fc_get(void *data
, u64
*val
)
1717 struct drm_device
*dev
= data
;
1718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1720 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1723 *val
= dev_priv
->fbc
.false_color
;
1728 static int i915_fbc_fc_set(void *data
, u64 val
)
1730 struct drm_device
*dev
= data
;
1731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1734 if (INTEL_INFO(dev
)->gen
< 7 || !HAS_FBC(dev
))
1737 mutex_lock(&dev_priv
->fbc
.lock
);
1739 reg
= I915_READ(ILK_DPFC_CONTROL
);
1740 dev_priv
->fbc
.false_color
= val
;
1742 I915_WRITE(ILK_DPFC_CONTROL
, val
?
1743 (reg
| FBC_CTL_FALSE_COLOR
) :
1744 (reg
& ~FBC_CTL_FALSE_COLOR
));
1746 mutex_unlock(&dev_priv
->fbc
.lock
);
1750 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops
,
1751 i915_fbc_fc_get
, i915_fbc_fc_set
,
1754 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1756 struct drm_info_node
*node
= m
->private;
1757 struct drm_device
*dev
= node
->minor
->dev
;
1758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1760 if (!HAS_IPS(dev
)) {
1761 seq_puts(m
, "not supported\n");
1765 intel_runtime_pm_get(dev_priv
);
1767 seq_printf(m
, "Enabled by kernel parameter: %s\n",
1768 yesno(i915
.enable_ips
));
1770 if (INTEL_INFO(dev
)->gen
>= 8) {
1771 seq_puts(m
, "Currently: unknown\n");
1773 if (I915_READ(IPS_CTL
) & IPS_ENABLE
)
1774 seq_puts(m
, "Currently: enabled\n");
1776 seq_puts(m
, "Currently: disabled\n");
1779 intel_runtime_pm_put(dev_priv
);
1784 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1786 struct drm_info_node
*node
= m
->private;
1787 struct drm_device
*dev
= node
->minor
->dev
;
1788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1789 bool sr_enabled
= false;
1791 intel_runtime_pm_get(dev_priv
);
1793 if (HAS_PCH_SPLIT(dev
))
1794 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1795 else if (IS_CRESTLINE(dev
) || IS_G4X(dev
) ||
1796 IS_I945G(dev
) || IS_I945GM(dev
))
1797 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1798 else if (IS_I915GM(dev
))
1799 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1800 else if (IS_PINEVIEW(dev
))
1801 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1802 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
1803 sr_enabled
= I915_READ(FW_BLC_SELF_VLV
) & FW_CSPWRDWNEN
;
1805 intel_runtime_pm_put(dev_priv
);
1807 seq_printf(m
, "self-refresh: %s\n",
1808 sr_enabled
? "enabled" : "disabled");
1813 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1815 struct drm_info_node
*node
= m
->private;
1816 struct drm_device
*dev
= node
->minor
->dev
;
1817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1818 unsigned long temp
, chipset
, gfx
;
1824 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1828 temp
= i915_mch_val(dev_priv
);
1829 chipset
= i915_chipset_val(dev_priv
);
1830 gfx
= i915_gfx_val(dev_priv
);
1831 mutex_unlock(&dev
->struct_mutex
);
1833 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1834 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1835 seq_printf(m
, "GFX power: %ld\n", gfx
);
1836 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1841 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1843 struct drm_info_node
*node
= m
->private;
1844 struct drm_device
*dev
= node
->minor
->dev
;
1845 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1847 int gpu_freq
, ia_freq
;
1848 unsigned int max_gpu_freq
, min_gpu_freq
;
1850 if (!HAS_CORE_RING_FREQ(dev
)) {
1851 seq_puts(m
, "unsupported on this chipset\n");
1855 intel_runtime_pm_get(dev_priv
);
1857 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1859 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1863 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
1864 /* Convert GT frequency to 50 HZ units */
1866 dev_priv
->rps
.min_freq_softlimit
/ GEN9_FREQ_SCALER
;
1868 dev_priv
->rps
.max_freq_softlimit
/ GEN9_FREQ_SCALER
;
1870 min_gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1871 max_gpu_freq
= dev_priv
->rps
.max_freq_softlimit
;
1874 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1876 for (gpu_freq
= min_gpu_freq
; gpu_freq
<= max_gpu_freq
; gpu_freq
++) {
1878 sandybridge_pcode_read(dev_priv
,
1879 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1881 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1882 intel_gpu_freq(dev_priv
, (gpu_freq
*
1883 (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
) ?
1884 GEN9_FREQ_SCALER
: 1))),
1885 ((ia_freq
>> 0) & 0xff) * 100,
1886 ((ia_freq
>> 8) & 0xff) * 100);
1889 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1892 intel_runtime_pm_put(dev_priv
);
1896 static int i915_opregion(struct seq_file
*m
, void *unused
)
1898 struct drm_info_node
*node
= m
->private;
1899 struct drm_device
*dev
= node
->minor
->dev
;
1900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1901 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1904 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1908 if (opregion
->header
)
1909 seq_write(m
, opregion
->header
, OPREGION_SIZE
);
1911 mutex_unlock(&dev
->struct_mutex
);
1917 static int i915_vbt(struct seq_file
*m
, void *unused
)
1919 struct drm_info_node
*node
= m
->private;
1920 struct drm_device
*dev
= node
->minor
->dev
;
1921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1922 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1925 seq_write(m
, opregion
->vbt
, opregion
->vbt_size
);
1930 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1932 struct drm_info_node
*node
= m
->private;
1933 struct drm_device
*dev
= node
->minor
->dev
;
1934 struct intel_framebuffer
*fbdev_fb
= NULL
;
1935 struct drm_framebuffer
*drm_fb
;
1938 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1942 #ifdef CONFIG_DRM_FBDEV_EMULATION
1943 if (to_i915(dev
)->fbdev
) {
1944 fbdev_fb
= to_intel_framebuffer(to_i915(dev
)->fbdev
->helper
.fb
);
1946 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1947 fbdev_fb
->base
.width
,
1948 fbdev_fb
->base
.height
,
1949 fbdev_fb
->base
.depth
,
1950 fbdev_fb
->base
.bits_per_pixel
,
1951 fbdev_fb
->base
.modifier
[0],
1952 drm_framebuffer_read_refcount(&fbdev_fb
->base
));
1953 describe_obj(m
, fbdev_fb
->obj
);
1958 mutex_lock(&dev
->mode_config
.fb_lock
);
1959 drm_for_each_fb(drm_fb
, dev
) {
1960 struct intel_framebuffer
*fb
= to_intel_framebuffer(drm_fb
);
1964 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1968 fb
->base
.bits_per_pixel
,
1969 fb
->base
.modifier
[0],
1970 drm_framebuffer_read_refcount(&fb
->base
));
1971 describe_obj(m
, fb
->obj
);
1974 mutex_unlock(&dev
->mode_config
.fb_lock
);
1975 mutex_unlock(&dev
->struct_mutex
);
1980 static void describe_ctx_ringbuf(struct seq_file
*m
,
1981 struct intel_ringbuffer
*ringbuf
)
1983 seq_printf(m
, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1984 ringbuf
->space
, ringbuf
->head
, ringbuf
->tail
,
1985 ringbuf
->last_retired_head
);
1988 static int i915_context_status(struct seq_file
*m
, void *unused
)
1990 struct drm_info_node
*node
= m
->private;
1991 struct drm_device
*dev
= node
->minor
->dev
;
1992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1993 struct intel_engine_cs
*engine
;
1994 struct intel_context
*ctx
;
1995 enum intel_engine_id id
;
1998 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2002 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
2003 if (!i915
.enable_execlists
&&
2004 ctx
->legacy_hw_ctx
.rcs_state
== NULL
)
2007 seq_puts(m
, "HW context ");
2008 describe_ctx(m
, ctx
);
2009 if (ctx
== dev_priv
->kernel_context
)
2010 seq_printf(m
, "(kernel context) ");
2012 if (i915
.enable_execlists
) {
2014 for_each_engine_id(engine
, dev_priv
, id
) {
2015 struct drm_i915_gem_object
*ctx_obj
=
2016 ctx
->engine
[id
].state
;
2017 struct intel_ringbuffer
*ringbuf
=
2018 ctx
->engine
[id
].ringbuf
;
2020 seq_printf(m
, "%s: ", engine
->name
);
2022 describe_obj(m
, ctx_obj
);
2024 describe_ctx_ringbuf(m
, ringbuf
);
2028 describe_obj(m
, ctx
->legacy_hw_ctx
.rcs_state
);
2034 mutex_unlock(&dev
->struct_mutex
);
2039 static void i915_dump_lrc_obj(struct seq_file
*m
,
2040 struct intel_context
*ctx
,
2041 struct intel_engine_cs
*engine
)
2044 uint32_t *reg_state
;
2046 struct drm_i915_gem_object
*ctx_obj
= ctx
->engine
[engine
->id
].state
;
2047 unsigned long ggtt_offset
= 0;
2049 if (ctx_obj
== NULL
) {
2050 seq_printf(m
, "Context on %s with no gem object\n",
2055 seq_printf(m
, "CONTEXT: %s %u\n", engine
->name
,
2056 intel_execlists_ctx_id(ctx
, engine
));
2058 if (!i915_gem_obj_ggtt_bound(ctx_obj
))
2059 seq_puts(m
, "\tNot bound in GGTT\n");
2061 ggtt_offset
= i915_gem_obj_ggtt_offset(ctx_obj
);
2063 if (i915_gem_object_get_pages(ctx_obj
)) {
2064 seq_puts(m
, "\tFailed to get pages for context object\n");
2068 page
= i915_gem_object_get_page(ctx_obj
, LRC_STATE_PN
);
2069 if (!WARN_ON(page
== NULL
)) {
2070 reg_state
= kmap_atomic(page
);
2072 for (j
= 0; j
< 0x600 / sizeof(u32
) / 4; j
+= 4) {
2073 seq_printf(m
, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2074 ggtt_offset
+ 4096 + (j
* 4),
2075 reg_state
[j
], reg_state
[j
+ 1],
2076 reg_state
[j
+ 2], reg_state
[j
+ 3]);
2078 kunmap_atomic(reg_state
);
2084 static int i915_dump_lrc(struct seq_file
*m
, void *unused
)
2086 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2087 struct drm_device
*dev
= node
->minor
->dev
;
2088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2089 struct intel_engine_cs
*engine
;
2090 struct intel_context
*ctx
;
2093 if (!i915
.enable_execlists
) {
2094 seq_printf(m
, "Logical Ring Contexts are disabled\n");
2098 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2102 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
)
2103 if (ctx
!= dev_priv
->kernel_context
)
2104 for_each_engine(engine
, dev_priv
)
2105 i915_dump_lrc_obj(m
, ctx
, engine
);
2107 mutex_unlock(&dev
->struct_mutex
);
2112 static int i915_execlists(struct seq_file
*m
, void *data
)
2114 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
2115 struct drm_device
*dev
= node
->minor
->dev
;
2116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2117 struct intel_engine_cs
*engine
;
2123 struct list_head
*cursor
;
2126 if (!i915
.enable_execlists
) {
2127 seq_puts(m
, "Logical Ring Contexts are disabled\n");
2131 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2135 intel_runtime_pm_get(dev_priv
);
2137 for_each_engine(engine
, dev_priv
) {
2138 struct drm_i915_gem_request
*head_req
= NULL
;
2141 seq_printf(m
, "%s\n", engine
->name
);
2143 status
= I915_READ(RING_EXECLIST_STATUS_LO(engine
));
2144 ctx_id
= I915_READ(RING_EXECLIST_STATUS_HI(engine
));
2145 seq_printf(m
, "\tExeclist status: 0x%08X, context: %u\n",
2148 status_pointer
= I915_READ(RING_CONTEXT_STATUS_PTR(engine
));
2149 seq_printf(m
, "\tStatus pointer: 0x%08X\n", status_pointer
);
2151 read_pointer
= engine
->next_context_status_buffer
;
2152 write_pointer
= GEN8_CSB_WRITE_PTR(status_pointer
);
2153 if (read_pointer
> write_pointer
)
2154 write_pointer
+= GEN8_CSB_ENTRIES
;
2155 seq_printf(m
, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2156 read_pointer
, write_pointer
);
2158 for (i
= 0; i
< GEN8_CSB_ENTRIES
; i
++) {
2159 status
= I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine
, i
));
2160 ctx_id
= I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine
, i
));
2162 seq_printf(m
, "\tStatus buffer %d: 0x%08X, context: %u\n",
2166 spin_lock_bh(&engine
->execlist_lock
);
2167 list_for_each(cursor
, &engine
->execlist_queue
)
2169 head_req
= list_first_entry_or_null(&engine
->execlist_queue
,
2170 struct drm_i915_gem_request
,
2172 spin_unlock_bh(&engine
->execlist_lock
);
2174 seq_printf(m
, "\t%d requests in queue\n", count
);
2176 seq_printf(m
, "\tHead request id: %u\n",
2177 intel_execlists_ctx_id(head_req
->ctx
, engine
));
2178 seq_printf(m
, "\tHead request tail: %u\n",
2185 intel_runtime_pm_put(dev_priv
);
2186 mutex_unlock(&dev
->struct_mutex
);
2191 static const char *swizzle_string(unsigned swizzle
)
2194 case I915_BIT_6_SWIZZLE_NONE
:
2196 case I915_BIT_6_SWIZZLE_9
:
2198 case I915_BIT_6_SWIZZLE_9_10
:
2199 return "bit9/bit10";
2200 case I915_BIT_6_SWIZZLE_9_11
:
2201 return "bit9/bit11";
2202 case I915_BIT_6_SWIZZLE_9_10_11
:
2203 return "bit9/bit10/bit11";
2204 case I915_BIT_6_SWIZZLE_9_17
:
2205 return "bit9/bit17";
2206 case I915_BIT_6_SWIZZLE_9_10_17
:
2207 return "bit9/bit10/bit17";
2208 case I915_BIT_6_SWIZZLE_UNKNOWN
:
2215 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
2217 struct drm_info_node
*node
= m
->private;
2218 struct drm_device
*dev
= node
->minor
->dev
;
2219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2222 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2225 intel_runtime_pm_get(dev_priv
);
2227 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
2228 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
2229 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
2230 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
2232 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
2233 seq_printf(m
, "DDC = 0x%08x\n",
2235 seq_printf(m
, "DDC2 = 0x%08x\n",
2237 seq_printf(m
, "C0DRB3 = 0x%04x\n",
2238 I915_READ16(C0DRB3
));
2239 seq_printf(m
, "C1DRB3 = 0x%04x\n",
2240 I915_READ16(C1DRB3
));
2241 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2242 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
2243 I915_READ(MAD_DIMM_C0
));
2244 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
2245 I915_READ(MAD_DIMM_C1
));
2246 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
2247 I915_READ(MAD_DIMM_C2
));
2248 seq_printf(m
, "TILECTL = 0x%08x\n",
2249 I915_READ(TILECTL
));
2250 if (INTEL_INFO(dev
)->gen
>= 8)
2251 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
2252 I915_READ(GAMTARBMODE
));
2254 seq_printf(m
, "ARB_MODE = 0x%08x\n",
2255 I915_READ(ARB_MODE
));
2256 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
2257 I915_READ(DISP_ARB_CTL
));
2260 if (dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2261 seq_puts(m
, "L-shaped memory detected\n");
2263 intel_runtime_pm_put(dev_priv
);
2264 mutex_unlock(&dev
->struct_mutex
);
2269 static int per_file_ctx(int id
, void *ptr
, void *data
)
2271 struct intel_context
*ctx
= ptr
;
2272 struct seq_file
*m
= data
;
2273 struct i915_hw_ppgtt
*ppgtt
= ctx
->ppgtt
;
2276 seq_printf(m
, " no ppgtt for context %d\n",
2281 if (i915_gem_context_is_default(ctx
))
2282 seq_puts(m
, " default context:\n");
2284 seq_printf(m
, " context %d:\n", ctx
->user_handle
);
2285 ppgtt
->debug_dump(ppgtt
, m
);
2290 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2292 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2293 struct intel_engine_cs
*engine
;
2294 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2300 for_each_engine(engine
, dev_priv
) {
2301 seq_printf(m
, "%s\n", engine
->name
);
2302 for (i
= 0; i
< 4; i
++) {
2303 u64 pdp
= I915_READ(GEN8_RING_PDP_UDW(engine
, i
));
2305 pdp
|= I915_READ(GEN8_RING_PDP_LDW(engine
, i
));
2306 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
2311 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
2313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2314 struct intel_engine_cs
*engine
;
2316 if (INTEL_INFO(dev
)->gen
== 6)
2317 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
2319 for_each_engine(engine
, dev_priv
) {
2320 seq_printf(m
, "%s\n", engine
->name
);
2321 if (INTEL_INFO(dev
)->gen
== 7)
2322 seq_printf(m
, "GFX_MODE: 0x%08x\n",
2323 I915_READ(RING_MODE_GEN7(engine
)));
2324 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n",
2325 I915_READ(RING_PP_DIR_BASE(engine
)));
2326 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n",
2327 I915_READ(RING_PP_DIR_BASE_READ(engine
)));
2328 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n",
2329 I915_READ(RING_PP_DIR_DCLV(engine
)));
2331 if (dev_priv
->mm
.aliasing_ppgtt
) {
2332 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
2334 seq_puts(m
, "aliasing PPGTT:\n");
2335 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd
.base
.ggtt_offset
);
2337 ppgtt
->debug_dump(ppgtt
, m
);
2340 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
2343 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
2345 struct drm_info_node
*node
= m
->private;
2346 struct drm_device
*dev
= node
->minor
->dev
;
2347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2348 struct drm_file
*file
;
2350 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
2353 intel_runtime_pm_get(dev_priv
);
2355 if (INTEL_INFO(dev
)->gen
>= 8)
2356 gen8_ppgtt_info(m
, dev
);
2357 else if (INTEL_INFO(dev
)->gen
>= 6)
2358 gen6_ppgtt_info(m
, dev
);
2360 mutex_lock(&dev
->filelist_mutex
);
2361 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2362 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2363 struct task_struct
*task
;
2365 task
= get_pid_task(file
->pid
, PIDTYPE_PID
);
2370 seq_printf(m
, "\nproc: %s\n", task
->comm
);
2371 put_task_struct(task
);
2372 idr_for_each(&file_priv
->context_idr
, per_file_ctx
,
2373 (void *)(unsigned long)m
);
2376 mutex_unlock(&dev
->filelist_mutex
);
2378 intel_runtime_pm_put(dev_priv
);
2379 mutex_unlock(&dev
->struct_mutex
);
2384 static int count_irq_waiters(struct drm_i915_private
*i915
)
2386 struct intel_engine_cs
*engine
;
2389 for_each_engine(engine
, i915
)
2390 count
+= engine
->irq_refcount
;
2395 static int i915_rps_boost_info(struct seq_file
*m
, void *data
)
2397 struct drm_info_node
*node
= m
->private;
2398 struct drm_device
*dev
= node
->minor
->dev
;
2399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2400 struct drm_file
*file
;
2402 seq_printf(m
, "RPS enabled? %d\n", dev_priv
->rps
.enabled
);
2403 seq_printf(m
, "GPU busy? %d\n", dev_priv
->mm
.busy
);
2404 seq_printf(m
, "CPU waiting? %d\n", count_irq_waiters(dev_priv
));
2405 seq_printf(m
, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2406 intel_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
2407 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
2408 intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
),
2409 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
),
2410 intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
));
2412 mutex_lock(&dev
->filelist_mutex
);
2413 spin_lock(&dev_priv
->rps
.client_lock
);
2414 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
2415 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2416 struct task_struct
*task
;
2419 task
= pid_task(file
->pid
, PIDTYPE_PID
);
2420 seq_printf(m
, "%s [%d]: %d boosts%s\n",
2421 task
? task
->comm
: "<unknown>",
2422 task
? task
->pid
: -1,
2423 file_priv
->rps
.boosts
,
2424 list_empty(&file_priv
->rps
.link
) ? "" : ", active");
2427 seq_printf(m
, "Semaphore boosts: %d%s\n",
2428 dev_priv
->rps
.semaphores
.boosts
,
2429 list_empty(&dev_priv
->rps
.semaphores
.link
) ? "" : ", active");
2430 seq_printf(m
, "MMIO flip boosts: %d%s\n",
2431 dev_priv
->rps
.mmioflips
.boosts
,
2432 list_empty(&dev_priv
->rps
.mmioflips
.link
) ? "" : ", active");
2433 seq_printf(m
, "Kernel boosts: %d\n", dev_priv
->rps
.boosts
);
2434 spin_unlock(&dev_priv
->rps
.client_lock
);
2435 mutex_unlock(&dev
->filelist_mutex
);
2440 static int i915_llc(struct seq_file
*m
, void *data
)
2442 struct drm_info_node
*node
= m
->private;
2443 struct drm_device
*dev
= node
->minor
->dev
;
2444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2445 const bool edram
= INTEL_GEN(dev_priv
) > 8;
2447 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
2448 seq_printf(m
, "%s: %lluMB\n", edram
? "eDRAM" : "eLLC",
2449 intel_uncore_edram_size(dev_priv
)/1024/1024);
2454 static int i915_guc_load_status_info(struct seq_file
*m
, void *data
)
2456 struct drm_info_node
*node
= m
->private;
2457 struct drm_i915_private
*dev_priv
= node
->minor
->dev
->dev_private
;
2458 struct intel_guc_fw
*guc_fw
= &dev_priv
->guc
.guc_fw
;
2461 if (!HAS_GUC_UCODE(dev_priv
))
2464 seq_printf(m
, "GuC firmware status:\n");
2465 seq_printf(m
, "\tpath: %s\n",
2466 guc_fw
->guc_fw_path
);
2467 seq_printf(m
, "\tfetch: %s\n",
2468 intel_guc_fw_status_repr(guc_fw
->guc_fw_fetch_status
));
2469 seq_printf(m
, "\tload: %s\n",
2470 intel_guc_fw_status_repr(guc_fw
->guc_fw_load_status
));
2471 seq_printf(m
, "\tversion wanted: %d.%d\n",
2472 guc_fw
->guc_fw_major_wanted
, guc_fw
->guc_fw_minor_wanted
);
2473 seq_printf(m
, "\tversion found: %d.%d\n",
2474 guc_fw
->guc_fw_major_found
, guc_fw
->guc_fw_minor_found
);
2475 seq_printf(m
, "\theader: offset is %d; size = %d\n",
2476 guc_fw
->header_offset
, guc_fw
->header_size
);
2477 seq_printf(m
, "\tuCode: offset is %d; size = %d\n",
2478 guc_fw
->ucode_offset
, guc_fw
->ucode_size
);
2479 seq_printf(m
, "\tRSA: offset is %d; size = %d\n",
2480 guc_fw
->rsa_offset
, guc_fw
->rsa_size
);
2482 tmp
= I915_READ(GUC_STATUS
);
2484 seq_printf(m
, "\nGuC status 0x%08x:\n", tmp
);
2485 seq_printf(m
, "\tBootrom status = 0x%x\n",
2486 (tmp
& GS_BOOTROM_MASK
) >> GS_BOOTROM_SHIFT
);
2487 seq_printf(m
, "\tuKernel status = 0x%x\n",
2488 (tmp
& GS_UKERNEL_MASK
) >> GS_UKERNEL_SHIFT
);
2489 seq_printf(m
, "\tMIA Core status = 0x%x\n",
2490 (tmp
& GS_MIA_MASK
) >> GS_MIA_SHIFT
);
2491 seq_puts(m
, "\nScratch registers:\n");
2492 for (i
= 0; i
< 16; i
++)
2493 seq_printf(m
, "\t%2d: \t0x%x\n", i
, I915_READ(SOFT_SCRATCH(i
)));
2498 static void i915_guc_client_info(struct seq_file
*m
,
2499 struct drm_i915_private
*dev_priv
,
2500 struct i915_guc_client
*client
)
2502 struct intel_engine_cs
*engine
;
2505 seq_printf(m
, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2506 client
->priority
, client
->ctx_index
, client
->proc_desc_offset
);
2507 seq_printf(m
, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2508 client
->doorbell_id
, client
->doorbell_offset
, client
->cookie
);
2509 seq_printf(m
, "\tWQ size %d, offset: 0x%x, tail %d\n",
2510 client
->wq_size
, client
->wq_offset
, client
->wq_tail
);
2512 seq_printf(m
, "\tFailed to queue: %u\n", client
->q_fail
);
2513 seq_printf(m
, "\tFailed doorbell: %u\n", client
->b_fail
);
2514 seq_printf(m
, "\tLast submission result: %d\n", client
->retcode
);
2516 for_each_engine(engine
, dev_priv
) {
2517 seq_printf(m
, "\tSubmissions: %llu %s\n",
2518 client
->submissions
[engine
->guc_id
],
2520 tot
+= client
->submissions
[engine
->guc_id
];
2522 seq_printf(m
, "\tTotal: %llu\n", tot
);
2525 static int i915_guc_info(struct seq_file
*m
, void *data
)
2527 struct drm_info_node
*node
= m
->private;
2528 struct drm_device
*dev
= node
->minor
->dev
;
2529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2530 struct intel_guc guc
;
2531 struct i915_guc_client client
= {};
2532 struct intel_engine_cs
*engine
;
2535 if (!HAS_GUC_SCHED(dev_priv
))
2538 if (mutex_lock_interruptible(&dev
->struct_mutex
))
2541 /* Take a local copy of the GuC data, so we can dump it at leisure */
2542 guc
= dev_priv
->guc
;
2543 if (guc
.execbuf_client
)
2544 client
= *guc
.execbuf_client
;
2546 mutex_unlock(&dev
->struct_mutex
);
2548 seq_printf(m
, "GuC total action count: %llu\n", guc
.action_count
);
2549 seq_printf(m
, "GuC action failure count: %u\n", guc
.action_fail
);
2550 seq_printf(m
, "GuC last action command: 0x%x\n", guc
.action_cmd
);
2551 seq_printf(m
, "GuC last action status: 0x%x\n", guc
.action_status
);
2552 seq_printf(m
, "GuC last action error code: %d\n", guc
.action_err
);
2554 seq_printf(m
, "\nGuC submissions:\n");
2555 for_each_engine(engine
, dev_priv
) {
2556 seq_printf(m
, "\t%-24s: %10llu, last seqno 0x%08x\n",
2557 engine
->name
, guc
.submissions
[engine
->guc_id
],
2558 guc
.last_seqno
[engine
->guc_id
]);
2559 total
+= guc
.submissions
[engine
->guc_id
];
2561 seq_printf(m
, "\t%s: %llu\n", "Total", total
);
2563 seq_printf(m
, "\nGuC execbuf client @ %p:\n", guc
.execbuf_client
);
2564 i915_guc_client_info(m
, dev_priv
, &client
);
2566 /* Add more as required ... */
2571 static int i915_guc_log_dump(struct seq_file
*m
, void *data
)
2573 struct drm_info_node
*node
= m
->private;
2574 struct drm_device
*dev
= node
->minor
->dev
;
2575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2576 struct drm_i915_gem_object
*log_obj
= dev_priv
->guc
.log_obj
;
2583 for (pg
= 0; pg
< log_obj
->base
.size
/ PAGE_SIZE
; pg
++) {
2584 log
= kmap_atomic(i915_gem_object_get_page(log_obj
, pg
));
2586 for (i
= 0; i
< PAGE_SIZE
/ sizeof(u32
); i
+= 4)
2587 seq_printf(m
, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2588 *(log
+ i
), *(log
+ i
+ 1),
2589 *(log
+ i
+ 2), *(log
+ i
+ 3));
2599 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
2601 struct drm_info_node
*node
= m
->private;
2602 struct drm_device
*dev
= node
->minor
->dev
;
2603 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2607 bool enabled
= false;
2609 if (!HAS_PSR(dev
)) {
2610 seq_puts(m
, "PSR not supported\n");
2614 intel_runtime_pm_get(dev_priv
);
2616 mutex_lock(&dev_priv
->psr
.lock
);
2617 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
2618 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
2619 seq_printf(m
, "Enabled: %s\n", yesno((bool)dev_priv
->psr
.enabled
));
2620 seq_printf(m
, "Active: %s\n", yesno(dev_priv
->psr
.active
));
2621 seq_printf(m
, "Busy frontbuffer bits: 0x%03x\n",
2622 dev_priv
->psr
.busy_frontbuffer_bits
);
2623 seq_printf(m
, "Re-enable work scheduled: %s\n",
2624 yesno(work_busy(&dev_priv
->psr
.work
.work
)));
2627 enabled
= I915_READ(EDP_PSR_CTL
) & EDP_PSR_ENABLE
;
2629 for_each_pipe(dev_priv
, pipe
) {
2630 stat
[pipe
] = I915_READ(VLV_PSRSTAT(pipe
)) &
2631 VLV_EDP_PSR_CURR_STATE_MASK
;
2632 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2633 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2638 seq_printf(m
, "Main link in standby mode: %s\n",
2639 yesno(dev_priv
->psr
.link_standby
));
2641 seq_printf(m
, "HW Enabled & Active bit: %s", yesno(enabled
));
2644 for_each_pipe(dev_priv
, pipe
) {
2645 if ((stat
[pipe
] == VLV_EDP_PSR_ACTIVE_NORFB_UP
) ||
2646 (stat
[pipe
] == VLV_EDP_PSR_ACTIVE_SF_UPDATE
))
2647 seq_printf(m
, " pipe %c", pipe_name(pipe
));
2652 * VLV/CHV PSR has no kind of performance counter
2653 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2655 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2656 psrperf
= I915_READ(EDP_PSR_PERF_CNT
) &
2657 EDP_PSR_PERF_CNT_MASK
;
2659 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
2661 mutex_unlock(&dev_priv
->psr
.lock
);
2663 intel_runtime_pm_put(dev_priv
);
2667 static int i915_sink_crc(struct seq_file
*m
, void *data
)
2669 struct drm_info_node
*node
= m
->private;
2670 struct drm_device
*dev
= node
->minor
->dev
;
2671 struct intel_encoder
*encoder
;
2672 struct intel_connector
*connector
;
2673 struct intel_dp
*intel_dp
= NULL
;
2677 drm_modeset_lock_all(dev
);
2678 for_each_intel_connector(dev
, connector
) {
2680 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
2683 if (!connector
->base
.encoder
)
2686 encoder
= to_intel_encoder(connector
->base
.encoder
);
2687 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
2690 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2692 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2696 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2697 crc
[0], crc
[1], crc
[2],
2698 crc
[3], crc
[4], crc
[5]);
2703 drm_modeset_unlock_all(dev
);
2707 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2709 struct drm_info_node
*node
= m
->private;
2710 struct drm_device
*dev
= node
->minor
->dev
;
2711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2715 if (INTEL_INFO(dev
)->gen
< 6)
2718 intel_runtime_pm_get(dev_priv
);
2720 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2721 power
= (power
& 0x1f00) >> 8;
2722 units
= 1000000 / (1 << power
); /* convert to uJ */
2723 power
= I915_READ(MCH_SECP_NRG_STTS
);
2726 intel_runtime_pm_put(dev_priv
);
2728 seq_printf(m
, "%llu", (long long unsigned)power
);
2733 static int i915_runtime_pm_status(struct seq_file
*m
, void *unused
)
2735 struct drm_info_node
*node
= m
->private;
2736 struct drm_device
*dev
= node
->minor
->dev
;
2737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 if (!HAS_RUNTIME_PM(dev_priv
))
2740 seq_puts(m
, "Runtime power management not supported\n");
2742 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2743 seq_printf(m
, "IRQs disabled: %s\n",
2744 yesno(!intel_irqs_enabled(dev_priv
)));
2746 seq_printf(m
, "Usage count: %d\n",
2747 atomic_read(&dev
->dev
->power
.usage_count
));
2749 seq_printf(m
, "Device Power Management (CONFIG_PM) disabled\n");
2751 seq_printf(m
, "PCI device power state: %s [%d]\n",
2752 pci_power_name(dev_priv
->dev
->pdev
->current_state
),
2753 dev_priv
->dev
->pdev
->current_state
);
2758 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2760 struct drm_info_node
*node
= m
->private;
2761 struct drm_device
*dev
= node
->minor
->dev
;
2762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2763 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2766 mutex_lock(&power_domains
->lock
);
2768 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2769 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2770 struct i915_power_well
*power_well
;
2771 enum intel_display_power_domain power_domain
;
2773 power_well
= &power_domains
->power_wells
[i
];
2774 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2777 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2779 if (!(BIT(power_domain
) & power_well
->domains
))
2782 seq_printf(m
, " %-23s %d\n",
2783 intel_display_power_domain_str(power_domain
),
2784 power_domains
->domain_use_count
[power_domain
]);
2788 mutex_unlock(&power_domains
->lock
);
2793 static int i915_dmc_info(struct seq_file
*m
, void *unused
)
2795 struct drm_info_node
*node
= m
->private;
2796 struct drm_device
*dev
= node
->minor
->dev
;
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 struct intel_csr
*csr
;
2800 if (!HAS_CSR(dev
)) {
2801 seq_puts(m
, "not supported\n");
2805 csr
= &dev_priv
->csr
;
2807 intel_runtime_pm_get(dev_priv
);
2809 seq_printf(m
, "fw loaded: %s\n", yesno(csr
->dmc_payload
!= NULL
));
2810 seq_printf(m
, "path: %s\n", csr
->fw_path
);
2812 if (!csr
->dmc_payload
)
2815 seq_printf(m
, "version: %d.%d\n", CSR_VERSION_MAJOR(csr
->version
),
2816 CSR_VERSION_MINOR(csr
->version
));
2818 if (IS_SKYLAKE(dev
) && csr
->version
>= CSR_VERSION(1, 6)) {
2819 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2820 I915_READ(SKL_CSR_DC3_DC5_COUNT
));
2821 seq_printf(m
, "DC5 -> DC6 count: %d\n",
2822 I915_READ(SKL_CSR_DC5_DC6_COUNT
));
2823 } else if (IS_BROXTON(dev
) && csr
->version
>= CSR_VERSION(1, 4)) {
2824 seq_printf(m
, "DC3 -> DC5 count: %d\n",
2825 I915_READ(BXT_CSR_DC3_DC5_COUNT
));
2829 seq_printf(m
, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2830 seq_printf(m
, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE
));
2831 seq_printf(m
, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL
));
2833 intel_runtime_pm_put(dev_priv
);
2838 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2839 struct drm_display_mode
*mode
)
2843 for (i
= 0; i
< tabs
; i
++)
2846 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2847 mode
->base
.id
, mode
->name
,
2848 mode
->vrefresh
, mode
->clock
,
2849 mode
->hdisplay
, mode
->hsync_start
,
2850 mode
->hsync_end
, mode
->htotal
,
2851 mode
->vdisplay
, mode
->vsync_start
,
2852 mode
->vsync_end
, mode
->vtotal
,
2853 mode
->type
, mode
->flags
);
2856 static void intel_encoder_info(struct seq_file
*m
,
2857 struct intel_crtc
*intel_crtc
,
2858 struct intel_encoder
*intel_encoder
)
2860 struct drm_info_node
*node
= m
->private;
2861 struct drm_device
*dev
= node
->minor
->dev
;
2862 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2863 struct intel_connector
*intel_connector
;
2864 struct drm_encoder
*encoder
;
2866 encoder
= &intel_encoder
->base
;
2867 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2868 encoder
->base
.id
, encoder
->name
);
2869 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2870 struct drm_connector
*connector
= &intel_connector
->base
;
2871 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2874 drm_get_connector_status_name(connector
->status
));
2875 if (connector
->status
== connector_status_connected
) {
2876 struct drm_display_mode
*mode
= &crtc
->mode
;
2877 seq_printf(m
, ", mode:\n");
2878 intel_seq_print_mode(m
, 2, mode
);
2885 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2887 struct drm_info_node
*node
= m
->private;
2888 struct drm_device
*dev
= node
->minor
->dev
;
2889 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2890 struct intel_encoder
*intel_encoder
;
2891 struct drm_plane_state
*plane_state
= crtc
->primary
->state
;
2892 struct drm_framebuffer
*fb
= plane_state
->fb
;
2895 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2896 fb
->base
.id
, plane_state
->src_x
>> 16,
2897 plane_state
->src_y
>> 16, fb
->width
, fb
->height
);
2899 seq_puts(m
, "\tprimary plane disabled\n");
2900 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2901 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2904 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2906 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2908 seq_printf(m
, "\tfixed mode:\n");
2909 intel_seq_print_mode(m
, 2, mode
);
2912 static void intel_dp_info(struct seq_file
*m
,
2913 struct intel_connector
*intel_connector
)
2915 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2916 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2918 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2919 seq_printf(m
, "\taudio support: %s\n", yesno(intel_dp
->has_audio
));
2920 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2921 intel_panel_info(m
, &intel_connector
->panel
);
2924 static void intel_hdmi_info(struct seq_file
*m
,
2925 struct intel_connector
*intel_connector
)
2927 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2928 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2930 seq_printf(m
, "\taudio support: %s\n", yesno(intel_hdmi
->has_audio
));
2933 static void intel_lvds_info(struct seq_file
*m
,
2934 struct intel_connector
*intel_connector
)
2936 intel_panel_info(m
, &intel_connector
->panel
);
2939 static void intel_connector_info(struct seq_file
*m
,
2940 struct drm_connector
*connector
)
2942 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2943 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2944 struct drm_display_mode
*mode
;
2946 seq_printf(m
, "connector %d: type %s, status: %s\n",
2947 connector
->base
.id
, connector
->name
,
2948 drm_get_connector_status_name(connector
->status
));
2949 if (connector
->status
== connector_status_connected
) {
2950 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2951 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2952 connector
->display_info
.width_mm
,
2953 connector
->display_info
.height_mm
);
2954 seq_printf(m
, "\tsubpixel order: %s\n",
2955 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2956 seq_printf(m
, "\tCEA rev: %d\n",
2957 connector
->display_info
.cea_rev
);
2959 if (intel_encoder
) {
2960 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2961 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2962 intel_dp_info(m
, intel_connector
);
2963 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2964 intel_hdmi_info(m
, intel_connector
);
2965 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2966 intel_lvds_info(m
, intel_connector
);
2969 seq_printf(m
, "\tmodes:\n");
2970 list_for_each_entry(mode
, &connector
->modes
, head
)
2971 intel_seq_print_mode(m
, 2, mode
);
2974 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2979 if (IS_845G(dev
) || IS_I865G(dev
))
2980 state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
2982 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2987 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2992 pos
= I915_READ(CURPOS(pipe
));
2994 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2995 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2998 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2999 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
3002 return cursor_active(dev
, pipe
);
3005 static const char *plane_type(enum drm_plane_type type
)
3008 case DRM_PLANE_TYPE_OVERLAY
:
3010 case DRM_PLANE_TYPE_PRIMARY
:
3012 case DRM_PLANE_TYPE_CURSOR
:
3015 * Deliberately omitting default: to generate compiler warnings
3016 * when a new drm_plane_type gets added.
3023 static const char *plane_rotation(unsigned int rotation
)
3025 static char buf
[48];
3027 * According to doc only one DRM_ROTATE_ is allowed but this
3028 * will print them all to visualize if the values are misused
3030 snprintf(buf
, sizeof(buf
),
3031 "%s%s%s%s%s%s(0x%08x)",
3032 (rotation
& BIT(DRM_ROTATE_0
)) ? "0 " : "",
3033 (rotation
& BIT(DRM_ROTATE_90
)) ? "90 " : "",
3034 (rotation
& BIT(DRM_ROTATE_180
)) ? "180 " : "",
3035 (rotation
& BIT(DRM_ROTATE_270
)) ? "270 " : "",
3036 (rotation
& BIT(DRM_REFLECT_X
)) ? "FLIPX " : "",
3037 (rotation
& BIT(DRM_REFLECT_Y
)) ? "FLIPY " : "",
3043 static void intel_plane_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3045 struct drm_info_node
*node
= m
->private;
3046 struct drm_device
*dev
= node
->minor
->dev
;
3047 struct intel_plane
*intel_plane
;
3049 for_each_intel_plane_on_crtc(dev
, intel_crtc
, intel_plane
) {
3050 struct drm_plane_state
*state
;
3051 struct drm_plane
*plane
= &intel_plane
->base
;
3053 if (!plane
->state
) {
3054 seq_puts(m
, "plane->state is NULL!\n");
3058 state
= plane
->state
;
3060 seq_printf(m
, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3062 plane_type(intel_plane
->base
.type
),
3063 state
->crtc_x
, state
->crtc_y
,
3064 state
->crtc_w
, state
->crtc_h
,
3065 (state
->src_x
>> 16),
3066 ((state
->src_x
& 0xffff) * 15625) >> 10,
3067 (state
->src_y
>> 16),
3068 ((state
->src_y
& 0xffff) * 15625) >> 10,
3069 (state
->src_w
>> 16),
3070 ((state
->src_w
& 0xffff) * 15625) >> 10,
3071 (state
->src_h
>> 16),
3072 ((state
->src_h
& 0xffff) * 15625) >> 10,
3073 state
->fb
? drm_get_format_name(state
->fb
->pixel_format
) : "N/A",
3074 plane_rotation(state
->rotation
));
3078 static void intel_scaler_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
3080 struct intel_crtc_state
*pipe_config
;
3081 int num_scalers
= intel_crtc
->num_scalers
;
3084 pipe_config
= to_intel_crtc_state(intel_crtc
->base
.state
);
3086 /* Not all platformas have a scaler */
3088 seq_printf(m
, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3090 pipe_config
->scaler_state
.scaler_users
,
3091 pipe_config
->scaler_state
.scaler_id
);
3093 for (i
= 0; i
< SKL_NUM_SCALERS
; i
++) {
3094 struct intel_scaler
*sc
=
3095 &pipe_config
->scaler_state
.scalers
[i
];
3097 seq_printf(m
, ", scalers[%d]: use=%s, mode=%x",
3098 i
, yesno(sc
->in_use
), sc
->mode
);
3102 seq_puts(m
, "\tNo scalers available on this platform\n");
3106 static int i915_display_info(struct seq_file
*m
, void *unused
)
3108 struct drm_info_node
*node
= m
->private;
3109 struct drm_device
*dev
= node
->minor
->dev
;
3110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3111 struct intel_crtc
*crtc
;
3112 struct drm_connector
*connector
;
3114 intel_runtime_pm_get(dev_priv
);
3115 drm_modeset_lock_all(dev
);
3116 seq_printf(m
, "CRTC info\n");
3117 seq_printf(m
, "---------\n");
3118 for_each_intel_crtc(dev
, crtc
) {
3120 struct intel_crtc_state
*pipe_config
;
3123 pipe_config
= to_intel_crtc_state(crtc
->base
.state
);
3125 seq_printf(m
, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3126 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
3127 yesno(pipe_config
->base
.active
),
3128 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
,
3129 yesno(pipe_config
->dither
), pipe_config
->pipe_bpp
);
3131 if (pipe_config
->base
.active
) {
3132 intel_crtc_info(m
, crtc
);
3134 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
3135 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3136 yesno(crtc
->cursor_base
),
3137 x
, y
, crtc
->base
.cursor
->state
->crtc_w
,
3138 crtc
->base
.cursor
->state
->crtc_h
,
3139 crtc
->cursor_addr
, yesno(active
));
3140 intel_scaler_info(m
, crtc
);
3141 intel_plane_info(m
, crtc
);
3144 seq_printf(m
, "\tunderrun reporting: cpu=%s pch=%s \n",
3145 yesno(!crtc
->cpu_fifo_underrun_disabled
),
3146 yesno(!crtc
->pch_fifo_underrun_disabled
));
3149 seq_printf(m
, "\n");
3150 seq_printf(m
, "Connector info\n");
3151 seq_printf(m
, "--------------\n");
3152 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3153 intel_connector_info(m
, connector
);
3155 drm_modeset_unlock_all(dev
);
3156 intel_runtime_pm_put(dev_priv
);
3161 static int i915_semaphore_status(struct seq_file
*m
, void *unused
)
3163 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3164 struct drm_device
*dev
= node
->minor
->dev
;
3165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3166 struct intel_engine_cs
*engine
;
3167 int num_rings
= hweight32(INTEL_INFO(dev
)->ring_mask
);
3168 enum intel_engine_id id
;
3171 if (!i915_semaphore_is_enabled(dev
)) {
3172 seq_puts(m
, "Semaphores are disabled\n");
3176 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3179 intel_runtime_pm_get(dev_priv
);
3181 if (IS_BROADWELL(dev
)) {
3185 page
= i915_gem_object_get_page(dev_priv
->semaphore_obj
, 0);
3187 seqno
= (uint64_t *)kmap_atomic(page
);
3188 for_each_engine_id(engine
, dev_priv
, id
) {
3191 seq_printf(m
, "%s\n", engine
->name
);
3193 seq_puts(m
, " Last signal:");
3194 for (j
= 0; j
< num_rings
; j
++) {
3195 offset
= id
* I915_NUM_ENGINES
+ j
;
3196 seq_printf(m
, "0x%08llx (0x%02llx) ",
3197 seqno
[offset
], offset
* 8);
3201 seq_puts(m
, " Last wait: ");
3202 for (j
= 0; j
< num_rings
; j
++) {
3203 offset
= id
+ (j
* I915_NUM_ENGINES
);
3204 seq_printf(m
, "0x%08llx (0x%02llx) ",
3205 seqno
[offset
], offset
* 8);
3210 kunmap_atomic(seqno
);
3212 seq_puts(m
, " Last signal:");
3213 for_each_engine(engine
, dev_priv
)
3214 for (j
= 0; j
< num_rings
; j
++)
3215 seq_printf(m
, "0x%08x\n",
3216 I915_READ(engine
->semaphore
.mbox
.signal
[j
]));
3220 seq_puts(m
, "\nSync seqno:\n");
3221 for_each_engine(engine
, dev_priv
) {
3222 for (j
= 0; j
< num_rings
; j
++)
3223 seq_printf(m
, " 0x%08x ",
3224 engine
->semaphore
.sync_seqno
[j
]);
3229 intel_runtime_pm_put(dev_priv
);
3230 mutex_unlock(&dev
->struct_mutex
);
3234 static int i915_shared_dplls_info(struct seq_file
*m
, void *unused
)
3236 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3237 struct drm_device
*dev
= node
->minor
->dev
;
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 drm_modeset_lock_all(dev
);
3242 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3243 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
3245 seq_printf(m
, "DPLL%i: %s, id: %i\n", i
, pll
->name
, pll
->id
);
3246 seq_printf(m
, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3247 pll
->config
.crtc_mask
, pll
->active_mask
, yesno(pll
->on
));
3248 seq_printf(m
, " tracked hardware state:\n");
3249 seq_printf(m
, " dpll: 0x%08x\n", pll
->config
.hw_state
.dpll
);
3250 seq_printf(m
, " dpll_md: 0x%08x\n",
3251 pll
->config
.hw_state
.dpll_md
);
3252 seq_printf(m
, " fp0: 0x%08x\n", pll
->config
.hw_state
.fp0
);
3253 seq_printf(m
, " fp1: 0x%08x\n", pll
->config
.hw_state
.fp1
);
3254 seq_printf(m
, " wrpll: 0x%08x\n", pll
->config
.hw_state
.wrpll
);
3256 drm_modeset_unlock_all(dev
);
3261 static int i915_wa_registers(struct seq_file
*m
, void *unused
)
3265 struct intel_engine_cs
*engine
;
3266 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3267 struct drm_device
*dev
= node
->minor
->dev
;
3268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3269 struct i915_workarounds
*workarounds
= &dev_priv
->workarounds
;
3270 enum intel_engine_id id
;
3272 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3276 intel_runtime_pm_get(dev_priv
);
3278 seq_printf(m
, "Workarounds applied: %d\n", workarounds
->count
);
3279 for_each_engine_id(engine
, dev_priv
, id
)
3280 seq_printf(m
, "HW whitelist count for %s: %d\n",
3281 engine
->name
, workarounds
->hw_whitelist_count
[id
]);
3282 for (i
= 0; i
< workarounds
->count
; ++i
) {
3284 u32 mask
, value
, read
;
3287 addr
= workarounds
->reg
[i
].addr
;
3288 mask
= workarounds
->reg
[i
].mask
;
3289 value
= workarounds
->reg
[i
].value
;
3290 read
= I915_READ(addr
);
3291 ok
= (value
& mask
) == (read
& mask
);
3292 seq_printf(m
, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3293 i915_mmio_reg_offset(addr
), value
, mask
, read
, ok
? "OK" : "FAIL");
3296 intel_runtime_pm_put(dev_priv
);
3297 mutex_unlock(&dev
->struct_mutex
);
3302 static int i915_ddb_info(struct seq_file
*m
, void *unused
)
3304 struct drm_info_node
*node
= m
->private;
3305 struct drm_device
*dev
= node
->minor
->dev
;
3306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3307 struct skl_ddb_allocation
*ddb
;
3308 struct skl_ddb_entry
*entry
;
3312 if (INTEL_INFO(dev
)->gen
< 9)
3315 drm_modeset_lock_all(dev
);
3317 ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
3319 seq_printf(m
, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3321 for_each_pipe(dev_priv
, pipe
) {
3322 seq_printf(m
, "Pipe %c\n", pipe_name(pipe
));
3324 for_each_plane(dev_priv
, pipe
, plane
) {
3325 entry
= &ddb
->plane
[pipe
][plane
];
3326 seq_printf(m
, " Plane%-8d%8u%8u%8u\n", plane
+ 1,
3327 entry
->start
, entry
->end
,
3328 skl_ddb_entry_size(entry
));
3331 entry
= &ddb
->plane
[pipe
][PLANE_CURSOR
];
3332 seq_printf(m
, " %-13s%8u%8u%8u\n", "Cursor", entry
->start
,
3333 entry
->end
, skl_ddb_entry_size(entry
));
3336 drm_modeset_unlock_all(dev
);
3341 static void drrs_status_per_crtc(struct seq_file
*m
,
3342 struct drm_device
*dev
, struct intel_crtc
*intel_crtc
)
3344 struct intel_encoder
*intel_encoder
;
3345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3346 struct i915_drrs
*drrs
= &dev_priv
->drrs
;
3349 for_each_encoder_on_crtc(dev
, &intel_crtc
->base
, intel_encoder
) {
3350 /* Encoder connected on this CRTC */
3351 switch (intel_encoder
->type
) {
3352 case INTEL_OUTPUT_EDP
:
3353 seq_puts(m
, "eDP:\n");
3355 case INTEL_OUTPUT_DSI
:
3356 seq_puts(m
, "DSI:\n");
3358 case INTEL_OUTPUT_HDMI
:
3359 seq_puts(m
, "HDMI:\n");
3361 case INTEL_OUTPUT_DISPLAYPORT
:
3362 seq_puts(m
, "DP:\n");
3365 seq_printf(m
, "Other encoder (id=%d).\n",
3366 intel_encoder
->type
);
3371 if (dev_priv
->vbt
.drrs_type
== STATIC_DRRS_SUPPORT
)
3372 seq_puts(m
, "\tVBT: DRRS_type: Static");
3373 else if (dev_priv
->vbt
.drrs_type
== SEAMLESS_DRRS_SUPPORT
)
3374 seq_puts(m
, "\tVBT: DRRS_type: Seamless");
3375 else if (dev_priv
->vbt
.drrs_type
== DRRS_NOT_SUPPORTED
)
3376 seq_puts(m
, "\tVBT: DRRS_type: None");
3378 seq_puts(m
, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3380 seq_puts(m
, "\n\n");
3382 if (to_intel_crtc_state(intel_crtc
->base
.state
)->has_drrs
) {
3383 struct intel_panel
*panel
;
3385 mutex_lock(&drrs
->mutex
);
3386 /* DRRS Supported */
3387 seq_puts(m
, "\tDRRS Supported: Yes\n");
3389 /* disable_drrs() will make drrs->dp NULL */
3391 seq_puts(m
, "Idleness DRRS: Disabled");
3392 mutex_unlock(&drrs
->mutex
);
3396 panel
= &drrs
->dp
->attached_connector
->panel
;
3397 seq_printf(m
, "\t\tBusy_frontbuffer_bits: 0x%X",
3398 drrs
->busy_frontbuffer_bits
);
3400 seq_puts(m
, "\n\t\t");
3401 if (drrs
->refresh_rate_type
== DRRS_HIGH_RR
) {
3402 seq_puts(m
, "DRRS_State: DRRS_HIGH_RR\n");
3403 vrefresh
= panel
->fixed_mode
->vrefresh
;
3404 } else if (drrs
->refresh_rate_type
== DRRS_LOW_RR
) {
3405 seq_puts(m
, "DRRS_State: DRRS_LOW_RR\n");
3406 vrefresh
= panel
->downclock_mode
->vrefresh
;
3408 seq_printf(m
, "DRRS_State: Unknown(%d)\n",
3409 drrs
->refresh_rate_type
);
3410 mutex_unlock(&drrs
->mutex
);
3413 seq_printf(m
, "\t\tVrefresh: %d", vrefresh
);
3415 seq_puts(m
, "\n\t\t");
3416 mutex_unlock(&drrs
->mutex
);
3418 /* DRRS not supported. Print the VBT parameter*/
3419 seq_puts(m
, "\tDRRS Supported : No");
3424 static int i915_drrs_status(struct seq_file
*m
, void *unused
)
3426 struct drm_info_node
*node
= m
->private;
3427 struct drm_device
*dev
= node
->minor
->dev
;
3428 struct intel_crtc
*intel_crtc
;
3429 int active_crtc_cnt
= 0;
3431 for_each_intel_crtc(dev
, intel_crtc
) {
3432 drm_modeset_lock(&intel_crtc
->base
.mutex
, NULL
);
3434 if (intel_crtc
->base
.state
->active
) {
3436 seq_printf(m
, "\nCRTC %d: ", active_crtc_cnt
);
3438 drrs_status_per_crtc(m
, dev
, intel_crtc
);
3441 drm_modeset_unlock(&intel_crtc
->base
.mutex
);
3444 if (!active_crtc_cnt
)
3445 seq_puts(m
, "No active crtc found\n");
3450 struct pipe_crc_info
{
3452 struct drm_device
*dev
;
3456 static int i915_dp_mst_info(struct seq_file
*m
, void *unused
)
3458 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
3459 struct drm_device
*dev
= node
->minor
->dev
;
3460 struct drm_encoder
*encoder
;
3461 struct intel_encoder
*intel_encoder
;
3462 struct intel_digital_port
*intel_dig_port
;
3463 drm_modeset_lock_all(dev
);
3464 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3465 intel_encoder
= to_intel_encoder(encoder
);
3466 if (intel_encoder
->type
!= INTEL_OUTPUT_DISPLAYPORT
)
3468 intel_dig_port
= enc_to_dig_port(encoder
);
3469 if (!intel_dig_port
->dp
.can_mst
)
3471 seq_printf(m
, "MST Source Port %c\n",
3472 port_name(intel_dig_port
->port
));
3473 drm_dp_mst_dump_topology(m
, &intel_dig_port
->dp
.mst_mgr
);
3475 drm_modeset_unlock_all(dev
);
3479 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
3481 struct pipe_crc_info
*info
= inode
->i_private
;
3482 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3483 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3485 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
3488 spin_lock_irq(&pipe_crc
->lock
);
3490 if (pipe_crc
->opened
) {
3491 spin_unlock_irq(&pipe_crc
->lock
);
3492 return -EBUSY
; /* already open */
3495 pipe_crc
->opened
= true;
3496 filep
->private_data
= inode
->i_private
;
3498 spin_unlock_irq(&pipe_crc
->lock
);
3503 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
3505 struct pipe_crc_info
*info
= inode
->i_private
;
3506 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
3507 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3509 spin_lock_irq(&pipe_crc
->lock
);
3510 pipe_crc
->opened
= false;
3511 spin_unlock_irq(&pipe_crc
->lock
);
3516 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3517 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3518 /* account for \'0' */
3519 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3521 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
3523 assert_spin_locked(&pipe_crc
->lock
);
3524 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3525 INTEL_PIPE_CRC_ENTRIES_NR
);
3529 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
3532 struct pipe_crc_info
*info
= filep
->private_data
;
3533 struct drm_device
*dev
= info
->dev
;
3534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3535 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
3536 char buf
[PIPE_CRC_BUFFER_LEN
];
3541 * Don't allow user space to provide buffers not big enough to hold
3544 if (count
< PIPE_CRC_LINE_LEN
)
3547 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
3550 /* nothing to read */
3551 spin_lock_irq(&pipe_crc
->lock
);
3552 while (pipe_crc_data_count(pipe_crc
) == 0) {
3555 if (filep
->f_flags
& O_NONBLOCK
) {
3556 spin_unlock_irq(&pipe_crc
->lock
);
3560 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
3561 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
3563 spin_unlock_irq(&pipe_crc
->lock
);
3568 /* We now have one or more entries to read */
3569 n_entries
= count
/ PIPE_CRC_LINE_LEN
;
3572 while (n_entries
> 0) {
3573 struct intel_pipe_crc_entry
*entry
=
3574 &pipe_crc
->entries
[pipe_crc
->tail
];
3577 if (CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
3578 INTEL_PIPE_CRC_ENTRIES_NR
) < 1)
3581 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
3582 pipe_crc
->tail
= (pipe_crc
->tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
3584 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
3585 "%8u %8x %8x %8x %8x %8x\n",
3586 entry
->frame
, entry
->crc
[0],
3587 entry
->crc
[1], entry
->crc
[2],
3588 entry
->crc
[3], entry
->crc
[4]);
3590 spin_unlock_irq(&pipe_crc
->lock
);
3592 ret
= copy_to_user(user_buf
, buf
, PIPE_CRC_LINE_LEN
);
3593 if (ret
== PIPE_CRC_LINE_LEN
)
3596 user_buf
+= PIPE_CRC_LINE_LEN
;
3599 spin_lock_irq(&pipe_crc
->lock
);
3602 spin_unlock_irq(&pipe_crc
->lock
);
3607 static const struct file_operations i915_pipe_crc_fops
= {
3608 .owner
= THIS_MODULE
,
3609 .open
= i915_pipe_crc_open
,
3610 .read
= i915_pipe_crc_read
,
3611 .release
= i915_pipe_crc_release
,
3614 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
3616 .name
= "i915_pipe_A_crc",
3620 .name
= "i915_pipe_B_crc",
3624 .name
= "i915_pipe_C_crc",
3629 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
3632 struct drm_device
*dev
= minor
->dev
;
3634 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
3637 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
3638 &i915_pipe_crc_fops
);
3642 return drm_add_fake_info_node(minor
, ent
, info
);
3645 static const char * const pipe_crc_sources
[] = {
3658 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
3660 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
3661 return pipe_crc_sources
[source
];
3664 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
3666 struct drm_device
*dev
= m
->private;
3667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3670 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
3671 seq_printf(m
, "%c %s\n", pipe_name(i
),
3672 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
3677 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
3679 struct drm_device
*dev
= inode
->i_private
;
3681 return single_open(file
, display_crc_ctl_show
, dev
);
3684 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3687 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3688 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3691 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3692 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
3694 case INTEL_PIPE_CRC_SOURCE_NONE
:
3704 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
3705 enum intel_pipe_crc_source
*source
)
3707 struct intel_encoder
*encoder
;
3708 struct intel_crtc
*crtc
;
3709 struct intel_digital_port
*dig_port
;
3712 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3714 drm_modeset_lock_all(dev
);
3715 for_each_intel_encoder(dev
, encoder
) {
3716 if (!encoder
->base
.crtc
)
3719 crtc
= to_intel_crtc(encoder
->base
.crtc
);
3721 if (crtc
->pipe
!= pipe
)
3724 switch (encoder
->type
) {
3725 case INTEL_OUTPUT_TVOUT
:
3726 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
3728 case INTEL_OUTPUT_DISPLAYPORT
:
3729 case INTEL_OUTPUT_EDP
:
3730 dig_port
= enc_to_dig_port(&encoder
->base
);
3731 switch (dig_port
->port
) {
3733 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
3736 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
3739 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
3742 WARN(1, "nonexisting DP port %c\n",
3743 port_name(dig_port
->port
));
3751 drm_modeset_unlock_all(dev
);
3756 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
3758 enum intel_pipe_crc_source
*source
,
3761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3762 bool need_stable_symbols
= false;
3764 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3765 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3771 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3772 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
3774 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3775 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
3776 need_stable_symbols
= true;
3778 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3779 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
3780 need_stable_symbols
= true;
3782 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3783 if (!IS_CHERRYVIEW(dev
))
3785 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_VLV
;
3786 need_stable_symbols
= true;
3788 case INTEL_PIPE_CRC_SOURCE_NONE
:
3796 * When the pipe CRC tap point is after the transcoders we need
3797 * to tweak symbol-level features to produce a deterministic series of
3798 * symbols for a given frame. We need to reset those features only once
3799 * a frame (instead of every nth symbol):
3800 * - DC-balance: used to ensure a better clock recovery from the data
3802 * - DisplayPort scrambling: used for EMI reduction
3804 if (need_stable_symbols
) {
3805 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3807 tmp
|= DC_BALANCE_RESET_VLV
;
3810 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3813 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3816 tmp
|= PIPE_C_SCRAMBLE_RESET
;
3821 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3827 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
3829 enum intel_pipe_crc_source
*source
,
3832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3833 bool need_stable_symbols
= false;
3835 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
3836 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
3842 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3843 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
3845 case INTEL_PIPE_CRC_SOURCE_TV
:
3846 if (!SUPPORTS_TV(dev
))
3848 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
3850 case INTEL_PIPE_CRC_SOURCE_DP_B
:
3853 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
3854 need_stable_symbols
= true;
3856 case INTEL_PIPE_CRC_SOURCE_DP_C
:
3859 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
3860 need_stable_symbols
= true;
3862 case INTEL_PIPE_CRC_SOURCE_DP_D
:
3865 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
3866 need_stable_symbols
= true;
3868 case INTEL_PIPE_CRC_SOURCE_NONE
:
3876 * When the pipe CRC tap point is after the transcoders we need
3877 * to tweak symbol-level features to produce a deterministic series of
3878 * symbols for a given frame. We need to reset those features only once
3879 * a frame (instead of every nth symbol):
3880 * - DC-balance: used to ensure a better clock recovery from the data
3882 * - DisplayPort scrambling: used for EMI reduction
3884 if (need_stable_symbols
) {
3885 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3887 WARN_ON(!IS_G4X(dev
));
3889 I915_WRITE(PORT_DFT_I9XX
,
3890 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
3893 tmp
|= PIPE_A_SCRAMBLE_RESET
;
3895 tmp
|= PIPE_B_SCRAMBLE_RESET
;
3897 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3903 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
3906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3907 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3911 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3914 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3917 tmp
&= ~PIPE_C_SCRAMBLE_RESET
;
3922 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
3923 tmp
&= ~DC_BALANCE_RESET_VLV
;
3924 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3928 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
3931 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3932 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
3935 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
3937 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
3938 I915_WRITE(PORT_DFT2_G4X
, tmp
);
3940 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
3941 I915_WRITE(PORT_DFT_I9XX
,
3942 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
3946 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
3949 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
3950 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
3953 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
3954 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
3956 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
3957 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
3959 case INTEL_PIPE_CRC_SOURCE_PIPE
:
3960 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
3962 case INTEL_PIPE_CRC_SOURCE_NONE
:
3972 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device
*dev
, bool enable
)
3974 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3975 struct intel_crtc
*crtc
=
3976 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_A
]);
3977 struct intel_crtc_state
*pipe_config
;
3978 struct drm_atomic_state
*state
;
3981 drm_modeset_lock_all(dev
);
3982 state
= drm_atomic_state_alloc(dev
);
3988 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(&crtc
->base
);
3989 pipe_config
= intel_atomic_get_crtc_state(state
, crtc
);
3990 if (IS_ERR(pipe_config
)) {
3991 ret
= PTR_ERR(pipe_config
);
3995 pipe_config
->pch_pfit
.force_thru
= enable
;
3996 if (pipe_config
->cpu_transcoder
== TRANSCODER_EDP
&&
3997 pipe_config
->pch_pfit
.enabled
!= enable
)
3998 pipe_config
->base
.connectors_changed
= true;
4000 ret
= drm_atomic_commit(state
);
4002 drm_modeset_unlock_all(dev
);
4003 WARN(ret
, "Toggling workaround to %i returns %i\n", enable
, ret
);
4005 drm_atomic_state_free(state
);
4008 static int ivb_pipe_crc_ctl_reg(struct drm_device
*dev
,
4010 enum intel_pipe_crc_source
*source
,
4013 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
4014 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
4017 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
4018 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
4020 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
4021 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
4023 case INTEL_PIPE_CRC_SOURCE_PF
:
4024 if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4025 hsw_trans_edp_pipe_A_crc_wa(dev
, true);
4027 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
4029 case INTEL_PIPE_CRC_SOURCE_NONE
:
4039 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
4040 enum intel_pipe_crc_source source
)
4042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4043 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
4044 struct intel_crtc
*crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
,
4046 enum intel_display_power_domain power_domain
;
4047 u32 val
= 0; /* shut up gcc */
4050 if (pipe_crc
->source
== source
)
4053 /* forbid changing the source without going back to 'none' */
4054 if (pipe_crc
->source
&& source
)
4057 power_domain
= POWER_DOMAIN_PIPE(pipe
);
4058 if (!intel_display_power_get_if_enabled(dev_priv
, power_domain
)) {
4059 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4064 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
4065 else if (INTEL_INFO(dev
)->gen
< 5)
4066 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4067 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4068 ret
= vlv_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4069 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
4070 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
4072 ret
= ivb_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
4077 /* none -> real source transition */
4079 struct intel_pipe_crc_entry
*entries
;
4081 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4082 pipe_name(pipe
), pipe_crc_source_name(source
));
4084 entries
= kcalloc(INTEL_PIPE_CRC_ENTRIES_NR
,
4085 sizeof(pipe_crc
->entries
[0]),
4093 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4094 * enabled and disabled dynamically based on package C states,
4095 * user space can't make reliable use of the CRCs, so let's just
4096 * completely disable it.
4098 hsw_disable_ips(crtc
);
4100 spin_lock_irq(&pipe_crc
->lock
);
4101 kfree(pipe_crc
->entries
);
4102 pipe_crc
->entries
= entries
;
4105 spin_unlock_irq(&pipe_crc
->lock
);
4108 pipe_crc
->source
= source
;
4110 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
4111 POSTING_READ(PIPE_CRC_CTL(pipe
));
4113 /* real source -> none transition */
4114 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
4115 struct intel_pipe_crc_entry
*entries
;
4116 struct intel_crtc
*crtc
=
4117 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
4119 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4122 drm_modeset_lock(&crtc
->base
.mutex
, NULL
);
4123 if (crtc
->base
.state
->active
)
4124 intel_wait_for_vblank(dev
, pipe
);
4125 drm_modeset_unlock(&crtc
->base
.mutex
);
4127 spin_lock_irq(&pipe_crc
->lock
);
4128 entries
= pipe_crc
->entries
;
4129 pipe_crc
->entries
= NULL
;
4132 spin_unlock_irq(&pipe_crc
->lock
);
4137 g4x_undo_pipe_scramble_reset(dev
, pipe
);
4138 else if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
4139 vlv_undo_pipe_scramble_reset(dev
, pipe
);
4140 else if (IS_HASWELL(dev
) && pipe
== PIPE_A
)
4141 hsw_trans_edp_pipe_A_crc_wa(dev
, false);
4143 hsw_enable_ips(crtc
);
4149 intel_display_power_put(dev_priv
, power_domain
);
4155 * Parse pipe CRC command strings:
4156 * command: wsp* object wsp+ name wsp+ source wsp*
4159 * source: (none | plane1 | plane2 | pf)
4160 * wsp: (#0x20 | #0x9 | #0xA)+
4163 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4164 * "pipe A none" -> Stop CRC
4166 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
4173 /* skip leading white space */
4174 buf
= skip_spaces(buf
);
4176 break; /* end of buffer */
4178 /* find end of word */
4179 for (end
= buf
; *end
&& !isspace(*end
); end
++)
4182 if (n_words
== max_words
) {
4183 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4185 return -EINVAL
; /* ran out of words[] before bytes */
4190 words
[n_words
++] = buf
;
4197 enum intel_pipe_crc_object
{
4198 PIPE_CRC_OBJECT_PIPE
,
4201 static const char * const pipe_crc_objects
[] = {
4206 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
4210 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
4211 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
4219 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
4221 const char name
= buf
[0];
4223 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
4232 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
4236 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
4237 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
4245 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
4249 char *words
[N_WORDS
];
4251 enum intel_pipe_crc_object object
;
4252 enum intel_pipe_crc_source source
;
4254 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
4255 if (n_words
!= N_WORDS
) {
4256 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4261 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
4262 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
4266 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
4267 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
4271 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
4272 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
4276 return pipe_crc_set_source(dev
, pipe
, source
);
4279 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
4280 size_t len
, loff_t
*offp
)
4282 struct seq_file
*m
= file
->private_data
;
4283 struct drm_device
*dev
= m
->private;
4290 if (len
> PAGE_SIZE
- 1) {
4291 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4296 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
4300 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
4306 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
4317 static const struct file_operations i915_display_crc_ctl_fops
= {
4318 .owner
= THIS_MODULE
,
4319 .open
= display_crc_ctl_open
,
4321 .llseek
= seq_lseek
,
4322 .release
= single_release
,
4323 .write
= display_crc_ctl_write
4326 static ssize_t
i915_displayport_test_active_write(struct file
*file
,
4327 const char __user
*ubuf
,
4328 size_t len
, loff_t
*offp
)
4332 struct drm_device
*dev
;
4333 struct drm_connector
*connector
;
4334 struct list_head
*connector_list
;
4335 struct intel_dp
*intel_dp
;
4338 dev
= ((struct seq_file
*)file
->private_data
)->private;
4340 connector_list
= &dev
->mode_config
.connector_list
;
4345 input_buffer
= kmalloc(len
+ 1, GFP_KERNEL
);
4349 if (copy_from_user(input_buffer
, ubuf
, len
)) {
4354 input_buffer
[len
] = '\0';
4355 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len
);
4357 list_for_each_entry(connector
, connector_list
, head
) {
4359 if (connector
->connector_type
!=
4360 DRM_MODE_CONNECTOR_DisplayPort
)
4363 if (connector
->status
== connector_status_connected
&&
4364 connector
->encoder
!= NULL
) {
4365 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4366 status
= kstrtoint(input_buffer
, 10, &val
);
4369 DRM_DEBUG_DRIVER("Got %d for test active\n", val
);
4370 /* To prevent erroneous activation of the compliance
4371 * testing code, only accept an actual value of 1 here
4374 intel_dp
->compliance_test_active
= 1;
4376 intel_dp
->compliance_test_active
= 0;
4380 kfree(input_buffer
);
4388 static int i915_displayport_test_active_show(struct seq_file
*m
, void *data
)
4390 struct drm_device
*dev
= m
->private;
4391 struct drm_connector
*connector
;
4392 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4393 struct intel_dp
*intel_dp
;
4395 list_for_each_entry(connector
, connector_list
, head
) {
4397 if (connector
->connector_type
!=
4398 DRM_MODE_CONNECTOR_DisplayPort
)
4401 if (connector
->status
== connector_status_connected
&&
4402 connector
->encoder
!= NULL
) {
4403 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4404 if (intel_dp
->compliance_test_active
)
4415 static int i915_displayport_test_active_open(struct inode
*inode
,
4418 struct drm_device
*dev
= inode
->i_private
;
4420 return single_open(file
, i915_displayport_test_active_show
, dev
);
4423 static const struct file_operations i915_displayport_test_active_fops
= {
4424 .owner
= THIS_MODULE
,
4425 .open
= i915_displayport_test_active_open
,
4427 .llseek
= seq_lseek
,
4428 .release
= single_release
,
4429 .write
= i915_displayport_test_active_write
4432 static int i915_displayport_test_data_show(struct seq_file
*m
, void *data
)
4434 struct drm_device
*dev
= m
->private;
4435 struct drm_connector
*connector
;
4436 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4437 struct intel_dp
*intel_dp
;
4439 list_for_each_entry(connector
, connector_list
, head
) {
4441 if (connector
->connector_type
!=
4442 DRM_MODE_CONNECTOR_DisplayPort
)
4445 if (connector
->status
== connector_status_connected
&&
4446 connector
->encoder
!= NULL
) {
4447 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4448 seq_printf(m
, "%lx", intel_dp
->compliance_test_data
);
4455 static int i915_displayport_test_data_open(struct inode
*inode
,
4458 struct drm_device
*dev
= inode
->i_private
;
4460 return single_open(file
, i915_displayport_test_data_show
, dev
);
4463 static const struct file_operations i915_displayport_test_data_fops
= {
4464 .owner
= THIS_MODULE
,
4465 .open
= i915_displayport_test_data_open
,
4467 .llseek
= seq_lseek
,
4468 .release
= single_release
4471 static int i915_displayport_test_type_show(struct seq_file
*m
, void *data
)
4473 struct drm_device
*dev
= m
->private;
4474 struct drm_connector
*connector
;
4475 struct list_head
*connector_list
= &dev
->mode_config
.connector_list
;
4476 struct intel_dp
*intel_dp
;
4478 list_for_each_entry(connector
, connector_list
, head
) {
4480 if (connector
->connector_type
!=
4481 DRM_MODE_CONNECTOR_DisplayPort
)
4484 if (connector
->status
== connector_status_connected
&&
4485 connector
->encoder
!= NULL
) {
4486 intel_dp
= enc_to_intel_dp(connector
->encoder
);
4487 seq_printf(m
, "%02lx", intel_dp
->compliance_test_type
);
4495 static int i915_displayport_test_type_open(struct inode
*inode
,
4498 struct drm_device
*dev
= inode
->i_private
;
4500 return single_open(file
, i915_displayport_test_type_show
, dev
);
4503 static const struct file_operations i915_displayport_test_type_fops
= {
4504 .owner
= THIS_MODULE
,
4505 .open
= i915_displayport_test_type_open
,
4507 .llseek
= seq_lseek
,
4508 .release
= single_release
4511 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[8])
4513 struct drm_device
*dev
= m
->private;
4517 if (IS_CHERRYVIEW(dev
))
4519 else if (IS_VALLEYVIEW(dev
))
4522 num_levels
= ilk_wm_max_level(dev
) + 1;
4524 drm_modeset_lock_all(dev
);
4526 for (level
= 0; level
< num_levels
; level
++) {
4527 unsigned int latency
= wm
[level
];
4530 * - WM1+ latency values in 0.5us units
4531 * - latencies are in us on gen9/vlv/chv
4533 if (INTEL_INFO(dev
)->gen
>= 9 || IS_VALLEYVIEW(dev
) ||
4539 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
4540 level
, wm
[level
], latency
/ 10, latency
% 10);
4543 drm_modeset_unlock_all(dev
);
4546 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
4548 struct drm_device
*dev
= m
->private;
4549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4550 const uint16_t *latencies
;
4552 if (INTEL_INFO(dev
)->gen
>= 9)
4553 latencies
= dev_priv
->wm
.skl_latency
;
4555 latencies
= to_i915(dev
)->wm
.pri_latency
;
4557 wm_latency_show(m
, latencies
);
4562 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
4564 struct drm_device
*dev
= m
->private;
4565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4566 const uint16_t *latencies
;
4568 if (INTEL_INFO(dev
)->gen
>= 9)
4569 latencies
= dev_priv
->wm
.skl_latency
;
4571 latencies
= to_i915(dev
)->wm
.spr_latency
;
4573 wm_latency_show(m
, latencies
);
4578 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
4580 struct drm_device
*dev
= m
->private;
4581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4582 const uint16_t *latencies
;
4584 if (INTEL_INFO(dev
)->gen
>= 9)
4585 latencies
= dev_priv
->wm
.skl_latency
;
4587 latencies
= to_i915(dev
)->wm
.cur_latency
;
4589 wm_latency_show(m
, latencies
);
4594 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
4596 struct drm_device
*dev
= inode
->i_private
;
4598 if (INTEL_INFO(dev
)->gen
< 5)
4601 return single_open(file
, pri_wm_latency_show
, dev
);
4604 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
4606 struct drm_device
*dev
= inode
->i_private
;
4608 if (HAS_GMCH_DISPLAY(dev
))
4611 return single_open(file
, spr_wm_latency_show
, dev
);
4614 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
4616 struct drm_device
*dev
= inode
->i_private
;
4618 if (HAS_GMCH_DISPLAY(dev
))
4621 return single_open(file
, cur_wm_latency_show
, dev
);
4624 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4625 size_t len
, loff_t
*offp
, uint16_t wm
[8])
4627 struct seq_file
*m
= file
->private_data
;
4628 struct drm_device
*dev
= m
->private;
4629 uint16_t new[8] = { 0 };
4635 if (IS_CHERRYVIEW(dev
))
4637 else if (IS_VALLEYVIEW(dev
))
4640 num_levels
= ilk_wm_max_level(dev
) + 1;
4642 if (len
>= sizeof(tmp
))
4645 if (copy_from_user(tmp
, ubuf
, len
))
4650 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu %hu %hu %hu",
4651 &new[0], &new[1], &new[2], &new[3],
4652 &new[4], &new[5], &new[6], &new[7]);
4653 if (ret
!= num_levels
)
4656 drm_modeset_lock_all(dev
);
4658 for (level
= 0; level
< num_levels
; level
++)
4659 wm
[level
] = new[level
];
4661 drm_modeset_unlock_all(dev
);
4667 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4668 size_t len
, loff_t
*offp
)
4670 struct seq_file
*m
= file
->private_data
;
4671 struct drm_device
*dev
= m
->private;
4672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4673 uint16_t *latencies
;
4675 if (INTEL_INFO(dev
)->gen
>= 9)
4676 latencies
= dev_priv
->wm
.skl_latency
;
4678 latencies
= to_i915(dev
)->wm
.pri_latency
;
4680 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4683 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4684 size_t len
, loff_t
*offp
)
4686 struct seq_file
*m
= file
->private_data
;
4687 struct drm_device
*dev
= m
->private;
4688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4689 uint16_t *latencies
;
4691 if (INTEL_INFO(dev
)->gen
>= 9)
4692 latencies
= dev_priv
->wm
.skl_latency
;
4694 latencies
= to_i915(dev
)->wm
.spr_latency
;
4696 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4699 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
4700 size_t len
, loff_t
*offp
)
4702 struct seq_file
*m
= file
->private_data
;
4703 struct drm_device
*dev
= m
->private;
4704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4705 uint16_t *latencies
;
4707 if (INTEL_INFO(dev
)->gen
>= 9)
4708 latencies
= dev_priv
->wm
.skl_latency
;
4710 latencies
= to_i915(dev
)->wm
.cur_latency
;
4712 return wm_latency_write(file
, ubuf
, len
, offp
, latencies
);
4715 static const struct file_operations i915_pri_wm_latency_fops
= {
4716 .owner
= THIS_MODULE
,
4717 .open
= pri_wm_latency_open
,
4719 .llseek
= seq_lseek
,
4720 .release
= single_release
,
4721 .write
= pri_wm_latency_write
4724 static const struct file_operations i915_spr_wm_latency_fops
= {
4725 .owner
= THIS_MODULE
,
4726 .open
= spr_wm_latency_open
,
4728 .llseek
= seq_lseek
,
4729 .release
= single_release
,
4730 .write
= spr_wm_latency_write
4733 static const struct file_operations i915_cur_wm_latency_fops
= {
4734 .owner
= THIS_MODULE
,
4735 .open
= cur_wm_latency_open
,
4737 .llseek
= seq_lseek
,
4738 .release
= single_release
,
4739 .write
= cur_wm_latency_write
4743 i915_wedged_get(void *data
, u64
*val
)
4745 struct drm_device
*dev
= data
;
4746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4748 *val
= i915_terminally_wedged(&dev_priv
->gpu_error
);
4754 i915_wedged_set(void *data
, u64 val
)
4756 struct drm_device
*dev
= data
;
4757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4760 * There is no safeguard against this debugfs entry colliding
4761 * with the hangcheck calling same i915_handle_error() in
4762 * parallel, causing an explosion. For now we assume that the
4763 * test harness is responsible enough not to inject gpu hangs
4764 * while it is writing to 'i915_wedged'
4767 if (i915_reset_in_progress(&dev_priv
->gpu_error
))
4770 intel_runtime_pm_get(dev_priv
);
4772 i915_handle_error(dev
, val
,
4773 "Manually setting wedged to %llu", val
);
4775 intel_runtime_pm_put(dev_priv
);
4780 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
4781 i915_wedged_get
, i915_wedged_set
,
4785 i915_ring_stop_get(void *data
, u64
*val
)
4787 struct drm_device
*dev
= data
;
4788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4790 *val
= dev_priv
->gpu_error
.stop_rings
;
4796 i915_ring_stop_set(void *data
, u64 val
)
4798 struct drm_device
*dev
= data
;
4799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4802 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
4804 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4808 dev_priv
->gpu_error
.stop_rings
= val
;
4809 mutex_unlock(&dev
->struct_mutex
);
4814 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
4815 i915_ring_stop_get
, i915_ring_stop_set
,
4819 i915_ring_missed_irq_get(void *data
, u64
*val
)
4821 struct drm_device
*dev
= data
;
4822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4824 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
4829 i915_ring_missed_irq_set(void *data
, u64 val
)
4831 struct drm_device
*dev
= data
;
4832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4835 /* Lock against concurrent debugfs callers */
4836 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4839 dev_priv
->gpu_error
.missed_irq_rings
= val
;
4840 mutex_unlock(&dev
->struct_mutex
);
4845 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
4846 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
4850 i915_ring_test_irq_get(void *data
, u64
*val
)
4852 struct drm_device
*dev
= data
;
4853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4855 *val
= dev_priv
->gpu_error
.test_irq_rings
;
4861 i915_ring_test_irq_set(void *data
, u64 val
)
4863 struct drm_device
*dev
= data
;
4864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4867 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
4869 /* Lock against concurrent debugfs callers */
4870 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4874 dev_priv
->gpu_error
.test_irq_rings
= val
;
4875 mutex_unlock(&dev
->struct_mutex
);
4880 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
4881 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
4884 #define DROP_UNBOUND 0x1
4885 #define DROP_BOUND 0x2
4886 #define DROP_RETIRE 0x4
4887 #define DROP_ACTIVE 0x8
4888 #define DROP_ALL (DROP_UNBOUND | \
4893 i915_drop_caches_get(void *data
, u64
*val
)
4901 i915_drop_caches_set(void *data
, u64 val
)
4903 struct drm_device
*dev
= data
;
4904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4907 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
4909 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4910 * on ioctls on -EAGAIN. */
4911 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
4915 if (val
& DROP_ACTIVE
) {
4916 ret
= i915_gpu_idle(dev
);
4921 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
4922 i915_gem_retire_requests(dev
);
4924 if (val
& DROP_BOUND
)
4925 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_BOUND
);
4927 if (val
& DROP_UNBOUND
)
4928 i915_gem_shrink(dev_priv
, LONG_MAX
, I915_SHRINK_UNBOUND
);
4931 mutex_unlock(&dev
->struct_mutex
);
4936 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
4937 i915_drop_caches_get
, i915_drop_caches_set
,
4941 i915_max_freq_get(void *data
, u64
*val
)
4943 struct drm_device
*dev
= data
;
4944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4947 if (INTEL_INFO(dev
)->gen
< 6)
4950 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4952 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4956 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
4957 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4963 i915_max_freq_set(void *data
, u64 val
)
4965 struct drm_device
*dev
= data
;
4966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4970 if (INTEL_INFO(dev
)->gen
< 6)
4973 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
4975 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
4977 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
4982 * Turbo will still be enabled, but won't go above the set value.
4984 val
= intel_freq_opcode(dev_priv
, val
);
4986 hw_max
= dev_priv
->rps
.max_freq
;
4987 hw_min
= dev_priv
->rps
.min_freq
;
4989 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
4990 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4994 dev_priv
->rps
.max_freq_softlimit
= val
;
4996 intel_set_rps(dev
, val
);
4998 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5003 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
5004 i915_max_freq_get
, i915_max_freq_set
,
5008 i915_min_freq_get(void *data
, u64
*val
)
5010 struct drm_device
*dev
= data
;
5011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5014 if (INTEL_INFO(dev
)->gen
< 6)
5017 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5019 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5023 *val
= intel_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
5024 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5030 i915_min_freq_set(void *data
, u64 val
)
5032 struct drm_device
*dev
= data
;
5033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5037 if (INTEL_INFO(dev
)->gen
< 6)
5040 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
5042 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
5044 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
5049 * Turbo will still be enabled, but won't go below the set value.
5051 val
= intel_freq_opcode(dev_priv
, val
);
5053 hw_max
= dev_priv
->rps
.max_freq
;
5054 hw_min
= dev_priv
->rps
.min_freq
;
5056 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
5057 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5061 dev_priv
->rps
.min_freq_softlimit
= val
;
5063 intel_set_rps(dev
, val
);
5065 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5070 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
5071 i915_min_freq_get
, i915_min_freq_set
,
5075 i915_cache_sharing_get(void *data
, u64
*val
)
5077 struct drm_device
*dev
= data
;
5078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5082 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5085 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
5088 intel_runtime_pm_get(dev_priv
);
5090 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5092 intel_runtime_pm_put(dev_priv
);
5093 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
5095 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
5101 i915_cache_sharing_set(void *data
, u64 val
)
5103 struct drm_device
*dev
= data
;
5104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5107 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
5113 intel_runtime_pm_get(dev_priv
);
5114 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
5116 /* Update the cache sharing policy here as well */
5117 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5118 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5119 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
5120 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5122 intel_runtime_pm_put(dev_priv
);
5126 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
5127 i915_cache_sharing_get
, i915_cache_sharing_set
,
5130 struct sseu_dev_status
{
5131 unsigned int slice_total
;
5132 unsigned int subslice_total
;
5133 unsigned int subslice_per_slice
;
5134 unsigned int eu_total
;
5135 unsigned int eu_per_subslice
;
5138 static void cherryview_sseu_device_status(struct drm_device
*dev
,
5139 struct sseu_dev_status
*stat
)
5141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5144 u32 sig1
[ss_max
], sig2
[ss_max
];
5146 sig1
[0] = I915_READ(CHV_POWER_SS0_SIG1
);
5147 sig1
[1] = I915_READ(CHV_POWER_SS1_SIG1
);
5148 sig2
[0] = I915_READ(CHV_POWER_SS0_SIG2
);
5149 sig2
[1] = I915_READ(CHV_POWER_SS1_SIG2
);
5151 for (ss
= 0; ss
< ss_max
; ss
++) {
5152 unsigned int eu_cnt
;
5154 if (sig1
[ss
] & CHV_SS_PG_ENABLE
)
5155 /* skip disabled subslice */
5158 stat
->slice_total
= 1;
5159 stat
->subslice_per_slice
++;
5160 eu_cnt
= ((sig1
[ss
] & CHV_EU08_PG_ENABLE
) ? 0 : 2) +
5161 ((sig1
[ss
] & CHV_EU19_PG_ENABLE
) ? 0 : 2) +
5162 ((sig1
[ss
] & CHV_EU210_PG_ENABLE
) ? 0 : 2) +
5163 ((sig2
[ss
] & CHV_EU311_PG_ENABLE
) ? 0 : 2);
5164 stat
->eu_total
+= eu_cnt
;
5165 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
, eu_cnt
);
5167 stat
->subslice_total
= stat
->subslice_per_slice
;
5170 static void gen9_sseu_device_status(struct drm_device
*dev
,
5171 struct sseu_dev_status
*stat
)
5173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5174 int s_max
= 3, ss_max
= 4;
5176 u32 s_reg
[s_max
], eu_reg
[2*s_max
], eu_mask
[2];
5178 /* BXT has a single slice and at most 3 subslices. */
5179 if (IS_BROXTON(dev
)) {
5184 for (s
= 0; s
< s_max
; s
++) {
5185 s_reg
[s
] = I915_READ(GEN9_SLICE_PGCTL_ACK(s
));
5186 eu_reg
[2*s
] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s
));
5187 eu_reg
[2*s
+ 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s
));
5190 eu_mask
[0] = GEN9_PGCTL_SSA_EU08_ACK
|
5191 GEN9_PGCTL_SSA_EU19_ACK
|
5192 GEN9_PGCTL_SSA_EU210_ACK
|
5193 GEN9_PGCTL_SSA_EU311_ACK
;
5194 eu_mask
[1] = GEN9_PGCTL_SSB_EU08_ACK
|
5195 GEN9_PGCTL_SSB_EU19_ACK
|
5196 GEN9_PGCTL_SSB_EU210_ACK
|
5197 GEN9_PGCTL_SSB_EU311_ACK
;
5199 for (s
= 0; s
< s_max
; s
++) {
5200 unsigned int ss_cnt
= 0;
5202 if ((s_reg
[s
] & GEN9_PGCTL_SLICE_ACK
) == 0)
5203 /* skip disabled slice */
5206 stat
->slice_total
++;
5208 if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
))
5209 ss_cnt
= INTEL_INFO(dev
)->subslice_per_slice
;
5211 for (ss
= 0; ss
< ss_max
; ss
++) {
5212 unsigned int eu_cnt
;
5214 if (IS_BROXTON(dev
) &&
5215 !(s_reg
[s
] & (GEN9_PGCTL_SS_ACK(ss
))))
5216 /* skip disabled subslice */
5219 if (IS_BROXTON(dev
))
5222 eu_cnt
= 2 * hweight32(eu_reg
[2*s
+ ss
/2] &
5224 stat
->eu_total
+= eu_cnt
;
5225 stat
->eu_per_subslice
= max(stat
->eu_per_subslice
,
5229 stat
->subslice_total
+= ss_cnt
;
5230 stat
->subslice_per_slice
= max(stat
->subslice_per_slice
,
5235 static void broadwell_sseu_device_status(struct drm_device
*dev
,
5236 struct sseu_dev_status
*stat
)
5238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5240 u32 slice_info
= I915_READ(GEN8_GT_SLICE_INFO
);
5242 stat
->slice_total
= hweight32(slice_info
& GEN8_LSLICESTAT_MASK
);
5244 if (stat
->slice_total
) {
5245 stat
->subslice_per_slice
= INTEL_INFO(dev
)->subslice_per_slice
;
5246 stat
->subslice_total
= stat
->slice_total
*
5247 stat
->subslice_per_slice
;
5248 stat
->eu_per_subslice
= INTEL_INFO(dev
)->eu_per_subslice
;
5249 stat
->eu_total
= stat
->eu_per_subslice
* stat
->subslice_total
;
5251 /* subtract fused off EU(s) from enabled slice(s) */
5252 for (s
= 0; s
< stat
->slice_total
; s
++) {
5253 u8 subslice_7eu
= INTEL_INFO(dev
)->subslice_7eu
[s
];
5255 stat
->eu_total
-= hweight8(subslice_7eu
);
5260 static int i915_sseu_status(struct seq_file
*m
, void *unused
)
5262 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
5263 struct drm_device
*dev
= node
->minor
->dev
;
5264 struct sseu_dev_status stat
;
5266 if (INTEL_INFO(dev
)->gen
< 8)
5269 seq_puts(m
, "SSEU Device Info\n");
5270 seq_printf(m
, " Available Slice Total: %u\n",
5271 INTEL_INFO(dev
)->slice_total
);
5272 seq_printf(m
, " Available Subslice Total: %u\n",
5273 INTEL_INFO(dev
)->subslice_total
);
5274 seq_printf(m
, " Available Subslice Per Slice: %u\n",
5275 INTEL_INFO(dev
)->subslice_per_slice
);
5276 seq_printf(m
, " Available EU Total: %u\n",
5277 INTEL_INFO(dev
)->eu_total
);
5278 seq_printf(m
, " Available EU Per Subslice: %u\n",
5279 INTEL_INFO(dev
)->eu_per_subslice
);
5280 seq_printf(m
, " Has Slice Power Gating: %s\n",
5281 yesno(INTEL_INFO(dev
)->has_slice_pg
));
5282 seq_printf(m
, " Has Subslice Power Gating: %s\n",
5283 yesno(INTEL_INFO(dev
)->has_subslice_pg
));
5284 seq_printf(m
, " Has EU Power Gating: %s\n",
5285 yesno(INTEL_INFO(dev
)->has_eu_pg
));
5287 seq_puts(m
, "SSEU Device Status\n");
5288 memset(&stat
, 0, sizeof(stat
));
5289 if (IS_CHERRYVIEW(dev
)) {
5290 cherryview_sseu_device_status(dev
, &stat
);
5291 } else if (IS_BROADWELL(dev
)) {
5292 broadwell_sseu_device_status(dev
, &stat
);
5293 } else if (INTEL_INFO(dev
)->gen
>= 9) {
5294 gen9_sseu_device_status(dev
, &stat
);
5296 seq_printf(m
, " Enabled Slice Total: %u\n",
5298 seq_printf(m
, " Enabled Subslice Total: %u\n",
5299 stat
.subslice_total
);
5300 seq_printf(m
, " Enabled Subslice Per Slice: %u\n",
5301 stat
.subslice_per_slice
);
5302 seq_printf(m
, " Enabled EU Total: %u\n",
5304 seq_printf(m
, " Enabled EU Per Subslice: %u\n",
5305 stat
.eu_per_subslice
);
5310 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
5312 struct drm_device
*dev
= inode
->i_private
;
5313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5315 if (INTEL_INFO(dev
)->gen
< 6)
5318 intel_runtime_pm_get(dev_priv
);
5319 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5324 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
5326 struct drm_device
*dev
= inode
->i_private
;
5327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5329 if (INTEL_INFO(dev
)->gen
< 6)
5332 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5333 intel_runtime_pm_put(dev_priv
);
5338 static const struct file_operations i915_forcewake_fops
= {
5339 .owner
= THIS_MODULE
,
5340 .open
= i915_forcewake_open
,
5341 .release
= i915_forcewake_release
,
5344 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
5346 struct drm_device
*dev
= minor
->dev
;
5349 ent
= debugfs_create_file("i915_forcewake_user",
5352 &i915_forcewake_fops
);
5356 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
5359 static int i915_debugfs_create(struct dentry
*root
,
5360 struct drm_minor
*minor
,
5362 const struct file_operations
*fops
)
5364 struct drm_device
*dev
= minor
->dev
;
5367 ent
= debugfs_create_file(name
,
5374 return drm_add_fake_info_node(minor
, ent
, fops
);
5377 static const struct drm_info_list i915_debugfs_list
[] = {
5378 {"i915_capabilities", i915_capabilities
, 0},
5379 {"i915_gem_objects", i915_gem_object_info
, 0},
5380 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
5381 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
5382 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
5383 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
5384 {"i915_gem_stolen", i915_gem_stolen_list_info
},
5385 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
5386 {"i915_gem_request", i915_gem_request_info
, 0},
5387 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
5388 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
5389 {"i915_gem_interrupt", i915_interrupt_info
, 0},
5390 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
5391 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
5392 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
5393 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
5394 {"i915_gem_batch_pool", i915_gem_batch_pool_info
, 0},
5395 {"i915_guc_info", i915_guc_info
, 0},
5396 {"i915_guc_load_status", i915_guc_load_status_info
, 0},
5397 {"i915_guc_log_dump", i915_guc_log_dump
, 0},
5398 {"i915_frequency_info", i915_frequency_info
, 0},
5399 {"i915_hangcheck_info", i915_hangcheck_info
, 0},
5400 {"i915_drpc_info", i915_drpc_info
, 0},
5401 {"i915_emon_status", i915_emon_status
, 0},
5402 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
5403 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking
, 0},
5404 {"i915_fbc_status", i915_fbc_status
, 0},
5405 {"i915_ips_status", i915_ips_status
, 0},
5406 {"i915_sr_status", i915_sr_status
, 0},
5407 {"i915_opregion", i915_opregion
, 0},
5408 {"i915_vbt", i915_vbt
, 0},
5409 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
5410 {"i915_context_status", i915_context_status
, 0},
5411 {"i915_dump_lrc", i915_dump_lrc
, 0},
5412 {"i915_execlists", i915_execlists
, 0},
5413 {"i915_forcewake_domains", i915_forcewake_domains
, 0},
5414 {"i915_swizzle_info", i915_swizzle_info
, 0},
5415 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
5416 {"i915_llc", i915_llc
, 0},
5417 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
5418 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
5419 {"i915_energy_uJ", i915_energy_uJ
, 0},
5420 {"i915_runtime_pm_status", i915_runtime_pm_status
, 0},
5421 {"i915_power_domain_info", i915_power_domain_info
, 0},
5422 {"i915_dmc_info", i915_dmc_info
, 0},
5423 {"i915_display_info", i915_display_info
, 0},
5424 {"i915_semaphore_status", i915_semaphore_status
, 0},
5425 {"i915_shared_dplls_info", i915_shared_dplls_info
, 0},
5426 {"i915_dp_mst_info", i915_dp_mst_info
, 0},
5427 {"i915_wa_registers", i915_wa_registers
, 0},
5428 {"i915_ddb_info", i915_ddb_info
, 0},
5429 {"i915_sseu_status", i915_sseu_status
, 0},
5430 {"i915_drrs_status", i915_drrs_status
, 0},
5431 {"i915_rps_boost_info", i915_rps_boost_info
, 0},
5433 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5435 static const struct i915_debugfs_files
{
5437 const struct file_operations
*fops
;
5438 } i915_debugfs_files
[] = {
5439 {"i915_wedged", &i915_wedged_fops
},
5440 {"i915_max_freq", &i915_max_freq_fops
},
5441 {"i915_min_freq", &i915_min_freq_fops
},
5442 {"i915_cache_sharing", &i915_cache_sharing_fops
},
5443 {"i915_ring_stop", &i915_ring_stop_fops
},
5444 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
5445 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
5446 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
5447 {"i915_error_state", &i915_error_state_fops
},
5448 {"i915_next_seqno", &i915_next_seqno_fops
},
5449 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
5450 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
5451 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
5452 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
5453 {"i915_fbc_false_color", &i915_fbc_fc_fops
},
5454 {"i915_dp_test_data", &i915_displayport_test_data_fops
},
5455 {"i915_dp_test_type", &i915_displayport_test_type_fops
},
5456 {"i915_dp_test_active", &i915_displayport_test_active_fops
}
5459 void intel_display_crc_init(struct drm_device
*dev
)
5461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5464 for_each_pipe(dev_priv
, pipe
) {
5465 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
5467 pipe_crc
->opened
= false;
5468 spin_lock_init(&pipe_crc
->lock
);
5469 init_waitqueue_head(&pipe_crc
->wq
);
5473 int i915_debugfs_init(struct drm_minor
*minor
)
5477 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
5481 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5482 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
5487 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5488 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
5489 i915_debugfs_files
[i
].name
,
5490 i915_debugfs_files
[i
].fops
);
5495 return drm_debugfs_create_files(i915_debugfs_list
,
5496 I915_DEBUGFS_ENTRIES
,
5497 minor
->debugfs_root
, minor
);
5500 void i915_debugfs_cleanup(struct drm_minor
*minor
)
5504 drm_debugfs_remove_files(i915_debugfs_list
,
5505 I915_DEBUGFS_ENTRIES
, minor
);
5507 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
5510 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
5511 struct drm_info_list
*info_list
=
5512 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
5514 drm_debugfs_remove_files(info_list
, 1, minor
);
5517 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
5518 struct drm_info_list
*info_list
=
5519 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
5521 drm_debugfs_remove_files(info_list
, 1, minor
);
5526 /* DPCD dump start address. */
5527 unsigned int offset
;
5528 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5530 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5532 /* Only valid for eDP. */
5536 static const struct dpcd_block i915_dpcd_debug
[] = {
5537 { .offset
= DP_DPCD_REV
, .size
= DP_RECEIVER_CAP_SIZE
},
5538 { .offset
= DP_PSR_SUPPORT
, .end
= DP_PSR_CAPS
},
5539 { .offset
= DP_DOWNSTREAM_PORT_0
, .size
= 16 },
5540 { .offset
= DP_LINK_BW_SET
, .end
= DP_EDP_CONFIGURATION_SET
},
5541 { .offset
= DP_SINK_COUNT
, .end
= DP_ADJUST_REQUEST_LANE2_3
},
5542 { .offset
= DP_SET_POWER
},
5543 { .offset
= DP_EDP_DPCD_REV
},
5544 { .offset
= DP_EDP_GENERAL_CAP_1
, .end
= DP_EDP_GENERAL_CAP_3
},
5545 { .offset
= DP_EDP_DISPLAY_CONTROL_REGISTER
, .end
= DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB
},
5546 { .offset
= DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET
, .end
= DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET
},
5549 static int i915_dpcd_show(struct seq_file
*m
, void *data
)
5551 struct drm_connector
*connector
= m
->private;
5552 struct intel_dp
*intel_dp
=
5553 enc_to_intel_dp(&intel_attached_encoder(connector
)->base
);
5558 if (connector
->status
!= connector_status_connected
)
5561 for (i
= 0; i
< ARRAY_SIZE(i915_dpcd_debug
); i
++) {
5562 const struct dpcd_block
*b
= &i915_dpcd_debug
[i
];
5563 size_t size
= b
->end
? b
->end
- b
->offset
+ 1 : (b
->size
?: 1);
5566 connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
5569 /* low tech for now */
5570 if (WARN_ON(size
> sizeof(buf
)))
5573 err
= drm_dp_dpcd_read(&intel_dp
->aux
, b
->offset
, buf
, size
);
5575 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5576 size
, b
->offset
, err
);
5580 seq_printf(m
, "%04x: %*ph\n", b
->offset
, (int) size
, buf
);
5586 static int i915_dpcd_open(struct inode
*inode
, struct file
*file
)
5588 return single_open(file
, i915_dpcd_show
, inode
->i_private
);
5591 static const struct file_operations i915_dpcd_fops
= {
5592 .owner
= THIS_MODULE
,
5593 .open
= i915_dpcd_open
,
5595 .llseek
= seq_lseek
,
5596 .release
= single_release
,
5600 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5601 * @connector: pointer to a registered drm_connector
5603 * Cleanup will be done by drm_connector_unregister() through a call to
5604 * drm_debugfs_connector_remove().
5606 * Returns 0 on success, negative error codes on error.
5608 int i915_debugfs_connector_add(struct drm_connector
*connector
)
5610 struct dentry
*root
= connector
->debugfs_entry
;
5612 /* The connector must have been registered beforehands. */
5616 if (connector
->connector_type
== DRM_MODE_CONNECTOR_DisplayPort
||
5617 connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
5618 debugfs_create_file("i915_dpcd", S_IRUGO
, root
, connector
,