2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v
)
51 return v
? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor
*minor
,
61 struct drm_info_node
*node
;
63 node
= kmalloc(sizeof(*node
), GFP_KERNEL
);
71 node
->info_ent
= (void *) key
;
73 mutex_lock(&minor
->debugfs_lock
);
74 list_add(&node
->list
, &minor
->debugfs_list
);
75 mutex_unlock(&minor
->debugfs_lock
);
80 static int i915_capabilities(struct seq_file
*m
, void *data
)
82 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
83 struct drm_device
*dev
= node
->minor
->dev
;
84 const struct intel_device_info
*info
= INTEL_INFO(dev
);
86 seq_printf(m
, "gen: %d\n", info
->gen
);
87 seq_printf(m
, "pch: %d\n", INTEL_PCH_TYPE(dev
));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG
, SEP_SEMICOLON
);
97 static const char *get_pin_flag(struct drm_i915_gem_object
*obj
)
99 if (obj
->user_pin_count
> 0)
101 else if (i915_gem_obj_is_pinned(obj
))
107 static const char *get_tiling_flag(struct drm_i915_gem_object
*obj
)
109 switch (obj
->tiling_mode
) {
111 case I915_TILING_NONE
: return " ";
112 case I915_TILING_X
: return "X";
113 case I915_TILING_Y
: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object
*obj
)
119 return obj
->has_global_gtt_mapping
? "g" : " ";
123 describe_obj(struct seq_file
*m
, struct drm_i915_gem_object
*obj
)
125 struct i915_vma
*vma
;
128 seq_printf(m
, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj
),
132 get_global_flag(obj
),
133 obj
->base
.size
/ 1024,
134 obj
->base
.read_domains
,
135 obj
->base
.write_domain
,
136 obj
->last_read_seqno
,
137 obj
->last_write_seqno
,
138 obj
->last_fenced_seqno
,
139 i915_cache_level_str(obj
->cache_level
),
140 obj
->dirty
? " dirty" : "",
141 obj
->madv
== I915_MADV_DONTNEED
? " purgeable" : "");
143 seq_printf(m
, " (name: %d)", obj
->base
.name
);
144 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
145 if (vma
->pin_count
> 0)
147 seq_printf(m
, " (pinned x %d)", pin_count
);
148 if (obj
->pin_display
)
149 seq_printf(m
, " (display)");
150 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
151 seq_printf(m
, " (fence: %d)", obj
->fence_reg
);
152 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
153 if (!i915_is_ggtt(vma
->vm
))
157 seq_printf(m
, "gtt offset: %08lx, size: %08lx)",
158 vma
->node
.start
, vma
->node
.size
);
161 seq_printf(m
, " (stolen: %08lx)", obj
->stolen
->start
);
162 if (obj
->pin_mappable
|| obj
->fault_mappable
) {
164 if (obj
->pin_mappable
)
166 if (obj
->fault_mappable
)
169 seq_printf(m
, " (%s mappable)", s
);
171 if (obj
->ring
!= NULL
)
172 seq_printf(m
, " (%s)", obj
->ring
->name
);
175 static void describe_ctx(struct seq_file
*m
, struct i915_hw_context
*ctx
)
177 seq_putc(m
, ctx
->is_initialized
? 'I' : 'i');
178 seq_putc(m
, ctx
->remap_slice
? 'R' : 'r');
182 static int i915_gem_object_list_info(struct seq_file
*m
, void *data
)
184 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
185 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
186 struct list_head
*head
;
187 struct drm_device
*dev
= node
->minor
->dev
;
188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
189 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
190 struct i915_vma
*vma
;
191 size_t total_obj_size
, total_gtt_size
;
194 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
198 /* FIXME: the user of this interface might want more than just GGTT */
201 seq_puts(m
, "Active:\n");
202 head
= &vm
->active_list
;
205 seq_puts(m
, "Inactive:\n");
206 head
= &vm
->inactive_list
;
209 mutex_unlock(&dev
->struct_mutex
);
213 total_obj_size
= total_gtt_size
= count
= 0;
214 list_for_each_entry(vma
, head
, mm_list
) {
216 describe_obj(m
, vma
->obj
);
218 total_obj_size
+= vma
->obj
->base
.size
;
219 total_gtt_size
+= vma
->node
.size
;
222 mutex_unlock(&dev
->struct_mutex
);
224 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count
, total_obj_size
, total_gtt_size
);
229 static int obj_rank_by_stolen(void *priv
,
230 struct list_head
*A
, struct list_head
*B
)
232 struct drm_i915_gem_object
*a
=
233 container_of(A
, struct drm_i915_gem_object
, obj_exec_link
);
234 struct drm_i915_gem_object
*b
=
235 container_of(B
, struct drm_i915_gem_object
, obj_exec_link
);
237 return a
->stolen
->start
- b
->stolen
->start
;
240 static int i915_gem_stolen_list_info(struct seq_file
*m
, void *data
)
242 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
243 struct drm_device
*dev
= node
->minor
->dev
;
244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
245 struct drm_i915_gem_object
*obj
;
246 size_t total_obj_size
, total_gtt_size
;
250 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
254 total_obj_size
= total_gtt_size
= count
= 0;
255 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
256 if (obj
->stolen
== NULL
)
259 list_add(&obj
->obj_exec_link
, &stolen
);
261 total_obj_size
+= obj
->base
.size
;
262 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
265 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
266 if (obj
->stolen
== NULL
)
269 list_add(&obj
->obj_exec_link
, &stolen
);
271 total_obj_size
+= obj
->base
.size
;
274 list_sort(NULL
, &stolen
, obj_rank_by_stolen
);
275 seq_puts(m
, "Stolen:\n");
276 while (!list_empty(&stolen
)) {
277 obj
= list_first_entry(&stolen
, typeof(*obj
), obj_exec_link
);
279 describe_obj(m
, obj
);
281 list_del_init(&obj
->obj_exec_link
);
283 mutex_unlock(&dev
->struct_mutex
);
285 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count
, total_obj_size
, total_gtt_size
);
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
302 struct drm_i915_file_private
*file_priv
;
304 size_t total
, unbound
;
305 size_t global
, shared
;
306 size_t active
, inactive
;
309 static int per_file_stats(int id
, void *ptr
, void *data
)
311 struct drm_i915_gem_object
*obj
= ptr
;
312 struct file_stats
*stats
= data
;
313 struct i915_vma
*vma
;
316 stats
->total
+= obj
->base
.size
;
318 if (obj
->base
.name
|| obj
->base
.dma_buf
)
319 stats
->shared
+= obj
->base
.size
;
321 if (USES_FULL_PPGTT(obj
->base
.dev
)) {
322 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
323 struct i915_hw_ppgtt
*ppgtt
;
325 if (!drm_mm_node_allocated(&vma
->node
))
328 if (i915_is_ggtt(vma
->vm
)) {
329 stats
->global
+= obj
->base
.size
;
333 ppgtt
= container_of(vma
->vm
, struct i915_hw_ppgtt
, base
);
334 if (ppgtt
->ctx
&& ppgtt
->ctx
->file_priv
!= stats
->file_priv
)
337 if (obj
->ring
) /* XXX per-vma statistic */
338 stats
->active
+= obj
->base
.size
;
340 stats
->inactive
+= obj
->base
.size
;
345 if (i915_gem_obj_ggtt_bound(obj
)) {
346 stats
->global
+= obj
->base
.size
;
348 stats
->active
+= obj
->base
.size
;
350 stats
->inactive
+= obj
->base
.size
;
355 if (!list_empty(&obj
->global_list
))
356 stats
->unbound
+= obj
->base
.size
;
361 #define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
372 static int i915_gem_object_info(struct seq_file
*m
, void* data
)
374 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
375 struct drm_device
*dev
= node
->minor
->dev
;
376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
377 u32 count
, mappable_count
, purgeable_count
;
378 size_t size
, mappable_size
, purgeable_size
;
379 struct drm_i915_gem_object
*obj
;
380 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
381 struct drm_file
*file
;
382 struct i915_vma
*vma
;
385 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
389 seq_printf(m
, "%u objects, %zu bytes\n",
390 dev_priv
->mm
.object_count
,
391 dev_priv
->mm
.object_memory
);
393 size
= count
= mappable_size
= mappable_count
= 0;
394 count_objects(&dev_priv
->mm
.bound_list
, global_list
);
395 seq_printf(m
, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count
, mappable_count
, size
, mappable_size
);
398 size
= count
= mappable_size
= mappable_count
= 0;
399 count_vmas(&vm
->active_list
, mm_list
);
400 seq_printf(m
, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count
, mappable_count
, size
, mappable_size
);
403 size
= count
= mappable_size
= mappable_count
= 0;
404 count_vmas(&vm
->inactive_list
, mm_list
);
405 seq_printf(m
, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count
, mappable_count
, size
, mappable_size
);
408 size
= count
= purgeable_size
= purgeable_count
= 0;
409 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
410 size
+= obj
->base
.size
, ++count
;
411 if (obj
->madv
== I915_MADV_DONTNEED
)
412 purgeable_size
+= obj
->base
.size
, ++purgeable_count
;
414 seq_printf(m
, "%u unbound objects, %zu bytes\n", count
, size
);
416 size
= count
= mappable_size
= mappable_count
= 0;
417 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
418 if (obj
->fault_mappable
) {
419 size
+= i915_gem_obj_ggtt_size(obj
);
422 if (obj
->pin_mappable
) {
423 mappable_size
+= i915_gem_obj_ggtt_size(obj
);
426 if (obj
->madv
== I915_MADV_DONTNEED
) {
427 purgeable_size
+= obj
->base
.size
;
431 seq_printf(m
, "%u purgeable objects, %zu bytes\n",
432 purgeable_count
, purgeable_size
);
433 seq_printf(m
, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count
, mappable_size
);
435 seq_printf(m
, "%u fault mappable objects, %zu bytes\n",
438 seq_printf(m
, "%zu [%lu] gtt total\n",
439 dev_priv
->gtt
.base
.total
,
440 dev_priv
->gtt
.mappable_end
- dev_priv
->gtt
.base
.start
);
443 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
444 struct file_stats stats
;
445 struct task_struct
*task
;
447 memset(&stats
, 0, sizeof(stats
));
448 stats
.file_priv
= file
->driver_priv
;
449 idr_for_each(&file
->object_idr
, per_file_stats
, &stats
);
451 * Although we have a valid reference on file->pid, that does
452 * not guarantee that the task_struct who called get_pid() is
453 * still alive (e.g. get_pid(current) => fork() => exit()).
454 * Therefore, we need to protect this ->comm access using RCU.
457 task
= pid_task(file
->pid
, PIDTYPE_PID
);
458 seq_printf(m
, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
459 task
? task
->comm
: "<unknown>",
470 mutex_unlock(&dev
->struct_mutex
);
475 static int i915_gem_gtt_info(struct seq_file
*m
, void *data
)
477 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
478 struct drm_device
*dev
= node
->minor
->dev
;
479 uintptr_t list
= (uintptr_t) node
->info_ent
->data
;
480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
481 struct drm_i915_gem_object
*obj
;
482 size_t total_obj_size
, total_gtt_size
;
485 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
489 total_obj_size
= total_gtt_size
= count
= 0;
490 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
491 if (list
== PINNED_LIST
&& !i915_gem_obj_is_pinned(obj
))
495 describe_obj(m
, obj
);
497 total_obj_size
+= obj
->base
.size
;
498 total_gtt_size
+= i915_gem_obj_ggtt_size(obj
);
502 mutex_unlock(&dev
->struct_mutex
);
504 seq_printf(m
, "Total %d objects, %zu bytes, %zu GTT size\n",
505 count
, total_obj_size
, total_gtt_size
);
510 static int i915_gem_pageflip_info(struct seq_file
*m
, void *data
)
512 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
513 struct drm_device
*dev
= node
->minor
->dev
;
515 struct intel_crtc
*crtc
;
517 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
518 const char pipe
= pipe_name(crtc
->pipe
);
519 const char plane
= plane_name(crtc
->plane
);
520 struct intel_unpin_work
*work
;
522 spin_lock_irqsave(&dev
->event_lock
, flags
);
523 work
= crtc
->unpin_work
;
525 seq_printf(m
, "No flip due on pipe %c (plane %c)\n",
528 if (atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
529 seq_printf(m
, "Flip queued on pipe %c (plane %c)\n",
532 seq_printf(m
, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
535 if (work
->enable_stall_check
)
536 seq_puts(m
, "Stall check enabled, ");
538 seq_puts(m
, "Stall check waiting for page flip ioctl, ");
539 seq_printf(m
, "%d prepares\n", atomic_read(&work
->pending
));
541 if (work
->old_fb_obj
) {
542 struct drm_i915_gem_object
*obj
= work
->old_fb_obj
;
544 seq_printf(m
, "Old framebuffer gtt_offset 0x%08lx\n",
545 i915_gem_obj_ggtt_offset(obj
));
547 if (work
->pending_flip_obj
) {
548 struct drm_i915_gem_object
*obj
= work
->pending_flip_obj
;
550 seq_printf(m
, "New framebuffer gtt_offset 0x%08lx\n",
551 i915_gem_obj_ggtt_offset(obj
));
554 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
560 static int i915_gem_request_info(struct seq_file
*m
, void *data
)
562 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
563 struct drm_device
*dev
= node
->minor
->dev
;
564 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
565 struct intel_ring_buffer
*ring
;
566 struct drm_i915_gem_request
*gem_request
;
569 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
574 for_each_ring(ring
, dev_priv
, i
) {
575 if (list_empty(&ring
->request_list
))
578 seq_printf(m
, "%s requests:\n", ring
->name
);
579 list_for_each_entry(gem_request
,
582 seq_printf(m
, " %d @ %d\n",
584 (int) (jiffies
- gem_request
->emitted_jiffies
));
588 mutex_unlock(&dev
->struct_mutex
);
591 seq_puts(m
, "No requests\n");
596 static void i915_ring_seqno_info(struct seq_file
*m
,
597 struct intel_ring_buffer
*ring
)
599 if (ring
->get_seqno
) {
600 seq_printf(m
, "Current sequence (%s): %u\n",
601 ring
->name
, ring
->get_seqno(ring
, false));
605 static int i915_gem_seqno_info(struct seq_file
*m
, void *data
)
607 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
608 struct drm_device
*dev
= node
->minor
->dev
;
609 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
610 struct intel_ring_buffer
*ring
;
613 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
616 intel_runtime_pm_get(dev_priv
);
618 for_each_ring(ring
, dev_priv
, i
)
619 i915_ring_seqno_info(m
, ring
);
621 intel_runtime_pm_put(dev_priv
);
622 mutex_unlock(&dev
->struct_mutex
);
628 static int i915_interrupt_info(struct seq_file
*m
, void *data
)
630 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
631 struct drm_device
*dev
= node
->minor
->dev
;
632 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
633 struct intel_ring_buffer
*ring
;
636 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
639 intel_runtime_pm_get(dev_priv
);
641 if (INTEL_INFO(dev
)->gen
>= 8) {
642 seq_printf(m
, "Master Interrupt Control:\t%08x\n",
643 I915_READ(GEN8_MASTER_IRQ
));
645 for (i
= 0; i
< 4; i
++) {
646 seq_printf(m
, "GT Interrupt IMR %d:\t%08x\n",
647 i
, I915_READ(GEN8_GT_IMR(i
)));
648 seq_printf(m
, "GT Interrupt IIR %d:\t%08x\n",
649 i
, I915_READ(GEN8_GT_IIR(i
)));
650 seq_printf(m
, "GT Interrupt IER %d:\t%08x\n",
651 i
, I915_READ(GEN8_GT_IER(i
)));
654 for_each_pipe(pipe
) {
655 seq_printf(m
, "Pipe %c IMR:\t%08x\n",
657 I915_READ(GEN8_DE_PIPE_IMR(pipe
)));
658 seq_printf(m
, "Pipe %c IIR:\t%08x\n",
660 I915_READ(GEN8_DE_PIPE_IIR(pipe
)));
661 seq_printf(m
, "Pipe %c IER:\t%08x\n",
663 I915_READ(GEN8_DE_PIPE_IER(pipe
)));
666 seq_printf(m
, "Display Engine port interrupt mask:\t%08x\n",
667 I915_READ(GEN8_DE_PORT_IMR
));
668 seq_printf(m
, "Display Engine port interrupt identity:\t%08x\n",
669 I915_READ(GEN8_DE_PORT_IIR
));
670 seq_printf(m
, "Display Engine port interrupt enable:\t%08x\n",
671 I915_READ(GEN8_DE_PORT_IER
));
673 seq_printf(m
, "Display Engine misc interrupt mask:\t%08x\n",
674 I915_READ(GEN8_DE_MISC_IMR
));
675 seq_printf(m
, "Display Engine misc interrupt identity:\t%08x\n",
676 I915_READ(GEN8_DE_MISC_IIR
));
677 seq_printf(m
, "Display Engine misc interrupt enable:\t%08x\n",
678 I915_READ(GEN8_DE_MISC_IER
));
680 seq_printf(m
, "PCU interrupt mask:\t%08x\n",
681 I915_READ(GEN8_PCU_IMR
));
682 seq_printf(m
, "PCU interrupt identity:\t%08x\n",
683 I915_READ(GEN8_PCU_IIR
));
684 seq_printf(m
, "PCU interrupt enable:\t%08x\n",
685 I915_READ(GEN8_PCU_IER
));
686 } else if (IS_VALLEYVIEW(dev
)) {
687 seq_printf(m
, "Display IER:\t%08x\n",
689 seq_printf(m
, "Display IIR:\t%08x\n",
691 seq_printf(m
, "Display IIR_RW:\t%08x\n",
692 I915_READ(VLV_IIR_RW
));
693 seq_printf(m
, "Display IMR:\t%08x\n",
696 seq_printf(m
, "Pipe %c stat:\t%08x\n",
698 I915_READ(PIPESTAT(pipe
)));
700 seq_printf(m
, "Master IER:\t%08x\n",
701 I915_READ(VLV_MASTER_IER
));
703 seq_printf(m
, "Render IER:\t%08x\n",
705 seq_printf(m
, "Render IIR:\t%08x\n",
707 seq_printf(m
, "Render IMR:\t%08x\n",
710 seq_printf(m
, "PM IER:\t\t%08x\n",
711 I915_READ(GEN6_PMIER
));
712 seq_printf(m
, "PM IIR:\t\t%08x\n",
713 I915_READ(GEN6_PMIIR
));
714 seq_printf(m
, "PM IMR:\t\t%08x\n",
715 I915_READ(GEN6_PMIMR
));
717 seq_printf(m
, "Port hotplug:\t%08x\n",
718 I915_READ(PORT_HOTPLUG_EN
));
719 seq_printf(m
, "DPFLIPSTAT:\t%08x\n",
720 I915_READ(VLV_DPFLIPSTAT
));
721 seq_printf(m
, "DPINVGTT:\t%08x\n",
722 I915_READ(DPINVGTT
));
724 } else if (!HAS_PCH_SPLIT(dev
)) {
725 seq_printf(m
, "Interrupt enable: %08x\n",
727 seq_printf(m
, "Interrupt identity: %08x\n",
729 seq_printf(m
, "Interrupt mask: %08x\n",
732 seq_printf(m
, "Pipe %c stat: %08x\n",
734 I915_READ(PIPESTAT(pipe
)));
736 seq_printf(m
, "North Display Interrupt enable: %08x\n",
738 seq_printf(m
, "North Display Interrupt identity: %08x\n",
740 seq_printf(m
, "North Display Interrupt mask: %08x\n",
742 seq_printf(m
, "South Display Interrupt enable: %08x\n",
744 seq_printf(m
, "South Display Interrupt identity: %08x\n",
746 seq_printf(m
, "South Display Interrupt mask: %08x\n",
748 seq_printf(m
, "Graphics Interrupt enable: %08x\n",
750 seq_printf(m
, "Graphics Interrupt identity: %08x\n",
752 seq_printf(m
, "Graphics Interrupt mask: %08x\n",
755 for_each_ring(ring
, dev_priv
, i
) {
756 if (INTEL_INFO(dev
)->gen
>= 6) {
758 "Graphics Interrupt mask (%s): %08x\n",
759 ring
->name
, I915_READ_IMR(ring
));
761 i915_ring_seqno_info(m
, ring
);
763 intel_runtime_pm_put(dev_priv
);
764 mutex_unlock(&dev
->struct_mutex
);
769 static int i915_gem_fence_regs_info(struct seq_file
*m
, void *data
)
771 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
772 struct drm_device
*dev
= node
->minor
->dev
;
773 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
776 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
780 seq_printf(m
, "Reserved fences = %d\n", dev_priv
->fence_reg_start
);
781 seq_printf(m
, "Total fences = %d\n", dev_priv
->num_fence_regs
);
782 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
783 struct drm_i915_gem_object
*obj
= dev_priv
->fence_regs
[i
].obj
;
785 seq_printf(m
, "Fence %d, pin count = %d, object = ",
786 i
, dev_priv
->fence_regs
[i
].pin_count
);
788 seq_puts(m
, "unused");
790 describe_obj(m
, obj
);
794 mutex_unlock(&dev
->struct_mutex
);
798 static int i915_hws_info(struct seq_file
*m
, void *data
)
800 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
801 struct drm_device
*dev
= node
->minor
->dev
;
802 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
803 struct intel_ring_buffer
*ring
;
807 ring
= &dev_priv
->ring
[(uintptr_t)node
->info_ent
->data
];
808 hws
= ring
->status_page
.page_addr
;
812 for (i
= 0; i
< 4096 / sizeof(u32
) / 4; i
+= 4) {
813 seq_printf(m
, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
815 hws
[i
], hws
[i
+ 1], hws
[i
+ 2], hws
[i
+ 3]);
821 i915_error_state_write(struct file
*filp
,
822 const char __user
*ubuf
,
826 struct i915_error_state_file_priv
*error_priv
= filp
->private_data
;
827 struct drm_device
*dev
= error_priv
->dev
;
830 DRM_DEBUG_DRIVER("Resetting error state\n");
832 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
836 i915_destroy_error_state(dev
);
837 mutex_unlock(&dev
->struct_mutex
);
842 static int i915_error_state_open(struct inode
*inode
, struct file
*file
)
844 struct drm_device
*dev
= inode
->i_private
;
845 struct i915_error_state_file_priv
*error_priv
;
847 error_priv
= kzalloc(sizeof(*error_priv
), GFP_KERNEL
);
851 error_priv
->dev
= dev
;
853 i915_error_state_get(dev
, error_priv
);
855 file
->private_data
= error_priv
;
860 static int i915_error_state_release(struct inode
*inode
, struct file
*file
)
862 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
864 i915_error_state_put(error_priv
);
870 static ssize_t
i915_error_state_read(struct file
*file
, char __user
*userbuf
,
871 size_t count
, loff_t
*pos
)
873 struct i915_error_state_file_priv
*error_priv
= file
->private_data
;
874 struct drm_i915_error_state_buf error_str
;
876 ssize_t ret_count
= 0;
879 ret
= i915_error_state_buf_init(&error_str
, count
, *pos
);
883 ret
= i915_error_state_to_str(&error_str
, error_priv
);
887 ret_count
= simple_read_from_buffer(userbuf
, count
, &tmp_pos
,
894 *pos
= error_str
.start
+ ret_count
;
896 i915_error_state_buf_release(&error_str
);
897 return ret
?: ret_count
;
900 static const struct file_operations i915_error_state_fops
= {
901 .owner
= THIS_MODULE
,
902 .open
= i915_error_state_open
,
903 .read
= i915_error_state_read
,
904 .write
= i915_error_state_write
,
905 .llseek
= default_llseek
,
906 .release
= i915_error_state_release
,
910 i915_next_seqno_get(void *data
, u64
*val
)
912 struct drm_device
*dev
= data
;
913 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
916 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
920 *val
= dev_priv
->next_seqno
;
921 mutex_unlock(&dev
->struct_mutex
);
927 i915_next_seqno_set(void *data
, u64 val
)
929 struct drm_device
*dev
= data
;
932 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
936 ret
= i915_gem_set_seqno(dev
, val
);
937 mutex_unlock(&dev
->struct_mutex
);
942 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops
,
943 i915_next_seqno_get
, i915_next_seqno_set
,
946 static int i915_rstdby_delays(struct seq_file
*m
, void *unused
)
948 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
949 struct drm_device
*dev
= node
->minor
->dev
;
950 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
954 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
957 intel_runtime_pm_get(dev_priv
);
959 crstanddelay
= I915_READ16(CRSTANDVID
);
961 intel_runtime_pm_put(dev_priv
);
962 mutex_unlock(&dev
->struct_mutex
);
964 seq_printf(m
, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay
>> 8) & 0x3f, (crstanddelay
& 0x3f));
969 static int i915_cur_delayinfo(struct seq_file
*m
, void *unused
)
971 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
972 struct drm_device
*dev
= node
->minor
->dev
;
973 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
976 intel_runtime_pm_get(dev_priv
);
978 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
981 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
982 u16 rgvstat
= I915_READ16(MEMSTAT_ILK
);
984 seq_printf(m
, "Requested P-state: %d\n", (rgvswctl
>> 8) & 0xf);
985 seq_printf(m
, "Requested VID: %d\n", rgvswctl
& 0x3f);
986 seq_printf(m
, "Current VID: %d\n", (rgvstat
& MEMSTAT_VID_MASK
) >>
988 seq_printf(m
, "Current P-state: %d\n",
989 (rgvstat
& MEMSTAT_PSTATE_MASK
) >> MEMSTAT_PSTATE_SHIFT
);
990 } else if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
991 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
992 u32 rp_state_limits
= I915_READ(GEN6_RP_STATE_LIMITS
);
993 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
994 u32 rpstat
, cagf
, reqf
;
995 u32 rpupei
, rpcurup
, rpprevup
;
996 u32 rpdownei
, rpcurdown
, rpprevdown
;
999 /* RPSTAT1 is in the GT power well */
1000 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1004 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
1006 reqf
= I915_READ(GEN6_RPNSWREQ
);
1007 reqf
&= ~GEN6_TURBO_DISABLE
;
1008 if (IS_HASWELL(dev
))
1012 reqf
*= GT_FREQUENCY_MULTIPLIER
;
1014 rpstat
= I915_READ(GEN6_RPSTAT1
);
1015 rpupei
= I915_READ(GEN6_RP_CUR_UP_EI
);
1016 rpcurup
= I915_READ(GEN6_RP_CUR_UP
);
1017 rpprevup
= I915_READ(GEN6_RP_PREV_UP
);
1018 rpdownei
= I915_READ(GEN6_RP_CUR_DOWN_EI
);
1019 rpcurdown
= I915_READ(GEN6_RP_CUR_DOWN
);
1020 rpprevdown
= I915_READ(GEN6_RP_PREV_DOWN
);
1021 if (IS_HASWELL(dev
))
1022 cagf
= (rpstat
& HSW_CAGF_MASK
) >> HSW_CAGF_SHIFT
;
1024 cagf
= (rpstat
& GEN6_CAGF_MASK
) >> GEN6_CAGF_SHIFT
;
1025 cagf
*= GT_FREQUENCY_MULTIPLIER
;
1027 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
1028 mutex_unlock(&dev
->struct_mutex
);
1030 seq_printf(m
, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status
);
1031 seq_printf(m
, "RPSTAT1: 0x%08x\n", rpstat
);
1032 seq_printf(m
, "Render p-state ratio: %d\n",
1033 (gt_perf_status
& 0xff00) >> 8);
1034 seq_printf(m
, "Render p-state VID: %d\n",
1035 gt_perf_status
& 0xff);
1036 seq_printf(m
, "Render p-state limit: %d\n",
1037 rp_state_limits
& 0xff);
1038 seq_printf(m
, "RPNSWREQ: %dMHz\n", reqf
);
1039 seq_printf(m
, "CAGF: %dMHz\n", cagf
);
1040 seq_printf(m
, "RP CUR UP EI: %dus\n", rpupei
&
1041 GEN6_CURICONT_MASK
);
1042 seq_printf(m
, "RP CUR UP: %dus\n", rpcurup
&
1043 GEN6_CURBSYTAVG_MASK
);
1044 seq_printf(m
, "RP PREV UP: %dus\n", rpprevup
&
1045 GEN6_CURBSYTAVG_MASK
);
1046 seq_printf(m
, "RP CUR DOWN EI: %dus\n", rpdownei
&
1048 seq_printf(m
, "RP CUR DOWN: %dus\n", rpcurdown
&
1049 GEN6_CURBSYTAVG_MASK
);
1050 seq_printf(m
, "RP PREV DOWN: %dus\n", rpprevdown
&
1051 GEN6_CURBSYTAVG_MASK
);
1053 max_freq
= (rp_state_cap
& 0xff0000) >> 16;
1054 seq_printf(m
, "Lowest (RPN) frequency: %dMHz\n",
1055 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1057 max_freq
= (rp_state_cap
& 0xff00) >> 8;
1058 seq_printf(m
, "Nominal (RP1) frequency: %dMHz\n",
1059 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1061 max_freq
= rp_state_cap
& 0xff;
1062 seq_printf(m
, "Max non-overclocked (RP0) frequency: %dMHz\n",
1063 max_freq
* GT_FREQUENCY_MULTIPLIER
);
1065 seq_printf(m
, "Max overclocked frequency: %dMHz\n",
1066 dev_priv
->rps
.max_freq
* GT_FREQUENCY_MULTIPLIER
);
1067 } else if (IS_VALLEYVIEW(dev
)) {
1070 mutex_lock(&dev_priv
->rps
.hw_lock
);
1071 freq_sts
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
1072 seq_printf(m
, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts
);
1073 seq_printf(m
, "DDR freq: %d MHz\n", dev_priv
->mem_freq
);
1075 val
= valleyview_rps_max_freq(dev_priv
);
1076 seq_printf(m
, "max GPU freq: %d MHz\n",
1077 vlv_gpu_freq(dev_priv
, val
));
1079 val
= valleyview_rps_min_freq(dev_priv
);
1080 seq_printf(m
, "min GPU freq: %d MHz\n",
1081 vlv_gpu_freq(dev_priv
, val
));
1083 seq_printf(m
, "current GPU freq: %d MHz\n",
1084 vlv_gpu_freq(dev_priv
, (freq_sts
>> 8) & 0xff));
1085 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1087 seq_puts(m
, "no P-state info available\n");
1091 intel_runtime_pm_put(dev_priv
);
1095 static int i915_delayfreq_table(struct seq_file
*m
, void *unused
)
1097 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1098 struct drm_device
*dev
= node
->minor
->dev
;
1099 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1103 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1106 intel_runtime_pm_get(dev_priv
);
1108 for (i
= 0; i
< 16; i
++) {
1109 delayfreq
= I915_READ(PXVFREQ_BASE
+ i
* 4);
1110 seq_printf(m
, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i
, delayfreq
,
1111 (delayfreq
& PXVFREQ_PX_MASK
) >> PXVFREQ_PX_SHIFT
);
1114 intel_runtime_pm_put(dev_priv
);
1116 mutex_unlock(&dev
->struct_mutex
);
1121 static inline int MAP_TO_MV(int map
)
1123 return 1250 - (map
* 25);
1126 static int i915_inttoext_table(struct seq_file
*m
, void *unused
)
1128 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1129 struct drm_device
*dev
= node
->minor
->dev
;
1130 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1137 intel_runtime_pm_get(dev_priv
);
1139 for (i
= 1; i
<= 32; i
++) {
1140 inttoext
= I915_READ(INTTOEXT_BASE_ILK
+ i
* 4);
1141 seq_printf(m
, "INTTOEXT%02d: 0x%08x\n", i
, inttoext
);
1144 intel_runtime_pm_put(dev_priv
);
1145 mutex_unlock(&dev
->struct_mutex
);
1150 static int ironlake_drpc_info(struct seq_file
*m
)
1152 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1153 struct drm_device
*dev
= node
->minor
->dev
;
1154 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1155 u32 rgvmodectl
, rstdbyctl
;
1159 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1162 intel_runtime_pm_get(dev_priv
);
1164 rgvmodectl
= I915_READ(MEMMODECTL
);
1165 rstdbyctl
= I915_READ(RSTDBYCTL
);
1166 crstandvid
= I915_READ16(CRSTANDVID
);
1168 intel_runtime_pm_put(dev_priv
);
1169 mutex_unlock(&dev
->struct_mutex
);
1171 seq_printf(m
, "HD boost: %s\n", (rgvmodectl
& MEMMODE_BOOST_EN
) ?
1173 seq_printf(m
, "Boost freq: %d\n",
1174 (rgvmodectl
& MEMMODE_BOOST_FREQ_MASK
) >>
1175 MEMMODE_BOOST_FREQ_SHIFT
);
1176 seq_printf(m
, "HW control enabled: %s\n",
1177 rgvmodectl
& MEMMODE_HWIDLE_EN
? "yes" : "no");
1178 seq_printf(m
, "SW control enabled: %s\n",
1179 rgvmodectl
& MEMMODE_SWMODE_EN
? "yes" : "no");
1180 seq_printf(m
, "Gated voltage change: %s\n",
1181 rgvmodectl
& MEMMODE_RCLK_GATE
? "yes" : "no");
1182 seq_printf(m
, "Starting frequency: P%d\n",
1183 (rgvmodectl
& MEMMODE_FSTART_MASK
) >> MEMMODE_FSTART_SHIFT
);
1184 seq_printf(m
, "Max P-state: P%d\n",
1185 (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
);
1186 seq_printf(m
, "Min P-state: P%d\n", (rgvmodectl
& MEMMODE_FMIN_MASK
));
1187 seq_printf(m
, "RS1 VID: %d\n", (crstandvid
& 0x3f));
1188 seq_printf(m
, "RS2 VID: %d\n", ((crstandvid
>> 8) & 0x3f));
1189 seq_printf(m
, "Render standby enabled: %s\n",
1190 (rstdbyctl
& RCX_SW_EXIT
) ? "no" : "yes");
1191 seq_puts(m
, "Current RS state: ");
1192 switch (rstdbyctl
& RSX_STATUS_MASK
) {
1194 seq_puts(m
, "on\n");
1196 case RSX_STATUS_RC1
:
1197 seq_puts(m
, "RC1\n");
1199 case RSX_STATUS_RC1E
:
1200 seq_puts(m
, "RC1E\n");
1202 case RSX_STATUS_RS1
:
1203 seq_puts(m
, "RS1\n");
1205 case RSX_STATUS_RS2
:
1206 seq_puts(m
, "RS2 (RC6)\n");
1208 case RSX_STATUS_RS3
:
1209 seq_puts(m
, "RC3 (RC6+)\n");
1212 seq_puts(m
, "unknown\n");
1219 static int vlv_drpc_info(struct seq_file
*m
)
1222 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1223 struct drm_device
*dev
= node
->minor
->dev
;
1224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1225 u32 rpmodectl1
, rcctl1
;
1226 unsigned fw_rendercount
= 0, fw_mediacount
= 0;
1228 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1229 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1231 seq_printf(m
, "Video Turbo Mode: %s\n",
1232 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1233 seq_printf(m
, "Turbo enabled: %s\n",
1234 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1235 seq_printf(m
, "HW control enabled: %s\n",
1236 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1237 seq_printf(m
, "SW control enabled: %s\n",
1238 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1239 GEN6_RP_MEDIA_SW_MODE
));
1240 seq_printf(m
, "RC6 Enabled: %s\n",
1241 yesno(rcctl1
& (GEN7_RC_CTL_TO_MODE
|
1242 GEN6_RC_CTL_EI_MODE(1))));
1243 seq_printf(m
, "Render Power Well: %s\n",
1244 (I915_READ(VLV_GTLC_PW_STATUS
) &
1245 VLV_GTLC_PW_RENDER_STATUS_MASK
) ? "Up" : "Down");
1246 seq_printf(m
, "Media Power Well: %s\n",
1247 (I915_READ(VLV_GTLC_PW_STATUS
) &
1248 VLV_GTLC_PW_MEDIA_STATUS_MASK
) ? "Up" : "Down");
1250 spin_lock_irq(&dev_priv
->uncore
.lock
);
1251 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1252 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1253 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1255 seq_printf(m
, "Forcewake Render Count = %u\n", fw_rendercount
);
1256 seq_printf(m
, "Forcewake Media Count = %u\n", fw_mediacount
);
1263 static int gen6_drpc_info(struct seq_file
*m
)
1266 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1267 struct drm_device
*dev
= node
->minor
->dev
;
1268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1269 u32 rpmodectl1
, gt_core_status
, rcctl1
, rc6vids
= 0;
1270 unsigned forcewake_count
;
1273 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1276 intel_runtime_pm_get(dev_priv
);
1278 spin_lock_irq(&dev_priv
->uncore
.lock
);
1279 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1280 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1282 if (forcewake_count
) {
1283 seq_puts(m
, "RC information inaccurate because somebody "
1284 "holds a forcewake reference \n");
1286 /* NB: we cannot use forcewake, else we read the wrong values */
1287 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
1289 seq_printf(m
, "RC information accurate: %s\n", yesno(count
< 51));
1292 gt_core_status
= readl(dev_priv
->regs
+ GEN6_GT_CORE_STATUS
);
1293 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS
, gt_core_status
, 4, true);
1295 rpmodectl1
= I915_READ(GEN6_RP_CONTROL
);
1296 rcctl1
= I915_READ(GEN6_RC_CONTROL
);
1297 mutex_unlock(&dev
->struct_mutex
);
1298 mutex_lock(&dev_priv
->rps
.hw_lock
);
1299 sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
1300 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1302 intel_runtime_pm_put(dev_priv
);
1304 seq_printf(m
, "Video Turbo Mode: %s\n",
1305 yesno(rpmodectl1
& GEN6_RP_MEDIA_TURBO
));
1306 seq_printf(m
, "HW control enabled: %s\n",
1307 yesno(rpmodectl1
& GEN6_RP_ENABLE
));
1308 seq_printf(m
, "SW control enabled: %s\n",
1309 yesno((rpmodectl1
& GEN6_RP_MEDIA_MODE_MASK
) ==
1310 GEN6_RP_MEDIA_SW_MODE
));
1311 seq_printf(m
, "RC1e Enabled: %s\n",
1312 yesno(rcctl1
& GEN6_RC_CTL_RC1e_ENABLE
));
1313 seq_printf(m
, "RC6 Enabled: %s\n",
1314 yesno(rcctl1
& GEN6_RC_CTL_RC6_ENABLE
));
1315 seq_printf(m
, "Deep RC6 Enabled: %s\n",
1316 yesno(rcctl1
& GEN6_RC_CTL_RC6p_ENABLE
));
1317 seq_printf(m
, "Deepest RC6 Enabled: %s\n",
1318 yesno(rcctl1
& GEN6_RC_CTL_RC6pp_ENABLE
));
1319 seq_puts(m
, "Current RC state: ");
1320 switch (gt_core_status
& GEN6_RCn_MASK
) {
1322 if (gt_core_status
& GEN6_CORE_CPD_STATE_MASK
)
1323 seq_puts(m
, "Core Power Down\n");
1325 seq_puts(m
, "on\n");
1328 seq_puts(m
, "RC3\n");
1331 seq_puts(m
, "RC6\n");
1334 seq_puts(m
, "RC7\n");
1337 seq_puts(m
, "Unknown\n");
1341 seq_printf(m
, "Core Power Down: %s\n",
1342 yesno(gt_core_status
& GEN6_CORE_CPD_STATE_MASK
));
1344 /* Not exactly sure what this is */
1345 seq_printf(m
, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1346 I915_READ(GEN6_GT_GFX_RC6_LOCKED
));
1347 seq_printf(m
, "RC6 residency since boot: %u\n",
1348 I915_READ(GEN6_GT_GFX_RC6
));
1349 seq_printf(m
, "RC6+ residency since boot: %u\n",
1350 I915_READ(GEN6_GT_GFX_RC6p
));
1351 seq_printf(m
, "RC6++ residency since boot: %u\n",
1352 I915_READ(GEN6_GT_GFX_RC6pp
));
1354 seq_printf(m
, "RC6 voltage: %dmV\n",
1355 GEN6_DECODE_RC6_VID(((rc6vids
>> 0) & 0xff)));
1356 seq_printf(m
, "RC6+ voltage: %dmV\n",
1357 GEN6_DECODE_RC6_VID(((rc6vids
>> 8) & 0xff)));
1358 seq_printf(m
, "RC6++ voltage: %dmV\n",
1359 GEN6_DECODE_RC6_VID(((rc6vids
>> 16) & 0xff)));
1363 static int i915_drpc_info(struct seq_file
*m
, void *unused
)
1365 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1366 struct drm_device
*dev
= node
->minor
->dev
;
1368 if (IS_VALLEYVIEW(dev
))
1369 return vlv_drpc_info(m
);
1370 else if (IS_GEN6(dev
) || IS_GEN7(dev
))
1371 return gen6_drpc_info(m
);
1373 return ironlake_drpc_info(m
);
1376 static int i915_fbc_status(struct seq_file
*m
, void *unused
)
1378 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1379 struct drm_device
*dev
= node
->minor
->dev
;
1380 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1382 if (!HAS_FBC(dev
)) {
1383 seq_puts(m
, "FBC unsupported on this chipset\n");
1387 intel_runtime_pm_get(dev_priv
);
1389 if (intel_fbc_enabled(dev
)) {
1390 seq_puts(m
, "FBC enabled\n");
1392 seq_puts(m
, "FBC disabled: ");
1393 switch (dev_priv
->fbc
.no_fbc_reason
) {
1395 seq_puts(m
, "FBC actived, but currently disabled in hardware");
1397 case FBC_UNSUPPORTED
:
1398 seq_puts(m
, "unsupported by this chipset");
1401 seq_puts(m
, "no outputs");
1403 case FBC_STOLEN_TOO_SMALL
:
1404 seq_puts(m
, "not enough stolen memory");
1406 case FBC_UNSUPPORTED_MODE
:
1407 seq_puts(m
, "mode not supported");
1409 case FBC_MODE_TOO_LARGE
:
1410 seq_puts(m
, "mode too large");
1413 seq_puts(m
, "FBC unsupported on plane");
1416 seq_puts(m
, "scanout buffer not tiled");
1418 case FBC_MULTIPLE_PIPES
:
1419 seq_puts(m
, "multiple pipes are enabled");
1421 case FBC_MODULE_PARAM
:
1422 seq_puts(m
, "disabled per module param (default off)");
1424 case FBC_CHIP_DEFAULT
:
1425 seq_puts(m
, "disabled per chip default");
1428 seq_puts(m
, "unknown reason");
1433 intel_runtime_pm_put(dev_priv
);
1438 static int i915_ips_status(struct seq_file
*m
, void *unused
)
1440 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1441 struct drm_device
*dev
= node
->minor
->dev
;
1442 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1444 if (!HAS_IPS(dev
)) {
1445 seq_puts(m
, "not supported\n");
1449 intel_runtime_pm_get(dev_priv
);
1451 if (IS_BROADWELL(dev
) || I915_READ(IPS_CTL
) & IPS_ENABLE
)
1452 seq_puts(m
, "enabled\n");
1454 seq_puts(m
, "disabled\n");
1456 intel_runtime_pm_put(dev_priv
);
1461 static int i915_sr_status(struct seq_file
*m
, void *unused
)
1463 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1464 struct drm_device
*dev
= node
->minor
->dev
;
1465 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1466 bool sr_enabled
= false;
1468 intel_runtime_pm_get(dev_priv
);
1470 if (HAS_PCH_SPLIT(dev
))
1471 sr_enabled
= I915_READ(WM1_LP_ILK
) & WM1_LP_SR_EN
;
1472 else if (IS_CRESTLINE(dev
) || IS_I945G(dev
) || IS_I945GM(dev
))
1473 sr_enabled
= I915_READ(FW_BLC_SELF
) & FW_BLC_SELF_EN
;
1474 else if (IS_I915GM(dev
))
1475 sr_enabled
= I915_READ(INSTPM
) & INSTPM_SELF_EN
;
1476 else if (IS_PINEVIEW(dev
))
1477 sr_enabled
= I915_READ(DSPFW3
) & PINEVIEW_SELF_REFRESH_EN
;
1479 intel_runtime_pm_put(dev_priv
);
1481 seq_printf(m
, "self-refresh: %s\n",
1482 sr_enabled
? "enabled" : "disabled");
1487 static int i915_emon_status(struct seq_file
*m
, void *unused
)
1489 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1490 struct drm_device
*dev
= node
->minor
->dev
;
1491 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1492 unsigned long temp
, chipset
, gfx
;
1498 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1502 temp
= i915_mch_val(dev_priv
);
1503 chipset
= i915_chipset_val(dev_priv
);
1504 gfx
= i915_gfx_val(dev_priv
);
1505 mutex_unlock(&dev
->struct_mutex
);
1507 seq_printf(m
, "GMCH temp: %ld\n", temp
);
1508 seq_printf(m
, "Chipset power: %ld\n", chipset
);
1509 seq_printf(m
, "GFX power: %ld\n", gfx
);
1510 seq_printf(m
, "Total power: %ld\n", chipset
+ gfx
);
1515 static int i915_ring_freq_table(struct seq_file
*m
, void *unused
)
1517 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1518 struct drm_device
*dev
= node
->minor
->dev
;
1519 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1521 int gpu_freq
, ia_freq
;
1523 if (!(IS_GEN6(dev
) || IS_GEN7(dev
))) {
1524 seq_puts(m
, "unsupported on this chipset\n");
1528 intel_runtime_pm_get(dev_priv
);
1530 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
1532 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
1536 seq_puts(m
, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1538 for (gpu_freq
= dev_priv
->rps
.min_freq_softlimit
;
1539 gpu_freq
<= dev_priv
->rps
.max_freq_softlimit
;
1542 sandybridge_pcode_read(dev_priv
,
1543 GEN6_PCODE_READ_MIN_FREQ_TABLE
,
1545 seq_printf(m
, "%d\t\t%d\t\t\t\t%d\n",
1546 gpu_freq
* GT_FREQUENCY_MULTIPLIER
,
1547 ((ia_freq
>> 0) & 0xff) * 100,
1548 ((ia_freq
>> 8) & 0xff) * 100);
1551 mutex_unlock(&dev_priv
->rps
.hw_lock
);
1554 intel_runtime_pm_put(dev_priv
);
1558 static int i915_gfxec(struct seq_file
*m
, void *unused
)
1560 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1561 struct drm_device
*dev
= node
->minor
->dev
;
1562 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1565 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1568 intel_runtime_pm_get(dev_priv
);
1570 seq_printf(m
, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1571 intel_runtime_pm_put(dev_priv
);
1573 mutex_unlock(&dev
->struct_mutex
);
1578 static int i915_opregion(struct seq_file
*m
, void *unused
)
1580 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1581 struct drm_device
*dev
= node
->minor
->dev
;
1582 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1583 struct intel_opregion
*opregion
= &dev_priv
->opregion
;
1584 void *data
= kmalloc(OPREGION_SIZE
, GFP_KERNEL
);
1590 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1594 if (opregion
->header
) {
1595 memcpy_fromio(data
, opregion
->header
, OPREGION_SIZE
);
1596 seq_write(m
, data
, OPREGION_SIZE
);
1599 mutex_unlock(&dev
->struct_mutex
);
1606 static int i915_gem_framebuffer_info(struct seq_file
*m
, void *data
)
1608 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1609 struct drm_device
*dev
= node
->minor
->dev
;
1610 struct intel_fbdev
*ifbdev
= NULL
;
1611 struct intel_framebuffer
*fb
;
1613 #ifdef CONFIG_DRM_I915_FBDEV
1614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1615 int ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1619 ifbdev
= dev_priv
->fbdev
;
1620 fb
= to_intel_framebuffer(ifbdev
->helper
.fb
);
1622 seq_printf(m
, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1626 fb
->base
.bits_per_pixel
,
1627 atomic_read(&fb
->base
.refcount
.refcount
));
1628 describe_obj(m
, fb
->obj
);
1630 mutex_unlock(&dev
->mode_config
.mutex
);
1633 mutex_lock(&dev
->mode_config
.fb_lock
);
1634 list_for_each_entry(fb
, &dev
->mode_config
.fb_list
, base
.head
) {
1635 if (ifbdev
&& &fb
->base
== ifbdev
->helper
.fb
)
1638 seq_printf(m
, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1642 fb
->base
.bits_per_pixel
,
1643 atomic_read(&fb
->base
.refcount
.refcount
));
1644 describe_obj(m
, fb
->obj
);
1647 mutex_unlock(&dev
->mode_config
.fb_lock
);
1652 static int i915_context_status(struct seq_file
*m
, void *unused
)
1654 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1655 struct drm_device
*dev
= node
->minor
->dev
;
1656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1657 struct intel_ring_buffer
*ring
;
1658 struct i915_hw_context
*ctx
;
1661 ret
= mutex_lock_interruptible(&dev
->mode_config
.mutex
);
1665 if (dev_priv
->ips
.pwrctx
) {
1666 seq_puts(m
, "power context ");
1667 describe_obj(m
, dev_priv
->ips
.pwrctx
);
1671 if (dev_priv
->ips
.renderctx
) {
1672 seq_puts(m
, "render context ");
1673 describe_obj(m
, dev_priv
->ips
.renderctx
);
1677 list_for_each_entry(ctx
, &dev_priv
->context_list
, link
) {
1678 seq_puts(m
, "HW context ");
1679 describe_ctx(m
, ctx
);
1680 for_each_ring(ring
, dev_priv
, i
)
1681 if (ring
->default_context
== ctx
)
1682 seq_printf(m
, "(default context %s) ", ring
->name
);
1684 describe_obj(m
, ctx
->obj
);
1688 mutex_unlock(&dev
->mode_config
.mutex
);
1693 static int i915_gen6_forcewake_count_info(struct seq_file
*m
, void *data
)
1695 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1696 struct drm_device
*dev
= node
->minor
->dev
;
1697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1698 unsigned forcewake_count
= 0, fw_rendercount
= 0, fw_mediacount
= 0;
1700 spin_lock_irq(&dev_priv
->uncore
.lock
);
1701 if (IS_VALLEYVIEW(dev
)) {
1702 fw_rendercount
= dev_priv
->uncore
.fw_rendercount
;
1703 fw_mediacount
= dev_priv
->uncore
.fw_mediacount
;
1705 forcewake_count
= dev_priv
->uncore
.forcewake_count
;
1706 spin_unlock_irq(&dev_priv
->uncore
.lock
);
1708 if (IS_VALLEYVIEW(dev
)) {
1709 seq_printf(m
, "fw_rendercount = %u\n", fw_rendercount
);
1710 seq_printf(m
, "fw_mediacount = %u\n", fw_mediacount
);
1712 seq_printf(m
, "forcewake count = %u\n", forcewake_count
);
1717 static const char *swizzle_string(unsigned swizzle
)
1720 case I915_BIT_6_SWIZZLE_NONE
:
1722 case I915_BIT_6_SWIZZLE_9
:
1724 case I915_BIT_6_SWIZZLE_9_10
:
1725 return "bit9/bit10";
1726 case I915_BIT_6_SWIZZLE_9_11
:
1727 return "bit9/bit11";
1728 case I915_BIT_6_SWIZZLE_9_10_11
:
1729 return "bit9/bit10/bit11";
1730 case I915_BIT_6_SWIZZLE_9_17
:
1731 return "bit9/bit17";
1732 case I915_BIT_6_SWIZZLE_9_10_17
:
1733 return "bit9/bit10/bit17";
1734 case I915_BIT_6_SWIZZLE_UNKNOWN
:
1741 static int i915_swizzle_info(struct seq_file
*m
, void *data
)
1743 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1744 struct drm_device
*dev
= node
->minor
->dev
;
1745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1748 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1751 intel_runtime_pm_get(dev_priv
);
1753 seq_printf(m
, "bit6 swizzle for X-tiling = %s\n",
1754 swizzle_string(dev_priv
->mm
.bit_6_swizzle_x
));
1755 seq_printf(m
, "bit6 swizzle for Y-tiling = %s\n",
1756 swizzle_string(dev_priv
->mm
.bit_6_swizzle_y
));
1758 if (IS_GEN3(dev
) || IS_GEN4(dev
)) {
1759 seq_printf(m
, "DDC = 0x%08x\n",
1761 seq_printf(m
, "C0DRB3 = 0x%04x\n",
1762 I915_READ16(C0DRB3
));
1763 seq_printf(m
, "C1DRB3 = 0x%04x\n",
1764 I915_READ16(C1DRB3
));
1765 } else if (INTEL_INFO(dev
)->gen
>= 6) {
1766 seq_printf(m
, "MAD_DIMM_C0 = 0x%08x\n",
1767 I915_READ(MAD_DIMM_C0
));
1768 seq_printf(m
, "MAD_DIMM_C1 = 0x%08x\n",
1769 I915_READ(MAD_DIMM_C1
));
1770 seq_printf(m
, "MAD_DIMM_C2 = 0x%08x\n",
1771 I915_READ(MAD_DIMM_C2
));
1772 seq_printf(m
, "TILECTL = 0x%08x\n",
1773 I915_READ(TILECTL
));
1775 seq_printf(m
, "GAMTARBMODE = 0x%08x\n",
1776 I915_READ(GAMTARBMODE
));
1778 seq_printf(m
, "ARB_MODE = 0x%08x\n",
1779 I915_READ(ARB_MODE
));
1780 seq_printf(m
, "DISP_ARB_CTL = 0x%08x\n",
1781 I915_READ(DISP_ARB_CTL
));
1783 intel_runtime_pm_put(dev_priv
);
1784 mutex_unlock(&dev
->struct_mutex
);
1789 static int per_file_ctx(int id
, void *ptr
, void *data
)
1791 struct i915_hw_context
*ctx
= ptr
;
1792 struct seq_file
*m
= data
;
1793 struct i915_hw_ppgtt
*ppgtt
= ctx_to_ppgtt(ctx
);
1795 ppgtt
->debug_dump(ppgtt
, m
);
1800 static void gen8_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
1802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1803 struct intel_ring_buffer
*ring
;
1804 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1810 seq_printf(m
, "Page directories: %d\n", ppgtt
->num_pd_pages
);
1811 seq_printf(m
, "Page tables: %d\n", ppgtt
->num_pd_entries
);
1812 for_each_ring(ring
, dev_priv
, unused
) {
1813 seq_printf(m
, "%s\n", ring
->name
);
1814 for (i
= 0; i
< 4; i
++) {
1815 u32 offset
= 0x270 + i
* 8;
1816 u64 pdp
= I915_READ(ring
->mmio_base
+ offset
+ 4);
1818 pdp
|= I915_READ(ring
->mmio_base
+ offset
);
1819 for (i
= 0; i
< 4; i
++)
1820 seq_printf(m
, "\tPDP%d 0x%016llx\n", i
, pdp
);
1825 static void gen6_ppgtt_info(struct seq_file
*m
, struct drm_device
*dev
)
1827 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1828 struct intel_ring_buffer
*ring
;
1829 struct drm_file
*file
;
1832 if (INTEL_INFO(dev
)->gen
== 6)
1833 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE
));
1835 for_each_ring(ring
, dev_priv
, i
) {
1836 seq_printf(m
, "%s\n", ring
->name
);
1837 if (INTEL_INFO(dev
)->gen
== 7)
1838 seq_printf(m
, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring
)));
1839 seq_printf(m
, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring
)));
1840 seq_printf(m
, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring
)));
1841 seq_printf(m
, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring
)));
1843 if (dev_priv
->mm
.aliasing_ppgtt
) {
1844 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
1846 seq_puts(m
, "aliasing PPGTT:\n");
1847 seq_printf(m
, "pd gtt offset: 0x%08x\n", ppgtt
->pd_offset
);
1849 ppgtt
->debug_dump(ppgtt
, m
);
1853 list_for_each_entry_reverse(file
, &dev
->filelist
, lhead
) {
1854 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1855 struct i915_hw_ppgtt
*pvt_ppgtt
;
1857 pvt_ppgtt
= ctx_to_ppgtt(file_priv
->private_default_ctx
);
1858 seq_printf(m
, "proc: %s\n",
1859 get_pid_task(file
->pid
, PIDTYPE_PID
)->comm
);
1860 seq_puts(m
, " default context:\n");
1861 idr_for_each(&file_priv
->context_idr
, per_file_ctx
, m
);
1863 seq_printf(m
, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK
));
1866 static int i915_ppgtt_info(struct seq_file
*m
, void *data
)
1868 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1869 struct drm_device
*dev
= node
->minor
->dev
;
1870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1872 int ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
1875 intel_runtime_pm_get(dev_priv
);
1877 if (INTEL_INFO(dev
)->gen
>= 8)
1878 gen8_ppgtt_info(m
, dev
);
1879 else if (INTEL_INFO(dev
)->gen
>= 6)
1880 gen6_ppgtt_info(m
, dev
);
1882 intel_runtime_pm_put(dev_priv
);
1883 mutex_unlock(&dev
->struct_mutex
);
1888 static int i915_dpio_info(struct seq_file
*m
, void *data
)
1890 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1891 struct drm_device
*dev
= node
->minor
->dev
;
1892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1896 if (!IS_VALLEYVIEW(dev
)) {
1897 seq_puts(m
, "unsupported\n");
1901 ret
= mutex_lock_interruptible(&dev_priv
->dpio_lock
);
1905 seq_printf(m
, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL
));
1907 seq_printf(m
, "DPIO PLL DW3 CH0 : 0x%08x\n",
1908 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW3(0)));
1909 seq_printf(m
, "DPIO PLL DW3 CH1: 0x%08x\n",
1910 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW3(1)));
1912 seq_printf(m
, "DPIO PLL DW5 CH0: 0x%08x\n",
1913 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW5(0)));
1914 seq_printf(m
, "DPIO PLL DW5 CH1: 0x%08x\n",
1915 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW5(1)));
1917 seq_printf(m
, "DPIO PLL DW7 CH0: 0x%08x\n",
1918 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW7(0)));
1919 seq_printf(m
, "DPIO PLL DW7 CH1: 0x%08x\n",
1920 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW7(1)));
1922 seq_printf(m
, "DPIO PLL DW10 CH0: 0x%08x\n",
1923 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW10(0)));
1924 seq_printf(m
, "DPIO PLL DW10 CH1: 0x%08x\n",
1925 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_PLL_DW10(1)));
1927 seq_printf(m
, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1928 vlv_dpio_read(dev_priv
, PIPE_A
, VLV_CMN_DW0
));
1930 mutex_unlock(&dev_priv
->dpio_lock
);
1935 static int i915_llc(struct seq_file
*m
, void *data
)
1937 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1938 struct drm_device
*dev
= node
->minor
->dev
;
1939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1941 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1942 seq_printf(m
, "LLC: %s\n", yesno(HAS_LLC(dev
)));
1943 seq_printf(m
, "eLLC: %zuMB\n", dev_priv
->ellc_size
);
1948 static int i915_edp_psr_status(struct seq_file
*m
, void *data
)
1950 struct drm_info_node
*node
= m
->private;
1951 struct drm_device
*dev
= node
->minor
->dev
;
1952 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1954 bool enabled
= false;
1956 intel_runtime_pm_get(dev_priv
);
1958 seq_printf(m
, "Sink_Support: %s\n", yesno(dev_priv
->psr
.sink_support
));
1959 seq_printf(m
, "Source_OK: %s\n", yesno(dev_priv
->psr
.source_ok
));
1961 enabled
= HAS_PSR(dev
) &&
1962 I915_READ(EDP_PSR_CTL(dev
)) & EDP_PSR_ENABLE
;
1963 seq_printf(m
, "Enabled: %s\n", yesno(enabled
));
1966 psrperf
= I915_READ(EDP_PSR_PERF_CNT(dev
)) &
1967 EDP_PSR_PERF_CNT_MASK
;
1968 seq_printf(m
, "Performance_Counter: %u\n", psrperf
);
1970 intel_runtime_pm_put(dev_priv
);
1974 static int i915_sink_crc(struct seq_file
*m
, void *data
)
1976 struct drm_info_node
*node
= m
->private;
1977 struct drm_device
*dev
= node
->minor
->dev
;
1978 struct intel_encoder
*encoder
;
1979 struct intel_connector
*connector
;
1980 struct intel_dp
*intel_dp
= NULL
;
1984 drm_modeset_lock_all(dev
);
1985 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
1988 if (connector
->base
.dpms
!= DRM_MODE_DPMS_ON
)
1991 if (!connector
->base
.encoder
)
1994 encoder
= to_intel_encoder(connector
->base
.encoder
);
1995 if (encoder
->type
!= INTEL_OUTPUT_EDP
)
1998 intel_dp
= enc_to_intel_dp(&encoder
->base
);
2000 ret
= intel_dp_sink_crc(intel_dp
, crc
);
2004 seq_printf(m
, "%02x%02x%02x%02x%02x%02x\n",
2005 crc
[0], crc
[1], crc
[2],
2006 crc
[3], crc
[4], crc
[5]);
2011 drm_modeset_unlock_all(dev
);
2015 static int i915_energy_uJ(struct seq_file
*m
, void *data
)
2017 struct drm_info_node
*node
= m
->private;
2018 struct drm_device
*dev
= node
->minor
->dev
;
2019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2023 if (INTEL_INFO(dev
)->gen
< 6)
2026 intel_runtime_pm_get(dev_priv
);
2028 rdmsrl(MSR_RAPL_POWER_UNIT
, power
);
2029 power
= (power
& 0x1f00) >> 8;
2030 units
= 1000000 / (1 << power
); /* convert to uJ */
2031 power
= I915_READ(MCH_SECP_NRG_STTS
);
2034 intel_runtime_pm_put(dev_priv
);
2036 seq_printf(m
, "%llu", (long long unsigned)power
);
2041 static int i915_pc8_status(struct seq_file
*m
, void *unused
)
2043 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2044 struct drm_device
*dev
= node
->minor
->dev
;
2045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2047 if (!IS_HASWELL(dev
)) {
2048 seq_puts(m
, "not supported\n");
2052 seq_printf(m
, "GPU idle: %s\n", yesno(!dev_priv
->mm
.busy
));
2053 seq_printf(m
, "IRQs disabled: %s\n",
2054 yesno(dev_priv
->pm
.irqs_disabled
));
2059 static const char *power_domain_str(enum intel_display_power_domain domain
)
2062 case POWER_DOMAIN_PIPE_A
:
2064 case POWER_DOMAIN_PIPE_B
:
2066 case POWER_DOMAIN_PIPE_C
:
2068 case POWER_DOMAIN_PIPE_A_PANEL_FITTER
:
2069 return "PIPE_A_PANEL_FITTER";
2070 case POWER_DOMAIN_PIPE_B_PANEL_FITTER
:
2071 return "PIPE_B_PANEL_FITTER";
2072 case POWER_DOMAIN_PIPE_C_PANEL_FITTER
:
2073 return "PIPE_C_PANEL_FITTER";
2074 case POWER_DOMAIN_TRANSCODER_A
:
2075 return "TRANSCODER_A";
2076 case POWER_DOMAIN_TRANSCODER_B
:
2077 return "TRANSCODER_B";
2078 case POWER_DOMAIN_TRANSCODER_C
:
2079 return "TRANSCODER_C";
2080 case POWER_DOMAIN_TRANSCODER_EDP
:
2081 return "TRANSCODER_EDP";
2082 case POWER_DOMAIN_PORT_DDI_A_2_LANES
:
2083 return "PORT_DDI_A_2_LANES";
2084 case POWER_DOMAIN_PORT_DDI_A_4_LANES
:
2085 return "PORT_DDI_A_4_LANES";
2086 case POWER_DOMAIN_PORT_DDI_B_2_LANES
:
2087 return "PORT_DDI_B_2_LANES";
2088 case POWER_DOMAIN_PORT_DDI_B_4_LANES
:
2089 return "PORT_DDI_B_4_LANES";
2090 case POWER_DOMAIN_PORT_DDI_C_2_LANES
:
2091 return "PORT_DDI_C_2_LANES";
2092 case POWER_DOMAIN_PORT_DDI_C_4_LANES
:
2093 return "PORT_DDI_C_4_LANES";
2094 case POWER_DOMAIN_PORT_DDI_D_2_LANES
:
2095 return "PORT_DDI_D_2_LANES";
2096 case POWER_DOMAIN_PORT_DDI_D_4_LANES
:
2097 return "PORT_DDI_D_4_LANES";
2098 case POWER_DOMAIN_PORT_DSI
:
2100 case POWER_DOMAIN_PORT_CRT
:
2102 case POWER_DOMAIN_PORT_OTHER
:
2103 return "PORT_OTHER";
2104 case POWER_DOMAIN_VGA
:
2106 case POWER_DOMAIN_AUDIO
:
2108 case POWER_DOMAIN_INIT
:
2116 static int i915_power_domain_info(struct seq_file
*m
, void *unused
)
2118 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2119 struct drm_device
*dev
= node
->minor
->dev
;
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2121 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
2124 mutex_lock(&power_domains
->lock
);
2126 seq_printf(m
, "%-25s %s\n", "Power well/domain", "Use count");
2127 for (i
= 0; i
< power_domains
->power_well_count
; i
++) {
2128 struct i915_power_well
*power_well
;
2129 enum intel_display_power_domain power_domain
;
2131 power_well
= &power_domains
->power_wells
[i
];
2132 seq_printf(m
, "%-25s %d\n", power_well
->name
,
2135 for (power_domain
= 0; power_domain
< POWER_DOMAIN_NUM
;
2137 if (!(BIT(power_domain
) & power_well
->domains
))
2140 seq_printf(m
, " %-23s %d\n",
2141 power_domain_str(power_domain
),
2142 power_domains
->domain_use_count
[power_domain
]);
2146 mutex_unlock(&power_domains
->lock
);
2151 static void intel_seq_print_mode(struct seq_file
*m
, int tabs
,
2152 struct drm_display_mode
*mode
)
2156 for (i
= 0; i
< tabs
; i
++)
2159 seq_printf(m
, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2160 mode
->base
.id
, mode
->name
,
2161 mode
->vrefresh
, mode
->clock
,
2162 mode
->hdisplay
, mode
->hsync_start
,
2163 mode
->hsync_end
, mode
->htotal
,
2164 mode
->vdisplay
, mode
->vsync_start
,
2165 mode
->vsync_end
, mode
->vtotal
,
2166 mode
->type
, mode
->flags
);
2169 static void intel_encoder_info(struct seq_file
*m
,
2170 struct intel_crtc
*intel_crtc
,
2171 struct intel_encoder
*intel_encoder
)
2173 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2174 struct drm_device
*dev
= node
->minor
->dev
;
2175 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2176 struct intel_connector
*intel_connector
;
2177 struct drm_encoder
*encoder
;
2179 encoder
= &intel_encoder
->base
;
2180 seq_printf(m
, "\tencoder %d: type: %s, connectors:\n",
2181 encoder
->base
.id
, drm_get_encoder_name(encoder
));
2182 for_each_connector_on_encoder(dev
, encoder
, intel_connector
) {
2183 struct drm_connector
*connector
= &intel_connector
->base
;
2184 seq_printf(m
, "\t\tconnector %d: type: %s, status: %s",
2186 drm_get_connector_name(connector
),
2187 drm_get_connector_status_name(connector
->status
));
2188 if (connector
->status
== connector_status_connected
) {
2189 struct drm_display_mode
*mode
= &crtc
->mode
;
2190 seq_printf(m
, ", mode:\n");
2191 intel_seq_print_mode(m
, 2, mode
);
2198 static void intel_crtc_info(struct seq_file
*m
, struct intel_crtc
*intel_crtc
)
2200 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2201 struct drm_device
*dev
= node
->minor
->dev
;
2202 struct drm_crtc
*crtc
= &intel_crtc
->base
;
2203 struct intel_encoder
*intel_encoder
;
2205 seq_printf(m
, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2206 crtc
->fb
->base
.id
, crtc
->x
, crtc
->y
,
2207 crtc
->fb
->width
, crtc
->fb
->height
);
2208 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
2209 intel_encoder_info(m
, intel_crtc
, intel_encoder
);
2212 static void intel_panel_info(struct seq_file
*m
, struct intel_panel
*panel
)
2214 struct drm_display_mode
*mode
= panel
->fixed_mode
;
2216 seq_printf(m
, "\tfixed mode:\n");
2217 intel_seq_print_mode(m
, 2, mode
);
2220 static void intel_dp_info(struct seq_file
*m
,
2221 struct intel_connector
*intel_connector
)
2223 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2224 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
2226 seq_printf(m
, "\tDPCD rev: %x\n", intel_dp
->dpcd
[DP_DPCD_REV
]);
2227 seq_printf(m
, "\taudio support: %s\n", intel_dp
->has_audio
? "yes" :
2229 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2230 intel_panel_info(m
, &intel_connector
->panel
);
2233 static void intel_hdmi_info(struct seq_file
*m
,
2234 struct intel_connector
*intel_connector
)
2236 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2237 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(&intel_encoder
->base
);
2239 seq_printf(m
, "\taudio support: %s\n", intel_hdmi
->has_audio
? "yes" :
2243 static void intel_lvds_info(struct seq_file
*m
,
2244 struct intel_connector
*intel_connector
)
2246 intel_panel_info(m
, &intel_connector
->panel
);
2249 static void intel_connector_info(struct seq_file
*m
,
2250 struct drm_connector
*connector
)
2252 struct intel_connector
*intel_connector
= to_intel_connector(connector
);
2253 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
2254 struct drm_display_mode
*mode
;
2256 seq_printf(m
, "connector %d: type %s, status: %s\n",
2257 connector
->base
.id
, drm_get_connector_name(connector
),
2258 drm_get_connector_status_name(connector
->status
));
2259 if (connector
->status
== connector_status_connected
) {
2260 seq_printf(m
, "\tname: %s\n", connector
->display_info
.name
);
2261 seq_printf(m
, "\tphysical dimensions: %dx%dmm\n",
2262 connector
->display_info
.width_mm
,
2263 connector
->display_info
.height_mm
);
2264 seq_printf(m
, "\tsubpixel order: %s\n",
2265 drm_get_subpixel_order_name(connector
->display_info
.subpixel_order
));
2266 seq_printf(m
, "\tCEA rev: %d\n",
2267 connector
->display_info
.cea_rev
);
2269 if (intel_encoder
->type
== INTEL_OUTPUT_DISPLAYPORT
||
2270 intel_encoder
->type
== INTEL_OUTPUT_EDP
)
2271 intel_dp_info(m
, intel_connector
);
2272 else if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
)
2273 intel_hdmi_info(m
, intel_connector
);
2274 else if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
)
2275 intel_lvds_info(m
, intel_connector
);
2277 seq_printf(m
, "\tmodes:\n");
2278 list_for_each_entry(mode
, &connector
->modes
, head
)
2279 intel_seq_print_mode(m
, 2, mode
);
2282 static bool cursor_active(struct drm_device
*dev
, int pipe
)
2284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2287 if (IS_845G(dev
) || IS_I865G(dev
))
2288 state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
2289 else if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
))
2290 state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
2292 state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
2297 static bool cursor_position(struct drm_device
*dev
, int pipe
, int *x
, int *y
)
2299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2302 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2303 pos
= I915_READ(CURPOS_IVB(pipe
));
2305 pos
= I915_READ(CURPOS(pipe
));
2307 *x
= (pos
>> CURSOR_X_SHIFT
) & CURSOR_POS_MASK
;
2308 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
))
2311 *y
= (pos
>> CURSOR_Y_SHIFT
) & CURSOR_POS_MASK
;
2312 if (pos
& (CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
))
2315 return cursor_active(dev
, pipe
);
2318 static int i915_display_info(struct seq_file
*m
, void *unused
)
2320 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
2321 struct drm_device
*dev
= node
->minor
->dev
;
2322 struct intel_crtc
*crtc
;
2323 struct drm_connector
*connector
;
2325 drm_modeset_lock_all(dev
);
2326 seq_printf(m
, "CRTC info\n");
2327 seq_printf(m
, "---------\n");
2328 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2332 seq_printf(m
, "CRTC %d: pipe: %c, active: %s\n",
2333 crtc
->base
.base
.id
, pipe_name(crtc
->pipe
),
2334 yesno(crtc
->active
));
2336 intel_crtc_info(m
, crtc
);
2338 active
= cursor_position(dev
, crtc
->pipe
, &x
, &y
);
2339 seq_printf(m
, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",
2340 yesno(crtc
->cursor_visible
),
2341 x
, y
, crtc
->cursor_addr
,
2345 seq_printf(m
, "\n");
2346 seq_printf(m
, "Connector info\n");
2347 seq_printf(m
, "--------------\n");
2348 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
2349 intel_connector_info(m
, connector
);
2351 drm_modeset_unlock_all(dev
);
2356 struct pipe_crc_info
{
2358 struct drm_device
*dev
;
2362 static int i915_pipe_crc_open(struct inode
*inode
, struct file
*filep
)
2364 struct pipe_crc_info
*info
= inode
->i_private
;
2365 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2366 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2368 if (info
->pipe
>= INTEL_INFO(info
->dev
)->num_pipes
)
2371 spin_lock_irq(&pipe_crc
->lock
);
2373 if (pipe_crc
->opened
) {
2374 spin_unlock_irq(&pipe_crc
->lock
);
2375 return -EBUSY
; /* already open */
2378 pipe_crc
->opened
= true;
2379 filep
->private_data
= inode
->i_private
;
2381 spin_unlock_irq(&pipe_crc
->lock
);
2386 static int i915_pipe_crc_release(struct inode
*inode
, struct file
*filep
)
2388 struct pipe_crc_info
*info
= inode
->i_private
;
2389 struct drm_i915_private
*dev_priv
= info
->dev
->dev_private
;
2390 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2392 spin_lock_irq(&pipe_crc
->lock
);
2393 pipe_crc
->opened
= false;
2394 spin_unlock_irq(&pipe_crc
->lock
);
2399 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2400 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2401 /* account for \'0' */
2402 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2404 static int pipe_crc_data_count(struct intel_pipe_crc
*pipe_crc
)
2406 assert_spin_locked(&pipe_crc
->lock
);
2407 return CIRC_CNT(pipe_crc
->head
, pipe_crc
->tail
,
2408 INTEL_PIPE_CRC_ENTRIES_NR
);
2412 i915_pipe_crc_read(struct file
*filep
, char __user
*user_buf
, size_t count
,
2415 struct pipe_crc_info
*info
= filep
->private_data
;
2416 struct drm_device
*dev
= info
->dev
;
2417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2418 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[info
->pipe
];
2419 char buf
[PIPE_CRC_BUFFER_LEN
];
2420 int head
, tail
, n_entries
, n
;
2424 * Don't allow user space to provide buffers not big enough to hold
2427 if (count
< PIPE_CRC_LINE_LEN
)
2430 if (pipe_crc
->source
== INTEL_PIPE_CRC_SOURCE_NONE
)
2433 /* nothing to read */
2434 spin_lock_irq(&pipe_crc
->lock
);
2435 while (pipe_crc_data_count(pipe_crc
) == 0) {
2438 if (filep
->f_flags
& O_NONBLOCK
) {
2439 spin_unlock_irq(&pipe_crc
->lock
);
2443 ret
= wait_event_interruptible_lock_irq(pipe_crc
->wq
,
2444 pipe_crc_data_count(pipe_crc
), pipe_crc
->lock
);
2446 spin_unlock_irq(&pipe_crc
->lock
);
2451 /* We now have one or more entries to read */
2452 head
= pipe_crc
->head
;
2453 tail
= pipe_crc
->tail
;
2454 n_entries
= min((size_t)CIRC_CNT(head
, tail
, INTEL_PIPE_CRC_ENTRIES_NR
),
2455 count
/ PIPE_CRC_LINE_LEN
);
2456 spin_unlock_irq(&pipe_crc
->lock
);
2461 struct intel_pipe_crc_entry
*entry
= &pipe_crc
->entries
[tail
];
2464 bytes_read
+= snprintf(buf
, PIPE_CRC_BUFFER_LEN
,
2465 "%8u %8x %8x %8x %8x %8x\n",
2466 entry
->frame
, entry
->crc
[0],
2467 entry
->crc
[1], entry
->crc
[2],
2468 entry
->crc
[3], entry
->crc
[4]);
2470 ret
= copy_to_user(user_buf
+ n
* PIPE_CRC_LINE_LEN
,
2471 buf
, PIPE_CRC_LINE_LEN
);
2472 if (ret
== PIPE_CRC_LINE_LEN
)
2475 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR
);
2476 tail
= (tail
+ 1) & (INTEL_PIPE_CRC_ENTRIES_NR
- 1);
2478 } while (--n_entries
);
2480 spin_lock_irq(&pipe_crc
->lock
);
2481 pipe_crc
->tail
= tail
;
2482 spin_unlock_irq(&pipe_crc
->lock
);
2487 static const struct file_operations i915_pipe_crc_fops
= {
2488 .owner
= THIS_MODULE
,
2489 .open
= i915_pipe_crc_open
,
2490 .read
= i915_pipe_crc_read
,
2491 .release
= i915_pipe_crc_release
,
2494 static struct pipe_crc_info i915_pipe_crc_data
[I915_MAX_PIPES
] = {
2496 .name
= "i915_pipe_A_crc",
2500 .name
= "i915_pipe_B_crc",
2504 .name
= "i915_pipe_C_crc",
2509 static int i915_pipe_crc_create(struct dentry
*root
, struct drm_minor
*minor
,
2512 struct drm_device
*dev
= minor
->dev
;
2514 struct pipe_crc_info
*info
= &i915_pipe_crc_data
[pipe
];
2517 ent
= debugfs_create_file(info
->name
, S_IRUGO
, root
, info
,
2518 &i915_pipe_crc_fops
);
2522 return drm_add_fake_info_node(minor
, ent
, info
);
2525 static const char * const pipe_crc_sources
[] = {
2538 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source
)
2540 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources
) != INTEL_PIPE_CRC_SOURCE_MAX
);
2541 return pipe_crc_sources
[source
];
2544 static int display_crc_ctl_show(struct seq_file
*m
, void *data
)
2546 struct drm_device
*dev
= m
->private;
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2550 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
2551 seq_printf(m
, "%c %s\n", pipe_name(i
),
2552 pipe_crc_source_name(dev_priv
->pipe_crc
[i
].source
));
2557 static int display_crc_ctl_open(struct inode
*inode
, struct file
*file
)
2559 struct drm_device
*dev
= inode
->i_private
;
2561 return single_open(file
, display_crc_ctl_show
, dev
);
2564 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2567 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2568 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2571 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2572 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_INCLUDE_BORDER_I8XX
;
2574 case INTEL_PIPE_CRC_SOURCE_NONE
:
2584 static int i9xx_pipe_crc_auto_source(struct drm_device
*dev
, enum pipe pipe
,
2585 enum intel_pipe_crc_source
*source
)
2587 struct intel_encoder
*encoder
;
2588 struct intel_crtc
*crtc
;
2589 struct intel_digital_port
*dig_port
;
2592 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2594 mutex_lock(&dev
->mode_config
.mutex
);
2595 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
2597 if (!encoder
->base
.crtc
)
2600 crtc
= to_intel_crtc(encoder
->base
.crtc
);
2602 if (crtc
->pipe
!= pipe
)
2605 switch (encoder
->type
) {
2606 case INTEL_OUTPUT_TVOUT
:
2607 *source
= INTEL_PIPE_CRC_SOURCE_TV
;
2609 case INTEL_OUTPUT_DISPLAYPORT
:
2610 case INTEL_OUTPUT_EDP
:
2611 dig_port
= enc_to_dig_port(&encoder
->base
);
2612 switch (dig_port
->port
) {
2614 *source
= INTEL_PIPE_CRC_SOURCE_DP_B
;
2617 *source
= INTEL_PIPE_CRC_SOURCE_DP_C
;
2620 *source
= INTEL_PIPE_CRC_SOURCE_DP_D
;
2623 WARN(1, "nonexisting DP port %c\n",
2624 port_name(dig_port
->port
));
2630 mutex_unlock(&dev
->mode_config
.mutex
);
2635 static int vlv_pipe_crc_ctl_reg(struct drm_device
*dev
,
2637 enum intel_pipe_crc_source
*source
,
2640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2641 bool need_stable_symbols
= false;
2643 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2644 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2650 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2651 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_VLV
;
2653 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2654 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_VLV
;
2655 need_stable_symbols
= true;
2657 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2658 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_VLV
;
2659 need_stable_symbols
= true;
2661 case INTEL_PIPE_CRC_SOURCE_NONE
:
2669 * When the pipe CRC tap point is after the transcoders we need
2670 * to tweak symbol-level features to produce a deterministic series of
2671 * symbols for a given frame. We need to reset those features only once
2672 * a frame (instead of every nth symbol):
2673 * - DC-balance: used to ensure a better clock recovery from the data
2675 * - DisplayPort scrambling: used for EMI reduction
2677 if (need_stable_symbols
) {
2678 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2680 tmp
|= DC_BALANCE_RESET_VLV
;
2682 tmp
|= PIPE_A_SCRAMBLE_RESET
;
2684 tmp
|= PIPE_B_SCRAMBLE_RESET
;
2686 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2692 static int i9xx_pipe_crc_ctl_reg(struct drm_device
*dev
,
2694 enum intel_pipe_crc_source
*source
,
2697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2698 bool need_stable_symbols
= false;
2700 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
) {
2701 int ret
= i9xx_pipe_crc_auto_source(dev
, pipe
, source
);
2707 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2708 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_I9XX
;
2710 case INTEL_PIPE_CRC_SOURCE_TV
:
2711 if (!SUPPORTS_TV(dev
))
2713 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_TV_PRE
;
2715 case INTEL_PIPE_CRC_SOURCE_DP_B
:
2718 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_B_G4X
;
2719 need_stable_symbols
= true;
2721 case INTEL_PIPE_CRC_SOURCE_DP_C
:
2724 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_C_G4X
;
2725 need_stable_symbols
= true;
2727 case INTEL_PIPE_CRC_SOURCE_DP_D
:
2730 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_DP_D_G4X
;
2731 need_stable_symbols
= true;
2733 case INTEL_PIPE_CRC_SOURCE_NONE
:
2741 * When the pipe CRC tap point is after the transcoders we need
2742 * to tweak symbol-level features to produce a deterministic series of
2743 * symbols for a given frame. We need to reset those features only once
2744 * a frame (instead of every nth symbol):
2745 * - DC-balance: used to ensure a better clock recovery from the data
2747 * - DisplayPort scrambling: used for EMI reduction
2749 if (need_stable_symbols
) {
2750 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2752 WARN_ON(!IS_G4X(dev
));
2754 I915_WRITE(PORT_DFT_I9XX
,
2755 I915_READ(PORT_DFT_I9XX
) | DC_BALANCE_RESET
);
2758 tmp
|= PIPE_A_SCRAMBLE_RESET
;
2760 tmp
|= PIPE_B_SCRAMBLE_RESET
;
2762 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2768 static void vlv_undo_pipe_scramble_reset(struct drm_device
*dev
,
2771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2772 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2775 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
2777 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
2778 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
))
2779 tmp
&= ~DC_BALANCE_RESET_VLV
;
2780 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2784 static void g4x_undo_pipe_scramble_reset(struct drm_device
*dev
,
2787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2788 uint32_t tmp
= I915_READ(PORT_DFT2_G4X
);
2791 tmp
&= ~PIPE_A_SCRAMBLE_RESET
;
2793 tmp
&= ~PIPE_B_SCRAMBLE_RESET
;
2794 I915_WRITE(PORT_DFT2_G4X
, tmp
);
2796 if (!(tmp
& PIPE_SCRAMBLE_RESET_MASK
)) {
2797 I915_WRITE(PORT_DFT_I9XX
,
2798 I915_READ(PORT_DFT_I9XX
) & ~DC_BALANCE_RESET
);
2802 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2805 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2806 *source
= INTEL_PIPE_CRC_SOURCE_PIPE
;
2809 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
2810 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_ILK
;
2812 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
2813 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_ILK
;
2815 case INTEL_PIPE_CRC_SOURCE_PIPE
:
2816 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PIPE_ILK
;
2818 case INTEL_PIPE_CRC_SOURCE_NONE
:
2828 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source
*source
,
2831 if (*source
== INTEL_PIPE_CRC_SOURCE_AUTO
)
2832 *source
= INTEL_PIPE_CRC_SOURCE_PF
;
2835 case INTEL_PIPE_CRC_SOURCE_PLANE1
:
2836 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PRIMARY_IVB
;
2838 case INTEL_PIPE_CRC_SOURCE_PLANE2
:
2839 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_SPRITE_IVB
;
2841 case INTEL_PIPE_CRC_SOURCE_PF
:
2842 *val
= PIPE_CRC_ENABLE
| PIPE_CRC_SOURCE_PF_IVB
;
2844 case INTEL_PIPE_CRC_SOURCE_NONE
:
2854 static int pipe_crc_set_source(struct drm_device
*dev
, enum pipe pipe
,
2855 enum intel_pipe_crc_source source
)
2857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2858 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
2859 u32 val
= 0; /* shut up gcc */
2862 if (pipe_crc
->source
== source
)
2865 /* forbid changing the source without going back to 'none' */
2866 if (pipe_crc
->source
&& source
)
2870 ret
= i8xx_pipe_crc_ctl_reg(&source
, &val
);
2871 else if (INTEL_INFO(dev
)->gen
< 5)
2872 ret
= i9xx_pipe_crc_ctl_reg(dev
, pipe
, &source
, &val
);
2873 else if (IS_VALLEYVIEW(dev
))
2874 ret
= vlv_pipe_crc_ctl_reg(dev
,pipe
, &source
, &val
);
2875 else if (IS_GEN5(dev
) || IS_GEN6(dev
))
2876 ret
= ilk_pipe_crc_ctl_reg(&source
, &val
);
2878 ret
= ivb_pipe_crc_ctl_reg(&source
, &val
);
2883 /* none -> real source transition */
2885 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2886 pipe_name(pipe
), pipe_crc_source_name(source
));
2888 pipe_crc
->entries
= kzalloc(sizeof(*pipe_crc
->entries
) *
2889 INTEL_PIPE_CRC_ENTRIES_NR
,
2891 if (!pipe_crc
->entries
)
2894 spin_lock_irq(&pipe_crc
->lock
);
2897 spin_unlock_irq(&pipe_crc
->lock
);
2900 pipe_crc
->source
= source
;
2902 I915_WRITE(PIPE_CRC_CTL(pipe
), val
);
2903 POSTING_READ(PIPE_CRC_CTL(pipe
));
2905 /* real source -> none transition */
2906 if (source
== INTEL_PIPE_CRC_SOURCE_NONE
) {
2907 struct intel_pipe_crc_entry
*entries
;
2909 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2912 intel_wait_for_vblank(dev
, pipe
);
2914 spin_lock_irq(&pipe_crc
->lock
);
2915 entries
= pipe_crc
->entries
;
2916 pipe_crc
->entries
= NULL
;
2917 spin_unlock_irq(&pipe_crc
->lock
);
2922 g4x_undo_pipe_scramble_reset(dev
, pipe
);
2923 else if (IS_VALLEYVIEW(dev
))
2924 vlv_undo_pipe_scramble_reset(dev
, pipe
);
2931 * Parse pipe CRC command strings:
2932 * command: wsp* object wsp+ name wsp+ source wsp*
2935 * source: (none | plane1 | plane2 | pf)
2936 * wsp: (#0x20 | #0x9 | #0xA)+
2939 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2940 * "pipe A none" -> Stop CRC
2942 static int display_crc_ctl_tokenize(char *buf
, char *words
[], int max_words
)
2949 /* skip leading white space */
2950 buf
= skip_spaces(buf
);
2952 break; /* end of buffer */
2954 /* find end of word */
2955 for (end
= buf
; *end
&& !isspace(*end
); end
++)
2958 if (n_words
== max_words
) {
2959 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2961 return -EINVAL
; /* ran out of words[] before bytes */
2966 words
[n_words
++] = buf
;
2973 enum intel_pipe_crc_object
{
2974 PIPE_CRC_OBJECT_PIPE
,
2977 static const char * const pipe_crc_objects
[] = {
2982 display_crc_ctl_parse_object(const char *buf
, enum intel_pipe_crc_object
*o
)
2986 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_objects
); i
++)
2987 if (!strcmp(buf
, pipe_crc_objects
[i
])) {
2995 static int display_crc_ctl_parse_pipe(const char *buf
, enum pipe
*pipe
)
2997 const char name
= buf
[0];
2999 if (name
< 'A' || name
>= pipe_name(I915_MAX_PIPES
))
3008 display_crc_ctl_parse_source(const char *buf
, enum intel_pipe_crc_source
*s
)
3012 for (i
= 0; i
< ARRAY_SIZE(pipe_crc_sources
); i
++)
3013 if (!strcmp(buf
, pipe_crc_sources
[i
])) {
3021 static int display_crc_ctl_parse(struct drm_device
*dev
, char *buf
, size_t len
)
3025 char *words
[N_WORDS
];
3027 enum intel_pipe_crc_object object
;
3028 enum intel_pipe_crc_source source
;
3030 n_words
= display_crc_ctl_tokenize(buf
, words
, N_WORDS
);
3031 if (n_words
!= N_WORDS
) {
3032 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3037 if (display_crc_ctl_parse_object(words
[0], &object
) < 0) {
3038 DRM_DEBUG_DRIVER("unknown object %s\n", words
[0]);
3042 if (display_crc_ctl_parse_pipe(words
[1], &pipe
) < 0) {
3043 DRM_DEBUG_DRIVER("unknown pipe %s\n", words
[1]);
3047 if (display_crc_ctl_parse_source(words
[2], &source
) < 0) {
3048 DRM_DEBUG_DRIVER("unknown source %s\n", words
[2]);
3052 return pipe_crc_set_source(dev
, pipe
, source
);
3055 static ssize_t
display_crc_ctl_write(struct file
*file
, const char __user
*ubuf
,
3056 size_t len
, loff_t
*offp
)
3058 struct seq_file
*m
= file
->private_data
;
3059 struct drm_device
*dev
= m
->private;
3066 if (len
> PAGE_SIZE
- 1) {
3067 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3072 tmpbuf
= kmalloc(len
+ 1, GFP_KERNEL
);
3076 if (copy_from_user(tmpbuf
, ubuf
, len
)) {
3082 ret
= display_crc_ctl_parse(dev
, tmpbuf
, len
);
3093 static const struct file_operations i915_display_crc_ctl_fops
= {
3094 .owner
= THIS_MODULE
,
3095 .open
= display_crc_ctl_open
,
3097 .llseek
= seq_lseek
,
3098 .release
= single_release
,
3099 .write
= display_crc_ctl_write
3102 static void wm_latency_show(struct seq_file
*m
, const uint16_t wm
[5])
3104 struct drm_device
*dev
= m
->private;
3105 int num_levels
= IS_HASWELL(dev
) || IS_BROADWELL(dev
) ? 5 : 4;
3108 drm_modeset_lock_all(dev
);
3110 for (level
= 0; level
< num_levels
; level
++) {
3111 unsigned int latency
= wm
[level
];
3113 /* WM1+ latency values in 0.5us units */
3117 seq_printf(m
, "WM%d %u (%u.%u usec)\n",
3119 latency
/ 10, latency
% 10);
3122 drm_modeset_unlock_all(dev
);
3125 static int pri_wm_latency_show(struct seq_file
*m
, void *data
)
3127 struct drm_device
*dev
= m
->private;
3129 wm_latency_show(m
, to_i915(dev
)->wm
.pri_latency
);
3134 static int spr_wm_latency_show(struct seq_file
*m
, void *data
)
3136 struct drm_device
*dev
= m
->private;
3138 wm_latency_show(m
, to_i915(dev
)->wm
.spr_latency
);
3143 static int cur_wm_latency_show(struct seq_file
*m
, void *data
)
3145 struct drm_device
*dev
= m
->private;
3147 wm_latency_show(m
, to_i915(dev
)->wm
.cur_latency
);
3152 static int pri_wm_latency_open(struct inode
*inode
, struct file
*file
)
3154 struct drm_device
*dev
= inode
->i_private
;
3156 if (!HAS_PCH_SPLIT(dev
))
3159 return single_open(file
, pri_wm_latency_show
, dev
);
3162 static int spr_wm_latency_open(struct inode
*inode
, struct file
*file
)
3164 struct drm_device
*dev
= inode
->i_private
;
3166 if (!HAS_PCH_SPLIT(dev
))
3169 return single_open(file
, spr_wm_latency_show
, dev
);
3172 static int cur_wm_latency_open(struct inode
*inode
, struct file
*file
)
3174 struct drm_device
*dev
= inode
->i_private
;
3176 if (!HAS_PCH_SPLIT(dev
))
3179 return single_open(file
, cur_wm_latency_show
, dev
);
3182 static ssize_t
wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3183 size_t len
, loff_t
*offp
, uint16_t wm
[5])
3185 struct seq_file
*m
= file
->private_data
;
3186 struct drm_device
*dev
= m
->private;
3187 uint16_t new[5] = { 0 };
3188 int num_levels
= IS_HASWELL(dev
) || IS_BROADWELL(dev
) ? 5 : 4;
3193 if (len
>= sizeof(tmp
))
3196 if (copy_from_user(tmp
, ubuf
, len
))
3201 ret
= sscanf(tmp
, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3202 if (ret
!= num_levels
)
3205 drm_modeset_lock_all(dev
);
3207 for (level
= 0; level
< num_levels
; level
++)
3208 wm
[level
] = new[level
];
3210 drm_modeset_unlock_all(dev
);
3216 static ssize_t
pri_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3217 size_t len
, loff_t
*offp
)
3219 struct seq_file
*m
= file
->private_data
;
3220 struct drm_device
*dev
= m
->private;
3222 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.pri_latency
);
3225 static ssize_t
spr_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3226 size_t len
, loff_t
*offp
)
3228 struct seq_file
*m
= file
->private_data
;
3229 struct drm_device
*dev
= m
->private;
3231 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.spr_latency
);
3234 static ssize_t
cur_wm_latency_write(struct file
*file
, const char __user
*ubuf
,
3235 size_t len
, loff_t
*offp
)
3237 struct seq_file
*m
= file
->private_data
;
3238 struct drm_device
*dev
= m
->private;
3240 return wm_latency_write(file
, ubuf
, len
, offp
, to_i915(dev
)->wm
.cur_latency
);
3243 static const struct file_operations i915_pri_wm_latency_fops
= {
3244 .owner
= THIS_MODULE
,
3245 .open
= pri_wm_latency_open
,
3247 .llseek
= seq_lseek
,
3248 .release
= single_release
,
3249 .write
= pri_wm_latency_write
3252 static const struct file_operations i915_spr_wm_latency_fops
= {
3253 .owner
= THIS_MODULE
,
3254 .open
= spr_wm_latency_open
,
3256 .llseek
= seq_lseek
,
3257 .release
= single_release
,
3258 .write
= spr_wm_latency_write
3261 static const struct file_operations i915_cur_wm_latency_fops
= {
3262 .owner
= THIS_MODULE
,
3263 .open
= cur_wm_latency_open
,
3265 .llseek
= seq_lseek
,
3266 .release
= single_release
,
3267 .write
= cur_wm_latency_write
3271 i915_wedged_get(void *data
, u64
*val
)
3273 struct drm_device
*dev
= data
;
3274 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3276 *val
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3282 i915_wedged_set(void *data
, u64 val
)
3284 struct drm_device
*dev
= data
;
3286 i915_handle_error(dev
, val
,
3287 "Manually setting wedged to %llu", val
);
3291 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops
,
3292 i915_wedged_get
, i915_wedged_set
,
3296 i915_ring_stop_get(void *data
, u64
*val
)
3298 struct drm_device
*dev
= data
;
3299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3301 *val
= dev_priv
->gpu_error
.stop_rings
;
3307 i915_ring_stop_set(void *data
, u64 val
)
3309 struct drm_device
*dev
= data
;
3310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3313 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val
);
3315 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3319 dev_priv
->gpu_error
.stop_rings
= val
;
3320 mutex_unlock(&dev
->struct_mutex
);
3325 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops
,
3326 i915_ring_stop_get
, i915_ring_stop_set
,
3330 i915_ring_missed_irq_get(void *data
, u64
*val
)
3332 struct drm_device
*dev
= data
;
3333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3335 *val
= dev_priv
->gpu_error
.missed_irq_rings
;
3340 i915_ring_missed_irq_set(void *data
, u64 val
)
3342 struct drm_device
*dev
= data
;
3343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3346 /* Lock against concurrent debugfs callers */
3347 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3350 dev_priv
->gpu_error
.missed_irq_rings
= val
;
3351 mutex_unlock(&dev
->struct_mutex
);
3356 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops
,
3357 i915_ring_missed_irq_get
, i915_ring_missed_irq_set
,
3361 i915_ring_test_irq_get(void *data
, u64
*val
)
3363 struct drm_device
*dev
= data
;
3364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3366 *val
= dev_priv
->gpu_error
.test_irq_rings
;
3372 i915_ring_test_irq_set(void *data
, u64 val
)
3374 struct drm_device
*dev
= data
;
3375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3378 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val
);
3380 /* Lock against concurrent debugfs callers */
3381 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3385 dev_priv
->gpu_error
.test_irq_rings
= val
;
3386 mutex_unlock(&dev
->struct_mutex
);
3391 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops
,
3392 i915_ring_test_irq_get
, i915_ring_test_irq_set
,
3395 #define DROP_UNBOUND 0x1
3396 #define DROP_BOUND 0x2
3397 #define DROP_RETIRE 0x4
3398 #define DROP_ACTIVE 0x8
3399 #define DROP_ALL (DROP_UNBOUND | \
3404 i915_drop_caches_get(void *data
, u64
*val
)
3412 i915_drop_caches_set(void *data
, u64 val
)
3414 struct drm_device
*dev
= data
;
3415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3416 struct drm_i915_gem_object
*obj
, *next
;
3417 struct i915_address_space
*vm
;
3418 struct i915_vma
*vma
, *x
;
3421 DRM_DEBUG("Dropping caches: 0x%08llx\n", val
);
3423 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3424 * on ioctls on -EAGAIN. */
3425 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3429 if (val
& DROP_ACTIVE
) {
3430 ret
= i915_gpu_idle(dev
);
3435 if (val
& (DROP_RETIRE
| DROP_ACTIVE
))
3436 i915_gem_retire_requests(dev
);
3438 if (val
& DROP_BOUND
) {
3439 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3440 list_for_each_entry_safe(vma
, x
, &vm
->inactive_list
,
3445 ret
= i915_vma_unbind(vma
);
3452 if (val
& DROP_UNBOUND
) {
3453 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
3455 if (obj
->pages_pin_count
== 0) {
3456 ret
= i915_gem_object_put_pages(obj
);
3463 mutex_unlock(&dev
->struct_mutex
);
3468 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops
,
3469 i915_drop_caches_get
, i915_drop_caches_set
,
3473 i915_max_freq_get(void *data
, u64
*val
)
3475 struct drm_device
*dev
= data
;
3476 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3479 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3482 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3484 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3488 if (IS_VALLEYVIEW(dev
))
3489 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq_softlimit
);
3491 *val
= dev_priv
->rps
.max_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3492 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3498 i915_max_freq_set(void *data
, u64 val
)
3500 struct drm_device
*dev
= data
;
3501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3502 u32 rp_state_cap
, hw_max
, hw_min
;
3505 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3508 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3510 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val
);
3512 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3517 * Turbo will still be enabled, but won't go above the set value.
3519 if (IS_VALLEYVIEW(dev
)) {
3520 val
= vlv_freq_opcode(dev_priv
, val
);
3522 hw_max
= valleyview_rps_max_freq(dev_priv
);
3523 hw_min
= valleyview_rps_min_freq(dev_priv
);
3525 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3527 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3528 hw_max
= dev_priv
->rps
.max_freq
;
3529 hw_min
= (rp_state_cap
>> 16) & 0xff;
3532 if (val
< hw_min
|| val
> hw_max
|| val
< dev_priv
->rps
.min_freq_softlimit
) {
3533 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3537 dev_priv
->rps
.max_freq_softlimit
= val
;
3539 if (IS_VALLEYVIEW(dev
))
3540 valleyview_set_rps(dev
, val
);
3542 gen6_set_rps(dev
, val
);
3544 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3549 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops
,
3550 i915_max_freq_get
, i915_max_freq_set
,
3554 i915_min_freq_get(void *data
, u64
*val
)
3556 struct drm_device
*dev
= data
;
3557 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3560 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3563 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3565 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3569 if (IS_VALLEYVIEW(dev
))
3570 *val
= vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq_softlimit
);
3572 *val
= dev_priv
->rps
.min_freq_softlimit
* GT_FREQUENCY_MULTIPLIER
;
3573 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3579 i915_min_freq_set(void *data
, u64 val
)
3581 struct drm_device
*dev
= data
;
3582 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3583 u32 rp_state_cap
, hw_max
, hw_min
;
3586 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3589 flush_delayed_work(&dev_priv
->rps
.delayed_resume_work
);
3591 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val
);
3593 ret
= mutex_lock_interruptible(&dev_priv
->rps
.hw_lock
);
3598 * Turbo will still be enabled, but won't go below the set value.
3600 if (IS_VALLEYVIEW(dev
)) {
3601 val
= vlv_freq_opcode(dev_priv
, val
);
3603 hw_max
= valleyview_rps_max_freq(dev_priv
);
3604 hw_min
= valleyview_rps_min_freq(dev_priv
);
3606 do_div(val
, GT_FREQUENCY_MULTIPLIER
);
3608 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3609 hw_max
= dev_priv
->rps
.max_freq
;
3610 hw_min
= (rp_state_cap
>> 16) & 0xff;
3613 if (val
< hw_min
|| val
> hw_max
|| val
> dev_priv
->rps
.max_freq_softlimit
) {
3614 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3618 dev_priv
->rps
.min_freq_softlimit
= val
;
3620 if (IS_VALLEYVIEW(dev
))
3621 valleyview_set_rps(dev
, val
);
3623 gen6_set_rps(dev
, val
);
3625 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3630 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops
,
3631 i915_min_freq_get
, i915_min_freq_set
,
3635 i915_cache_sharing_get(void *data
, u64
*val
)
3637 struct drm_device
*dev
= data
;
3638 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3642 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3645 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
3648 intel_runtime_pm_get(dev_priv
);
3650 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3652 intel_runtime_pm_put(dev_priv
);
3653 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
3655 *val
= (snpcr
& GEN6_MBC_SNPCR_MASK
) >> GEN6_MBC_SNPCR_SHIFT
;
3661 i915_cache_sharing_set(void *data
, u64 val
)
3663 struct drm_device
*dev
= data
;
3664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3667 if (!(IS_GEN6(dev
) || IS_GEN7(dev
)))
3673 intel_runtime_pm_get(dev_priv
);
3674 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val
);
3676 /* Update the cache sharing policy here as well */
3677 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
3678 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
3679 snpcr
|= (val
<< GEN6_MBC_SNPCR_SHIFT
);
3680 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
3682 intel_runtime_pm_put(dev_priv
);
3686 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops
,
3687 i915_cache_sharing_get
, i915_cache_sharing_set
,
3690 static int i915_forcewake_open(struct inode
*inode
, struct file
*file
)
3692 struct drm_device
*dev
= inode
->i_private
;
3693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 if (INTEL_INFO(dev
)->gen
< 6)
3698 intel_runtime_pm_get(dev_priv
);
3699 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3704 static int i915_forcewake_release(struct inode
*inode
, struct file
*file
)
3706 struct drm_device
*dev
= inode
->i_private
;
3707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3709 if (INTEL_INFO(dev
)->gen
< 6)
3712 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3713 intel_runtime_pm_put(dev_priv
);
3718 static const struct file_operations i915_forcewake_fops
= {
3719 .owner
= THIS_MODULE
,
3720 .open
= i915_forcewake_open
,
3721 .release
= i915_forcewake_release
,
3724 static int i915_forcewake_create(struct dentry
*root
, struct drm_minor
*minor
)
3726 struct drm_device
*dev
= minor
->dev
;
3729 ent
= debugfs_create_file("i915_forcewake_user",
3732 &i915_forcewake_fops
);
3736 return drm_add_fake_info_node(minor
, ent
, &i915_forcewake_fops
);
3739 static int i915_debugfs_create(struct dentry
*root
,
3740 struct drm_minor
*minor
,
3742 const struct file_operations
*fops
)
3744 struct drm_device
*dev
= minor
->dev
;
3747 ent
= debugfs_create_file(name
,
3754 return drm_add_fake_info_node(minor
, ent
, fops
);
3757 static const struct drm_info_list i915_debugfs_list
[] = {
3758 {"i915_capabilities", i915_capabilities
, 0},
3759 {"i915_gem_objects", i915_gem_object_info
, 0},
3760 {"i915_gem_gtt", i915_gem_gtt_info
, 0},
3761 {"i915_gem_pinned", i915_gem_gtt_info
, 0, (void *) PINNED_LIST
},
3762 {"i915_gem_active", i915_gem_object_list_info
, 0, (void *) ACTIVE_LIST
},
3763 {"i915_gem_inactive", i915_gem_object_list_info
, 0, (void *) INACTIVE_LIST
},
3764 {"i915_gem_stolen", i915_gem_stolen_list_info
},
3765 {"i915_gem_pageflip", i915_gem_pageflip_info
, 0},
3766 {"i915_gem_request", i915_gem_request_info
, 0},
3767 {"i915_gem_seqno", i915_gem_seqno_info
, 0},
3768 {"i915_gem_fence_regs", i915_gem_fence_regs_info
, 0},
3769 {"i915_gem_interrupt", i915_interrupt_info
, 0},
3770 {"i915_gem_hws", i915_hws_info
, 0, (void *)RCS
},
3771 {"i915_gem_hws_blt", i915_hws_info
, 0, (void *)BCS
},
3772 {"i915_gem_hws_bsd", i915_hws_info
, 0, (void *)VCS
},
3773 {"i915_gem_hws_vebox", i915_hws_info
, 0, (void *)VECS
},
3774 {"i915_rstdby_delays", i915_rstdby_delays
, 0},
3775 {"i915_cur_delayinfo", i915_cur_delayinfo
, 0},
3776 {"i915_delayfreq_table", i915_delayfreq_table
, 0},
3777 {"i915_inttoext_table", i915_inttoext_table
, 0},
3778 {"i915_drpc_info", i915_drpc_info
, 0},
3779 {"i915_emon_status", i915_emon_status
, 0},
3780 {"i915_ring_freq_table", i915_ring_freq_table
, 0},
3781 {"i915_gfxec", i915_gfxec
, 0},
3782 {"i915_fbc_status", i915_fbc_status
, 0},
3783 {"i915_ips_status", i915_ips_status
, 0},
3784 {"i915_sr_status", i915_sr_status
, 0},
3785 {"i915_opregion", i915_opregion
, 0},
3786 {"i915_gem_framebuffer", i915_gem_framebuffer_info
, 0},
3787 {"i915_context_status", i915_context_status
, 0},
3788 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info
, 0},
3789 {"i915_swizzle_info", i915_swizzle_info
, 0},
3790 {"i915_ppgtt_info", i915_ppgtt_info
, 0},
3791 {"i915_dpio", i915_dpio_info
, 0},
3792 {"i915_llc", i915_llc
, 0},
3793 {"i915_edp_psr_status", i915_edp_psr_status
, 0},
3794 {"i915_sink_crc_eDP1", i915_sink_crc
, 0},
3795 {"i915_energy_uJ", i915_energy_uJ
, 0},
3796 {"i915_pc8_status", i915_pc8_status
, 0},
3797 {"i915_power_domain_info", i915_power_domain_info
, 0},
3798 {"i915_display_info", i915_display_info
, 0},
3800 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3802 static const struct i915_debugfs_files
{
3804 const struct file_operations
*fops
;
3805 } i915_debugfs_files
[] = {
3806 {"i915_wedged", &i915_wedged_fops
},
3807 {"i915_max_freq", &i915_max_freq_fops
},
3808 {"i915_min_freq", &i915_min_freq_fops
},
3809 {"i915_cache_sharing", &i915_cache_sharing_fops
},
3810 {"i915_ring_stop", &i915_ring_stop_fops
},
3811 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops
},
3812 {"i915_ring_test_irq", &i915_ring_test_irq_fops
},
3813 {"i915_gem_drop_caches", &i915_drop_caches_fops
},
3814 {"i915_error_state", &i915_error_state_fops
},
3815 {"i915_next_seqno", &i915_next_seqno_fops
},
3816 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops
},
3817 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops
},
3818 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops
},
3819 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops
},
3822 void intel_display_crc_init(struct drm_device
*dev
)
3824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3827 for_each_pipe(pipe
) {
3828 struct intel_pipe_crc
*pipe_crc
= &dev_priv
->pipe_crc
[pipe
];
3830 pipe_crc
->opened
= false;
3831 spin_lock_init(&pipe_crc
->lock
);
3832 init_waitqueue_head(&pipe_crc
->wq
);
3836 int i915_debugfs_init(struct drm_minor
*minor
)
3840 ret
= i915_forcewake_create(minor
->debugfs_root
, minor
);
3844 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
3845 ret
= i915_pipe_crc_create(minor
->debugfs_root
, minor
, i
);
3850 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
3851 ret
= i915_debugfs_create(minor
->debugfs_root
, minor
,
3852 i915_debugfs_files
[i
].name
,
3853 i915_debugfs_files
[i
].fops
);
3858 return drm_debugfs_create_files(i915_debugfs_list
,
3859 I915_DEBUGFS_ENTRIES
,
3860 minor
->debugfs_root
, minor
);
3863 void i915_debugfs_cleanup(struct drm_minor
*minor
)
3867 drm_debugfs_remove_files(i915_debugfs_list
,
3868 I915_DEBUGFS_ENTRIES
, minor
);
3870 drm_debugfs_remove_files((struct drm_info_list
*) &i915_forcewake_fops
,
3873 for (i
= 0; i
< ARRAY_SIZE(i915_pipe_crc_data
); i
++) {
3874 struct drm_info_list
*info_list
=
3875 (struct drm_info_list
*)&i915_pipe_crc_data
[i
];
3877 drm_debugfs_remove_files(info_list
, 1, minor
);
3880 for (i
= 0; i
< ARRAY_SIZE(i915_debugfs_files
); i
++) {
3881 struct drm_info_list
*info_list
=
3882 (struct drm_info_list
*) i915_debugfs_files
[i
].fops
;
3884 drm_debugfs_remove_files(info_list
, 1, minor
);