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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <linux/acpi.h>
32 #include <drm/drmP.h>
33 #include <drm/i915_drm.h>
34 #include "i915_drv.h"
35 #include "i915_trace.h"
36 #include "intel_drv.h"
37
38 #include <linux/apple-gmux.h>
39 #include <linux/console.h>
40 #include <linux/module.h>
41 #include <linux/pm_runtime.h>
42 #include <linux/vgaarb.h>
43 #include <linux/vga_switcheroo.h>
44 #include <drm/drm_crtc_helper.h>
45
46 static struct drm_driver driver;
47
48 #define GEN_DEFAULT_PIPEOFFSETS \
49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
50 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
52 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
54
55 #define GEN_CHV_PIPEOFFSETS \
56 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
57 CHV_PIPE_C_OFFSET }, \
58 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
59 CHV_TRANSCODER_C_OFFSET, }, \
60 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
61 CHV_PALETTE_C_OFFSET }
62
63 #define CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
65
66 #define IVB_CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68
69 #define BDW_COLORS \
70 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
71 #define CHV_COLORS \
72 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
73
74 static const struct intel_device_info intel_i830_info = {
75 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
76 .has_overlay = 1, .overlay_needs_physical = 1,
77 .ring_mask = RENDER_RING,
78 GEN_DEFAULT_PIPEOFFSETS,
79 CURSOR_OFFSETS,
80 };
81
82 static const struct intel_device_info intel_845g_info = {
83 .gen = 2, .num_pipes = 1,
84 .has_overlay = 1, .overlay_needs_physical = 1,
85 .ring_mask = RENDER_RING,
86 GEN_DEFAULT_PIPEOFFSETS,
87 CURSOR_OFFSETS,
88 };
89
90 static const struct intel_device_info intel_i85x_info = {
91 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
92 .cursor_needs_physical = 1,
93 .has_overlay = 1, .overlay_needs_physical = 1,
94 .has_fbc = 1,
95 .ring_mask = RENDER_RING,
96 GEN_DEFAULT_PIPEOFFSETS,
97 CURSOR_OFFSETS,
98 };
99
100 static const struct intel_device_info intel_i865g_info = {
101 .gen = 2, .num_pipes = 1,
102 .has_overlay = 1, .overlay_needs_physical = 1,
103 .ring_mask = RENDER_RING,
104 GEN_DEFAULT_PIPEOFFSETS,
105 CURSOR_OFFSETS,
106 };
107
108 static const struct intel_device_info intel_i915g_info = {
109 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
110 .has_overlay = 1, .overlay_needs_physical = 1,
111 .ring_mask = RENDER_RING,
112 GEN_DEFAULT_PIPEOFFSETS,
113 CURSOR_OFFSETS,
114 };
115 static const struct intel_device_info intel_i915gm_info = {
116 .gen = 3, .is_mobile = 1, .num_pipes = 2,
117 .cursor_needs_physical = 1,
118 .has_overlay = 1, .overlay_needs_physical = 1,
119 .supports_tv = 1,
120 .has_fbc = 1,
121 .ring_mask = RENDER_RING,
122 GEN_DEFAULT_PIPEOFFSETS,
123 CURSOR_OFFSETS,
124 };
125 static const struct intel_device_info intel_i945g_info = {
126 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
127 .has_overlay = 1, .overlay_needs_physical = 1,
128 .ring_mask = RENDER_RING,
129 GEN_DEFAULT_PIPEOFFSETS,
130 CURSOR_OFFSETS,
131 };
132 static const struct intel_device_info intel_i945gm_info = {
133 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
134 .has_hotplug = 1, .cursor_needs_physical = 1,
135 .has_overlay = 1, .overlay_needs_physical = 1,
136 .supports_tv = 1,
137 .has_fbc = 1,
138 .ring_mask = RENDER_RING,
139 GEN_DEFAULT_PIPEOFFSETS,
140 CURSOR_OFFSETS,
141 };
142
143 static const struct intel_device_info intel_i965g_info = {
144 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
145 .has_hotplug = 1,
146 .has_overlay = 1,
147 .ring_mask = RENDER_RING,
148 GEN_DEFAULT_PIPEOFFSETS,
149 CURSOR_OFFSETS,
150 };
151
152 static const struct intel_device_info intel_i965gm_info = {
153 .gen = 4, .is_crestline = 1, .num_pipes = 2,
154 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
155 .has_overlay = 1,
156 .supports_tv = 1,
157 .ring_mask = RENDER_RING,
158 GEN_DEFAULT_PIPEOFFSETS,
159 CURSOR_OFFSETS,
160 };
161
162 static const struct intel_device_info intel_g33_info = {
163 .gen = 3, .is_g33 = 1, .num_pipes = 2,
164 .need_gfx_hws = 1, .has_hotplug = 1,
165 .has_overlay = 1,
166 .ring_mask = RENDER_RING,
167 GEN_DEFAULT_PIPEOFFSETS,
168 CURSOR_OFFSETS,
169 };
170
171 static const struct intel_device_info intel_g45_info = {
172 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
173 .has_pipe_cxsr = 1, .has_hotplug = 1,
174 .ring_mask = RENDER_RING | BSD_RING,
175 GEN_DEFAULT_PIPEOFFSETS,
176 CURSOR_OFFSETS,
177 };
178
179 static const struct intel_device_info intel_gm45_info = {
180 .gen = 4, .is_g4x = 1, .num_pipes = 2,
181 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
182 .has_pipe_cxsr = 1, .has_hotplug = 1,
183 .supports_tv = 1,
184 .ring_mask = RENDER_RING | BSD_RING,
185 GEN_DEFAULT_PIPEOFFSETS,
186 CURSOR_OFFSETS,
187 };
188
189 static const struct intel_device_info intel_pineview_info = {
190 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
191 .need_gfx_hws = 1, .has_hotplug = 1,
192 .has_overlay = 1,
193 GEN_DEFAULT_PIPEOFFSETS,
194 CURSOR_OFFSETS,
195 };
196
197 static const struct intel_device_info intel_ironlake_d_info = {
198 .gen = 5, .num_pipes = 2,
199 .need_gfx_hws = 1, .has_hotplug = 1,
200 .ring_mask = RENDER_RING | BSD_RING,
201 GEN_DEFAULT_PIPEOFFSETS,
202 CURSOR_OFFSETS,
203 };
204
205 static const struct intel_device_info intel_ironlake_m_info = {
206 .gen = 5, .is_mobile = 1, .num_pipes = 2,
207 .need_gfx_hws = 1, .has_hotplug = 1,
208 .has_fbc = 1,
209 .ring_mask = RENDER_RING | BSD_RING,
210 GEN_DEFAULT_PIPEOFFSETS,
211 CURSOR_OFFSETS,
212 };
213
214 static const struct intel_device_info intel_sandybridge_d_info = {
215 .gen = 6, .num_pipes = 2,
216 .need_gfx_hws = 1, .has_hotplug = 1,
217 .has_fbc = 1,
218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
219 .has_llc = 1,
220 GEN_DEFAULT_PIPEOFFSETS,
221 CURSOR_OFFSETS,
222 };
223
224 static const struct intel_device_info intel_sandybridge_m_info = {
225 .gen = 6, .is_mobile = 1, .num_pipes = 2,
226 .need_gfx_hws = 1, .has_hotplug = 1,
227 .has_fbc = 1,
228 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
229 .has_llc = 1,
230 GEN_DEFAULT_PIPEOFFSETS,
231 CURSOR_OFFSETS,
232 };
233
234 #define GEN7_FEATURES \
235 .gen = 7, .num_pipes = 3, \
236 .need_gfx_hws = 1, .has_hotplug = 1, \
237 .has_fbc = 1, \
238 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
239 .has_llc = 1, \
240 GEN_DEFAULT_PIPEOFFSETS, \
241 IVB_CURSOR_OFFSETS
242
243 static const struct intel_device_info intel_ivybridge_d_info = {
244 GEN7_FEATURES,
245 .is_ivybridge = 1,
246 };
247
248 static const struct intel_device_info intel_ivybridge_m_info = {
249 GEN7_FEATURES,
250 .is_ivybridge = 1,
251 .is_mobile = 1,
252 };
253
254 static const struct intel_device_info intel_ivybridge_q_info = {
255 GEN7_FEATURES,
256 .is_ivybridge = 1,
257 .num_pipes = 0, /* legal, last one wins */
258 };
259
260 #define VLV_FEATURES \
261 .gen = 7, .num_pipes = 2, \
262 .need_gfx_hws = 1, .has_hotplug = 1, \
263 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
264 .display_mmio_offset = VLV_DISPLAY_BASE, \
265 GEN_DEFAULT_PIPEOFFSETS, \
266 CURSOR_OFFSETS
267
268 static const struct intel_device_info intel_valleyview_m_info = {
269 VLV_FEATURES,
270 .is_valleyview = 1,
271 .is_mobile = 1,
272 };
273
274 static const struct intel_device_info intel_valleyview_d_info = {
275 VLV_FEATURES,
276 .is_valleyview = 1,
277 };
278
279 #define HSW_FEATURES \
280 GEN7_FEATURES, \
281 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
282 .has_ddi = 1, \
283 .has_fpga_dbg = 1
284
285 static const struct intel_device_info intel_haswell_d_info = {
286 HSW_FEATURES,
287 .is_haswell = 1,
288 };
289
290 static const struct intel_device_info intel_haswell_m_info = {
291 HSW_FEATURES,
292 .is_haswell = 1,
293 .is_mobile = 1,
294 };
295
296 #define BDW_FEATURES \
297 HSW_FEATURES, \
298 BDW_COLORS
299
300 static const struct intel_device_info intel_broadwell_d_info = {
301 BDW_FEATURES,
302 .gen = 8,
303 };
304
305 static const struct intel_device_info intel_broadwell_m_info = {
306 BDW_FEATURES,
307 .gen = 8, .is_mobile = 1,
308 };
309
310 static const struct intel_device_info intel_broadwell_gt3d_info = {
311 BDW_FEATURES,
312 .gen = 8,
313 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
314 };
315
316 static const struct intel_device_info intel_broadwell_gt3m_info = {
317 BDW_FEATURES,
318 .gen = 8, .is_mobile = 1,
319 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
320 };
321
322 static const struct intel_device_info intel_cherryview_info = {
323 .gen = 8, .num_pipes = 3,
324 .need_gfx_hws = 1, .has_hotplug = 1,
325 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
326 .is_cherryview = 1,
327 .display_mmio_offset = VLV_DISPLAY_BASE,
328 GEN_CHV_PIPEOFFSETS,
329 CURSOR_OFFSETS,
330 CHV_COLORS,
331 };
332
333 static const struct intel_device_info intel_skylake_info = {
334 BDW_FEATURES,
335 .is_skylake = 1,
336 .gen = 9,
337 };
338
339 static const struct intel_device_info intel_skylake_gt3_info = {
340 BDW_FEATURES,
341 .is_skylake = 1,
342 .gen = 9,
343 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
344 };
345
346 static const struct intel_device_info intel_broxton_info = {
347 .is_preliminary = 1,
348 .is_broxton = 1,
349 .gen = 9,
350 .need_gfx_hws = 1, .has_hotplug = 1,
351 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
352 .num_pipes = 3,
353 .has_ddi = 1,
354 .has_fpga_dbg = 1,
355 .has_fbc = 1,
356 GEN_DEFAULT_PIPEOFFSETS,
357 IVB_CURSOR_OFFSETS,
358 BDW_COLORS,
359 };
360
361 static const struct intel_device_info intel_kabylake_info = {
362 BDW_FEATURES,
363 .is_kabylake = 1,
364 .gen = 9,
365 };
366
367 static const struct intel_device_info intel_kabylake_gt3_info = {
368 BDW_FEATURES,
369 .is_kabylake = 1,
370 .gen = 9,
371 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
372 };
373
374 /*
375 * Make sure any device matches here are from most specific to most
376 * general. For example, since the Quanta match is based on the subsystem
377 * and subvendor IDs, we need it to come before the more general IVB
378 * PCI ID matches, otherwise we'll use the wrong info struct above.
379 */
380 static const struct pci_device_id pciidlist[] = {
381 INTEL_I830_IDS(&intel_i830_info),
382 INTEL_I845G_IDS(&intel_845g_info),
383 INTEL_I85X_IDS(&intel_i85x_info),
384 INTEL_I865G_IDS(&intel_i865g_info),
385 INTEL_I915G_IDS(&intel_i915g_info),
386 INTEL_I915GM_IDS(&intel_i915gm_info),
387 INTEL_I945G_IDS(&intel_i945g_info),
388 INTEL_I945GM_IDS(&intel_i945gm_info),
389 INTEL_I965G_IDS(&intel_i965g_info),
390 INTEL_G33_IDS(&intel_g33_info),
391 INTEL_I965GM_IDS(&intel_i965gm_info),
392 INTEL_GM45_IDS(&intel_gm45_info),
393 INTEL_G45_IDS(&intel_g45_info),
394 INTEL_PINEVIEW_IDS(&intel_pineview_info),
395 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
396 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
397 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
398 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
399 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
400 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
401 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
402 INTEL_HSW_D_IDS(&intel_haswell_d_info),
403 INTEL_HSW_M_IDS(&intel_haswell_m_info),
404 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
405 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
406 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
407 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
408 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
409 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
410 INTEL_CHV_IDS(&intel_cherryview_info),
411 INTEL_SKL_GT1_IDS(&intel_skylake_info),
412 INTEL_SKL_GT2_IDS(&intel_skylake_info),
413 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
414 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
415 INTEL_BXT_IDS(&intel_broxton_info),
416 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
417 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
418 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
419 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
420 {0, 0, 0}
421 };
422
423 MODULE_DEVICE_TABLE(pci, pciidlist);
424
425 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
426 {
427 enum intel_pch ret = PCH_NOP;
428
429 /*
430 * In a virtualized passthrough environment we can be in a
431 * setup where the ISA bridge is not able to be passed through.
432 * In this case, a south bridge can be emulated and we have to
433 * make an educated guess as to which PCH is really there.
434 */
435
436 if (IS_GEN5(dev)) {
437 ret = PCH_IBX;
438 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
439 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
440 ret = PCH_CPT;
441 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
442 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
443 ret = PCH_LPT;
444 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
445 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
446 ret = PCH_SPT;
447 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
448 }
449
450 return ret;
451 }
452
453 void intel_detect_pch(struct drm_device *dev)
454 {
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct pci_dev *pch = NULL;
457
458 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
459 * (which really amounts to a PCH but no South Display).
460 */
461 if (INTEL_INFO(dev)->num_pipes == 0) {
462 dev_priv->pch_type = PCH_NOP;
463 return;
464 }
465
466 /*
467 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
468 * make graphics device passthrough work easy for VMM, that only
469 * need to expose ISA bridge to let driver know the real hardware
470 * underneath. This is a requirement from virtualization team.
471 *
472 * In some virtualized environments (e.g. XEN), there is irrelevant
473 * ISA bridge in the system. To work reliably, we should scan trhough
474 * all the ISA bridge devices and check for the first match, instead
475 * of only checking the first one.
476 */
477 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
478 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
479 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
480 dev_priv->pch_id = id;
481
482 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
483 dev_priv->pch_type = PCH_IBX;
484 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
485 WARN_ON(!IS_GEN5(dev));
486 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
487 dev_priv->pch_type = PCH_CPT;
488 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
489 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
490 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
491 /* PantherPoint is CPT compatible */
492 dev_priv->pch_type = PCH_CPT;
493 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
494 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
495 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
496 dev_priv->pch_type = PCH_LPT;
497 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
498 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
499 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
500 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
501 dev_priv->pch_type = PCH_LPT;
502 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
503 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
504 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
505 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
506 dev_priv->pch_type = PCH_SPT;
507 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
508 WARN_ON(!IS_SKYLAKE(dev) &&
509 !IS_KABYLAKE(dev));
510 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
511 dev_priv->pch_type = PCH_SPT;
512 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
513 WARN_ON(!IS_SKYLAKE(dev) &&
514 !IS_KABYLAKE(dev));
515 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
516 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
517 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
518 pch->subsystem_vendor == 0x1af4 &&
519 pch->subsystem_device == 0x1100)) {
520 dev_priv->pch_type = intel_virt_detect_pch(dev);
521 } else
522 continue;
523
524 break;
525 }
526 }
527 if (!pch)
528 DRM_DEBUG_KMS("No PCH found.\n");
529
530 pci_dev_put(pch);
531 }
532
533 bool i915_semaphore_is_enabled(struct drm_device *dev)
534 {
535 if (INTEL_INFO(dev)->gen < 6)
536 return false;
537
538 if (i915.semaphores >= 0)
539 return i915.semaphores;
540
541 /* TODO: make semaphores and Execlists play nicely together */
542 if (i915.enable_execlists)
543 return false;
544
545 /* Until we get further testing... */
546 if (IS_GEN8(dev))
547 return false;
548
549 #ifdef CONFIG_INTEL_IOMMU
550 /* Enable semaphores on SNB when IO remapping is off */
551 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
552 return false;
553 #endif
554
555 return true;
556 }
557
558 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
559 {
560 struct drm_device *dev = dev_priv->dev;
561 struct intel_encoder *encoder;
562
563 drm_modeset_lock_all(dev);
564 for_each_intel_encoder(dev, encoder)
565 if (encoder->suspend)
566 encoder->suspend(encoder);
567 drm_modeset_unlock_all(dev);
568 }
569
570 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
571 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
572 bool rpm_resume);
573 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
574
575 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
576 {
577 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
578 if (acpi_target_system_state() < ACPI_STATE_S3)
579 return true;
580 #endif
581 return false;
582 }
583
584 static int i915_drm_suspend(struct drm_device *dev)
585 {
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 pci_power_t opregion_target_state;
588 int error;
589
590 /* ignore lid events during suspend */
591 mutex_lock(&dev_priv->modeset_restore_lock);
592 dev_priv->modeset_restore = MODESET_SUSPENDED;
593 mutex_unlock(&dev_priv->modeset_restore_lock);
594
595 disable_rpm_wakeref_asserts(dev_priv);
596
597 /* We do a lot of poking in a lot of registers, make sure they work
598 * properly. */
599 intel_display_set_init_power(dev_priv, true);
600
601 drm_kms_helper_poll_disable(dev);
602
603 pci_save_state(dev->pdev);
604
605 error = i915_gem_suspend(dev);
606 if (error) {
607 dev_err(&dev->pdev->dev,
608 "GEM idle failed, resume might fail\n");
609 goto out;
610 }
611
612 intel_guc_suspend(dev);
613
614 intel_suspend_gt_powersave(dev);
615
616 intel_display_suspend(dev);
617
618 intel_dp_mst_suspend(dev);
619
620 intel_runtime_pm_disable_interrupts(dev_priv);
621 intel_hpd_cancel_work(dev_priv);
622
623 intel_suspend_encoders(dev_priv);
624
625 intel_suspend_hw(dev);
626
627 i915_gem_suspend_gtt_mappings(dev);
628
629 i915_save_state(dev);
630
631 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
632 intel_opregion_notify_adapter(dev, opregion_target_state);
633
634 intel_uncore_forcewake_reset(dev, false);
635 intel_opregion_fini(dev);
636
637 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
638
639 dev_priv->suspend_count++;
640
641 intel_display_set_init_power(dev_priv, false);
642
643 if (HAS_CSR(dev_priv))
644 flush_work(&dev_priv->csr.work);
645
646 out:
647 enable_rpm_wakeref_asserts(dev_priv);
648
649 return error;
650 }
651
652 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
653 {
654 struct drm_i915_private *dev_priv = drm_dev->dev_private;
655 bool fw_csr;
656 int ret;
657
658 disable_rpm_wakeref_asserts(dev_priv);
659
660 fw_csr = !IS_BROXTON(dev_priv) &&
661 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
662 /*
663 * In case of firmware assisted context save/restore don't manually
664 * deinit the power domains. This also means the CSR/DMC firmware will
665 * stay active, it will power down any HW resources as required and
666 * also enable deeper system power states that would be blocked if the
667 * firmware was inactive.
668 */
669 if (!fw_csr)
670 intel_power_domains_suspend(dev_priv);
671
672 ret = intel_suspend_complete(dev_priv);
673
674 if (ret) {
675 DRM_ERROR("Suspend complete failed: %d\n", ret);
676 if (!fw_csr)
677 intel_power_domains_init_hw(dev_priv, true);
678
679 goto out;
680 }
681
682 pci_disable_device(drm_dev->pdev);
683 /*
684 * During hibernation on some platforms the BIOS may try to access
685 * the device even though it's already in D3 and hang the machine. So
686 * leave the device in D0 on those platforms and hope the BIOS will
687 * power down the device properly. The issue was seen on multiple old
688 * GENs with different BIOS vendors, so having an explicit blacklist
689 * is inpractical; apply the workaround on everything pre GEN6. The
690 * platforms where the issue was seen:
691 * Lenovo Thinkpad X301, X61s, X60, T60, X41
692 * Fujitsu FSC S7110
693 * Acer Aspire 1830T
694 */
695 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
696 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
697
698 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
699
700 out:
701 enable_rpm_wakeref_asserts(dev_priv);
702
703 return ret;
704 }
705
706 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
707 {
708 int error;
709
710 if (!dev || !dev->dev_private) {
711 DRM_ERROR("dev: %p\n", dev);
712 DRM_ERROR("DRM not initialized, aborting suspend.\n");
713 return -ENODEV;
714 }
715
716 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
717 state.event != PM_EVENT_FREEZE))
718 return -EINVAL;
719
720 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
721 return 0;
722
723 error = i915_drm_suspend(dev);
724 if (error)
725 return error;
726
727 return i915_drm_suspend_late(dev, false);
728 }
729
730 static int i915_drm_resume(struct drm_device *dev)
731 {
732 struct drm_i915_private *dev_priv = dev->dev_private;
733
734 disable_rpm_wakeref_asserts(dev_priv);
735
736 mutex_lock(&dev->struct_mutex);
737 i915_gem_restore_gtt_mappings(dev);
738 mutex_unlock(&dev->struct_mutex);
739
740 i915_restore_state(dev);
741 intel_opregion_setup(dev);
742
743 intel_init_pch_refclk(dev);
744 drm_mode_config_reset(dev);
745
746 /*
747 * Interrupts have to be enabled before any batches are run. If not the
748 * GPU will hang. i915_gem_init_hw() will initiate batches to
749 * update/restore the context.
750 *
751 * Modeset enabling in intel_modeset_init_hw() also needs working
752 * interrupts.
753 */
754 intel_runtime_pm_enable_interrupts(dev_priv);
755
756 mutex_lock(&dev->struct_mutex);
757 if (i915_gem_init_hw(dev)) {
758 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
759 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
760 }
761 mutex_unlock(&dev->struct_mutex);
762
763 intel_guc_resume(dev);
764
765 intel_modeset_init_hw(dev);
766
767 spin_lock_irq(&dev_priv->irq_lock);
768 if (dev_priv->display.hpd_irq_setup)
769 dev_priv->display.hpd_irq_setup(dev);
770 spin_unlock_irq(&dev_priv->irq_lock);
771
772 intel_dp_mst_resume(dev);
773
774 intel_display_resume(dev);
775
776 /*
777 * ... but also need to make sure that hotplug processing
778 * doesn't cause havoc. Like in the driver load code we don't
779 * bother with the tiny race here where we might loose hotplug
780 * notifications.
781 * */
782 intel_hpd_init(dev_priv);
783 /* Config may have changed between suspend and resume */
784 drm_helper_hpd_irq_event(dev);
785
786 intel_opregion_init(dev);
787
788 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
789
790 mutex_lock(&dev_priv->modeset_restore_lock);
791 dev_priv->modeset_restore = MODESET_DONE;
792 mutex_unlock(&dev_priv->modeset_restore_lock);
793
794 intel_opregion_notify_adapter(dev, PCI_D0);
795
796 drm_kms_helper_poll_enable(dev);
797
798 enable_rpm_wakeref_asserts(dev_priv);
799
800 return 0;
801 }
802
803 static int i915_drm_resume_early(struct drm_device *dev)
804 {
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 int ret;
807
808 /*
809 * We have a resume ordering issue with the snd-hda driver also
810 * requiring our device to be power up. Due to the lack of a
811 * parent/child relationship we currently solve this with an early
812 * resume hook.
813 *
814 * FIXME: This should be solved with a special hdmi sink device or
815 * similar so that power domains can be employed.
816 */
817
818 /*
819 * Note that we need to set the power state explicitly, since we
820 * powered off the device during freeze and the PCI core won't power
821 * it back up for us during thaw. Powering off the device during
822 * freeze is not a hard requirement though, and during the
823 * suspend/resume phases the PCI core makes sure we get here with the
824 * device powered on. So in case we change our freeze logic and keep
825 * the device powered we can also remove the following set power state
826 * call.
827 */
828 ret = pci_set_power_state(dev->pdev, PCI_D0);
829 if (ret) {
830 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
831 goto out;
832 }
833
834 /*
835 * Note that pci_enable_device() first enables any parent bridge
836 * device and only then sets the power state for this device. The
837 * bridge enabling is a nop though, since bridge devices are resumed
838 * first. The order of enabling power and enabling the device is
839 * imposed by the PCI core as described above, so here we preserve the
840 * same order for the freeze/thaw phases.
841 *
842 * TODO: eventually we should remove pci_disable_device() /
843 * pci_enable_enable_device() from suspend/resume. Due to how they
844 * depend on the device enable refcount we can't anyway depend on them
845 * disabling/enabling the device.
846 */
847 if (pci_enable_device(dev->pdev)) {
848 ret = -EIO;
849 goto out;
850 }
851
852 pci_set_master(dev->pdev);
853
854 disable_rpm_wakeref_asserts(dev_priv);
855
856 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
857 ret = vlv_resume_prepare(dev_priv, false);
858 if (ret)
859 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
860 ret);
861
862 intel_uncore_early_sanitize(dev, true);
863
864 if (IS_BROXTON(dev))
865 ret = bxt_resume_prepare(dev_priv);
866 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
867 hsw_disable_pc8(dev_priv);
868
869 intel_uncore_sanitize(dev);
870
871 if (IS_BROXTON(dev_priv) ||
872 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
873 intel_power_domains_init_hw(dev_priv, true);
874
875 enable_rpm_wakeref_asserts(dev_priv);
876
877 out:
878 dev_priv->suspended_to_idle = false;
879
880 return ret;
881 }
882
883 int i915_resume_switcheroo(struct drm_device *dev)
884 {
885 int ret;
886
887 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
888 return 0;
889
890 ret = i915_drm_resume_early(dev);
891 if (ret)
892 return ret;
893
894 return i915_drm_resume(dev);
895 }
896
897 /**
898 * i915_reset - reset chip after a hang
899 * @dev: drm device to reset
900 *
901 * Reset the chip. Useful if a hang is detected. Returns zero on successful
902 * reset or otherwise an error code.
903 *
904 * Procedure is fairly simple:
905 * - reset the chip using the reset reg
906 * - re-init context state
907 * - re-init hardware status page
908 * - re-init ring buffer
909 * - re-init interrupt state
910 * - re-init display
911 */
912 int i915_reset(struct drm_device *dev)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915 struct i915_gpu_error *error = &dev_priv->gpu_error;
916 unsigned reset_counter;
917 int ret;
918
919 intel_reset_gt_powersave(dev);
920
921 mutex_lock(&dev->struct_mutex);
922
923 /* Clear any previous failed attempts at recovery. Time to try again. */
924 atomic_andnot(I915_WEDGED, &error->reset_counter);
925
926 /* Clear the reset-in-progress flag and increment the reset epoch. */
927 reset_counter = atomic_inc_return(&error->reset_counter);
928 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
929 ret = -EIO;
930 goto error;
931 }
932
933 i915_gem_reset(dev);
934
935 ret = intel_gpu_reset(dev, ALL_ENGINES);
936
937 /* Also reset the gpu hangman. */
938 if (error->stop_rings != 0) {
939 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
940 error->stop_rings = 0;
941 if (ret == -ENODEV) {
942 DRM_INFO("Reset not implemented, but ignoring "
943 "error for simulated gpu hangs\n");
944 ret = 0;
945 }
946 }
947
948 if (i915_stop_ring_allow_warn(dev_priv))
949 pr_notice("drm/i915: Resetting chip after gpu hang\n");
950
951 if (ret) {
952 if (ret != -ENODEV)
953 DRM_ERROR("Failed to reset chip: %i\n", ret);
954 else
955 DRM_DEBUG_DRIVER("GPU reset disabled\n");
956 goto error;
957 }
958
959 intel_overlay_reset(dev_priv);
960
961 /* Ok, now get things going again... */
962
963 /*
964 * Everything depends on having the GTT running, so we need to start
965 * there. Fortunately we don't need to do this unless we reset the
966 * chip at a PCI level.
967 *
968 * Next we need to restore the context, but we don't use those
969 * yet either...
970 *
971 * Ring buffer needs to be re-initialized in the KMS case, or if X
972 * was running at the time of the reset (i.e. we weren't VT
973 * switched away).
974 */
975 ret = i915_gem_init_hw(dev);
976 if (ret) {
977 DRM_ERROR("Failed hw init on reset %d\n", ret);
978 goto error;
979 }
980
981 mutex_unlock(&dev->struct_mutex);
982
983 /*
984 * rps/rc6 re-init is necessary to restore state lost after the
985 * reset and the re-install of gt irqs. Skip for ironlake per
986 * previous concerns that it doesn't respond well to some forms
987 * of re-init after reset.
988 */
989 if (INTEL_INFO(dev)->gen > 5)
990 intel_enable_gt_powersave(dev);
991
992 return 0;
993
994 error:
995 atomic_or(I915_WEDGED, &error->reset_counter);
996 mutex_unlock(&dev->struct_mutex);
997 return ret;
998 }
999
1000 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1001 {
1002 struct intel_device_info *intel_info =
1003 (struct intel_device_info *) ent->driver_data;
1004
1005 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
1006 DRM_INFO("This hardware requires preliminary hardware support.\n"
1007 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1008 return -ENODEV;
1009 }
1010
1011 /* Only bind to function 0 of the device. Early generations
1012 * used function 1 as a placeholder for multi-head. This causes
1013 * us confusion instead, especially on the systems where both
1014 * functions have the same PCI-ID!
1015 */
1016 if (PCI_FUNC(pdev->devfn))
1017 return -ENODEV;
1018
1019 /*
1020 * apple-gmux is needed on dual GPU MacBook Pro
1021 * to probe the panel if we're the inactive GPU.
1022 */
1023 if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1024 apple_gmux_present() && pdev != vga_default_device() &&
1025 !vga_switcheroo_handler_flags())
1026 return -EPROBE_DEFER;
1027
1028 return drm_get_pci_dev(pdev, ent, &driver);
1029 }
1030
1031 static void
1032 i915_pci_remove(struct pci_dev *pdev)
1033 {
1034 struct drm_device *dev = pci_get_drvdata(pdev);
1035
1036 drm_put_dev(dev);
1037 }
1038
1039 static int i915_pm_suspend(struct device *dev)
1040 {
1041 struct pci_dev *pdev = to_pci_dev(dev);
1042 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1043
1044 if (!drm_dev || !drm_dev->dev_private) {
1045 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1046 return -ENODEV;
1047 }
1048
1049 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1050 return 0;
1051
1052 return i915_drm_suspend(drm_dev);
1053 }
1054
1055 static int i915_pm_suspend_late(struct device *dev)
1056 {
1057 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1058
1059 /*
1060 * We have a suspend ordering issue with the snd-hda driver also
1061 * requiring our device to be power up. Due to the lack of a
1062 * parent/child relationship we currently solve this with an late
1063 * suspend hook.
1064 *
1065 * FIXME: This should be solved with a special hdmi sink device or
1066 * similar so that power domains can be employed.
1067 */
1068 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1069 return 0;
1070
1071 return i915_drm_suspend_late(drm_dev, false);
1072 }
1073
1074 static int i915_pm_poweroff_late(struct device *dev)
1075 {
1076 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1077
1078 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1079 return 0;
1080
1081 return i915_drm_suspend_late(drm_dev, true);
1082 }
1083
1084 static int i915_pm_resume_early(struct device *dev)
1085 {
1086 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1087
1088 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1089 return 0;
1090
1091 return i915_drm_resume_early(drm_dev);
1092 }
1093
1094 static int i915_pm_resume(struct device *dev)
1095 {
1096 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1097
1098 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1099 return 0;
1100
1101 return i915_drm_resume(drm_dev);
1102 }
1103
1104 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1105 {
1106 hsw_enable_pc8(dev_priv);
1107
1108 return 0;
1109 }
1110
1111 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1112 {
1113 bxt_display_core_uninit(dev_priv);
1114 bxt_enable_dc9(dev_priv);
1115
1116 return 0;
1117 }
1118
1119 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1120 {
1121 bxt_disable_dc9(dev_priv);
1122 bxt_display_core_init(dev_priv, true);
1123
1124 return 0;
1125 }
1126
1127 /*
1128 * Save all Gunit registers that may be lost after a D3 and a subsequent
1129 * S0i[R123] transition. The list of registers needing a save/restore is
1130 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1131 * registers in the following way:
1132 * - Driver: saved/restored by the driver
1133 * - Punit : saved/restored by the Punit firmware
1134 * - No, w/o marking: no need to save/restore, since the register is R/O or
1135 * used internally by the HW in a way that doesn't depend
1136 * keeping the content across a suspend/resume.
1137 * - Debug : used for debugging
1138 *
1139 * We save/restore all registers marked with 'Driver', with the following
1140 * exceptions:
1141 * - Registers out of use, including also registers marked with 'Debug'.
1142 * These have no effect on the driver's operation, so we don't save/restore
1143 * them to reduce the overhead.
1144 * - Registers that are fully setup by an initialization function called from
1145 * the resume path. For example many clock gating and RPS/RC6 registers.
1146 * - Registers that provide the right functionality with their reset defaults.
1147 *
1148 * TODO: Except for registers that based on the above 3 criteria can be safely
1149 * ignored, we save/restore all others, practically treating the HW context as
1150 * a black-box for the driver. Further investigation is needed to reduce the
1151 * saved/restored registers even further, by following the same 3 criteria.
1152 */
1153 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1154 {
1155 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1156 int i;
1157
1158 /* GAM 0x4000-0x4770 */
1159 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1160 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1161 s->arb_mode = I915_READ(ARB_MODE);
1162 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1163 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1164
1165 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1166 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1167
1168 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1169 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1170
1171 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1172 s->ecochk = I915_READ(GAM_ECOCHK);
1173 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1174 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1175
1176 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1177
1178 /* MBC 0x9024-0x91D0, 0x8500 */
1179 s->g3dctl = I915_READ(VLV_G3DCTL);
1180 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1181 s->mbctl = I915_READ(GEN6_MBCTL);
1182
1183 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1184 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1185 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1186 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1187 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1188 s->rstctl = I915_READ(GEN6_RSTCTL);
1189 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1190
1191 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1192 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1193 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1194 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1195 s->ecobus = I915_READ(ECOBUS);
1196 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1197 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1198 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1199 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1200 s->rcedata = I915_READ(VLV_RCEDATA);
1201 s->spare2gh = I915_READ(VLV_SPAREG2H);
1202
1203 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1204 s->gt_imr = I915_READ(GTIMR);
1205 s->gt_ier = I915_READ(GTIER);
1206 s->pm_imr = I915_READ(GEN6_PMIMR);
1207 s->pm_ier = I915_READ(GEN6_PMIER);
1208
1209 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1210 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1211
1212 /* GT SA CZ domain, 0x100000-0x138124 */
1213 s->tilectl = I915_READ(TILECTL);
1214 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1215 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1216 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1217 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1218
1219 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1220 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1221 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1222 s->pcbr = I915_READ(VLV_PCBR);
1223 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1224
1225 /*
1226 * Not saving any of:
1227 * DFT, 0x9800-0x9EC0
1228 * SARB, 0xB000-0xB1FC
1229 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1230 * PCI CFG
1231 */
1232 }
1233
1234 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1235 {
1236 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1237 u32 val;
1238 int i;
1239
1240 /* GAM 0x4000-0x4770 */
1241 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1242 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1243 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1244 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1245 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1246
1247 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1248 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1249
1250 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1251 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1252
1253 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1254 I915_WRITE(GAM_ECOCHK, s->ecochk);
1255 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1256 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1257
1258 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1259
1260 /* MBC 0x9024-0x91D0, 0x8500 */
1261 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1262 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1263 I915_WRITE(GEN6_MBCTL, s->mbctl);
1264
1265 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1266 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1267 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1268 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1269 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1270 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1271 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1272
1273 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1274 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1275 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1276 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1277 I915_WRITE(ECOBUS, s->ecobus);
1278 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1279 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1280 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1281 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1282 I915_WRITE(VLV_RCEDATA, s->rcedata);
1283 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1284
1285 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1286 I915_WRITE(GTIMR, s->gt_imr);
1287 I915_WRITE(GTIER, s->gt_ier);
1288 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1289 I915_WRITE(GEN6_PMIER, s->pm_ier);
1290
1291 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1292 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1293
1294 /* GT SA CZ domain, 0x100000-0x138124 */
1295 I915_WRITE(TILECTL, s->tilectl);
1296 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1297 /*
1298 * Preserve the GT allow wake and GFX force clock bit, they are not
1299 * be restored, as they are used to control the s0ix suspend/resume
1300 * sequence by the caller.
1301 */
1302 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1303 val &= VLV_GTLC_ALLOWWAKEREQ;
1304 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1305 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1306
1307 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1308 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1309 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1310 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1311
1312 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1313
1314 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1315 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1316 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1317 I915_WRITE(VLV_PCBR, s->pcbr);
1318 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1319 }
1320
1321 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1322 {
1323 u32 val;
1324 int err;
1325
1326 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1327
1328 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1329 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1330 if (force_on)
1331 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1332 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1333
1334 if (!force_on)
1335 return 0;
1336
1337 err = wait_for(COND, 20);
1338 if (err)
1339 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1340 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1341
1342 return err;
1343 #undef COND
1344 }
1345
1346 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1347 {
1348 u32 val;
1349 int err = 0;
1350
1351 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1352 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1353 if (allow)
1354 val |= VLV_GTLC_ALLOWWAKEREQ;
1355 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1356 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1357
1358 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1359 allow)
1360 err = wait_for(COND, 1);
1361 if (err)
1362 DRM_ERROR("timeout disabling GT waking\n");
1363 return err;
1364 #undef COND
1365 }
1366
1367 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1368 bool wait_for_on)
1369 {
1370 u32 mask;
1371 u32 val;
1372 int err;
1373
1374 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1375 val = wait_for_on ? mask : 0;
1376 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1377 if (COND)
1378 return 0;
1379
1380 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1381 onoff(wait_for_on),
1382 I915_READ(VLV_GTLC_PW_STATUS));
1383
1384 /*
1385 * RC6 transitioning can be delayed up to 2 msec (see
1386 * valleyview_enable_rps), use 3 msec for safety.
1387 */
1388 err = wait_for(COND, 3);
1389 if (err)
1390 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1391 onoff(wait_for_on));
1392
1393 return err;
1394 #undef COND
1395 }
1396
1397 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1398 {
1399 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1400 return;
1401
1402 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1403 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1404 }
1405
1406 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1407 {
1408 u32 mask;
1409 int err;
1410
1411 /*
1412 * Bspec defines the following GT well on flags as debug only, so
1413 * don't treat them as hard failures.
1414 */
1415 (void)vlv_wait_for_gt_wells(dev_priv, false);
1416
1417 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1418 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1419
1420 vlv_check_no_gt_access(dev_priv);
1421
1422 err = vlv_force_gfx_clock(dev_priv, true);
1423 if (err)
1424 goto err1;
1425
1426 err = vlv_allow_gt_wake(dev_priv, false);
1427 if (err)
1428 goto err2;
1429
1430 if (!IS_CHERRYVIEW(dev_priv))
1431 vlv_save_gunit_s0ix_state(dev_priv);
1432
1433 err = vlv_force_gfx_clock(dev_priv, false);
1434 if (err)
1435 goto err2;
1436
1437 return 0;
1438
1439 err2:
1440 /* For safety always re-enable waking and disable gfx clock forcing */
1441 vlv_allow_gt_wake(dev_priv, true);
1442 err1:
1443 vlv_force_gfx_clock(dev_priv, false);
1444
1445 return err;
1446 }
1447
1448 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1449 bool rpm_resume)
1450 {
1451 struct drm_device *dev = dev_priv->dev;
1452 int err;
1453 int ret;
1454
1455 /*
1456 * If any of the steps fail just try to continue, that's the best we
1457 * can do at this point. Return the first error code (which will also
1458 * leave RPM permanently disabled).
1459 */
1460 ret = vlv_force_gfx_clock(dev_priv, true);
1461
1462 if (!IS_CHERRYVIEW(dev_priv))
1463 vlv_restore_gunit_s0ix_state(dev_priv);
1464
1465 err = vlv_allow_gt_wake(dev_priv, true);
1466 if (!ret)
1467 ret = err;
1468
1469 err = vlv_force_gfx_clock(dev_priv, false);
1470 if (!ret)
1471 ret = err;
1472
1473 vlv_check_no_gt_access(dev_priv);
1474
1475 if (rpm_resume) {
1476 intel_init_clock_gating(dev);
1477 i915_gem_restore_fences(dev);
1478 }
1479
1480 return ret;
1481 }
1482
1483 static int intel_runtime_suspend(struct device *device)
1484 {
1485 struct pci_dev *pdev = to_pci_dev(device);
1486 struct drm_device *dev = pci_get_drvdata(pdev);
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 int ret;
1489
1490 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1491 return -ENODEV;
1492
1493 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1494 return -ENODEV;
1495
1496 DRM_DEBUG_KMS("Suspending device\n");
1497
1498 /*
1499 * We could deadlock here in case another thread holding struct_mutex
1500 * calls RPM suspend concurrently, since the RPM suspend will wait
1501 * first for this RPM suspend to finish. In this case the concurrent
1502 * RPM resume will be followed by its RPM suspend counterpart. Still
1503 * for consistency return -EAGAIN, which will reschedule this suspend.
1504 */
1505 if (!mutex_trylock(&dev->struct_mutex)) {
1506 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1507 /*
1508 * Bump the expiration timestamp, otherwise the suspend won't
1509 * be rescheduled.
1510 */
1511 pm_runtime_mark_last_busy(device);
1512
1513 return -EAGAIN;
1514 }
1515
1516 disable_rpm_wakeref_asserts(dev_priv);
1517
1518 /*
1519 * We are safe here against re-faults, since the fault handler takes
1520 * an RPM reference.
1521 */
1522 i915_gem_release_all_mmaps(dev_priv);
1523 mutex_unlock(&dev->struct_mutex);
1524
1525 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1526
1527 intel_guc_suspend(dev);
1528
1529 intel_suspend_gt_powersave(dev);
1530 intel_runtime_pm_disable_interrupts(dev_priv);
1531
1532 ret = intel_suspend_complete(dev_priv);
1533 if (ret) {
1534 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1535 intel_runtime_pm_enable_interrupts(dev_priv);
1536
1537 enable_rpm_wakeref_asserts(dev_priv);
1538
1539 return ret;
1540 }
1541
1542 intel_uncore_forcewake_reset(dev, false);
1543
1544 enable_rpm_wakeref_asserts(dev_priv);
1545 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1546
1547 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1548 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1549
1550 dev_priv->pm.suspended = true;
1551
1552 /*
1553 * FIXME: We really should find a document that references the arguments
1554 * used below!
1555 */
1556 if (IS_BROADWELL(dev)) {
1557 /*
1558 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1559 * being detected, and the call we do at intel_runtime_resume()
1560 * won't be able to restore them. Since PCI_D3hot matches the
1561 * actual specification and appears to be working, use it.
1562 */
1563 intel_opregion_notify_adapter(dev, PCI_D3hot);
1564 } else {
1565 /*
1566 * current versions of firmware which depend on this opregion
1567 * notification have repurposed the D1 definition to mean
1568 * "runtime suspended" vs. what you would normally expect (D3)
1569 * to distinguish it from notifications that might be sent via
1570 * the suspend path.
1571 */
1572 intel_opregion_notify_adapter(dev, PCI_D1);
1573 }
1574
1575 assert_forcewakes_inactive(dev_priv);
1576
1577 DRM_DEBUG_KMS("Device suspended\n");
1578 return 0;
1579 }
1580
1581 static int intel_runtime_resume(struct device *device)
1582 {
1583 struct pci_dev *pdev = to_pci_dev(device);
1584 struct drm_device *dev = pci_get_drvdata(pdev);
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 int ret = 0;
1587
1588 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1589 return -ENODEV;
1590
1591 DRM_DEBUG_KMS("Resuming device\n");
1592
1593 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1594 disable_rpm_wakeref_asserts(dev_priv);
1595
1596 intel_opregion_notify_adapter(dev, PCI_D0);
1597 dev_priv->pm.suspended = false;
1598 if (intel_uncore_unclaimed_mmio(dev_priv))
1599 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1600
1601 intel_guc_resume(dev);
1602
1603 if (IS_GEN6(dev_priv))
1604 intel_init_pch_refclk(dev);
1605
1606 if (IS_BROXTON(dev))
1607 ret = bxt_resume_prepare(dev_priv);
1608 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1609 hsw_disable_pc8(dev_priv);
1610 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1611 ret = vlv_resume_prepare(dev_priv, true);
1612
1613 /*
1614 * No point of rolling back things in case of an error, as the best
1615 * we can do is to hope that things will still work (and disable RPM).
1616 */
1617 i915_gem_init_swizzling(dev);
1618 gen6_update_ring_freq(dev);
1619
1620 intel_runtime_pm_enable_interrupts(dev_priv);
1621
1622 /*
1623 * On VLV/CHV display interrupts are part of the display
1624 * power well, so hpd is reinitialized from there. For
1625 * everyone else do it here.
1626 */
1627 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1628 intel_hpd_init(dev_priv);
1629
1630 intel_enable_gt_powersave(dev);
1631
1632 enable_rpm_wakeref_asserts(dev_priv);
1633
1634 if (ret)
1635 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1636 else
1637 DRM_DEBUG_KMS("Device resumed\n");
1638
1639 return ret;
1640 }
1641
1642 /*
1643 * This function implements common functionality of runtime and system
1644 * suspend sequence.
1645 */
1646 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1647 {
1648 int ret;
1649
1650 if (IS_BROXTON(dev_priv))
1651 ret = bxt_suspend_complete(dev_priv);
1652 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1653 ret = hsw_suspend_complete(dev_priv);
1654 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1655 ret = vlv_suspend_complete(dev_priv);
1656 else
1657 ret = 0;
1658
1659 return ret;
1660 }
1661
1662 static const struct dev_pm_ops i915_pm_ops = {
1663 /*
1664 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1665 * PMSG_RESUME]
1666 */
1667 .suspend = i915_pm_suspend,
1668 .suspend_late = i915_pm_suspend_late,
1669 .resume_early = i915_pm_resume_early,
1670 .resume = i915_pm_resume,
1671
1672 /*
1673 * S4 event handlers
1674 * @freeze, @freeze_late : called (1) before creating the
1675 * hibernation image [PMSG_FREEZE] and
1676 * (2) after rebooting, before restoring
1677 * the image [PMSG_QUIESCE]
1678 * @thaw, @thaw_early : called (1) after creating the hibernation
1679 * image, before writing it [PMSG_THAW]
1680 * and (2) after failing to create or
1681 * restore the image [PMSG_RECOVER]
1682 * @poweroff, @poweroff_late: called after writing the hibernation
1683 * image, before rebooting [PMSG_HIBERNATE]
1684 * @restore, @restore_early : called after rebooting and restoring the
1685 * hibernation image [PMSG_RESTORE]
1686 */
1687 .freeze = i915_pm_suspend,
1688 .freeze_late = i915_pm_suspend_late,
1689 .thaw_early = i915_pm_resume_early,
1690 .thaw = i915_pm_resume,
1691 .poweroff = i915_pm_suspend,
1692 .poweroff_late = i915_pm_poweroff_late,
1693 .restore_early = i915_pm_resume_early,
1694 .restore = i915_pm_resume,
1695
1696 /* S0ix (via runtime suspend) event handlers */
1697 .runtime_suspend = intel_runtime_suspend,
1698 .runtime_resume = intel_runtime_resume,
1699 };
1700
1701 static const struct vm_operations_struct i915_gem_vm_ops = {
1702 .fault = i915_gem_fault,
1703 .open = drm_gem_vm_open,
1704 .close = drm_gem_vm_close,
1705 };
1706
1707 static const struct file_operations i915_driver_fops = {
1708 .owner = THIS_MODULE,
1709 .open = drm_open,
1710 .release = drm_release,
1711 .unlocked_ioctl = drm_ioctl,
1712 .mmap = drm_gem_mmap,
1713 .poll = drm_poll,
1714 .read = drm_read,
1715 #ifdef CONFIG_COMPAT
1716 .compat_ioctl = i915_compat_ioctl,
1717 #endif
1718 .llseek = noop_llseek,
1719 };
1720
1721 static struct drm_driver driver = {
1722 /* Don't use MTRRs here; the Xserver or userspace app should
1723 * deal with them for Intel hardware.
1724 */
1725 .driver_features =
1726 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1727 DRIVER_RENDER | DRIVER_MODESET,
1728 .load = i915_driver_load,
1729 .unload = i915_driver_unload,
1730 .open = i915_driver_open,
1731 .lastclose = i915_driver_lastclose,
1732 .preclose = i915_driver_preclose,
1733 .postclose = i915_driver_postclose,
1734 .set_busid = drm_pci_set_busid,
1735
1736 #if defined(CONFIG_DEBUG_FS)
1737 .debugfs_init = i915_debugfs_init,
1738 .debugfs_cleanup = i915_debugfs_cleanup,
1739 #endif
1740 .gem_free_object = i915_gem_free_object,
1741 .gem_vm_ops = &i915_gem_vm_ops,
1742
1743 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1744 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1745 .gem_prime_export = i915_gem_prime_export,
1746 .gem_prime_import = i915_gem_prime_import,
1747
1748 .dumb_create = i915_gem_dumb_create,
1749 .dumb_map_offset = i915_gem_mmap_gtt,
1750 .dumb_destroy = drm_gem_dumb_destroy,
1751 .ioctls = i915_ioctls,
1752 .fops = &i915_driver_fops,
1753 .name = DRIVER_NAME,
1754 .desc = DRIVER_DESC,
1755 .date = DRIVER_DATE,
1756 .major = DRIVER_MAJOR,
1757 .minor = DRIVER_MINOR,
1758 .patchlevel = DRIVER_PATCHLEVEL,
1759 };
1760
1761 static struct pci_driver i915_pci_driver = {
1762 .name = DRIVER_NAME,
1763 .id_table = pciidlist,
1764 .probe = i915_pci_probe,
1765 .remove = i915_pci_remove,
1766 .driver.pm = &i915_pm_ops,
1767 };
1768
1769 static int __init i915_init(void)
1770 {
1771 driver.num_ioctls = i915_max_ioctl;
1772
1773 /*
1774 * Enable KMS by default, unless explicitly overriden by
1775 * either the i915.modeset prarameter or by the
1776 * vga_text_mode_force boot option.
1777 */
1778
1779 if (i915.modeset == 0)
1780 driver.driver_features &= ~DRIVER_MODESET;
1781
1782 #ifdef CONFIG_VGA_CONSOLE
1783 if (vgacon_text_force() && i915.modeset == -1)
1784 driver.driver_features &= ~DRIVER_MODESET;
1785 #endif
1786
1787 if (!(driver.driver_features & DRIVER_MODESET)) {
1788 /* Silently fail loading to not upset userspace. */
1789 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1790 return 0;
1791 }
1792
1793 if (i915.nuclear_pageflip)
1794 driver.driver_features |= DRIVER_ATOMIC;
1795
1796 return drm_pci_init(&driver, &i915_pci_driver);
1797 }
1798
1799 static void __exit i915_exit(void)
1800 {
1801 if (!(driver.driver_features & DRIVER_MODESET))
1802 return; /* Never loaded a driver. */
1803
1804 drm_pci_exit(&driver, &i915_pci_driver);
1805 }
1806
1807 module_init(i915_init);
1808 module_exit(i915_exit);
1809
1810 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1811 MODULE_AUTHOR("Intel Corporation");
1812
1813 MODULE_DESCRIPTION(DRIVER_DESC);
1814 MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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