1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
40 static int i915_modeset
= -1;
41 module_param_named(modeset
, i915_modeset
, int, 0400);
43 unsigned int i915_fbpercrtc
= 0;
44 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
46 unsigned int i915_powersave
= 1;
47 module_param_named(powersave
, i915_powersave
, int, 0600);
49 unsigned int i915_lvds_downclock
= 0;
50 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
52 static struct drm_driver driver
;
53 extern int intel_agp_enabled
;
55 #define INTEL_VGA_DEVICE(id, info) { \
56 .class = PCI_CLASS_DISPLAY_VGA << 8, \
57 .class_mask = 0xffff00, \
60 .subvendor = PCI_ANY_ID, \
61 .subdevice = PCI_ANY_ID, \
62 .driver_data = (unsigned long) info }
64 static const struct intel_device_info intel_i830_info
= {
65 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1,
66 .has_overlay
= 1, .overlay_needs_physical
= 1,
69 static const struct intel_device_info intel_845g_info
= {
71 .has_overlay
= 1, .overlay_needs_physical
= 1,
74 static const struct intel_device_info intel_i85x_info
= {
75 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1,
76 .cursor_needs_physical
= 1,
77 .has_overlay
= 1, .overlay_needs_physical
= 1,
80 static const struct intel_device_info intel_i865g_info
= {
82 .has_overlay
= 1, .overlay_needs_physical
= 1,
85 static const struct intel_device_info intel_i915g_info
= {
86 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1,
87 .has_overlay
= 1, .overlay_needs_physical
= 1,
89 static const struct intel_device_info intel_i915gm_info
= {
90 .gen
= 3, .is_mobile
= 1,
91 .cursor_needs_physical
= 1,
92 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 static const struct intel_device_info intel_i945g_info
= {
96 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1,
97 .has_overlay
= 1, .overlay_needs_physical
= 1,
99 static const struct intel_device_info intel_i945gm_info
= {
100 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1,
101 .has_hotplug
= 1, .cursor_needs_physical
= 1,
102 .has_overlay
= 1, .overlay_needs_physical
= 1,
106 static const struct intel_device_info intel_i965g_info
= {
107 .gen
= 4, .is_broadwater
= 1,
112 static const struct intel_device_info intel_i965gm_info
= {
113 .gen
= 4, .is_crestline
= 1,
114 .is_mobile
= 1, .has_fbc
= 1, .has_rc6
= 1, .has_hotplug
= 1,
119 static const struct intel_device_info intel_g33_info
= {
120 .gen
= 3, .is_g33
= 1,
121 .need_gfx_hws
= 1, .has_hotplug
= 1,
125 static const struct intel_device_info intel_g45_info
= {
126 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1,
127 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
131 static const struct intel_device_info intel_gm45_info
= {
132 .gen
= 4, .is_g4x
= 1,
133 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1, .has_rc6
= 1,
134 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
139 static const struct intel_device_info intel_pineview_info
= {
140 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1,
141 .need_gfx_hws
= 1, .has_hotplug
= 1,
145 static const struct intel_device_info intel_ironlake_d_info
= {
147 .need_gfx_hws
= 1, .has_pipe_cxsr
= 1, .has_hotplug
= 1,
151 static const struct intel_device_info intel_ironlake_m_info
= {
152 .gen
= 5, .is_mobile
= 1,
153 .need_gfx_hws
= 1, .has_rc6
= 1, .has_hotplug
= 1,
154 .has_fbc
= 0, /* disabled due to buggy hardware */
158 static const struct intel_device_info intel_sandybridge_d_info
= {
160 .need_gfx_hws
= 1, .has_hotplug
= 1,
165 static const struct intel_device_info intel_sandybridge_m_info
= {
166 .gen
= 6, .is_mobile
= 1,
167 .need_gfx_hws
= 1, .has_hotplug
= 1,
172 static const struct pci_device_id pciidlist
[] = { /* aka */
173 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
174 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
175 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
176 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
177 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
178 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
179 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
180 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
181 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
182 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
183 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
184 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
185 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
186 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
187 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
188 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
189 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
190 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
191 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
192 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
193 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
194 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
195 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
196 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
197 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
198 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
199 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
200 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
201 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
202 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
203 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
204 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
205 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
206 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
207 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
208 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
209 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
210 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
214 #if defined(CONFIG_DRM_I915_KMS)
215 MODULE_DEVICE_TABLE(pci
, pciidlist
);
218 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
219 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
221 void intel_detect_pch (struct drm_device
*dev
)
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
227 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
228 * make graphics device passthrough work easy for VMM, that only
229 * need to expose ISA bridge to let driver know the real hardware
230 * underneath. This is a requirement from virtualization team.
232 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
234 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
236 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
238 if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
239 dev_priv
->pch_type
= PCH_CPT
;
240 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
247 static int i915_drm_freeze(struct drm_device
*dev
)
249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
251 pci_save_state(dev
->pdev
);
253 /* If KMS is active, we do the leavevt stuff here */
254 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
255 int error
= i915_gem_idle(dev
);
257 dev_err(&dev
->pdev
->dev
,
258 "GEM idle failed, resume might fail\n");
261 drm_irq_uninstall(dev
);
264 i915_save_state(dev
);
266 intel_opregion_fini(dev
);
268 /* Modeset on resume, not lid events */
269 dev_priv
->modeset_on_lid
= 0;
274 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
278 if (!dev
|| !dev
->dev_private
) {
279 DRM_ERROR("dev: %p\n", dev
);
280 DRM_ERROR("DRM not initialized, aborting suspend.\n");
284 if (state
.event
== PM_EVENT_PRETHAW
)
287 drm_kms_helper_poll_disable(dev
);
289 error
= i915_drm_freeze(dev
);
293 if (state
.event
== PM_EVENT_SUSPEND
) {
294 /* Shut down the device */
295 pci_disable_device(dev
->pdev
);
296 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
302 static int i915_drm_thaw(struct drm_device
*dev
)
304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
307 i915_restore_state(dev
);
308 intel_opregion_setup(dev
);
310 /* KMS EnterVT equivalent */
311 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
312 mutex_lock(&dev
->struct_mutex
);
313 dev_priv
->mm
.suspended
= 0;
315 error
= i915_gem_init_ringbuffer(dev
);
316 mutex_unlock(&dev
->struct_mutex
);
318 drm_irq_install(dev
);
320 /* Resume the modeset for every activated CRTC */
321 drm_helper_resume_force_mode(dev
);
324 intel_opregion_init(dev
);
326 dev_priv
->modeset_on_lid
= 0;
331 int i915_resume(struct drm_device
*dev
)
335 if (pci_enable_device(dev
->pdev
))
338 pci_set_master(dev
->pdev
);
340 ret
= i915_drm_thaw(dev
);
344 drm_kms_helper_poll_enable(dev
);
348 static int i8xx_do_reset(struct drm_device
*dev
, u8 flags
)
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
355 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
356 POSTING_READ(D_STATE
);
358 if (IS_I830(dev
) || IS_845G(dev
)) {
359 I915_WRITE(DEBUG_RESET_I830
,
360 DEBUG_RESET_DISPLAY
|
363 POSTING_READ(DEBUG_RESET_I830
);
366 I915_WRITE(DEBUG_RESET_I830
, 0);
367 POSTING_READ(DEBUG_RESET_I830
);
372 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
373 POSTING_READ(D_STATE
);
378 static int i965_reset_complete(struct drm_device
*dev
)
381 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
385 static int i965_do_reset(struct drm_device
*dev
, u8 flags
)
390 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
391 * well as the reset bit (GR/bit 0). Setting the GR bit
392 * triggers the reset; when done, the hardware will clear it.
394 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
395 pci_write_config_byte(dev
->pdev
, I965_GDRST
, gdrst
| flags
| 0x1);
397 return wait_for(i965_reset_complete(dev
), 500);
400 static int ironlake_do_reset(struct drm_device
*dev
, u8 flags
)
402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
403 u32 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
404 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
, gdrst
| flags
| 0x1);
405 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
409 * i965_reset - reset chip after a hang
410 * @dev: drm device to reset
411 * @flags: reset domains
413 * Reset the chip. Useful if a hang is detected. Returns zero on successful
414 * reset or otherwise an error code.
416 * Procedure is fairly simple:
417 * - reset the chip using the reset reg
418 * - re-init context state
419 * - re-init hardware status page
420 * - re-init ring buffer
421 * - re-init interrupt state
424 int i915_reset(struct drm_device
*dev
, u8 flags
)
426 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
428 * We really should only reset the display subsystem if we actually
431 bool need_display
= true;
434 mutex_lock(&dev
->struct_mutex
);
439 if (get_seconds() - dev_priv
->last_gpu_reset
< 5) {
440 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
441 } else switch (INTEL_INFO(dev
)->gen
) {
443 ret
= ironlake_do_reset(dev
, flags
);
446 ret
= i965_do_reset(dev
, flags
);
449 ret
= i8xx_do_reset(dev
, flags
);
452 dev_priv
->last_gpu_reset
= get_seconds();
454 DRM_ERROR("Failed to reset chip.\n");
455 mutex_unlock(&dev
->struct_mutex
);
459 /* Ok, now get things going again... */
462 * Everything depends on having the GTT running, so we need to start
463 * there. Fortunately we don't need to do this unless we reset the
464 * chip at a PCI level.
466 * Next we need to restore the context, but we don't use those
469 * Ring buffer needs to be re-initialized in the KMS case, or if X
470 * was running at the time of the reset (i.e. we weren't VT
473 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
474 !dev_priv
->mm
.suspended
) {
475 struct intel_ring_buffer
*ring
= &dev_priv
->render_ring
;
476 dev_priv
->mm
.suspended
= 0;
477 ring
->init(dev
, ring
);
478 mutex_unlock(&dev
->struct_mutex
);
479 drm_irq_uninstall(dev
);
480 drm_irq_install(dev
);
481 mutex_lock(&dev
->struct_mutex
);
484 mutex_unlock(&dev
->struct_mutex
);
487 * Perform a full modeset as on later generations, e.g. Ironlake, we may
488 * need to retrain the display link and cannot just restore the register
492 mutex_lock(&dev
->mode_config
.mutex
);
493 drm_helper_resume_force_mode(dev
);
494 mutex_unlock(&dev
->mode_config
.mutex
);
502 i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
504 return drm_get_pci_dev(pdev
, ent
, &driver
);
508 i915_pci_remove(struct pci_dev
*pdev
)
510 struct drm_device
*dev
= pci_get_drvdata(pdev
);
515 static int i915_pm_suspend(struct device
*dev
)
517 struct pci_dev
*pdev
= to_pci_dev(dev
);
518 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
521 if (!drm_dev
|| !drm_dev
->dev_private
) {
522 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
526 error
= i915_drm_freeze(drm_dev
);
530 pci_disable_device(pdev
);
531 pci_set_power_state(pdev
, PCI_D3hot
);
536 static int i915_pm_resume(struct device
*dev
)
538 struct pci_dev
*pdev
= to_pci_dev(dev
);
539 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
541 return i915_resume(drm_dev
);
544 static int i915_pm_freeze(struct device
*dev
)
546 struct pci_dev
*pdev
= to_pci_dev(dev
);
547 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
549 if (!drm_dev
|| !drm_dev
->dev_private
) {
550 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
554 return i915_drm_freeze(drm_dev
);
557 static int i915_pm_thaw(struct device
*dev
)
559 struct pci_dev
*pdev
= to_pci_dev(dev
);
560 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
562 return i915_drm_thaw(drm_dev
);
565 static int i915_pm_poweroff(struct device
*dev
)
567 struct pci_dev
*pdev
= to_pci_dev(dev
);
568 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
570 return i915_drm_freeze(drm_dev
);
573 static const struct dev_pm_ops i915_pm_ops
= {
574 .suspend
= i915_pm_suspend
,
575 .resume
= i915_pm_resume
,
576 .freeze
= i915_pm_freeze
,
577 .thaw
= i915_pm_thaw
,
578 .poweroff
= i915_pm_poweroff
,
579 .restore
= i915_pm_resume
,
582 static struct vm_operations_struct i915_gem_vm_ops
= {
583 .fault
= i915_gem_fault
,
584 .open
= drm_gem_vm_open
,
585 .close
= drm_gem_vm_close
,
588 static struct drm_driver driver
= {
589 /* don't use mtrr's here, the Xserver or user space app should
590 * deal with them for intel hardware.
593 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
594 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
,
595 .load
= i915_driver_load
,
596 .unload
= i915_driver_unload
,
597 .open
= i915_driver_open
,
598 .lastclose
= i915_driver_lastclose
,
599 .preclose
= i915_driver_preclose
,
600 .postclose
= i915_driver_postclose
,
602 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
603 .suspend
= i915_suspend
,
604 .resume
= i915_resume
,
606 .device_is_agp
= i915_driver_device_is_agp
,
607 .enable_vblank
= i915_enable_vblank
,
608 .disable_vblank
= i915_disable_vblank
,
609 .irq_preinstall
= i915_driver_irq_preinstall
,
610 .irq_postinstall
= i915_driver_irq_postinstall
,
611 .irq_uninstall
= i915_driver_irq_uninstall
,
612 .irq_handler
= i915_driver_irq_handler
,
613 .reclaim_buffers
= drm_core_reclaim_buffers
,
614 .master_create
= i915_master_create
,
615 .master_destroy
= i915_master_destroy
,
616 #if defined(CONFIG_DEBUG_FS)
617 .debugfs_init
= i915_debugfs_init
,
618 .debugfs_cleanup
= i915_debugfs_cleanup
,
620 .gem_init_object
= i915_gem_init_object
,
621 .gem_free_object
= i915_gem_free_object
,
622 .gem_vm_ops
= &i915_gem_vm_ops
,
623 .ioctls
= i915_ioctls
,
625 .owner
= THIS_MODULE
,
627 .release
= drm_release
,
628 .unlocked_ioctl
= drm_ioctl
,
629 .mmap
= drm_gem_mmap
,
631 .fasync
= drm_fasync
,
634 .compat_ioctl
= i915_compat_ioctl
,
636 .llseek
= noop_llseek
,
641 .id_table
= pciidlist
,
642 .probe
= i915_pci_probe
,
643 .remove
= i915_pci_remove
,
644 .driver
.pm
= &i915_pm_ops
,
650 .major
= DRIVER_MAJOR
,
651 .minor
= DRIVER_MINOR
,
652 .patchlevel
= DRIVER_PATCHLEVEL
,
655 static int __init
i915_init(void)
657 if (!intel_agp_enabled
) {
658 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
662 driver
.num_ioctls
= i915_max_ioctl
;
664 i915_gem_shrinker_init();
667 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
668 * explicitly disabled with the module pararmeter.
670 * Otherwise, just follow the parameter (defaulting to off).
672 * Allow optional vga_text_mode_force boot option to override
673 * the default behavior.
675 #if defined(CONFIG_DRM_I915_KMS)
676 if (i915_modeset
!= 0)
677 driver
.driver_features
|= DRIVER_MODESET
;
679 if (i915_modeset
== 1)
680 driver
.driver_features
|= DRIVER_MODESET
;
682 #ifdef CONFIG_VGA_CONSOLE
683 if (vgacon_text_force() && i915_modeset
== -1)
684 driver
.driver_features
&= ~DRIVER_MODESET
;
687 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
688 driver
.suspend
= i915_suspend
;
689 driver
.resume
= i915_resume
;
692 return drm_init(&driver
);
695 static void __exit
i915_exit(void)
697 i915_gem_shrinker_exit();
701 module_init(i915_init
);
702 module_exit(i915_exit
);
704 MODULE_AUTHOR(DRIVER_AUTHOR
);
705 MODULE_DESCRIPTION(DRIVER_DESC
);
706 MODULE_LICENSE("GPL and additional rights");