1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/acpi.h>
31 #include <linux/device.h>
32 #include <linux/oom.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pnp.h>
38 #include <linux/slab.h>
39 #include <linux/vgaarb.h>
40 #include <linux/vga_switcheroo.h>
42 #include <acpi/video.h>
45 #include <drm/drm_crtc_helper.h>
46 #include <drm/i915_drm.h>
49 #include "i915_trace.h"
50 #include "i915_vgpu.h"
51 #include "intel_drv.h"
53 static struct drm_driver driver
;
55 static unsigned int i915_load_fail_count
;
57 bool __i915_inject_load_failure(const char *func
, int line
)
59 if (i915_load_fail_count
>= i915
.inject_load_failure
)
62 if (++i915_load_fail_count
== i915
.inject_load_failure
) {
63 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
64 i915
.inject_load_failure
, func
, line
);
71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
73 "providing the dmesg log by booting with drm.debug=0xf"
76 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
79 static bool shown_bug_once
;
80 struct device
*dev
= dev_priv
->drm
.dev
;
81 bool is_error
= level
[1] <= KERN_ERR
[1];
82 bool is_debug
= level
[1] == KERN_DEBUG
[1];
86 if (is_debug
&& !(drm_debug
& DRM_UT_DRIVER
))
94 dev_printk(level
, dev
, "[" DRM_NAME
":%ps] %pV",
95 __builtin_return_address(0), &vaf
);
97 if (is_error
&& !shown_bug_once
) {
98 dev_notice(dev
, "%s", FDO_BUG_MSG
);
99 shown_bug_once
= true;
105 static bool i915_error_injected(struct drm_i915_private
*dev_priv
)
107 return i915
.inject_load_failure
&&
108 i915_load_fail_count
== i915
.inject_load_failure
;
111 #define i915_load_error(dev_priv, fmt, ...) \
112 __i915_printk(dev_priv, \
113 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
117 static enum intel_pch
intel_virt_detect_pch(struct drm_device
*dev
)
119 enum intel_pch ret
= PCH_NOP
;
122 * In a virtualized passthrough environment we can be in a
123 * setup where the ISA bridge is not able to be passed through.
124 * In this case, a south bridge can be emulated and we have to
125 * make an educated guess as to which PCH is really there.
130 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
131 } else if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
133 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
134 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
136 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
137 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
139 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
145 static void intel_detect_pch(struct drm_device
*dev
)
147 struct drm_i915_private
*dev_priv
= to_i915(dev
);
148 struct pci_dev
*pch
= NULL
;
150 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
151 * (which really amounts to a PCH but no South Display).
153 if (INTEL_INFO(dev
)->num_pipes
== 0) {
154 dev_priv
->pch_type
= PCH_NOP
;
159 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
160 * make graphics device passthrough work easy for VMM, that only
161 * need to expose ISA bridge to let driver know the real hardware
162 * underneath. This is a requirement from virtualization team.
164 * In some virtualized environments (e.g. XEN), there is irrelevant
165 * ISA bridge in the system. To work reliably, we should scan trhough
166 * all the ISA bridge devices and check for the first match, instead
167 * of only checking the first one.
169 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
170 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
171 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
172 dev_priv
->pch_id
= id
;
174 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
175 dev_priv
->pch_type
= PCH_IBX
;
176 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
177 WARN_ON(!IS_GEN5(dev
));
178 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
179 dev_priv
->pch_type
= PCH_CPT
;
180 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
181 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
182 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
183 /* PantherPoint is CPT compatible */
184 dev_priv
->pch_type
= PCH_CPT
;
185 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
186 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
187 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
188 dev_priv
->pch_type
= PCH_LPT
;
189 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
190 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
191 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
192 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
193 dev_priv
->pch_type
= PCH_LPT
;
194 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
195 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
196 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
197 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
198 dev_priv
->pch_type
= PCH_SPT
;
199 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
200 WARN_ON(!IS_SKYLAKE(dev
) &&
202 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
203 dev_priv
->pch_type
= PCH_SPT
;
204 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
205 WARN_ON(!IS_SKYLAKE(dev
) &&
207 } else if (id
== INTEL_PCH_KBP_DEVICE_ID_TYPE
) {
208 dev_priv
->pch_type
= PCH_KBP
;
209 DRM_DEBUG_KMS("Found KabyPoint PCH\n");
210 WARN_ON(!IS_KABYLAKE(dev
));
211 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
212 (id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
) ||
213 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
214 pch
->subsystem_vendor
==
215 PCI_SUBVENDOR_ID_REDHAT_QUMRANET
&&
216 pch
->subsystem_device
==
217 PCI_SUBDEVICE_ID_QEMU
)) {
218 dev_priv
->pch_type
= intel_virt_detect_pch(dev
);
226 DRM_DEBUG_KMS("No PCH found.\n");
231 bool i915_semaphore_is_enabled(struct drm_i915_private
*dev_priv
)
233 if (INTEL_GEN(dev_priv
) < 6)
236 if (i915
.semaphores
>= 0)
237 return i915
.semaphores
;
239 /* TODO: make semaphores and Execlists play nicely together */
240 if (i915
.enable_execlists
)
243 #ifdef CONFIG_INTEL_IOMMU
244 /* Enable semaphores on SNB when IO remapping is off */
245 if (IS_GEN6(dev_priv
) && intel_iommu_gfx_mapped
)
252 static int i915_getparam(struct drm_device
*dev
, void *data
,
253 struct drm_file
*file_priv
)
255 struct drm_i915_private
*dev_priv
= to_i915(dev
);
256 drm_i915_getparam_t
*param
= data
;
259 switch (param
->param
) {
260 case I915_PARAM_IRQ_ACTIVE
:
261 case I915_PARAM_ALLOW_BATCHBUFFER
:
262 case I915_PARAM_LAST_DISPATCH
:
263 /* Reject all old ums/dri params. */
265 case I915_PARAM_CHIPSET_ID
:
266 value
= dev
->pdev
->device
;
268 case I915_PARAM_REVISION
:
269 value
= dev
->pdev
->revision
;
271 case I915_PARAM_HAS_GEM
:
274 case I915_PARAM_NUM_FENCES_AVAIL
:
275 value
= dev_priv
->num_fence_regs
;
277 case I915_PARAM_HAS_OVERLAY
:
278 value
= dev_priv
->overlay
? 1 : 0;
280 case I915_PARAM_HAS_PAGEFLIPPING
:
283 case I915_PARAM_HAS_EXECBUF2
:
287 case I915_PARAM_HAS_BSD
:
288 value
= intel_engine_initialized(&dev_priv
->engine
[VCS
]);
290 case I915_PARAM_HAS_BLT
:
291 value
= intel_engine_initialized(&dev_priv
->engine
[BCS
]);
293 case I915_PARAM_HAS_VEBOX
:
294 value
= intel_engine_initialized(&dev_priv
->engine
[VECS
]);
296 case I915_PARAM_HAS_BSD2
:
297 value
= intel_engine_initialized(&dev_priv
->engine
[VCS2
]);
299 case I915_PARAM_HAS_RELAXED_FENCING
:
302 case I915_PARAM_HAS_COHERENT_RINGS
:
305 case I915_PARAM_HAS_EXEC_CONSTANTS
:
306 value
= INTEL_INFO(dev
)->gen
>= 4;
308 case I915_PARAM_HAS_RELAXED_DELTA
:
311 case I915_PARAM_HAS_GEN7_SOL_RESET
:
314 case I915_PARAM_HAS_LLC
:
315 value
= HAS_LLC(dev
);
317 case I915_PARAM_HAS_WT
:
320 case I915_PARAM_HAS_ALIASING_PPGTT
:
321 value
= USES_PPGTT(dev
);
323 case I915_PARAM_HAS_WAIT_TIMEOUT
:
326 case I915_PARAM_HAS_SEMAPHORES
:
327 value
= i915_semaphore_is_enabled(dev_priv
);
329 case I915_PARAM_HAS_PRIME_VMAP_FLUSH
:
332 case I915_PARAM_HAS_SECURE_BATCHES
:
333 value
= capable(CAP_SYS_ADMIN
);
335 case I915_PARAM_HAS_PINNED_BATCHES
:
338 case I915_PARAM_HAS_EXEC_NO_RELOC
:
341 case I915_PARAM_HAS_EXEC_HANDLE_LUT
:
344 case I915_PARAM_CMD_PARSER_VERSION
:
345 value
= i915_cmd_parser_get_version(dev_priv
);
347 case I915_PARAM_HAS_COHERENT_PHYS_GTT
:
350 case I915_PARAM_MMAP_VERSION
:
353 case I915_PARAM_SUBSLICE_TOTAL
:
354 value
= INTEL_INFO(dev
)->subslice_total
;
358 case I915_PARAM_EU_TOTAL
:
359 value
= INTEL_INFO(dev
)->eu_total
;
363 case I915_PARAM_HAS_GPU_RESET
:
364 value
= i915
.enable_hangcheck
&& intel_has_gpu_reset(dev_priv
);
366 case I915_PARAM_HAS_RESOURCE_STREAMER
:
367 value
= HAS_RESOURCE_STREAMER(dev
);
369 case I915_PARAM_HAS_EXEC_SOFTPIN
:
372 case I915_PARAM_HAS_POOLED_EU
:
373 value
= HAS_POOLED_EU(dev
);
375 case I915_PARAM_MIN_EU_IN_POOL
:
376 value
= INTEL_INFO(dev
)->min_eu_in_pool
;
379 DRM_DEBUG("Unknown parameter %d\n", param
->param
);
383 if (put_user(value
, param
->value
))
389 static int i915_get_bridge_dev(struct drm_device
*dev
)
391 struct drm_i915_private
*dev_priv
= to_i915(dev
);
393 dev_priv
->bridge_dev
= pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
394 if (!dev_priv
->bridge_dev
) {
395 DRM_ERROR("bridge device not found\n");
401 /* Allocate space for the MCH regs if needed, return nonzero on error */
403 intel_alloc_mchbar_resource(struct drm_device
*dev
)
405 struct drm_i915_private
*dev_priv
= to_i915(dev
);
406 int reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
407 u32 temp_lo
, temp_hi
= 0;
411 if (INTEL_INFO(dev
)->gen
>= 4)
412 pci_read_config_dword(dev_priv
->bridge_dev
, reg
+ 4, &temp_hi
);
413 pci_read_config_dword(dev_priv
->bridge_dev
, reg
, &temp_lo
);
414 mchbar_addr
= ((u64
)temp_hi
<< 32) | temp_lo
;
416 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
419 pnp_range_reserved(mchbar_addr
, mchbar_addr
+ MCHBAR_SIZE
))
423 /* Get some space for it */
424 dev_priv
->mch_res
.name
= "i915 MCHBAR";
425 dev_priv
->mch_res
.flags
= IORESOURCE_MEM
;
426 ret
= pci_bus_alloc_resource(dev_priv
->bridge_dev
->bus
,
428 MCHBAR_SIZE
, MCHBAR_SIZE
,
430 0, pcibios_align_resource
,
431 dev_priv
->bridge_dev
);
433 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret
);
434 dev_priv
->mch_res
.start
= 0;
438 if (INTEL_INFO(dev
)->gen
>= 4)
439 pci_write_config_dword(dev_priv
->bridge_dev
, reg
+ 4,
440 upper_32_bits(dev_priv
->mch_res
.start
));
442 pci_write_config_dword(dev_priv
->bridge_dev
, reg
,
443 lower_32_bits(dev_priv
->mch_res
.start
));
447 /* Setup MCHBAR if possible, return true if we should disable it again */
449 intel_setup_mchbar(struct drm_device
*dev
)
451 struct drm_i915_private
*dev_priv
= to_i915(dev
);
452 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
456 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
459 dev_priv
->mchbar_need_disable
= false;
461 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
462 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
, &temp
);
463 enabled
= !!(temp
& DEVEN_MCHBAR_EN
);
465 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
469 /* If it's already enabled, don't have to do anything */
473 if (intel_alloc_mchbar_resource(dev
))
476 dev_priv
->mchbar_need_disable
= true;
478 /* Space is allocated or reserved, so enable it. */
479 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
480 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
481 temp
| DEVEN_MCHBAR_EN
);
483 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, &temp
);
484 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
, temp
| 1);
489 intel_teardown_mchbar(struct drm_device
*dev
)
491 struct drm_i915_private
*dev_priv
= to_i915(dev
);
492 int mchbar_reg
= INTEL_INFO(dev
)->gen
>= 4 ? MCHBAR_I965
: MCHBAR_I915
;
494 if (dev_priv
->mchbar_need_disable
) {
495 if (IS_I915G(dev
) || IS_I915GM(dev
)) {
498 pci_read_config_dword(dev_priv
->bridge_dev
, DEVEN
,
500 deven_val
&= ~DEVEN_MCHBAR_EN
;
501 pci_write_config_dword(dev_priv
->bridge_dev
, DEVEN
,
506 pci_read_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
509 pci_write_config_dword(dev_priv
->bridge_dev
, mchbar_reg
,
514 if (dev_priv
->mch_res
.start
)
515 release_resource(&dev_priv
->mch_res
);
518 /* true = enable decode, false = disable decoder */
519 static unsigned int i915_vga_set_decode(void *cookie
, bool state
)
521 struct drm_device
*dev
= cookie
;
523 intel_modeset_vga_set_state(dev
, state
);
525 return VGA_RSRC_LEGACY_IO
| VGA_RSRC_LEGACY_MEM
|
526 VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
528 return VGA_RSRC_NORMAL_IO
| VGA_RSRC_NORMAL_MEM
;
531 static void i915_switcheroo_set_state(struct pci_dev
*pdev
, enum vga_switcheroo_state state
)
533 struct drm_device
*dev
= pci_get_drvdata(pdev
);
534 pm_message_t pmm
= { .event
= PM_EVENT_SUSPEND
};
536 if (state
== VGA_SWITCHEROO_ON
) {
537 pr_info("switched on\n");
538 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
539 /* i915 resume handler doesn't set to D0 */
540 pci_set_power_state(dev
->pdev
, PCI_D0
);
541 i915_resume_switcheroo(dev
);
542 dev
->switch_power_state
= DRM_SWITCH_POWER_ON
;
544 pr_info("switched off\n");
545 dev
->switch_power_state
= DRM_SWITCH_POWER_CHANGING
;
546 i915_suspend_switcheroo(dev
, pmm
);
547 dev
->switch_power_state
= DRM_SWITCH_POWER_OFF
;
551 static bool i915_switcheroo_can_switch(struct pci_dev
*pdev
)
553 struct drm_device
*dev
= pci_get_drvdata(pdev
);
556 * FIXME: open_count is protected by drm_global_mutex but that would lead to
557 * locking inversion with the driver load path. And the access here is
558 * completely racy anyway. So don't bother with locking for now.
560 return dev
->open_count
== 0;
563 static const struct vga_switcheroo_client_ops i915_switcheroo_ops
= {
564 .set_gpu_state
= i915_switcheroo_set_state
,
566 .can_switch
= i915_switcheroo_can_switch
,
569 static void i915_gem_fini(struct drm_device
*dev
)
571 struct drm_i915_private
*dev_priv
= to_i915(dev
);
574 * Neither the BIOS, ourselves or any other kernel
575 * expects the system to be in execlists mode on startup,
576 * so we need to reset the GPU back to legacy mode. And the only
577 * known way to disable logical contexts is through a GPU reset.
579 * So in order to leave the system in a known default configuration,
580 * always reset the GPU upon unload. Afterwards we then clean up the
581 * GEM state tracking, flushing off the requests and leaving the
582 * system in a known idle state.
584 * Note that is of the upmost importance that the GPU is idle and
585 * all stray writes are flushed *before* we dismantle the backing
586 * storage for the pinned objects.
588 * However, since we are uncertain that reseting the GPU on older
589 * machines is a good idea, we don't - just in case it leaves the
590 * machine in an unusable condition.
592 if (HAS_HW_CONTEXTS(dev
)) {
593 int reset
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
594 WARN_ON(reset
&& reset
!= -ENODEV
);
597 mutex_lock(&dev
->struct_mutex
);
599 i915_gem_cleanup_engines(dev
);
600 i915_gem_context_fini(dev
);
601 mutex_unlock(&dev
->struct_mutex
);
603 WARN_ON(!list_empty(&to_i915(dev
)->context_list
));
606 static int i915_load_modeset_init(struct drm_device
*dev
)
608 struct drm_i915_private
*dev_priv
= to_i915(dev
);
611 if (i915_inject_load_failure())
614 ret
= intel_bios_init(dev_priv
);
616 DRM_INFO("failed to find VBIOS tables\n");
618 /* If we have > 1 VGA cards, then we need to arbitrate access
619 * to the common VGA resources.
621 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
622 * then we do not take part in VGA arbitration and the
623 * vga_client_register() fails with -ENODEV.
625 ret
= vga_client_register(dev
->pdev
, dev
, NULL
, i915_vga_set_decode
);
626 if (ret
&& ret
!= -ENODEV
)
629 intel_register_dsm_handler();
631 ret
= vga_switcheroo_register_client(dev
->pdev
, &i915_switcheroo_ops
, false);
633 goto cleanup_vga_client
;
635 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
636 intel_update_rawclk(dev_priv
);
638 intel_power_domains_init_hw(dev_priv
, false);
640 intel_csr_ucode_init(dev_priv
);
642 ret
= intel_irq_install(dev_priv
);
646 intel_setup_gmbus(dev
);
648 /* Important: The output setup functions called by modeset_init need
649 * working irqs for e.g. gmbus and dp aux transfers. */
650 intel_modeset_init(dev
);
654 ret
= i915_gem_init(dev
);
658 intel_modeset_gem_init(dev
);
660 if (INTEL_INFO(dev
)->num_pipes
== 0)
663 ret
= intel_fbdev_init(dev
);
667 /* Only enable hotplug handling once the fbdev is fully set up. */
668 intel_hpd_init(dev_priv
);
670 drm_kms_helper_poll_init(dev
);
678 drm_irq_uninstall(dev
);
679 intel_teardown_gmbus(dev
);
681 intel_csr_ucode_fini(dev_priv
);
682 intel_power_domains_fini(dev_priv
);
683 vga_switcheroo_unregister_client(dev
->pdev
);
685 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
690 #if IS_ENABLED(CONFIG_FB)
691 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
693 struct apertures_struct
*ap
;
694 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
695 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
699 ap
= alloc_apertures(1);
703 ap
->ranges
[0].base
= ggtt
->mappable_base
;
704 ap
->ranges
[0].size
= ggtt
->mappable_end
;
707 pdev
->resource
[PCI_ROM_RESOURCE
].flags
& IORESOURCE_ROM_SHADOW
;
709 ret
= remove_conflicting_framebuffers(ap
, "inteldrmfb", primary
);
716 static int i915_kick_out_firmware_fb(struct drm_i915_private
*dev_priv
)
722 #if !defined(CONFIG_VGA_CONSOLE)
723 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
727 #elif !defined(CONFIG_DUMMY_CONSOLE)
728 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
733 static int i915_kick_out_vgacon(struct drm_i915_private
*dev_priv
)
737 DRM_INFO("Replacing VGA console driver\n");
740 if (con_is_bound(&vga_con
))
741 ret
= do_take_over_console(&dummy_con
, 0, MAX_NR_CONSOLES
- 1, 1);
743 ret
= do_unregister_con_driver(&vga_con
);
745 /* Ignore "already unregistered". */
755 static void intel_init_dpio(struct drm_i915_private
*dev_priv
)
758 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
759 * CHV x1 PHY (DP/HDMI D)
760 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
762 if (IS_CHERRYVIEW(dev_priv
)) {
763 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
764 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
765 } else if (IS_VALLEYVIEW(dev_priv
)) {
766 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
770 static int i915_workqueues_init(struct drm_i915_private
*dev_priv
)
773 * The i915 workqueue is primarily used for batched retirement of
774 * requests (and thus managing bo) once the task has been completed
775 * by the GPU. i915_gem_retire_requests() is called directly when we
776 * need high-priority retirement, such as waiting for an explicit
779 * It is also used for periodic low-priority events, such as
780 * idle-timers and recording error state.
782 * All tasks on the workqueue are expected to acquire the dev mutex
783 * so there is no point in running more than one instance of the
784 * workqueue at any time. Use an ordered one.
786 dev_priv
->wq
= alloc_ordered_workqueue("i915", 0);
787 if (dev_priv
->wq
== NULL
)
790 dev_priv
->hotplug
.dp_wq
= alloc_ordered_workqueue("i915-dp", 0);
791 if (dev_priv
->hotplug
.dp_wq
== NULL
)
797 destroy_workqueue(dev_priv
->wq
);
799 DRM_ERROR("Failed to allocate workqueues.\n");
804 static void i915_workqueues_cleanup(struct drm_i915_private
*dev_priv
)
806 destroy_workqueue(dev_priv
->hotplug
.dp_wq
);
807 destroy_workqueue(dev_priv
->wq
);
811 * i915_driver_init_early - setup state not requiring device access
812 * @dev_priv: device private
814 * Initialize everything that is a "SW-only" state, that is state not
815 * requiring accessing the device or exposing the driver via kernel internal
816 * or userspace interfaces. Example steps belonging here: lock initialization,
817 * system memory allocation, setting up device specific attributes and
818 * function hooks not requiring accessing the device.
820 static int i915_driver_init_early(struct drm_i915_private
*dev_priv
,
821 const struct pci_device_id
*ent
)
823 const struct intel_device_info
*match_info
=
824 (struct intel_device_info
*)ent
->driver_data
;
825 struct intel_device_info
*device_info
;
828 if (i915_inject_load_failure())
831 /* Setup the write-once "constant" device info */
832 device_info
= mkwrite_device_info(dev_priv
);
833 memcpy(device_info
, match_info
, sizeof(*device_info
));
834 device_info
->device_id
= dev_priv
->drm
.pdev
->device
;
836 BUG_ON(device_info
->gen
> sizeof(device_info
->gen_mask
) * BITS_PER_BYTE
);
837 device_info
->gen_mask
= BIT(device_info
->gen
- 1);
839 spin_lock_init(&dev_priv
->irq_lock
);
840 spin_lock_init(&dev_priv
->gpu_error
.lock
);
841 mutex_init(&dev_priv
->backlight_lock
);
842 spin_lock_init(&dev_priv
->uncore
.lock
);
843 spin_lock_init(&dev_priv
->mm
.object_stat_lock
);
844 spin_lock_init(&dev_priv
->mmio_flip_lock
);
845 mutex_init(&dev_priv
->sb_lock
);
846 mutex_init(&dev_priv
->modeset_restore_lock
);
847 mutex_init(&dev_priv
->av_mutex
);
848 mutex_init(&dev_priv
->wm
.wm_mutex
);
849 mutex_init(&dev_priv
->pps_mutex
);
851 ret
= i915_workqueues_init(dev_priv
);
855 ret
= intel_gvt_init(dev_priv
);
859 /* This must be called before any calls to HAS_PCH_* */
860 intel_detect_pch(&dev_priv
->drm
);
862 intel_pm_setup(&dev_priv
->drm
);
863 intel_init_dpio(dev_priv
);
864 intel_power_domains_init(dev_priv
);
865 intel_irq_init(dev_priv
);
866 intel_init_display_hooks(dev_priv
);
867 intel_init_clock_gating_hooks(dev_priv
);
868 intel_init_audio_hooks(dev_priv
);
869 i915_gem_load_init(&dev_priv
->drm
);
871 intel_display_crc_init(&dev_priv
->drm
);
873 intel_device_info_dump(dev_priv
);
875 /* Not all pre-production machines fall into this category, only the
876 * very first ones. Almost everything should work, except for maybe
877 * suspend/resume. And we don't implement workarounds that affect only
878 * pre-production machines. */
879 if (IS_HSW_EARLY_SDV(dev_priv
))
880 DRM_INFO("This is an early pre-production Haswell machine. "
881 "It may not be fully functional.\n");
886 i915_workqueues_cleanup(dev_priv
);
891 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
892 * @dev_priv: device private
894 static void i915_driver_cleanup_early(struct drm_i915_private
*dev_priv
)
896 i915_gem_load_cleanup(&dev_priv
->drm
);
897 i915_workqueues_cleanup(dev_priv
);
900 static int i915_mmio_setup(struct drm_device
*dev
)
902 struct drm_i915_private
*dev_priv
= to_i915(dev
);
906 mmio_bar
= IS_GEN2(dev
) ? 1 : 0;
908 * Before gen4, the registers and the GTT are behind different BARs.
909 * However, from gen4 onwards, the registers and the GTT are shared
910 * in the same BAR, so we want to restrict this ioremap from
911 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
912 * the register BAR remains the same size for all the earlier
913 * generations up to Ironlake.
915 if (INTEL_INFO(dev
)->gen
< 5)
916 mmio_size
= 512 * 1024;
918 mmio_size
= 2 * 1024 * 1024;
919 dev_priv
->regs
= pci_iomap(dev
->pdev
, mmio_bar
, mmio_size
);
920 if (dev_priv
->regs
== NULL
) {
921 DRM_ERROR("failed to map registers\n");
926 /* Try to make sure MCHBAR is enabled before poking at it */
927 intel_setup_mchbar(dev
);
932 static void i915_mmio_cleanup(struct drm_device
*dev
)
934 struct drm_i915_private
*dev_priv
= to_i915(dev
);
936 intel_teardown_mchbar(dev
);
937 pci_iounmap(dev
->pdev
, dev_priv
->regs
);
941 * i915_driver_init_mmio - setup device MMIO
942 * @dev_priv: device private
944 * Setup minimal device state necessary for MMIO accesses later in the
945 * initialization sequence. The setup here should avoid any other device-wide
946 * side effects or exposing the driver via kernel internal or user space
949 static int i915_driver_init_mmio(struct drm_i915_private
*dev_priv
)
951 struct drm_device
*dev
= &dev_priv
->drm
;
954 if (i915_inject_load_failure())
957 if (i915_get_bridge_dev(dev
))
960 ret
= i915_mmio_setup(dev
);
964 intel_uncore_init(dev_priv
);
969 pci_dev_put(dev_priv
->bridge_dev
);
975 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
976 * @dev_priv: device private
978 static void i915_driver_cleanup_mmio(struct drm_i915_private
*dev_priv
)
980 struct drm_device
*dev
= &dev_priv
->drm
;
982 intel_uncore_fini(dev_priv
);
983 i915_mmio_cleanup(dev
);
984 pci_dev_put(dev_priv
->bridge_dev
);
987 static void intel_sanitize_options(struct drm_i915_private
*dev_priv
)
989 i915
.enable_execlists
=
990 intel_sanitize_enable_execlists(dev_priv
,
991 i915
.enable_execlists
);
994 * i915.enable_ppgtt is read-only, so do an early pass to validate the
995 * user's requested state against the hardware/driver capabilities. We
996 * do this now so that we can print out any log messages once rather
997 * than every time we check intel_enable_ppgtt().
1000 intel_sanitize_enable_ppgtt(dev_priv
, i915
.enable_ppgtt
);
1001 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915
.enable_ppgtt
);
1005 * i915_driver_init_hw - setup state requiring device access
1006 * @dev_priv: device private
1008 * Setup state that requires accessing the device, but doesn't require
1009 * exposing the driver via kernel internal or userspace interfaces.
1011 static int i915_driver_init_hw(struct drm_i915_private
*dev_priv
)
1013 struct drm_device
*dev
= &dev_priv
->drm
;
1014 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1015 uint32_t aperture_size
;
1018 if (i915_inject_load_failure())
1021 intel_device_info_runtime_init(dev_priv
);
1023 intel_sanitize_options(dev_priv
);
1025 ret
= i915_ggtt_init_hw(dev
);
1029 ret
= i915_ggtt_enable_hw(dev
);
1031 DRM_ERROR("failed to enable GGTT\n");
1035 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1036 * otherwise the vga fbdev driver falls over. */
1037 ret
= i915_kick_out_firmware_fb(dev_priv
);
1039 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1043 ret
= i915_kick_out_vgacon(dev_priv
);
1045 DRM_ERROR("failed to remove conflicting VGA console\n");
1049 pci_set_master(dev
->pdev
);
1051 /* overlay on gen2 is broken and can't address above 1G */
1053 ret
= dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(30));
1055 DRM_ERROR("failed to set DMA mask\n");
1062 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1063 * using 32bit addressing, overwriting memory if HWS is located
1066 * The documentation also mentions an issue with undefined
1067 * behaviour if any general state is accessed within a page above 4GB,
1068 * which also needs to be handled carefully.
1070 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
)) {
1071 ret
= dma_set_coherent_mask(&dev
->pdev
->dev
, DMA_BIT_MASK(32));
1074 DRM_ERROR("failed to set DMA mask\n");
1080 aperture_size
= ggtt
->mappable_end
;
1083 io_mapping_create_wc(ggtt
->mappable_base
,
1085 if (!ggtt
->mappable
) {
1090 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->mappable_base
,
1093 pm_qos_add_request(&dev_priv
->pm_qos
, PM_QOS_CPU_DMA_LATENCY
,
1094 PM_QOS_DEFAULT_VALUE
);
1096 intel_uncore_sanitize(dev_priv
);
1098 intel_opregion_setup(dev_priv
);
1100 i915_gem_load_init_fences(dev_priv
);
1102 /* On the 945G/GM, the chipset reports the MSI capability on the
1103 * integrated graphics even though the support isn't actually there
1104 * according to the published specs. It doesn't appear to function
1105 * correctly in testing on 945G.
1106 * This may be a side effect of MSI having been made available for PEG
1107 * and the registers being closely associated.
1109 * According to chipset errata, on the 965GM, MSI interrupts may
1110 * be lost or delayed, but we use them anyways to avoid
1111 * stuck interrupts on some machines.
1113 if (!IS_I945G(dev
) && !IS_I945GM(dev
)) {
1114 if (pci_enable_msi(dev
->pdev
) < 0)
1115 DRM_DEBUG_DRIVER("can't enable MSI");
1121 i915_ggtt_cleanup_hw(dev
);
1127 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1128 * @dev_priv: device private
1130 static void i915_driver_cleanup_hw(struct drm_i915_private
*dev_priv
)
1132 struct drm_device
*dev
= &dev_priv
->drm
;
1133 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1135 if (dev
->pdev
->msi_enabled
)
1136 pci_disable_msi(dev
->pdev
);
1138 pm_qos_remove_request(&dev_priv
->pm_qos
);
1139 arch_phys_wc_del(ggtt
->mtrr
);
1140 io_mapping_free(ggtt
->mappable
);
1141 i915_ggtt_cleanup_hw(dev
);
1145 * i915_driver_register - register the driver with the rest of the system
1146 * @dev_priv: device private
1148 * Perform any steps necessary to make the driver available via kernel
1149 * internal or userspace interfaces.
1151 static void i915_driver_register(struct drm_i915_private
*dev_priv
)
1153 struct drm_device
*dev
= &dev_priv
->drm
;
1155 i915_gem_shrinker_init(dev_priv
);
1158 * Notify a valid surface after modesetting,
1159 * when running inside a VM.
1161 if (intel_vgpu_active(dev_priv
))
1162 I915_WRITE(vgtif_reg(display_ready
), VGT_DRV_DISPLAY_READY
);
1164 /* Reveal our presence to userspace */
1165 if (drm_dev_register(dev
, 0) == 0) {
1166 i915_debugfs_register(dev_priv
);
1167 i915_setup_sysfs(dev
);
1169 DRM_ERROR("Failed to register driver for userspace access!\n");
1171 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1172 /* Must be done after probing outputs */
1173 intel_opregion_register(dev_priv
);
1174 acpi_video_register();
1177 if (IS_GEN5(dev_priv
))
1178 intel_gpu_ips_init(dev_priv
);
1180 i915_audio_component_init(dev_priv
);
1183 * Some ports require correctly set-up hpd registers for detection to
1184 * work properly (leading to ghost connected connector status), e.g. VGA
1185 * on gm45. Hence we can only set up the initial fbdev config after hpd
1186 * irqs are fully enabled. We do it last so that the async config
1187 * cannot run before the connectors are registered.
1189 intel_fbdev_initial_config_async(dev
);
1193 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1194 * @dev_priv: device private
1196 static void i915_driver_unregister(struct drm_i915_private
*dev_priv
)
1198 i915_audio_component_cleanup(dev_priv
);
1200 intel_gpu_ips_teardown();
1201 acpi_video_unregister();
1202 intel_opregion_unregister(dev_priv
);
1204 i915_teardown_sysfs(&dev_priv
->drm
);
1205 i915_debugfs_unregister(dev_priv
);
1206 drm_dev_unregister(&dev_priv
->drm
);
1208 i915_gem_shrinker_cleanup(dev_priv
);
1212 * i915_driver_load - setup chip and create an initial config
1214 * @flags: startup flags
1216 * The driver load routine has to do several things:
1217 * - drive output discovery via intel_modeset_init()
1218 * - initialize the memory manager
1219 * - allocate initial config memory
1220 * - setup the DRM framebuffer with the allocated memory
1222 int i915_driver_load(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1224 struct drm_i915_private
*dev_priv
;
1227 if (i915
.nuclear_pageflip
)
1228 driver
.driver_features
|= DRIVER_ATOMIC
;
1231 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
1233 ret
= drm_dev_init(&dev_priv
->drm
, &driver
, &pdev
->dev
);
1235 dev_printk(KERN_ERR
, &pdev
->dev
,
1236 "[" DRM_NAME
":%s] allocation failed\n", __func__
);
1241 dev_priv
->drm
.pdev
= pdev
;
1242 dev_priv
->drm
.dev_private
= dev_priv
;
1244 ret
= pci_enable_device(pdev
);
1248 pci_set_drvdata(pdev
, &dev_priv
->drm
);
1250 ret
= i915_driver_init_early(dev_priv
, ent
);
1252 goto out_pci_disable
;
1254 intel_runtime_pm_get(dev_priv
);
1256 ret
= i915_driver_init_mmio(dev_priv
);
1258 goto out_runtime_pm_put
;
1260 ret
= i915_driver_init_hw(dev_priv
);
1262 goto out_cleanup_mmio
;
1265 * TODO: move the vblank init and parts of modeset init steps into one
1266 * of the i915_driver_init_/i915_driver_register functions according
1267 * to the role/effect of the given init step.
1269 if (INTEL_INFO(dev_priv
)->num_pipes
) {
1270 ret
= drm_vblank_init(&dev_priv
->drm
,
1271 INTEL_INFO(dev_priv
)->num_pipes
);
1273 goto out_cleanup_hw
;
1276 ret
= i915_load_modeset_init(&dev_priv
->drm
);
1278 goto out_cleanup_vblank
;
1280 i915_driver_register(dev_priv
);
1282 intel_runtime_pm_enable(dev_priv
);
1284 intel_runtime_pm_put(dev_priv
);
1289 drm_vblank_cleanup(&dev_priv
->drm
);
1291 i915_driver_cleanup_hw(dev_priv
);
1293 i915_driver_cleanup_mmio(dev_priv
);
1295 intel_runtime_pm_put(dev_priv
);
1296 i915_driver_cleanup_early(dev_priv
);
1298 pci_disable_device(pdev
);
1300 i915_load_error(dev_priv
, "Device initialization failed (%d)\n", ret
);
1301 drm_dev_unref(&dev_priv
->drm
);
1305 void i915_driver_unload(struct drm_device
*dev
)
1307 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1309 intel_fbdev_fini(dev
);
1311 if (i915_gem_suspend(dev
))
1312 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1314 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
1316 i915_driver_unregister(dev_priv
);
1318 drm_vblank_cleanup(dev
);
1320 intel_modeset_cleanup(dev
);
1323 * free the memory space allocated for the child device
1324 * config parsed from VBT
1326 if (dev_priv
->vbt
.child_dev
&& dev_priv
->vbt
.child_dev_num
) {
1327 kfree(dev_priv
->vbt
.child_dev
);
1328 dev_priv
->vbt
.child_dev
= NULL
;
1329 dev_priv
->vbt
.child_dev_num
= 0;
1331 kfree(dev_priv
->vbt
.sdvo_lvds_vbt_mode
);
1332 dev_priv
->vbt
.sdvo_lvds_vbt_mode
= NULL
;
1333 kfree(dev_priv
->vbt
.lfp_lvds_vbt_mode
);
1334 dev_priv
->vbt
.lfp_lvds_vbt_mode
= NULL
;
1336 vga_switcheroo_unregister_client(dev
->pdev
);
1337 vga_client_register(dev
->pdev
, NULL
, NULL
, NULL
);
1339 intel_csr_ucode_fini(dev_priv
);
1341 /* Free error state after interrupts are fully disabled. */
1342 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1343 i915_destroy_error_state(dev
);
1345 /* Flush any outstanding unpin_work. */
1346 flush_workqueue(dev_priv
->wq
);
1348 intel_guc_fini(dev
);
1350 intel_fbc_cleanup_cfb(dev_priv
);
1352 intel_power_domains_fini(dev_priv
);
1354 i915_driver_cleanup_hw(dev_priv
);
1355 i915_driver_cleanup_mmio(dev_priv
);
1357 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
1359 i915_driver_cleanup_early(dev_priv
);
1362 static int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
)
1366 ret
= i915_gem_open(dev
, file
);
1374 * i915_driver_lastclose - clean up after all DRM clients have exited
1377 * Take care of cleaning up after all DRM clients have exited. In the
1378 * mode setting case, we want to restore the kernel's initial mode (just
1379 * in case the last client left us in a bad state).
1381 * Additionally, in the non-mode setting case, we'll tear down the GTT
1382 * and DMA structures, since the kernel won't be using them, and clea
1385 static void i915_driver_lastclose(struct drm_device
*dev
)
1387 intel_fbdev_restore_mode(dev
);
1388 vga_switcheroo_process_delayed_switch();
1391 static void i915_driver_preclose(struct drm_device
*dev
, struct drm_file
*file
)
1393 mutex_lock(&dev
->struct_mutex
);
1394 i915_gem_context_close(dev
, file
);
1395 i915_gem_release(dev
, file
);
1396 mutex_unlock(&dev
->struct_mutex
);
1399 static void i915_driver_postclose(struct drm_device
*dev
, struct drm_file
*file
)
1401 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1406 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
1408 struct drm_device
*dev
= &dev_priv
->drm
;
1409 struct intel_encoder
*encoder
;
1411 drm_modeset_lock_all(dev
);
1412 for_each_intel_encoder(dev
, encoder
)
1413 if (encoder
->suspend
)
1414 encoder
->suspend(encoder
);
1415 drm_modeset_unlock_all(dev
);
1418 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1420 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
1422 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
1424 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1425 if (acpi_target_system_state() < ACPI_STATE_S3
)
1431 static int i915_drm_suspend(struct drm_device
*dev
)
1433 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1434 pci_power_t opregion_target_state
;
1437 /* ignore lid events during suspend */
1438 mutex_lock(&dev_priv
->modeset_restore_lock
);
1439 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
1440 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1442 disable_rpm_wakeref_asserts(dev_priv
);
1444 /* We do a lot of poking in a lot of registers, make sure they work
1446 intel_display_set_init_power(dev_priv
, true);
1448 drm_kms_helper_poll_disable(dev
);
1450 pci_save_state(dev
->pdev
);
1452 error
= i915_gem_suspend(dev
);
1454 dev_err(&dev
->pdev
->dev
,
1455 "GEM idle failed, resume might fail\n");
1459 intel_guc_suspend(dev
);
1461 intel_suspend_gt_powersave(dev_priv
);
1463 intel_display_suspend(dev
);
1465 intel_dp_mst_suspend(dev
);
1467 intel_runtime_pm_disable_interrupts(dev_priv
);
1468 intel_hpd_cancel_work(dev_priv
);
1470 intel_suspend_encoders(dev_priv
);
1472 intel_suspend_hw(dev
);
1474 i915_gem_suspend_gtt_mappings(dev
);
1476 i915_save_state(dev
);
1478 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
1479 intel_opregion_notify_adapter(dev_priv
, opregion_target_state
);
1481 intel_uncore_forcewake_reset(dev_priv
, false);
1482 intel_opregion_unregister(dev_priv
);
1484 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
1486 dev_priv
->suspend_count
++;
1488 intel_display_set_init_power(dev_priv
, false);
1490 intel_csr_ucode_suspend(dev_priv
);
1493 enable_rpm_wakeref_asserts(dev_priv
);
1498 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
1500 struct drm_i915_private
*dev_priv
= to_i915(drm_dev
);
1504 disable_rpm_wakeref_asserts(dev_priv
);
1506 fw_csr
= !IS_BROXTON(dev_priv
) &&
1507 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
1509 * In case of firmware assisted context save/restore don't manually
1510 * deinit the power domains. This also means the CSR/DMC firmware will
1511 * stay active, it will power down any HW resources as required and
1512 * also enable deeper system power states that would be blocked if the
1513 * firmware was inactive.
1516 intel_power_domains_suspend(dev_priv
);
1519 if (IS_BROXTON(dev_priv
))
1520 bxt_enable_dc9(dev_priv
);
1521 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1522 hsw_enable_pc8(dev_priv
);
1523 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1524 ret
= vlv_suspend_complete(dev_priv
);
1527 DRM_ERROR("Suspend complete failed: %d\n", ret
);
1529 intel_power_domains_init_hw(dev_priv
, true);
1534 pci_disable_device(drm_dev
->pdev
);
1536 * During hibernation on some platforms the BIOS may try to access
1537 * the device even though it's already in D3 and hang the machine. So
1538 * leave the device in D0 on those platforms and hope the BIOS will
1539 * power down the device properly. The issue was seen on multiple old
1540 * GENs with different BIOS vendors, so having an explicit blacklist
1541 * is inpractical; apply the workaround on everything pre GEN6. The
1542 * platforms where the issue was seen:
1543 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1547 if (!(hibernation
&& INTEL_INFO(dev_priv
)->gen
< 6))
1548 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
1550 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
1553 enable_rpm_wakeref_asserts(dev_priv
);
1558 int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
1563 DRM_ERROR("dev: %p\n", dev
);
1564 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1568 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
1569 state
.event
!= PM_EVENT_FREEZE
))
1572 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1575 error
= i915_drm_suspend(dev
);
1579 return i915_drm_suspend_late(dev
, false);
1582 static int i915_drm_resume(struct drm_device
*dev
)
1584 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1587 disable_rpm_wakeref_asserts(dev_priv
);
1589 ret
= i915_ggtt_enable_hw(dev
);
1591 DRM_ERROR("failed to re-enable GGTT\n");
1593 intel_csr_ucode_resume(dev_priv
);
1595 mutex_lock(&dev
->struct_mutex
);
1596 i915_gem_restore_gtt_mappings(dev
);
1597 mutex_unlock(&dev
->struct_mutex
);
1599 i915_restore_state(dev
);
1600 intel_opregion_setup(dev_priv
);
1602 intel_init_pch_refclk(dev
);
1603 drm_mode_config_reset(dev
);
1606 * Interrupts have to be enabled before any batches are run. If not the
1607 * GPU will hang. i915_gem_init_hw() will initiate batches to
1608 * update/restore the context.
1610 * Modeset enabling in intel_modeset_init_hw() also needs working
1613 intel_runtime_pm_enable_interrupts(dev_priv
);
1615 mutex_lock(&dev
->struct_mutex
);
1616 if (i915_gem_init_hw(dev
)) {
1617 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1618 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
1620 mutex_unlock(&dev
->struct_mutex
);
1622 intel_guc_resume(dev
);
1624 intel_modeset_init_hw(dev
);
1626 spin_lock_irq(&dev_priv
->irq_lock
);
1627 if (dev_priv
->display
.hpd_irq_setup
)
1628 dev_priv
->display
.hpd_irq_setup(dev_priv
);
1629 spin_unlock_irq(&dev_priv
->irq_lock
);
1631 intel_dp_mst_resume(dev
);
1633 intel_display_resume(dev
);
1636 * ... but also need to make sure that hotplug processing
1637 * doesn't cause havoc. Like in the driver load code we don't
1638 * bother with the tiny race here where we might loose hotplug
1641 intel_hpd_init(dev_priv
);
1642 /* Config may have changed between suspend and resume */
1643 drm_helper_hpd_irq_event(dev
);
1645 intel_opregion_register(dev_priv
);
1647 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
1649 mutex_lock(&dev_priv
->modeset_restore_lock
);
1650 dev_priv
->modeset_restore
= MODESET_DONE
;
1651 mutex_unlock(&dev_priv
->modeset_restore_lock
);
1653 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
1655 drm_kms_helper_poll_enable(dev
);
1657 enable_rpm_wakeref_asserts(dev_priv
);
1662 static int i915_drm_resume_early(struct drm_device
*dev
)
1664 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1668 * We have a resume ordering issue with the snd-hda driver also
1669 * requiring our device to be power up. Due to the lack of a
1670 * parent/child relationship we currently solve this with an early
1673 * FIXME: This should be solved with a special hdmi sink device or
1674 * similar so that power domains can be employed.
1678 * Note that we need to set the power state explicitly, since we
1679 * powered off the device during freeze and the PCI core won't power
1680 * it back up for us during thaw. Powering off the device during
1681 * freeze is not a hard requirement though, and during the
1682 * suspend/resume phases the PCI core makes sure we get here with the
1683 * device powered on. So in case we change our freeze logic and keep
1684 * the device powered we can also remove the following set power state
1687 ret
= pci_set_power_state(dev
->pdev
, PCI_D0
);
1689 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
1694 * Note that pci_enable_device() first enables any parent bridge
1695 * device and only then sets the power state for this device. The
1696 * bridge enabling is a nop though, since bridge devices are resumed
1697 * first. The order of enabling power and enabling the device is
1698 * imposed by the PCI core as described above, so here we preserve the
1699 * same order for the freeze/thaw phases.
1701 * TODO: eventually we should remove pci_disable_device() /
1702 * pci_enable_enable_device() from suspend/resume. Due to how they
1703 * depend on the device enable refcount we can't anyway depend on them
1704 * disabling/enabling the device.
1706 if (pci_enable_device(dev
->pdev
)) {
1711 pci_set_master(dev
->pdev
);
1713 disable_rpm_wakeref_asserts(dev_priv
);
1715 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
1716 ret
= vlv_resume_prepare(dev_priv
, false);
1718 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1721 intel_uncore_early_sanitize(dev_priv
, true);
1723 if (IS_BROXTON(dev_priv
)) {
1724 if (!dev_priv
->suspended_to_idle
)
1725 gen9_sanitize_dc_state(dev_priv
);
1726 bxt_disable_dc9(dev_priv
);
1727 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1728 hsw_disable_pc8(dev_priv
);
1731 intel_uncore_sanitize(dev_priv
);
1733 if (IS_BROXTON(dev_priv
) ||
1734 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
1735 intel_power_domains_init_hw(dev_priv
, true);
1737 enable_rpm_wakeref_asserts(dev_priv
);
1740 dev_priv
->suspended_to_idle
= false;
1745 int i915_resume_switcheroo(struct drm_device
*dev
)
1749 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1752 ret
= i915_drm_resume_early(dev
);
1756 return i915_drm_resume(dev
);
1760 * i915_reset - reset chip after a hang
1761 * @dev: drm device to reset
1763 * Reset the chip. Useful if a hang is detected. Returns zero on successful
1764 * reset or otherwise an error code.
1766 * Procedure is fairly simple:
1767 * - reset the chip using the reset reg
1768 * - re-init context state
1769 * - re-init hardware status page
1770 * - re-init ring buffer
1771 * - re-init interrupt state
1774 int i915_reset(struct drm_i915_private
*dev_priv
)
1776 struct drm_device
*dev
= &dev_priv
->drm
;
1777 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
1778 unsigned reset_counter
;
1781 intel_reset_gt_powersave(dev_priv
);
1783 mutex_lock(&dev
->struct_mutex
);
1785 /* Clear any previous failed attempts at recovery. Time to try again. */
1786 atomic_andnot(I915_WEDGED
, &error
->reset_counter
);
1788 /* Clear the reset-in-progress flag and increment the reset epoch. */
1789 reset_counter
= atomic_inc_return(&error
->reset_counter
);
1790 if (WARN_ON(__i915_reset_in_progress(reset_counter
))) {
1795 pr_notice("drm/i915: Resetting chip after gpu hang\n");
1797 i915_gem_reset(dev
);
1799 ret
= intel_gpu_reset(dev_priv
, ALL_ENGINES
);
1802 DRM_ERROR("Failed to reset chip: %i\n", ret
);
1804 DRM_DEBUG_DRIVER("GPU reset disabled\n");
1808 intel_overlay_reset(dev_priv
);
1810 /* Ok, now get things going again... */
1813 * Everything depends on having the GTT running, so we need to start
1814 * there. Fortunately we don't need to do this unless we reset the
1815 * chip at a PCI level.
1817 * Next we need to restore the context, but we don't use those
1820 * Ring buffer needs to be re-initialized in the KMS case, or if X
1821 * was running at the time of the reset (i.e. we weren't VT
1824 ret
= i915_gem_init_hw(dev
);
1826 DRM_ERROR("Failed hw init on reset %d\n", ret
);
1830 mutex_unlock(&dev
->struct_mutex
);
1833 * rps/rc6 re-init is necessary to restore state lost after the
1834 * reset and the re-install of gt irqs. Skip for ironlake per
1835 * previous concerns that it doesn't respond well to some forms
1836 * of re-init after reset.
1838 if (INTEL_INFO(dev
)->gen
> 5)
1839 intel_enable_gt_powersave(dev_priv
);
1844 atomic_or(I915_WEDGED
, &error
->reset_counter
);
1845 mutex_unlock(&dev
->struct_mutex
);
1849 static int i915_pm_suspend(struct device
*dev
)
1851 struct pci_dev
*pdev
= to_pci_dev(dev
);
1852 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1855 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1859 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1862 return i915_drm_suspend(drm_dev
);
1865 static int i915_pm_suspend_late(struct device
*dev
)
1867 struct drm_device
*drm_dev
= &dev_to_i915(dev
)->drm
;
1870 * We have a suspend ordering issue with the snd-hda driver also
1871 * requiring our device to be power up. Due to the lack of a
1872 * parent/child relationship we currently solve this with an late
1875 * FIXME: This should be solved with a special hdmi sink device or
1876 * similar so that power domains can be employed.
1878 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1881 return i915_drm_suspend_late(drm_dev
, false);
1884 static int i915_pm_poweroff_late(struct device
*dev
)
1886 struct drm_device
*drm_dev
= &dev_to_i915(dev
)->drm
;
1888 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1891 return i915_drm_suspend_late(drm_dev
, true);
1894 static int i915_pm_resume_early(struct device
*dev
)
1896 struct drm_device
*drm_dev
= &dev_to_i915(dev
)->drm
;
1898 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1901 return i915_drm_resume_early(drm_dev
);
1904 static int i915_pm_resume(struct device
*dev
)
1906 struct drm_device
*drm_dev
= &dev_to_i915(dev
)->drm
;
1908 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1911 return i915_drm_resume(drm_dev
);
1914 /* freeze: before creating the hibernation_image */
1915 static int i915_pm_freeze(struct device
*dev
)
1917 return i915_pm_suspend(dev
);
1920 static int i915_pm_freeze_late(struct device
*dev
)
1924 ret
= i915_pm_suspend_late(dev
);
1928 ret
= i915_gem_freeze_late(dev_to_i915(dev
));
1935 /* thaw: called after creating the hibernation image, but before turning off. */
1936 static int i915_pm_thaw_early(struct device
*dev
)
1938 return i915_pm_resume_early(dev
);
1941 static int i915_pm_thaw(struct device
*dev
)
1943 return i915_pm_resume(dev
);
1946 /* restore: called after loading the hibernation image. */
1947 static int i915_pm_restore_early(struct device
*dev
)
1949 return i915_pm_resume_early(dev
);
1952 static int i915_pm_restore(struct device
*dev
)
1954 return i915_pm_resume(dev
);
1958 * Save all Gunit registers that may be lost after a D3 and a subsequent
1959 * S0i[R123] transition. The list of registers needing a save/restore is
1960 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1961 * registers in the following way:
1962 * - Driver: saved/restored by the driver
1963 * - Punit : saved/restored by the Punit firmware
1964 * - No, w/o marking: no need to save/restore, since the register is R/O or
1965 * used internally by the HW in a way that doesn't depend
1966 * keeping the content across a suspend/resume.
1967 * - Debug : used for debugging
1969 * We save/restore all registers marked with 'Driver', with the following
1971 * - Registers out of use, including also registers marked with 'Debug'.
1972 * These have no effect on the driver's operation, so we don't save/restore
1973 * them to reduce the overhead.
1974 * - Registers that are fully setup by an initialization function called from
1975 * the resume path. For example many clock gating and RPS/RC6 registers.
1976 * - Registers that provide the right functionality with their reset defaults.
1978 * TODO: Except for registers that based on the above 3 criteria can be safely
1979 * ignored, we save/restore all others, practically treating the HW context as
1980 * a black-box for the driver. Further investigation is needed to reduce the
1981 * saved/restored registers even further, by following the same 3 criteria.
1983 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1985 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1988 /* GAM 0x4000-0x4770 */
1989 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1990 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1991 s
->arb_mode
= I915_READ(ARB_MODE
);
1992 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1993 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1995 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1996 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1998 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1999 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
2001 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
2002 s
->ecochk
= I915_READ(GAM_ECOCHK
);
2003 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
2004 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
2006 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
2008 /* MBC 0x9024-0x91D0, 0x8500 */
2009 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
2010 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
2011 s
->mbctl
= I915_READ(GEN6_MBCTL
);
2013 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2014 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
2015 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
2016 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
2017 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
2018 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
2019 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
2021 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2022 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
2023 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
2024 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
2025 s
->ecobus
= I915_READ(ECOBUS
);
2026 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
2027 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
2028 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
2029 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
2030 s
->rcedata
= I915_READ(VLV_RCEDATA
);
2031 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
2033 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2034 s
->gt_imr
= I915_READ(GTIMR
);
2035 s
->gt_ier
= I915_READ(GTIER
);
2036 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
2037 s
->pm_ier
= I915_READ(GEN6_PMIER
);
2039 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2040 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
2042 /* GT SA CZ domain, 0x100000-0x138124 */
2043 s
->tilectl
= I915_READ(TILECTL
);
2044 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
2045 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2046 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2047 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
2049 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2050 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
2051 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
2052 s
->pcbr
= I915_READ(VLV_PCBR
);
2053 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
2056 * Not saving any of:
2057 * DFT, 0x9800-0x9EC0
2058 * SARB, 0xB000-0xB1FC
2059 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2064 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
2066 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
2070 /* GAM 0x4000-0x4770 */
2071 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
2072 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
2073 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
2074 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
2075 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
2077 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
2078 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
2080 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
2081 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
2083 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
2084 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
2085 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
2086 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
2088 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
2090 /* MBC 0x9024-0x91D0, 0x8500 */
2091 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
2092 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
2093 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
2095 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2096 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
2097 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
2098 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
2099 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
2100 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
2101 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
2103 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2104 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
2105 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
2106 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
2107 I915_WRITE(ECOBUS
, s
->ecobus
);
2108 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
2109 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
2110 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
2111 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
2112 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
2113 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
2115 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2116 I915_WRITE(GTIMR
, s
->gt_imr
);
2117 I915_WRITE(GTIER
, s
->gt_ier
);
2118 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
2119 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
2121 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
2122 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
2124 /* GT SA CZ domain, 0x100000-0x138124 */
2125 I915_WRITE(TILECTL
, s
->tilectl
);
2126 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
2128 * Preserve the GT allow wake and GFX force clock bit, they are not
2129 * be restored, as they are used to control the s0ix suspend/resume
2130 * sequence by the caller.
2132 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2133 val
&= VLV_GTLC_ALLOWWAKEREQ
;
2134 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
2135 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2137 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2138 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
2139 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
2140 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2142 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
2144 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2145 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
2146 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
2147 I915_WRITE(VLV_PCBR
, s
->pcbr
);
2148 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
2151 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
2156 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
2157 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
2159 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
2160 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
2165 err
= intel_wait_for_register(dev_priv
,
2166 VLV_GTLC_SURVIVABILITY_REG
,
2167 VLV_GFX_CLK_STATUS_BIT
,
2168 VLV_GFX_CLK_STATUS_BIT
,
2171 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2172 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
2177 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
2182 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
2183 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
2185 val
|= VLV_GTLC_ALLOWWAKEREQ
;
2186 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
2187 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
2189 err
= intel_wait_for_register(dev_priv
,
2191 VLV_GTLC_ALLOWWAKEACK
,
2195 DRM_ERROR("timeout disabling GT waking\n");
2200 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
2207 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
2208 val
= wait_for_on
? mask
: 0;
2209 if ((I915_READ(VLV_GTLC_PW_STATUS
) & mask
) == val
)
2212 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2214 I915_READ(VLV_GTLC_PW_STATUS
));
2217 * RC6 transitioning can be delayed up to 2 msec (see
2218 * valleyview_enable_rps), use 3 msec for safety.
2220 err
= intel_wait_for_register(dev_priv
,
2221 VLV_GTLC_PW_STATUS
, mask
, val
,
2224 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2225 onoff(wait_for_on
));
2230 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
2232 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
2235 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2236 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
2239 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
2245 * Bspec defines the following GT well on flags as debug only, so
2246 * don't treat them as hard failures.
2248 (void)vlv_wait_for_gt_wells(dev_priv
, false);
2250 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
2251 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
2253 vlv_check_no_gt_access(dev_priv
);
2255 err
= vlv_force_gfx_clock(dev_priv
, true);
2259 err
= vlv_allow_gt_wake(dev_priv
, false);
2263 if (!IS_CHERRYVIEW(dev_priv
))
2264 vlv_save_gunit_s0ix_state(dev_priv
);
2266 err
= vlv_force_gfx_clock(dev_priv
, false);
2273 /* For safety always re-enable waking and disable gfx clock forcing */
2274 vlv_allow_gt_wake(dev_priv
, true);
2276 vlv_force_gfx_clock(dev_priv
, false);
2281 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
2284 struct drm_device
*dev
= &dev_priv
->drm
;
2289 * If any of the steps fail just try to continue, that's the best we
2290 * can do at this point. Return the first error code (which will also
2291 * leave RPM permanently disabled).
2293 ret
= vlv_force_gfx_clock(dev_priv
, true);
2295 if (!IS_CHERRYVIEW(dev_priv
))
2296 vlv_restore_gunit_s0ix_state(dev_priv
);
2298 err
= vlv_allow_gt_wake(dev_priv
, true);
2302 err
= vlv_force_gfx_clock(dev_priv
, false);
2306 vlv_check_no_gt_access(dev_priv
);
2309 intel_init_clock_gating(dev
);
2310 i915_gem_restore_fences(dev
);
2316 static int intel_runtime_suspend(struct device
*device
)
2318 struct pci_dev
*pdev
= to_pci_dev(device
);
2319 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2320 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2323 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6())))
2326 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
2329 DRM_DEBUG_KMS("Suspending device\n");
2332 * We could deadlock here in case another thread holding struct_mutex
2333 * calls RPM suspend concurrently, since the RPM suspend will wait
2334 * first for this RPM suspend to finish. In this case the concurrent
2335 * RPM resume will be followed by its RPM suspend counterpart. Still
2336 * for consistency return -EAGAIN, which will reschedule this suspend.
2338 if (!mutex_trylock(&dev
->struct_mutex
)) {
2339 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2341 * Bump the expiration timestamp, otherwise the suspend won't
2344 pm_runtime_mark_last_busy(device
);
2349 disable_rpm_wakeref_asserts(dev_priv
);
2352 * We are safe here against re-faults, since the fault handler takes
2355 i915_gem_release_all_mmaps(dev_priv
);
2356 mutex_unlock(&dev
->struct_mutex
);
2358 intel_guc_suspend(dev
);
2360 intel_runtime_pm_disable_interrupts(dev_priv
);
2363 if (IS_BROXTON(dev_priv
)) {
2364 bxt_display_core_uninit(dev_priv
);
2365 bxt_enable_dc9(dev_priv
);
2366 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2367 hsw_enable_pc8(dev_priv
);
2368 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2369 ret
= vlv_suspend_complete(dev_priv
);
2373 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
2374 intel_runtime_pm_enable_interrupts(dev_priv
);
2376 enable_rpm_wakeref_asserts(dev_priv
);
2381 intel_uncore_forcewake_reset(dev_priv
, false);
2383 enable_rpm_wakeref_asserts(dev_priv
);
2384 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2386 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
2387 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2389 dev_priv
->pm
.suspended
= true;
2392 * FIXME: We really should find a document that references the arguments
2395 if (IS_BROADWELL(dev_priv
)) {
2397 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2398 * being detected, and the call we do at intel_runtime_resume()
2399 * won't be able to restore them. Since PCI_D3hot matches the
2400 * actual specification and appears to be working, use it.
2402 intel_opregion_notify_adapter(dev_priv
, PCI_D3hot
);
2405 * current versions of firmware which depend on this opregion
2406 * notification have repurposed the D1 definition to mean
2407 * "runtime suspended" vs. what you would normally expect (D3)
2408 * to distinguish it from notifications that might be sent via
2411 intel_opregion_notify_adapter(dev_priv
, PCI_D1
);
2414 assert_forcewakes_inactive(dev_priv
);
2416 if (!IS_VALLEYVIEW(dev_priv
) || !IS_CHERRYVIEW(dev_priv
))
2417 intel_hpd_poll_init(dev_priv
);
2419 DRM_DEBUG_KMS("Device suspended\n");
2423 static int intel_runtime_resume(struct device
*device
)
2425 struct pci_dev
*pdev
= to_pci_dev(device
);
2426 struct drm_device
*dev
= pci_get_drvdata(pdev
);
2427 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2430 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
2433 DRM_DEBUG_KMS("Resuming device\n");
2435 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
2436 disable_rpm_wakeref_asserts(dev_priv
);
2438 intel_opregion_notify_adapter(dev_priv
, PCI_D0
);
2439 dev_priv
->pm
.suspended
= false;
2440 if (intel_uncore_unclaimed_mmio(dev_priv
))
2441 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2443 intel_guc_resume(dev
);
2445 if (IS_GEN6(dev_priv
))
2446 intel_init_pch_refclk(dev
);
2448 if (IS_BROXTON(dev
)) {
2449 bxt_disable_dc9(dev_priv
);
2450 bxt_display_core_init(dev_priv
, true);
2451 if (dev_priv
->csr
.dmc_payload
&&
2452 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
2453 gen9_enable_dc5(dev_priv
);
2454 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
2455 hsw_disable_pc8(dev_priv
);
2456 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
2457 ret
= vlv_resume_prepare(dev_priv
, true);
2461 * No point of rolling back things in case of an error, as the best
2462 * we can do is to hope that things will still work (and disable RPM).
2464 i915_gem_init_swizzling(dev
);
2465 gen6_update_ring_freq(dev_priv
);
2467 intel_runtime_pm_enable_interrupts(dev_priv
);
2470 * On VLV/CHV display interrupts are part of the display
2471 * power well, so hpd is reinitialized from there. For
2472 * everyone else do it here.
2474 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
2475 intel_hpd_init(dev_priv
);
2477 enable_rpm_wakeref_asserts(dev_priv
);
2480 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
2482 DRM_DEBUG_KMS("Device resumed\n");
2487 const struct dev_pm_ops i915_pm_ops
= {
2489 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2492 .suspend
= i915_pm_suspend
,
2493 .suspend_late
= i915_pm_suspend_late
,
2494 .resume_early
= i915_pm_resume_early
,
2495 .resume
= i915_pm_resume
,
2499 * @freeze, @freeze_late : called (1) before creating the
2500 * hibernation image [PMSG_FREEZE] and
2501 * (2) after rebooting, before restoring
2502 * the image [PMSG_QUIESCE]
2503 * @thaw, @thaw_early : called (1) after creating the hibernation
2504 * image, before writing it [PMSG_THAW]
2505 * and (2) after failing to create or
2506 * restore the image [PMSG_RECOVER]
2507 * @poweroff, @poweroff_late: called after writing the hibernation
2508 * image, before rebooting [PMSG_HIBERNATE]
2509 * @restore, @restore_early : called after rebooting and restoring the
2510 * hibernation image [PMSG_RESTORE]
2512 .freeze
= i915_pm_freeze
,
2513 .freeze_late
= i915_pm_freeze_late
,
2514 .thaw_early
= i915_pm_thaw_early
,
2515 .thaw
= i915_pm_thaw
,
2516 .poweroff
= i915_pm_suspend
,
2517 .poweroff_late
= i915_pm_poweroff_late
,
2518 .restore_early
= i915_pm_restore_early
,
2519 .restore
= i915_pm_restore
,
2521 /* S0ix (via runtime suspend) event handlers */
2522 .runtime_suspend
= intel_runtime_suspend
,
2523 .runtime_resume
= intel_runtime_resume
,
2526 static const struct vm_operations_struct i915_gem_vm_ops
= {
2527 .fault
= i915_gem_fault
,
2528 .open
= drm_gem_vm_open
,
2529 .close
= drm_gem_vm_close
,
2532 static const struct file_operations i915_driver_fops
= {
2533 .owner
= THIS_MODULE
,
2535 .release
= drm_release
,
2536 .unlocked_ioctl
= drm_ioctl
,
2537 .mmap
= drm_gem_mmap
,
2540 #ifdef CONFIG_COMPAT
2541 .compat_ioctl
= i915_compat_ioctl
,
2543 .llseek
= noop_llseek
,
2547 i915_gem_reject_pin_ioctl(struct drm_device
*dev
, void *data
,
2548 struct drm_file
*file
)
2553 static const struct drm_ioctl_desc i915_ioctls
[] = {
2554 DRM_IOCTL_DEF_DRV(I915_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2555 DRM_IOCTL_DEF_DRV(I915_FLUSH
, drm_noop
, DRM_AUTH
),
2556 DRM_IOCTL_DEF_DRV(I915_FLIP
, drm_noop
, DRM_AUTH
),
2557 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER
, drm_noop
, DRM_AUTH
),
2558 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT
, drm_noop
, DRM_AUTH
),
2559 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT
, drm_noop
, DRM_AUTH
),
2560 DRM_IOCTL_DEF_DRV(I915_GETPARAM
, i915_getparam
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2561 DRM_IOCTL_DEF_DRV(I915_SETPARAM
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2562 DRM_IOCTL_DEF_DRV(I915_ALLOC
, drm_noop
, DRM_AUTH
),
2563 DRM_IOCTL_DEF_DRV(I915_FREE
, drm_noop
, DRM_AUTH
),
2564 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2565 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER
, drm_noop
, DRM_AUTH
),
2566 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2567 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2568 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE
, drm_noop
, DRM_AUTH
),
2569 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP
, drm_noop
, DRM_AUTH
),
2570 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2571 DRM_IOCTL_DEF_DRV(I915_GEM_INIT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2572 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER
, i915_gem_execbuffer
, DRM_AUTH
),
2573 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2
, i915_gem_execbuffer2
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2574 DRM_IOCTL_DEF_DRV(I915_GEM_PIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2575 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN
, i915_gem_reject_pin_ioctl
, DRM_AUTH
|DRM_ROOT_ONLY
),
2576 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY
, i915_gem_busy_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2577 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING
, i915_gem_set_caching_ioctl
, DRM_RENDER_ALLOW
),
2578 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING
, i915_gem_get_caching_ioctl
, DRM_RENDER_ALLOW
),
2579 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE
, i915_gem_throttle_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2580 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2581 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT
, drm_noop
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
),
2582 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE
, i915_gem_create_ioctl
, DRM_RENDER_ALLOW
),
2583 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD
, i915_gem_pread_ioctl
, DRM_RENDER_ALLOW
),
2584 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE
, i915_gem_pwrite_ioctl
, DRM_RENDER_ALLOW
),
2585 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP
, i915_gem_mmap_ioctl
, DRM_RENDER_ALLOW
),
2586 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT
, i915_gem_mmap_gtt_ioctl
, DRM_RENDER_ALLOW
),
2587 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN
, i915_gem_set_domain_ioctl
, DRM_RENDER_ALLOW
),
2588 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH
, i915_gem_sw_finish_ioctl
, DRM_RENDER_ALLOW
),
2589 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING
, i915_gem_set_tiling
, DRM_RENDER_ALLOW
),
2590 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING
, i915_gem_get_tiling
, DRM_RENDER_ALLOW
),
2591 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE
, i915_gem_get_aperture_ioctl
, DRM_RENDER_ALLOW
),
2592 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID
, intel_get_pipe_from_crtc_id
, 0),
2593 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE
, i915_gem_madvise_ioctl
, DRM_RENDER_ALLOW
),
2594 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE
, intel_overlay_put_image_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2595 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS
, intel_overlay_attrs_ioctl
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2596 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY
, intel_sprite_set_colorkey
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2597 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY
, drm_noop
, DRM_MASTER
|DRM_CONTROL_ALLOW
),
2598 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT
, i915_gem_wait_ioctl
, DRM_AUTH
|DRM_RENDER_ALLOW
),
2599 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE
, i915_gem_context_create_ioctl
, DRM_RENDER_ALLOW
),
2600 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY
, i915_gem_context_destroy_ioctl
, DRM_RENDER_ALLOW
),
2601 DRM_IOCTL_DEF_DRV(I915_REG_READ
, i915_reg_read_ioctl
, DRM_RENDER_ALLOW
),
2602 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS
, i915_gem_context_reset_stats_ioctl
, DRM_RENDER_ALLOW
),
2603 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR
, i915_gem_userptr_ioctl
, DRM_RENDER_ALLOW
),
2604 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM
, i915_gem_context_getparam_ioctl
, DRM_RENDER_ALLOW
),
2605 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM
, i915_gem_context_setparam_ioctl
, DRM_RENDER_ALLOW
),
2608 static struct drm_driver driver
= {
2609 /* Don't use MTRRs here; the Xserver or userspace app should
2610 * deal with them for Intel hardware.
2613 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
2614 DRIVER_RENDER
| DRIVER_MODESET
,
2615 .open
= i915_driver_open
,
2616 .lastclose
= i915_driver_lastclose
,
2617 .preclose
= i915_driver_preclose
,
2618 .postclose
= i915_driver_postclose
,
2619 .set_busid
= drm_pci_set_busid
,
2621 .gem_free_object
= i915_gem_free_object
,
2622 .gem_vm_ops
= &i915_gem_vm_ops
,
2624 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
2625 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
2626 .gem_prime_export
= i915_gem_prime_export
,
2627 .gem_prime_import
= i915_gem_prime_import
,
2629 .dumb_create
= i915_gem_dumb_create
,
2630 .dumb_map_offset
= i915_gem_mmap_gtt
,
2631 .dumb_destroy
= drm_gem_dumb_destroy
,
2632 .ioctls
= i915_ioctls
,
2633 .num_ioctls
= ARRAY_SIZE(i915_ioctls
),
2634 .fops
= &i915_driver_fops
,
2635 .name
= DRIVER_NAME
,
2636 .desc
= DRIVER_DESC
,
2637 .date
= DRIVER_DATE
,
2638 .major
= DRIVER_MAJOR
,
2639 .minor
= DRIVER_MINOR
,
2640 .patchlevel
= DRIVER_PATCHLEVEL
,