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i915: remove settable use_mi_batchbuffer_start
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 /* General customization:
34 */
35
36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
37
38 #define DRIVER_NAME "i915"
39 #define DRIVER_DESC "Intel Graphics"
40 #define DRIVER_DATE "20060119"
41
42 /* Interface history:
43 *
44 * 1.1: Original.
45 * 1.2: Add Power Management
46 * 1.3: Add vblank support
47 * 1.4: Fix cmdbuffer path, add heap destroy
48 * 1.5: Add vblank pipe configuration
49 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
50 * - Support vertical blank on secondary display pipe
51 */
52 #define DRIVER_MAJOR 1
53 #define DRIVER_MINOR 6
54 #define DRIVER_PATCHLEVEL 0
55
56 typedef struct _drm_i915_ring_buffer {
57 int tail_mask;
58 unsigned long Start;
59 unsigned long End;
60 unsigned long Size;
61 u8 *virtual_start;
62 int head;
63 int tail;
64 int space;
65 drm_local_map_t map;
66 } drm_i915_ring_buffer_t;
67
68 struct mem_block {
69 struct mem_block *next;
70 struct mem_block *prev;
71 int start;
72 int size;
73 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
74 };
75
76 typedef struct _drm_i915_vbl_swap {
77 struct list_head head;
78 drm_drawable_t drw_id;
79 unsigned int pipe;
80 unsigned int sequence;
81 } drm_i915_vbl_swap_t;
82
83 typedef struct drm_i915_private {
84 drm_local_map_t *sarea;
85 drm_local_map_t *mmio_map;
86
87 drm_i915_sarea_t *sarea_priv;
88 drm_i915_ring_buffer_t ring;
89
90 drm_dma_handle_t *status_page_dmah;
91 void *hw_status_page;
92 dma_addr_t dma_status_page;
93 unsigned long counter;
94 unsigned int status_gfx_addr;
95 drm_local_map_t hws_map;
96
97 unsigned int cpp;
98 int back_offset;
99 int front_offset;
100 int current_page;
101 int page_flipping;
102
103 wait_queue_head_t irq_queue;
104 atomic_t irq_received;
105 atomic_t irq_emitted;
106
107 int tex_lru_log_granularity;
108 int allow_batchbuffer;
109 struct mem_block *agp_heap;
110 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
111 int vblank_pipe;
112
113 spinlock_t swaps_lock;
114 drm_i915_vbl_swap_t vbl_swaps;
115 unsigned int swaps_pending;
116
117 /* Register state */
118 u8 saveLBB;
119 u32 saveDSPACNTR;
120 u32 saveDSPBCNTR;
121 u32 saveDSPARB;
122 u32 savePIPEACONF;
123 u32 savePIPEBCONF;
124 u32 savePIPEASRC;
125 u32 savePIPEBSRC;
126 u32 saveFPA0;
127 u32 saveFPA1;
128 u32 saveDPLL_A;
129 u32 saveDPLL_A_MD;
130 u32 saveHTOTAL_A;
131 u32 saveHBLANK_A;
132 u32 saveHSYNC_A;
133 u32 saveVTOTAL_A;
134 u32 saveVBLANK_A;
135 u32 saveVSYNC_A;
136 u32 saveBCLRPAT_A;
137 u32 savePIPEASTAT;
138 u32 saveDSPASTRIDE;
139 u32 saveDSPASIZE;
140 u32 saveDSPAPOS;
141 u32 saveDSPABASE;
142 u32 saveDSPASURF;
143 u32 saveDSPATILEOFF;
144 u32 savePFIT_PGM_RATIOS;
145 u32 saveBLC_PWM_CTL;
146 u32 saveBLC_PWM_CTL2;
147 u32 saveFPB0;
148 u32 saveFPB1;
149 u32 saveDPLL_B;
150 u32 saveDPLL_B_MD;
151 u32 saveHTOTAL_B;
152 u32 saveHBLANK_B;
153 u32 saveHSYNC_B;
154 u32 saveVTOTAL_B;
155 u32 saveVBLANK_B;
156 u32 saveVSYNC_B;
157 u32 saveBCLRPAT_B;
158 u32 savePIPEBSTAT;
159 u32 saveDSPBSTRIDE;
160 u32 saveDSPBSIZE;
161 u32 saveDSPBPOS;
162 u32 saveDSPBBASE;
163 u32 saveDSPBSURF;
164 u32 saveDSPBTILEOFF;
165 u32 saveVCLK_DIVISOR_VGA0;
166 u32 saveVCLK_DIVISOR_VGA1;
167 u32 saveVCLK_POST_DIV;
168 u32 saveVGACNTRL;
169 u32 saveADPA;
170 u32 saveLVDS;
171 u32 saveLVDSPP_ON;
172 u32 saveLVDSPP_OFF;
173 u32 saveDVOA;
174 u32 saveDVOB;
175 u32 saveDVOC;
176 u32 savePP_ON;
177 u32 savePP_OFF;
178 u32 savePP_CONTROL;
179 u32 savePP_CYCLE;
180 u32 savePFIT_CONTROL;
181 u32 save_palette_a[256];
182 u32 save_palette_b[256];
183 u32 saveFBC_CFB_BASE;
184 u32 saveFBC_LL_BASE;
185 u32 saveFBC_CONTROL;
186 u32 saveFBC_CONTROL2;
187 u32 saveIER;
188 u32 saveIIR;
189 u32 saveIMR;
190 u32 saveCACHE_MODE_0;
191 u32 saveD_STATE;
192 u32 saveDSPCLK_GATE_D;
193 u32 saveMI_ARB_STATE;
194 u32 saveSWF0[16];
195 u32 saveSWF1[16];
196 u32 saveSWF2[3];
197 u8 saveMSR;
198 u8 saveSR[8];
199 u8 saveGR[25];
200 u8 saveAR_INDEX;
201 u8 saveAR[21];
202 u8 saveDACMASK;
203 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
204 u8 saveCR[37];
205 } drm_i915_private_t;
206
207 extern struct drm_ioctl_desc i915_ioctls[];
208 extern int i915_max_ioctl;
209
210 /* i915_dma.c */
211 extern void i915_kernel_lost_context(struct drm_device * dev);
212 extern int i915_driver_load(struct drm_device *, unsigned long flags);
213 extern int i915_driver_unload(struct drm_device *);
214 extern void i915_driver_lastclose(struct drm_device * dev);
215 extern void i915_driver_preclose(struct drm_device *dev,
216 struct drm_file *file_priv);
217 extern int i915_driver_device_is_agp(struct drm_device * dev);
218 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
219 unsigned long arg);
220
221 /* i915_irq.c */
222 extern int i915_irq_emit(struct drm_device *dev, void *data,
223 struct drm_file *file_priv);
224 extern int i915_irq_wait(struct drm_device *dev, void *data,
225 struct drm_file *file_priv);
226
227 extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
228 extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
229 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
230 extern void i915_driver_irq_preinstall(struct drm_device * dev);
231 extern void i915_driver_irq_postinstall(struct drm_device * dev);
232 extern void i915_driver_irq_uninstall(struct drm_device * dev);
233 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
234 struct drm_file *file_priv);
235 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
236 struct drm_file *file_priv);
237 extern int i915_vblank_swap(struct drm_device *dev, void *data,
238 struct drm_file *file_priv);
239
240 /* i915_mem.c */
241 extern int i915_mem_alloc(struct drm_device *dev, void *data,
242 struct drm_file *file_priv);
243 extern int i915_mem_free(struct drm_device *dev, void *data,
244 struct drm_file *file_priv);
245 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
246 struct drm_file *file_priv);
247 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
248 struct drm_file *file_priv);
249 extern void i915_mem_takedown(struct mem_block **heap);
250 extern void i915_mem_release(struct drm_device * dev,
251 struct drm_file *file_priv, struct mem_block *heap);
252
253 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
254 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
255 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
256 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
257
258 #define I915_VERBOSE 0
259
260 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
261 volatile char *virt;
262
263 #define BEGIN_LP_RING(n) do { \
264 if (I915_VERBOSE) \
265 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
266 if (dev_priv->ring.space < (n)*4) \
267 i915_wait_ring(dev, (n)*4, __func__); \
268 outcount = 0; \
269 outring = dev_priv->ring.tail; \
270 ringmask = dev_priv->ring.tail_mask; \
271 virt = dev_priv->ring.virtual_start; \
272 } while (0)
273
274 #define OUT_RING(n) do { \
275 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
276 *(volatile unsigned int *)(virt + outring) = (n); \
277 outcount++; \
278 outring += 4; \
279 outring &= ringmask; \
280 } while (0)
281
282 #define ADVANCE_LP_RING() do { \
283 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
284 dev_priv->ring.tail = outring; \
285 dev_priv->ring.space -= outcount * 4; \
286 I915_WRITE(LP_RING + RING_TAIL, outring); \
287 } while(0)
288
289 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
290
291 /* Extended config space */
292 #define LBB 0xf4
293
294 /* VGA stuff */
295
296 #define VGA_ST01_MDA 0x3ba
297 #define VGA_ST01_CGA 0x3da
298
299 #define VGA_MSR_WRITE 0x3c2
300 #define VGA_MSR_READ 0x3cc
301 #define VGA_MSR_MEM_EN (1<<1)
302 #define VGA_MSR_CGA_MODE (1<<0)
303
304 #define VGA_SR_INDEX 0x3c4
305 #define VGA_SR_DATA 0x3c5
306
307 #define VGA_AR_INDEX 0x3c0
308 #define VGA_AR_VID_EN (1<<5)
309 #define VGA_AR_DATA_WRITE 0x3c0
310 #define VGA_AR_DATA_READ 0x3c1
311
312 #define VGA_GR_INDEX 0x3ce
313 #define VGA_GR_DATA 0x3cf
314 /* GR05 */
315 #define VGA_GR_MEM_READ_MODE_SHIFT 3
316 #define VGA_GR_MEM_READ_MODE_PLANE 1
317 /* GR06 */
318 #define VGA_GR_MEM_MODE_MASK 0xc
319 #define VGA_GR_MEM_MODE_SHIFT 2
320 #define VGA_GR_MEM_A0000_AFFFF 0
321 #define VGA_GR_MEM_A0000_BFFFF 1
322 #define VGA_GR_MEM_B0000_B7FFF 2
323 #define VGA_GR_MEM_B0000_BFFFF 3
324
325 #define VGA_DACMASK 0x3c6
326 #define VGA_DACRX 0x3c7
327 #define VGA_DACWX 0x3c8
328 #define VGA_DACDATA 0x3c9
329
330 #define VGA_CR_INDEX_MDA 0x3b4
331 #define VGA_CR_DATA_MDA 0x3b5
332 #define VGA_CR_INDEX_CGA 0x3d4
333 #define VGA_CR_DATA_CGA 0x3d5
334
335 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
336 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
337 #define CMD_REPORT_HEAD (7<<23)
338 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
339 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
340
341 #define INST_PARSER_CLIENT 0x00000000
342 #define INST_OP_FLUSH 0x02000000
343 #define INST_FLUSH_MAP_CACHE 0x00000001
344
345 #define BB1_START_ADDR_MASK (~0x7)
346 #define BB1_PROTECTED (1<<0)
347 #define BB1_UNPROTECTED (0<<0)
348 #define BB2_END_ADDR_MASK (~0x7)
349
350 /* Framebuffer compression */
351 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
352 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
353 #define FBC_CONTROL 0x03208
354 #define FBC_CTL_EN (1<<31)
355 #define FBC_CTL_PERIODIC (1<<30)
356 #define FBC_CTL_INTERVAL_SHIFT (16)
357 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
358 #define FBC_CTL_STRIDE_SHIFT (5)
359 #define FBC_CTL_FENCENO (1<<0)
360 #define FBC_COMMAND 0x0320c
361 #define FBC_CMD_COMPRESS (1<<0)
362 #define FBC_STATUS 0x03210
363 #define FBC_STAT_COMPRESSING (1<<31)
364 #define FBC_STAT_COMPRESSED (1<<30)
365 #define FBC_STAT_MODIFIED (1<<29)
366 #define FBC_STAT_CURRENT_LINE (1<<0)
367 #define FBC_CONTROL2 0x03214
368 #define FBC_CTL_FENCE_DBL (0<<4)
369 #define FBC_CTL_IDLE_IMM (0<<2)
370 #define FBC_CTL_IDLE_FULL (1<<2)
371 #define FBC_CTL_IDLE_LINE (2<<2)
372 #define FBC_CTL_IDLE_DEBUG (3<<2)
373 #define FBC_CTL_CPU_FENCE (1<<1)
374 #define FBC_CTL_PLANEA (0<<0)
375 #define FBC_CTL_PLANEB (1<<0)
376 #define FBC_FENCE_OFF 0x0321b
377
378 #define FBC_LL_SIZE (1536)
379 #define FBC_LL_PAD (32)
380
381 /* Interrupt bits:
382 */
383 #define USER_INT_FLAG (1<<1)
384 #define VSYNC_PIPEB_FLAG (1<<5)
385 #define VSYNC_PIPEA_FLAG (1<<7)
386 #define HWB_OOM_FLAG (1<<13) /* binner out of memory */
387
388 #define I915REG_HWSTAM 0x02098
389 #define I915REG_INT_IDENTITY_R 0x020a4
390 #define I915REG_INT_MASK_R 0x020a8
391 #define I915REG_INT_ENABLE_R 0x020a0
392
393 #define I915REG_PIPEASTAT 0x70024
394 #define I915REG_PIPEBSTAT 0x71024
395
396 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
397 #define I915_VBLANK_CLEAR (1UL<<1)
398
399 #define SRX_INDEX 0x3c4
400 #define SRX_DATA 0x3c5
401 #define SR01 1
402 #define SR01_SCREEN_OFF (1<<5)
403
404 #define PPCR 0x61204
405 #define PPCR_ON (1<<0)
406
407 #define DVOB 0x61140
408 #define DVOB_ON (1<<31)
409 #define DVOC 0x61160
410 #define DVOC_ON (1<<31)
411 #define LVDS 0x61180
412 #define LVDS_ON (1<<31)
413
414 #define ADPA 0x61100
415 #define ADPA_DPMS_MASK (~(3<<10))
416 #define ADPA_DPMS_ON (0<<10)
417 #define ADPA_DPMS_SUSPEND (1<<10)
418 #define ADPA_DPMS_STANDBY (2<<10)
419 #define ADPA_DPMS_OFF (3<<10)
420
421 #define NOPID 0x2094
422 #define LP_RING 0x2030
423 #define HP_RING 0x2040
424 /* The binner has its own ring buffer:
425 */
426 #define HWB_RING 0x2400
427
428 #define RING_TAIL 0x00
429 #define TAIL_ADDR 0x001FFFF8
430 #define RING_HEAD 0x04
431 #define HEAD_WRAP_COUNT 0xFFE00000
432 #define HEAD_WRAP_ONE 0x00200000
433 #define HEAD_ADDR 0x001FFFFC
434 #define RING_START 0x08
435 #define START_ADDR 0x0xFFFFF000
436 #define RING_LEN 0x0C
437 #define RING_NR_PAGES 0x001FF000
438 #define RING_REPORT_MASK 0x00000006
439 #define RING_REPORT_64K 0x00000002
440 #define RING_REPORT_128K 0x00000004
441 #define RING_NO_REPORT 0x00000000
442 #define RING_VALID_MASK 0x00000001
443 #define RING_VALID 0x00000001
444 #define RING_INVALID 0x00000000
445
446 /* Instruction parser error reg:
447 */
448 #define IPEIR 0x2088
449
450 /* Scratch pad debug 0 reg:
451 */
452 #define SCPD0 0x209c
453
454 /* Error status reg:
455 */
456 #define ESR 0x20b8
457
458 /* Secondary DMA fetch address debug reg:
459 */
460 #define DMA_FADD_S 0x20d4
461
462 /* Memory Interface Arbitration State
463 */
464 #define MI_ARB_STATE 0x20e4
465
466 /* Cache mode 0 reg.
467 * - Manipulating render cache behaviour is central
468 * to the concept of zone rendering, tuning this reg can help avoid
469 * unnecessary render cache reads and even writes (for z/stencil)
470 * at beginning and end of scene.
471 *
472 * - To change a bit, write to this reg with a mask bit set and the
473 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
474 */
475 #define Cache_Mode_0 0x2120
476 #define CACHE_MODE_0 0x2120
477 #define CM0_MASK_SHIFT 16
478 #define CM0_IZ_OPT_DISABLE (1<<6)
479 #define CM0_ZR_OPT_DISABLE (1<<5)
480 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
481 #define CM0_COLOR_EVICT_DISABLE (1<<3)
482 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
483 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
484
485
486 /* Graphics flush control. A CPU write flushes the GWB of all writes.
487 * The data is discarded.
488 */
489 #define GFX_FLSH_CNTL 0x2170
490
491 /* Binner control. Defines the location of the bin pointer list:
492 */
493 #define BINCTL 0x2420
494 #define BC_MASK (1 << 9)
495
496 /* Binned scene info.
497 */
498 #define BINSCENE 0x2428
499 #define BS_OP_LOAD (1 << 8)
500 #define BS_MASK (1 << 22)
501
502 /* Bin command parser debug reg:
503 */
504 #define BCPD 0x2480
505
506 /* Bin memory control debug reg:
507 */
508 #define BMCD 0x2484
509
510 /* Bin data cache debug reg:
511 */
512 #define BDCD 0x2488
513
514 /* Binner pointer cache debug reg:
515 */
516 #define BPCD 0x248c
517
518 /* Binner scratch pad debug reg:
519 */
520 #define BINSKPD 0x24f0
521
522 /* HWB scratch pad debug reg:
523 */
524 #define HWBSKPD 0x24f4
525
526 /* Binner memory pool reg:
527 */
528 #define BMP_BUFFER 0x2430
529 #define BMP_PAGE_SIZE_4K (0 << 10)
530 #define BMP_BUFFER_SIZE_SHIFT 1
531 #define BMP_ENABLE (1 << 0)
532
533 /* Get/put memory from the binner memory pool:
534 */
535 #define BMP_GET 0x2438
536 #define BMP_PUT 0x2440
537 #define BMP_OFFSET_SHIFT 5
538
539 /* 3D state packets:
540 */
541 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
542
543 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
544 #define SC_UPDATE_SCISSOR (0x1<<1)
545 #define SC_ENABLE_MASK (0x1<<0)
546 #define SC_ENABLE (0x1<<0)
547
548 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
549
550 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
551 #define SCI_YMIN_MASK (0xffff<<16)
552 #define SCI_XMIN_MASK (0xffff<<0)
553 #define SCI_YMAX_MASK (0xffff<<16)
554 #define SCI_XMAX_MASK (0xffff<<0)
555
556 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
557 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
558 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
559 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
560 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
561 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
562 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
563
564 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
565
566 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
567 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
568 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
569 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
570 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
571 #define XY_SRC_COPY_BLT_DST_TILED (1<<11)
572
573 #define MI_BATCH_BUFFER ((0x30<<23)|1)
574 #define MI_BATCH_BUFFER_START (0x31<<23)
575 #define MI_BATCH_BUFFER_END (0xA<<23)
576 #define MI_BATCH_NON_SECURE (1)
577 #define MI_BATCH_NON_SECURE_I965 (1<<8)
578
579 #define MI_WAIT_FOR_EVENT ((0x3<<23))
580 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
581 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
582 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
583
584 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
585
586 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
587 #define ASYNC_FLIP (1<<22)
588 #define DISPLAY_PLANE_A (0<<20)
589 #define DISPLAY_PLANE_B (1<<20)
590
591 /* Display regs */
592 #define DSPACNTR 0x70180
593 #define DSPBCNTR 0x71180
594 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
595
596 /* Define the region of interest for the binner:
597 */
598 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
599
600 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
601
602 #define CMD_MI_FLUSH (0x04 << 23)
603 #define MI_NO_WRITE_FLUSH (1 << 2)
604 #define MI_READ_FLUSH (1 << 0)
605 #define MI_EXE_FLUSH (1 << 1)
606 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
607 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
608
609 #define BREADCRUMB_BITS 31
610 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
611
612 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
613 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
614
615 #define BLC_PWM_CTL 0x61254
616 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
617
618 #define BLC_PWM_CTL2 0x61250
619 /**
620 * This is the most significant 15 bits of the number of backlight cycles in a
621 * complete cycle of the modulated backlight control.
622 *
623 * The actual value is this field multiplied by two.
624 */
625 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
626 #define BLM_LEGACY_MODE (1 << 16)
627 /**
628 * This is the number of cycles out of the backlight modulation cycle for which
629 * the backlight is on.
630 *
631 * This field must be no greater than the number of cycles in the complete
632 * backlight modulation cycle.
633 */
634 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
635 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
636
637 #define I915_GCFGC 0xf0
638 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
639 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
640 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
641 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
642
643 #define I855_HPLLCC 0xc0
644 #define I855_CLOCK_CONTROL_MASK (3 << 0)
645 #define I855_CLOCK_133_200 (0 << 0)
646 #define I855_CLOCK_100_200 (1 << 0)
647 #define I855_CLOCK_100_133 (2 << 0)
648 #define I855_CLOCK_166_250 (3 << 0)
649
650 /* p317, 319
651 */
652 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
653 #define VCLK2_VCO_N 0x600a
654 #define VCLK2_VCO_DIV_SEL 0x6012
655
656 #define VCLK_DIVISOR_VGA0 0x6000
657 #define VCLK_DIVISOR_VGA1 0x6004
658 #define VCLK_POST_DIV 0x6010
659 /** Selects a post divisor of 4 instead of 2. */
660 # define VGA1_PD_P2_DIV_4 (1 << 15)
661 /** Overrides the p2 post divisor field */
662 # define VGA1_PD_P1_DIV_2 (1 << 13)
663 # define VGA1_PD_P1_SHIFT 8
664 /** P1 value is 2 greater than this field */
665 # define VGA1_PD_P1_MASK (0x1f << 8)
666 /** Selects a post divisor of 4 instead of 2. */
667 # define VGA0_PD_P2_DIV_4 (1 << 7)
668 /** Overrides the p2 post divisor field */
669 # define VGA0_PD_P1_DIV_2 (1 << 5)
670 # define VGA0_PD_P1_SHIFT 0
671 /** P1 value is 2 greater than this field */
672 # define VGA0_PD_P1_MASK (0x1f << 0)
673
674 /* PCI D state control register */
675 #define D_STATE 0x6104
676 #define DSPCLK_GATE_D 0x6200
677
678 /* I830 CRTC registers */
679 #define HTOTAL_A 0x60000
680 #define HBLANK_A 0x60004
681 #define HSYNC_A 0x60008
682 #define VTOTAL_A 0x6000c
683 #define VBLANK_A 0x60010
684 #define VSYNC_A 0x60014
685 #define PIPEASRC 0x6001c
686 #define BCLRPAT_A 0x60020
687 #define VSYNCSHIFT_A 0x60028
688
689 #define HTOTAL_B 0x61000
690 #define HBLANK_B 0x61004
691 #define HSYNC_B 0x61008
692 #define VTOTAL_B 0x6100c
693 #define VBLANK_B 0x61010
694 #define VSYNC_B 0x61014
695 #define PIPEBSRC 0x6101c
696 #define BCLRPAT_B 0x61020
697 #define VSYNCSHIFT_B 0x61028
698
699 #define PP_STATUS 0x61200
700 # define PP_ON (1 << 31)
701 /**
702 * Indicates that all dependencies of the panel are on:
703 *
704 * - PLL enabled
705 * - pipe enabled
706 * - LVDS/DVOB/DVOC on
707 */
708 # define PP_READY (1 << 30)
709 # define PP_SEQUENCE_NONE (0 << 28)
710 # define PP_SEQUENCE_ON (1 << 28)
711 # define PP_SEQUENCE_OFF (2 << 28)
712 # define PP_SEQUENCE_MASK 0x30000000
713 #define PP_CONTROL 0x61204
714 # define POWER_TARGET_ON (1 << 0)
715
716 #define LVDSPP_ON 0x61208
717 #define LVDSPP_OFF 0x6120c
718 #define PP_CYCLE 0x61210
719
720 #define PFIT_CONTROL 0x61230
721 # define PFIT_ENABLE (1 << 31)
722 # define PFIT_PIPE_MASK (3 << 29)
723 # define PFIT_PIPE_SHIFT 29
724 # define VERT_INTERP_DISABLE (0 << 10)
725 # define VERT_INTERP_BILINEAR (1 << 10)
726 # define VERT_INTERP_MASK (3 << 10)
727 # define VERT_AUTO_SCALE (1 << 9)
728 # define HORIZ_INTERP_DISABLE (0 << 6)
729 # define HORIZ_INTERP_BILINEAR (1 << 6)
730 # define HORIZ_INTERP_MASK (3 << 6)
731 # define HORIZ_AUTO_SCALE (1 << 5)
732 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
733
734 #define PFIT_PGM_RATIOS 0x61234
735 # define PFIT_VERT_SCALE_MASK 0xfff00000
736 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
737
738 #define PFIT_AUTO_RATIOS 0x61238
739
740
741 #define DPLL_A 0x06014
742 #define DPLL_B 0x06018
743 # define DPLL_VCO_ENABLE (1 << 31)
744 # define DPLL_DVO_HIGH_SPEED (1 << 30)
745 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
746 # define DPLL_VGA_MODE_DIS (1 << 28)
747 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
748 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
749 # define DPLL_MODE_MASK (3 << 26)
750 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
751 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
752 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
753 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
754 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
755 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
756 /**
757 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
758 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
759 */
760 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
761 /**
762 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
763 * this field (only one bit may be set).
764 */
765 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
766 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
767 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
768 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
769 # define PLL_REF_INPUT_DREFCLK (0 << 13)
770 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
771 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
772 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
773 # define PLL_REF_INPUT_MASK (3 << 13)
774 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
775 /*
776 * Parallel to Serial Load Pulse phase selection.
777 * Selects the phase for the 10X DPLL clock for the PCIe
778 * digital display port. The range is 4 to 13; 10 or more
779 * is just a flip delay. The default is 6
780 */
781 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
782 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
783
784 /**
785 * SDVO multiplier for 945G/GM. Not used on 965.
786 *
787 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
788 */
789 # define SDVO_MULTIPLIER_MASK 0x000000ff
790 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
791 # define SDVO_MULTIPLIER_SHIFT_VGA 0
792
793 /** @defgroup DPLL_MD
794 * @{
795 */
796 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
797 #define DPLL_A_MD 0x0601c
798 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
799 #define DPLL_B_MD 0x06020
800 /**
801 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
802 *
803 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
804 */
805 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
806 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
807 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
808 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
809 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
810 /**
811 * SDVO/UDI pixel multiplier.
812 *
813 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
814 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
815 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
816 * dummy bytes in the datastream at an increased clock rate, with both sides of
817 * the link knowing how many bytes are fill.
818 *
819 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
820 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
821 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
822 * through an SDVO command.
823 *
824 * This register field has values of multiplication factor minus 1, with
825 * a maximum multiplier of 5 for SDVO.
826 */
827 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
828 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
829 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
830 * This best be set to the default value (3) or the CRT won't work. No,
831 * I don't entirely understand what this does...
832 */
833 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
834 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
835 /** @} */
836
837 #define DPLL_TEST 0x606c
838 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
839 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
840 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
841 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
842 # define DPLLB_TEST_N_BYPASS (1 << 19)
843 # define DPLLB_TEST_M_BYPASS (1 << 18)
844 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
845 # define DPLLA_TEST_N_BYPASS (1 << 3)
846 # define DPLLA_TEST_M_BYPASS (1 << 2)
847 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
848
849 #define ADPA 0x61100
850 #define ADPA_DAC_ENABLE (1<<31)
851 #define ADPA_DAC_DISABLE 0
852 #define ADPA_PIPE_SELECT_MASK (1<<30)
853 #define ADPA_PIPE_A_SELECT 0
854 #define ADPA_PIPE_B_SELECT (1<<30)
855 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
856 #define ADPA_SETS_HVPOLARITY 0
857 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
858 #define ADPA_VSYNC_CNTL_ENABLE 0
859 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
860 #define ADPA_HSYNC_CNTL_ENABLE 0
861 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
862 #define ADPA_VSYNC_ACTIVE_LOW 0
863 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
864 #define ADPA_HSYNC_ACTIVE_LOW 0
865
866 #define FPA0 0x06040
867 #define FPA1 0x06044
868 #define FPB0 0x06048
869 #define FPB1 0x0604c
870 # define FP_N_DIV_MASK 0x003f0000
871 # define FP_N_DIV_SHIFT 16
872 # define FP_M1_DIV_MASK 0x00003f00
873 # define FP_M1_DIV_SHIFT 8
874 # define FP_M2_DIV_MASK 0x0000003f
875 # define FP_M2_DIV_SHIFT 0
876
877
878 #define PORT_HOTPLUG_EN 0x61110
879 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
880 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
881 # define TV_HOTPLUG_INT_EN (1 << 18)
882 # define CRT_HOTPLUG_INT_EN (1 << 9)
883 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
884
885 #define PORT_HOTPLUG_STAT 0x61114
886 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
887 # define TV_HOTPLUG_INT_STATUS (1 << 10)
888 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
889 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
890 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
891 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
892 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
893 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
894
895 #define SDVOB 0x61140
896 #define SDVOC 0x61160
897 #define SDVO_ENABLE (1 << 31)
898 #define SDVO_PIPE_B_SELECT (1 << 30)
899 #define SDVO_STALL_SELECT (1 << 29)
900 #define SDVO_INTERRUPT_ENABLE (1 << 26)
901 /**
902 * 915G/GM SDVO pixel multiplier.
903 *
904 * Programmed value is multiplier - 1, up to 5x.
905 *
906 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
907 */
908 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
909 #define SDVO_PORT_MULTIPLY_SHIFT 23
910 #define SDVO_PHASE_SELECT_MASK (15 << 19)
911 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
912 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
913 #define SDVOC_GANG_MODE (1 << 16)
914 #define SDVO_BORDER_ENABLE (1 << 7)
915 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
916 #define SDVO_DETECTED (1 << 2)
917 /* Bits to be preserved when writing */
918 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
919 #define SDVOC_PRESERVE_MASK (1 << 17)
920
921 /** @defgroup LVDS
922 * @{
923 */
924 /**
925 * This register controls the LVDS output enable, pipe selection, and data
926 * format selection.
927 *
928 * All of the clock/data pairs are force powered down by power sequencing.
929 */
930 #define LVDS 0x61180
931 /**
932 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
933 * the DPLL semantics change when the LVDS is assigned to that pipe.
934 */
935 # define LVDS_PORT_EN (1 << 31)
936 /** Selects pipe B for LVDS data. Must be set on pre-965. */
937 # define LVDS_PIPEB_SELECT (1 << 30)
938
939 /**
940 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
941 * pixel.
942 */
943 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
944 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
945 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
946 /**
947 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
948 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
949 * on.
950 */
951 # define LVDS_A3_POWER_MASK (3 << 6)
952 # define LVDS_A3_POWER_DOWN (0 << 6)
953 # define LVDS_A3_POWER_UP (3 << 6)
954 /**
955 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
956 * is set.
957 */
958 # define LVDS_CLKB_POWER_MASK (3 << 4)
959 # define LVDS_CLKB_POWER_DOWN (0 << 4)
960 # define LVDS_CLKB_POWER_UP (3 << 4)
961
962 /**
963 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
964 * setting for whether we are in dual-channel mode. The B3 pair will
965 * additionally only be powered up when LVDS_A3_POWER_UP is set.
966 */
967 # define LVDS_B0B3_POWER_MASK (3 << 2)
968 # define LVDS_B0B3_POWER_DOWN (0 << 2)
969 # define LVDS_B0B3_POWER_UP (3 << 2)
970
971 #define PIPEACONF 0x70008
972 #define PIPEACONF_ENABLE (1<<31)
973 #define PIPEACONF_DISABLE 0
974 #define PIPEACONF_DOUBLE_WIDE (1<<30)
975 #define I965_PIPECONF_ACTIVE (1<<30)
976 #define PIPEACONF_SINGLE_WIDE 0
977 #define PIPEACONF_PIPE_UNLOCKED 0
978 #define PIPEACONF_PIPE_LOCKED (1<<25)
979 #define PIPEACONF_PALETTE 0
980 #define PIPEACONF_GAMMA (1<<24)
981 #define PIPECONF_FORCE_BORDER (1<<25)
982 #define PIPECONF_PROGRESSIVE (0 << 21)
983 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
984 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
985
986 #define DSPARB 0x70030
987 #define DSPARB_CSTART_MASK (0x7f << 7)
988 #define DSPARB_CSTART_SHIFT 7
989 #define DSPARB_BSTART_MASK (0x7f)
990 #define DSPARB_BSTART_SHIFT 0
991
992 #define PIPEBCONF 0x71008
993 #define PIPEBCONF_ENABLE (1<<31)
994 #define PIPEBCONF_DISABLE 0
995 #define PIPEBCONF_DOUBLE_WIDE (1<<30)
996 #define PIPEBCONF_DISABLE 0
997 #define PIPEBCONF_GAMMA (1<<24)
998 #define PIPEBCONF_PALETTE 0
999
1000 #define PIPEBGCMAXRED 0x71010
1001 #define PIPEBGCMAXGREEN 0x71014
1002 #define PIPEBGCMAXBLUE 0x71018
1003 #define PIPEBSTAT 0x71024
1004 #define PIPEBFRAMEHIGH 0x71040
1005 #define PIPEBFRAMEPIXEL 0x71044
1006
1007 #define DSPACNTR 0x70180
1008 #define DSPBCNTR 0x71180
1009 #define DISPLAY_PLANE_ENABLE (1<<31)
1010 #define DISPLAY_PLANE_DISABLE 0
1011 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1012 #define DISPPLANE_GAMMA_DISABLE 0
1013 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1014 #define DISPPLANE_8BPP (0x2<<26)
1015 #define DISPPLANE_15_16BPP (0x4<<26)
1016 #define DISPPLANE_16BPP (0x5<<26)
1017 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1018 #define DISPPLANE_32BPP (0x7<<26)
1019 #define DISPPLANE_STEREO_ENABLE (1<<25)
1020 #define DISPPLANE_STEREO_DISABLE 0
1021 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1022 #define DISPPLANE_SEL_PIPE_A 0
1023 #define DISPPLANE_SEL_PIPE_B (1<<24)
1024 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1025 #define DISPPLANE_SRC_KEY_DISABLE 0
1026 #define DISPPLANE_LINE_DOUBLE (1<<20)
1027 #define DISPPLANE_NO_LINE_DOUBLE 0
1028 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1029 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1030 /* plane B only */
1031 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1032 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1033 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1034 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1035
1036 #define DSPABASE 0x70184
1037 #define DSPASTRIDE 0x70188
1038
1039 #define DSPBBASE 0x71184
1040 #define DSPBADDR DSPBBASE
1041 #define DSPBSTRIDE 0x71188
1042
1043 #define DSPAKEYVAL 0x70194
1044 #define DSPAKEYMASK 0x70198
1045
1046 #define DSPAPOS 0x7018C /* reserved */
1047 #define DSPASIZE 0x70190
1048 #define DSPBPOS 0x7118C
1049 #define DSPBSIZE 0x71190
1050
1051 #define DSPASURF 0x7019C
1052 #define DSPATILEOFF 0x701A4
1053
1054 #define DSPBSURF 0x7119C
1055 #define DSPBTILEOFF 0x711A4
1056
1057 #define VGACNTRL 0x71400
1058 # define VGA_DISP_DISABLE (1 << 31)
1059 # define VGA_2X_MODE (1 << 30)
1060 # define VGA_PIPE_B_SELECT (1 << 29)
1061
1062 /*
1063 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1064 * of video memory available to the BIOS in SWF1.
1065 */
1066
1067 #define SWF0 0x71410
1068
1069 /*
1070 * 855 scratch registers.
1071 */
1072 #define SWF10 0x70410
1073
1074 #define SWF30 0x72414
1075
1076 /*
1077 * Overlay registers. These are overlay registers accessed via MMIO.
1078 * Those loaded via the overlay register page are defined in i830_video.c.
1079 */
1080 #define OVADD 0x30000
1081
1082 #define DOVSTA 0x30008
1083 #define OC_BUF (0x3<<20)
1084
1085 #define OGAMC5 0x30010
1086 #define OGAMC4 0x30014
1087 #define OGAMC3 0x30018
1088 #define OGAMC2 0x3001c
1089 #define OGAMC1 0x30020
1090 #define OGAMC0 0x30024
1091 /*
1092 * Palette registers
1093 */
1094 #define PALETTE_A 0x0a000
1095 #define PALETTE_B 0x0a800
1096
1097 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1098 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1099 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1100 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
1101 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1102
1103 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
1104 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1105 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1106 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
1107 (dev)->pci_device == 0x27AE)
1108 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1109 (dev)->pci_device == 0x2982 || \
1110 (dev)->pci_device == 0x2992 || \
1111 (dev)->pci_device == 0x29A2 || \
1112 (dev)->pci_device == 0x2A02 || \
1113 (dev)->pci_device == 0x2A12 || \
1114 (dev)->pci_device == 0x2A42 || \
1115 (dev)->pci_device == 0x2E02 || \
1116 (dev)->pci_device == 0x2E12 || \
1117 (dev)->pci_device == 0x2E22)
1118
1119 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1120
1121 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1122
1123 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1124 (dev)->pci_device == 0x2E12 || \
1125 (dev)->pci_device == 0x2E22)
1126
1127 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1128 (dev)->pci_device == 0x29B2 || \
1129 (dev)->pci_device == 0x29D2)
1130
1131 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1132 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1133
1134 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1135 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1136
1137 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
1138
1139 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
1140
1141 #endif
Linux kernel - Deliverables
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