1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
105 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
106 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
107 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
108 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
112 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
113 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
123 #define I915_GEM_GPU_DOMAINS \
124 (I915_GEM_DOMAIN_RENDER | \
125 I915_GEM_DOMAIN_SAMPLER | \
126 I915_GEM_DOMAIN_COMMAND | \
127 I915_GEM_DOMAIN_INSTRUCTION | \
128 I915_GEM_DOMAIN_VERTEX)
130 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
132 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
133 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
134 if ((intel_encoder)->base.crtc == (__crtc))
136 struct drm_i915_private
;
139 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
140 /* real shared dpll ids must be >= 0 */
144 #define I915_NUM_PLLS 2
146 struct intel_dpll_hw_state
{
153 struct intel_shared_dpll
{
154 int refcount
; /* count of number of CRTCs sharing this PLL */
155 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
156 bool on
; /* is the PLL actually active? Disabled during modeset */
158 /* should match the index in the dev_priv->shared_dplls array */
159 enum intel_dpll_id id
;
160 struct intel_dpll_hw_state hw_state
;
161 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
162 struct intel_shared_dpll
*pll
);
163 void (*enable
)(struct drm_i915_private
*dev_priv
,
164 struct intel_shared_dpll
*pll
);
165 void (*disable
)(struct drm_i915_private
*dev_priv
,
166 struct intel_shared_dpll
*pll
);
167 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
168 struct intel_shared_dpll
*pll
,
169 struct intel_dpll_hw_state
*hw_state
);
172 /* Used by dp and fdi links */
173 struct intel_link_m_n
{
181 void intel_link_compute_m_n(int bpp
, int nlanes
,
182 int pixel_clock
, int link_clock
,
183 struct intel_link_m_n
*m_n
);
185 struct intel_ddi_plls
{
191 /* Interface history:
194 * 1.2: Add Power Management
195 * 1.3: Add vblank support
196 * 1.4: Fix cmdbuffer path, add heap destroy
197 * 1.5: Add vblank pipe configuration
198 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
199 * - Support vertical blank on secondary display pipe
201 #define DRIVER_MAJOR 1
202 #define DRIVER_MINOR 6
203 #define DRIVER_PATCHLEVEL 0
205 #define WATCH_LISTS 0
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
213 struct drm_i915_gem_phys_object
{
215 struct page
**page_list
;
216 drm_dma_handle_t
*handle
;
217 struct drm_i915_gem_object
*cur_obj
;
220 struct opregion_header
;
221 struct opregion_acpi
;
222 struct opregion_swsci
;
223 struct opregion_asle
;
225 struct intel_opregion
{
226 struct opregion_header __iomem
*header
;
227 struct opregion_acpi __iomem
*acpi
;
228 struct opregion_swsci __iomem
*swsci
;
229 u32 swsci_gbda_sub_functions
;
230 u32 swsci_sbcb_sub_functions
;
231 struct opregion_asle __iomem
*asle
;
233 u32 __iomem
*lid_state
;
235 #define OPREGION_SIZE (8*1024)
237 struct intel_overlay
;
238 struct intel_overlay_error_state
;
240 struct drm_i915_master_private
{
241 drm_local_map_t
*sarea
;
242 struct _drm_i915_sarea
*sarea_priv
;
244 #define I915_FENCE_REG_NONE -1
245 #define I915_MAX_NUM_FENCES 32
246 /* 32 fences + sign bit for FENCE_REG_NONE */
247 #define I915_MAX_NUM_FENCE_BITS 6
249 struct drm_i915_fence_reg
{
250 struct list_head lru_list
;
251 struct drm_i915_gem_object
*obj
;
255 struct sdvo_device_mapping
{
264 struct intel_display_error_state
;
266 struct drm_i915_error_state
{
274 bool waiting
[I915_NUM_RINGS
];
275 u32 pipestat
[I915_MAX_PIPES
];
276 u32 tail
[I915_NUM_RINGS
];
277 u32 head
[I915_NUM_RINGS
];
278 u32 ctl
[I915_NUM_RINGS
];
279 u32 ipeir
[I915_NUM_RINGS
];
280 u32 ipehr
[I915_NUM_RINGS
];
281 u32 instdone
[I915_NUM_RINGS
];
282 u32 acthd
[I915_NUM_RINGS
];
283 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
284 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
285 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
286 /* our own tracking of ring head and tail */
287 u32 cpu_ring_head
[I915_NUM_RINGS
];
288 u32 cpu_ring_tail
[I915_NUM_RINGS
];
289 u32 error
; /* gen6+ */
290 u32 err_int
; /* gen7 */
291 u32 instpm
[I915_NUM_RINGS
];
292 u32 instps
[I915_NUM_RINGS
];
293 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
294 u32 seqno
[I915_NUM_RINGS
];
296 u32 fault_reg
[I915_NUM_RINGS
];
298 u32 faddr
[I915_NUM_RINGS
];
299 u64 fence
[I915_MAX_NUM_FENCES
];
301 struct drm_i915_error_ring
{
302 struct drm_i915_error_object
{
306 } *ringbuffer
, *batchbuffer
, *ctx
;
307 struct drm_i915_error_request
{
313 } ring
[I915_NUM_RINGS
];
314 struct drm_i915_error_buffer
{
321 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
328 } **active_bo
, **pinned_bo
;
329 u32
*active_bo_count
, *pinned_bo_count
;
330 struct intel_overlay_error_state
*overlay
;
331 struct intel_display_error_state
*display
;
332 int hangcheck_score
[I915_NUM_RINGS
];
333 enum intel_ring_hangcheck_action hangcheck_action
[I915_NUM_RINGS
];
336 struct intel_crtc_config
;
341 struct drm_i915_display_funcs
{
342 bool (*fbc_enabled
)(struct drm_device
*dev
);
343 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
344 void (*disable_fbc
)(struct drm_device
*dev
);
345 int (*get_display_clock_speed
)(struct drm_device
*dev
);
346 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
348 * find_dpll() - Find the best values for the PLL
349 * @limit: limits for the PLL
350 * @crtc: current CRTC
351 * @target: target frequency in kHz
352 * @refclk: reference clock frequency in kHz
353 * @match_clock: if provided, @best_clock P divider must
354 * match the P divider from @match_clock
355 * used for LVDS downclocking
356 * @best_clock: best PLL values found
358 * Returns true on success, false on failure.
360 bool (*find_dpll
)(const struct intel_limit
*limit
,
361 struct drm_crtc
*crtc
,
362 int target
, int refclk
,
363 struct dpll
*match_clock
,
364 struct dpll
*best_clock
);
365 void (*update_wm
)(struct drm_crtc
*crtc
);
366 void (*update_sprite_wm
)(struct drm_plane
*plane
,
367 struct drm_crtc
*crtc
,
368 uint32_t sprite_width
, int pixel_size
,
369 bool enable
, bool scaled
);
370 void (*modeset_global_resources
)(struct drm_device
*dev
);
371 /* Returns the active state of the crtc, and if the crtc is active,
372 * fills out the pipe-config with the hw state. */
373 bool (*get_pipe_config
)(struct intel_crtc
*,
374 struct intel_crtc_config
*);
375 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
377 struct drm_framebuffer
*old_fb
);
378 void (*crtc_enable
)(struct drm_crtc
*crtc
);
379 void (*crtc_disable
)(struct drm_crtc
*crtc
);
380 void (*off
)(struct drm_crtc
*crtc
);
381 void (*write_eld
)(struct drm_connector
*connector
,
382 struct drm_crtc
*crtc
);
383 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
384 void (*init_clock_gating
)(struct drm_device
*dev
);
385 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
386 struct drm_framebuffer
*fb
,
387 struct drm_i915_gem_object
*obj
,
389 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
391 void (*hpd_irq_setup
)(struct drm_device
*dev
);
392 /* clock updates for mode set */
394 /* render clock increase/decrease */
395 /* display clock increase/decrease */
396 /* pll clock increase/decrease */
399 struct intel_uncore_funcs
{
400 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
401 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
403 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
404 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
405 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
406 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
408 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
409 uint8_t val
, bool trace
);
410 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
411 uint16_t val
, bool trace
);
412 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
413 uint32_t val
, bool trace
);
414 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
415 uint64_t val
, bool trace
);
418 struct intel_uncore
{
419 spinlock_t lock
; /** lock is also taken in irq contexts. */
421 struct intel_uncore_funcs funcs
;
424 unsigned forcewake_count
;
426 struct delayed_work force_wake_work
;
429 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
430 func(is_mobile) sep \
433 func(is_i945gm) sep \
435 func(need_gfx_hws) sep \
437 func(is_pineview) sep \
438 func(is_broadwater) sep \
439 func(is_crestline) sep \
440 func(is_ivybridge) sep \
441 func(is_valleyview) sep \
442 func(is_haswell) sep \
443 func(is_preliminary) sep \
445 func(has_pipe_cxsr) sep \
446 func(has_hotplug) sep \
447 func(cursor_needs_physical) sep \
448 func(has_overlay) sep \
449 func(overlay_needs_physical) sep \
450 func(supports_tv) sep \
451 func(has_bsd_ring) sep \
452 func(has_blt_ring) sep \
453 func(has_vebox_ring) sep \
458 #define DEFINE_FLAG(name) u8 name:1
459 #define SEP_SEMICOLON ;
461 struct intel_device_info
{
462 u32 display_mmio_offset
;
465 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
471 enum i915_cache_level
{
473 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
474 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
475 caches, eg sampler/render caches, and the
476 large Last-Level-Cache. LLC is coherent with
477 the CPU, but L3 is only visible to the GPU. */
478 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
481 typedef uint32_t gen6_gtt_pte_t
;
483 struct i915_address_space
{
485 struct drm_device
*dev
;
486 struct list_head global_link
;
487 unsigned long start
; /* Start offset always 0 for dri2 */
488 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
496 * List of objects currently involved in rendering.
498 * Includes buffers having the contents of their GPU caches
499 * flushed, not necessarily primitives. last_rendering_seqno
500 * represents when the rendering involved will be completed.
502 * A reference is held on the buffer while on this list.
504 struct list_head active_list
;
507 * LRU list of objects which are not in the ringbuffer and
508 * are ready to unbind, but are still in the GTT.
510 * last_rendering_seqno is 0 while an object is in this list.
512 * A reference is not held on the buffer while on this list,
513 * as merely being GTT-bound shouldn't prevent its being
514 * freed, and we'll pull it off the list in the free path.
516 struct list_head inactive_list
;
518 /* FIXME: Need a more generic return type */
519 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
520 enum i915_cache_level level
);
521 void (*clear_range
)(struct i915_address_space
*vm
,
522 unsigned int first_entry
,
523 unsigned int num_entries
);
524 void (*insert_entries
)(struct i915_address_space
*vm
,
526 unsigned int first_entry
,
527 enum i915_cache_level cache_level
);
528 void (*cleanup
)(struct i915_address_space
*vm
);
531 /* The Graphics Translation Table is the way in which GEN hardware translates a
532 * Graphics Virtual Address into a Physical Address. In addition to the normal
533 * collateral associated with any va->pa translations GEN hardware also has a
534 * portion of the GTT which can be mapped by the CPU and remain both coherent
535 * and correct (in cases like swizzling). That region is referred to as GMADR in
539 struct i915_address_space base
;
540 size_t stolen_size
; /* Total size of stolen memory */
542 unsigned long mappable_end
; /* End offset that we can CPU map */
543 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
544 phys_addr_t mappable_base
; /* PA of our GMADR */
546 /** "Graphics Stolen Memory" holds the global PTEs */
554 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
555 size_t *stolen
, phys_addr_t
*mappable_base
,
556 unsigned long *mappable_end
);
558 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
560 struct i915_hw_ppgtt
{
561 struct i915_address_space base
;
562 unsigned num_pd_entries
;
563 struct page
**pt_pages
;
565 dma_addr_t
*pt_dma_addr
;
567 int (*enable
)(struct drm_device
*dev
);
571 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
572 * VMA's presence cannot be guaranteed before binding, or after unbinding the
573 * object into/from the address space.
575 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
576 * will always be <= an objects lifetime. So object refcounting should cover us.
579 struct drm_mm_node node
;
580 struct drm_i915_gem_object
*obj
;
581 struct i915_address_space
*vm
;
583 /** This object's place on the active/inactive lists */
584 struct list_head mm_list
;
586 struct list_head vma_link
; /* Link in the object's VMA list */
588 /** This vma's place in the batchbuffer or on the eviction list */
589 struct list_head exec_list
;
592 * Used for performing relocations during execbuffer insertion.
594 struct hlist_node exec_node
;
595 unsigned long exec_handle
;
596 struct drm_i915_gem_exec_object2
*exec_entry
;
600 struct i915_ctx_hang_stats
{
601 /* This context had batch pending when hang was declared */
602 unsigned batch_pending
;
604 /* This context had batch active when hang was declared */
605 unsigned batch_active
;
607 /* Time when this context was last blamed for a GPU reset */
608 unsigned long guilty_ts
;
610 /* This context is banned to submit more work */
614 /* This must match up with the value previously used for execbuf2.rsvd1. */
615 #define DEFAULT_CONTEXT_ID 0
616 struct i915_hw_context
{
621 struct drm_i915_file_private
*file_priv
;
622 struct intel_ring_buffer
*ring
;
623 struct drm_i915_gem_object
*obj
;
624 struct i915_ctx_hang_stats hang_stats
;
626 struct list_head link
;
635 struct drm_mm_node
*compressed_fb
;
636 struct drm_mm_node
*compressed_llb
;
638 struct intel_fbc_work
{
639 struct delayed_work work
;
640 struct drm_crtc
*crtc
;
641 struct drm_framebuffer
*fb
;
646 FBC_OK
, /* FBC is enabled */
647 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
648 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
649 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
650 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
651 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
652 FBC_BAD_PLANE
, /* fbc not supported on plane */
653 FBC_NOT_TILED
, /* buffer not tiled */
654 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
656 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
666 PCH_NONE
= 0, /* No PCH present */
667 PCH_IBX
, /* Ibexpeak PCH */
668 PCH_CPT
, /* Cougarpoint PCH */
669 PCH_LPT
, /* Lynxpoint PCH */
673 enum intel_sbi_destination
{
678 #define QUIRK_PIPEA_FORCE (1<<0)
679 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
680 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
681 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
684 struct intel_fbc_work
;
687 struct i2c_adapter adapter
;
691 struct i2c_algo_bit_data bit_algo
;
692 struct drm_i915_private
*dev_priv
;
695 struct i915_suspend_saved_registers
{
716 u32 saveTRANS_HTOTAL_A
;
717 u32 saveTRANS_HBLANK_A
;
718 u32 saveTRANS_HSYNC_A
;
719 u32 saveTRANS_VTOTAL_A
;
720 u32 saveTRANS_VBLANK_A
;
721 u32 saveTRANS_VSYNC_A
;
729 u32 savePFIT_PGM_RATIOS
;
730 u32 saveBLC_HIST_CTL
;
732 u32 saveBLC_PWM_CTL2
;
733 u32 saveBLC_CPU_PWM_CTL
;
734 u32 saveBLC_CPU_PWM_CTL2
;
747 u32 saveTRANS_HTOTAL_B
;
748 u32 saveTRANS_HBLANK_B
;
749 u32 saveTRANS_HSYNC_B
;
750 u32 saveTRANS_VTOTAL_B
;
751 u32 saveTRANS_VBLANK_B
;
752 u32 saveTRANS_VSYNC_B
;
766 u32 savePP_ON_DELAYS
;
767 u32 savePP_OFF_DELAYS
;
775 u32 savePFIT_CONTROL
;
776 u32 save_palette_a
[256];
777 u32 save_palette_b
[256];
778 u32 saveDPFC_CB_BASE
;
779 u32 saveFBC_CFB_BASE
;
782 u32 saveFBC_CONTROL2
;
792 u32 saveCACHE_MODE_0
;
793 u32 saveMI_ARB_STATE
;
804 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
815 u32 savePIPEA_GMCH_DATA_M
;
816 u32 savePIPEB_GMCH_DATA_M
;
817 u32 savePIPEA_GMCH_DATA_N
;
818 u32 savePIPEB_GMCH_DATA_N
;
819 u32 savePIPEA_DP_LINK_M
;
820 u32 savePIPEB_DP_LINK_M
;
821 u32 savePIPEA_DP_LINK_N
;
822 u32 savePIPEB_DP_LINK_N
;
833 u32 savePCH_DREF_CONTROL
;
834 u32 saveDISP_ARB_CTL
;
835 u32 savePIPEA_DATA_M1
;
836 u32 savePIPEA_DATA_N1
;
837 u32 savePIPEA_LINK_M1
;
838 u32 savePIPEA_LINK_N1
;
839 u32 savePIPEB_DATA_M1
;
840 u32 savePIPEB_DATA_N1
;
841 u32 savePIPEB_LINK_M1
;
842 u32 savePIPEB_LINK_N1
;
843 u32 saveMCHBAR_RENDER_STANDBY
;
844 u32 savePCH_PORT_HOTPLUG
;
847 struct intel_gen6_power_mgmt
{
848 /* work and pm_iir are protected by dev_priv->irq_lock */
849 struct work_struct work
;
852 /* The below variables an all the rps hw state are protected by
853 * dev->struct mutext. */
863 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
866 struct delayed_work delayed_resume_work
;
869 * Protects RPS/RC6 register access and PCU communication.
870 * Must be taken after struct_mutex if nested.
872 struct mutex hw_lock
;
875 /* defined intel_pm.c */
876 extern spinlock_t mchdev_lock
;
878 struct intel_ilk_power_mgmt
{
886 unsigned long last_time1
;
887 unsigned long chipset_power
;
889 struct timespec last_time2
;
890 unsigned long gfx_power
;
896 struct drm_i915_gem_object
*pwrctx
;
897 struct drm_i915_gem_object
*renderctx
;
900 /* Power well structure for haswell */
901 struct i915_power_well
{
902 struct drm_device
*device
;
904 /* power well enable/disable usage count */
909 struct i915_dri1_state
{
910 unsigned allow_batchbuffer
: 1;
911 u32 __iomem
*gfx_hws_cpu_addr
;
922 struct i915_ums_state
{
924 * Flag if the X Server, and thus DRM, is not currently in
925 * control of the device.
927 * This is set between LeaveVT and EnterVT. It needs to be
928 * replaced with a semaphore. It also needs to be
929 * transitioned away from for kernel modesetting.
934 #define MAX_L3_SLICES 2
935 struct intel_l3_parity
{
936 u32
*remap_info
[MAX_L3_SLICES
];
937 struct work_struct error_work
;
942 /** Memory allocator for GTT stolen memory */
943 struct drm_mm stolen
;
944 /** List of all objects in gtt_space. Used to restore gtt
945 * mappings on resume */
946 struct list_head bound_list
;
948 * List of objects which are not bound to the GTT (thus
949 * are idle and not used by the GPU) but still have
950 * (presumably uncached) pages still attached.
952 struct list_head unbound_list
;
954 /** Usable portion of the GTT for GEM */
955 unsigned long stolen_base
; /* limited to low memory (32-bit) */
957 /** PPGTT used for aliasing the PPGTT with the GTT */
958 struct i915_hw_ppgtt
*aliasing_ppgtt
;
960 struct shrinker inactive_shrinker
;
961 bool shrinker_no_lock_stealing
;
963 /** LRU list of objects with fence regs on them. */
964 struct list_head fence_list
;
967 * We leave the user IRQ off as much as possible,
968 * but this means that requests will finish and never
969 * be retired once the system goes idle. Set a timer to
970 * fire periodically while the ring is running. When it
971 * fires, go retire requests.
973 struct delayed_work retire_work
;
976 * When we detect an idle GPU, we want to turn on
977 * powersaving features. So once we see that there
978 * are no more requests outstanding and no more
979 * arrive within a small period of time, we fire
982 struct delayed_work idle_work
;
985 * Are we in a non-interruptible section of code like
990 /** Bit 6 swizzling required for X tiling */
991 uint32_t bit_6_swizzle_x
;
992 /** Bit 6 swizzling required for Y tiling */
993 uint32_t bit_6_swizzle_y
;
995 /* storage for physical objects */
996 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
998 /* accounting, useful for userland debugging */
999 spinlock_t object_stat_lock
;
1000 size_t object_memory
;
1004 struct drm_i915_error_state_buf
{
1013 struct i915_error_state_file_priv
{
1014 struct drm_device
*dev
;
1015 struct drm_i915_error_state
*error
;
1018 struct i915_gpu_error
{
1019 /* For hangcheck timer */
1020 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1021 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1022 /* Hang gpu twice in this window and your context gets banned */
1023 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1025 struct timer_list hangcheck_timer
;
1027 /* For reset and error_state handling. */
1029 /* Protected by the above dev->gpu_error.lock. */
1030 struct drm_i915_error_state
*first_error
;
1031 struct work_struct work
;
1034 unsigned long missed_irq_rings
;
1037 * State variable and reset counter controlling the reset flow
1039 * Upper bits are for the reset counter. This counter is used by the
1040 * wait_seqno code to race-free noticed that a reset event happened and
1041 * that it needs to restart the entire ioctl (since most likely the
1042 * seqno it waited for won't ever signal anytime soon).
1044 * This is important for lock-free wait paths, where no contended lock
1045 * naturally enforces the correct ordering between the bail-out of the
1046 * waiter and the gpu reset work code.
1048 * Lowest bit controls the reset state machine: Set means a reset is in
1049 * progress. This state will (presuming we don't have any bugs) decay
1050 * into either unset (successful reset) or the special WEDGED value (hw
1051 * terminally sour). All waiters on the reset_queue will be woken when
1054 atomic_t reset_counter
;
1057 * Special values/flags for reset_counter
1059 * Note that the code relies on
1060 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1063 #define I915_RESET_IN_PROGRESS_FLAG 1
1064 #define I915_WEDGED 0xffffffff
1067 * Waitqueue to signal when the reset has completed. Used by clients
1068 * that wait for dev_priv->mm.wedged to settle.
1070 wait_queue_head_t reset_queue
;
1072 /* For gpu hang simulation. */
1073 unsigned int stop_rings
;
1075 /* For missed irq/seqno simulation. */
1076 unsigned int test_irq_rings
;
1079 enum modeset_restore
{
1080 MODESET_ON_LID_OPEN
,
1085 struct ddi_vbt_port_info
{
1086 uint8_t hdmi_level_shift
;
1088 uint8_t supports_dvi
:1;
1089 uint8_t supports_hdmi
:1;
1090 uint8_t supports_dp
:1;
1093 struct intel_vbt_data
{
1094 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1095 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1098 unsigned int int_tv_support
:1;
1099 unsigned int lvds_dither
:1;
1100 unsigned int lvds_vbt
:1;
1101 unsigned int int_crt_support
:1;
1102 unsigned int lvds_use_ssc
:1;
1103 unsigned int display_clock_mode
:1;
1104 unsigned int fdi_rx_polarity_inverted
:1;
1106 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1111 int edp_preemphasis
;
1113 bool edp_initialized
;
1116 struct edp_power_seq edp_pps
;
1126 union child_device_config
*child_dev
;
1128 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1131 enum intel_ddb_partitioning
{
1133 INTEL_DDB_PART_5_6
, /* IVB+ */
1136 struct intel_wm_level
{
1145 * This struct tracks the state needed for the Package C8+ feature.
1147 * Package states C8 and deeper are really deep PC states that can only be
1148 * reached when all the devices on the system allow it, so even if the graphics
1149 * device allows PC8+, it doesn't mean the system will actually get to these
1152 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1153 * is disabled and the GPU is idle. When these conditions are met, we manually
1154 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1157 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1158 * the state of some registers, so when we come back from PC8+ we need to
1159 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1160 * need to take care of the registers kept by RC6.
1162 * The interrupt disabling is part of the requirements. We can only leave the
1163 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1164 * can lock the machine.
1166 * Ideally every piece of our code that needs PC8+ disabled would call
1167 * hsw_disable_package_c8, which would increment disable_count and prevent the
1168 * system from reaching PC8+. But we don't have a symmetric way to do this for
1169 * everything, so we have the requirements_met and gpu_idle variables. When we
1170 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1171 * increase it in the opposite case. The requirements_met variable is true when
1172 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1173 * variable is true when the GPU is idle.
1175 * In addition to everything, we only actually enable PC8+ if disable_count
1176 * stays at zero for at least some seconds. This is implemented with the
1177 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1178 * consecutive times when all screens are disabled and some background app
1179 * queries the state of our connectors, or we have some application constantly
1180 * waking up to use the GPU. Only after the enable_work function actually
1181 * enables PC8+ the "enable" variable will become true, which means that it can
1182 * be false even if disable_count is 0.
1184 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1185 * goes back to false exactly before we reenable the IRQs. We use this variable
1186 * to check if someone is trying to enable/disable IRQs while they're supposed
1187 * to be disabled. This shouldn't happen and we'll print some error messages in
1188 * case it happens, but if it actually happens we'll also update the variables
1189 * inside struct regsave so when we restore the IRQs they will contain the
1190 * latest expected values.
1192 * For more, read "Display Sequences for Package C8" on our documentation.
1194 struct i915_package_c8
{
1195 bool requirements_met
;
1198 /* Only true after the delayed work task actually enables it. */
1202 struct delayed_work enable_work
;
1209 uint32_t gen6_pmimr
;
1213 typedef struct drm_i915_private
{
1214 struct drm_device
*dev
;
1215 struct kmem_cache
*slab
;
1217 const struct intel_device_info
*info
;
1219 int relative_constants_mode
;
1223 struct intel_uncore uncore
;
1225 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1228 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1229 * controller on different i2c buses. */
1230 struct mutex gmbus_mutex
;
1233 * Base address of the gmbus and gpio block.
1235 uint32_t gpio_mmio_base
;
1237 wait_queue_head_t gmbus_wait_queue
;
1239 struct pci_dev
*bridge_dev
;
1240 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1241 uint32_t last_seqno
, next_seqno
;
1243 drm_dma_handle_t
*status_page_dmah
;
1244 struct resource mch_res
;
1246 atomic_t irq_received
;
1248 /* protects the irq masks */
1249 spinlock_t irq_lock
;
1251 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1252 struct pm_qos_request pm_qos
;
1254 /* DPIO indirect register protection */
1255 struct mutex dpio_lock
;
1257 /** Cached value of IMR to avoid reads in updating the bitfield */
1262 struct work_struct hotplug_work
;
1263 bool enable_hotplug_processing
;
1265 unsigned long hpd_last_jiffies
;
1270 HPD_MARK_DISABLED
= 2
1272 } hpd_stats
[HPD_NUM_PINS
];
1274 struct timer_list hotplug_reenable_timer
;
1278 struct i915_fbc fbc
;
1279 struct intel_opregion opregion
;
1280 struct intel_vbt_data vbt
;
1283 struct intel_overlay
*overlay
;
1284 unsigned int sprite_scaling_enabled
;
1290 spinlock_t lock
; /* bl registers and the above bl fields */
1291 struct backlight_device
*device
;
1295 bool no_aux_handshake
;
1297 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1298 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1299 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1301 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1304 * wq - Driver workqueue for GEM.
1306 * NOTE: Work items scheduled here are not allowed to grab any modeset
1307 * locks, for otherwise the flushing done in the pageflip code will
1308 * result in deadlocks.
1310 struct workqueue_struct
*wq
;
1312 /* Display functions */
1313 struct drm_i915_display_funcs display
;
1315 /* PCH chipset type */
1316 enum intel_pch pch_type
;
1317 unsigned short pch_id
;
1319 unsigned long quirks
;
1321 enum modeset_restore modeset_restore
;
1322 struct mutex modeset_restore_lock
;
1324 struct list_head vm_list
; /* Global list of all address spaces */
1325 struct i915_gtt gtt
; /* VMA representing the global address space */
1327 struct i915_gem_mm mm
;
1329 /* Kernel Modesetting */
1331 struct sdvo_device_mapping sdvo_mappings
[2];
1333 struct drm_crtc
*plane_to_crtc_mapping
[3];
1334 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1335 wait_queue_head_t pending_flip_queue
;
1337 int num_shared_dpll
;
1338 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1339 struct intel_ddi_plls ddi_plls
;
1341 /* Reclocking support */
1342 bool render_reclock_avail
;
1343 bool lvds_downclock_avail
;
1344 /* indicates the reduced downclock for LVDS*/
1348 bool mchbar_need_disable
;
1350 struct intel_l3_parity l3_parity
;
1352 /* Cannot be determined by PCIID. You must always read a register. */
1355 /* gen6+ rps state */
1356 struct intel_gen6_power_mgmt rps
;
1358 /* ilk-only ips/rps state. Everything in here is protected by the global
1359 * mchdev_lock in intel_pm.c */
1360 struct intel_ilk_power_mgmt ips
;
1362 /* Haswell power well */
1363 struct i915_power_well power_well
;
1365 struct i915_psr psr
;
1367 struct i915_gpu_error gpu_error
;
1369 struct drm_i915_gem_object
*vlv_pctx
;
1371 #ifdef CONFIG_DRM_I915_FBDEV
1372 /* list of fbdev register on this device */
1373 struct intel_fbdev
*fbdev
;
1377 * The console may be contended at resume, but we don't
1378 * want it to block on it.
1380 struct work_struct console_resume_work
;
1382 struct drm_property
*broadcast_rgb_property
;
1383 struct drm_property
*force_audio_property
;
1385 bool hw_contexts_disabled
;
1386 uint32_t hw_context_size
;
1387 struct list_head context_list
;
1391 struct i915_suspend_saved_registers regfile
;
1395 * Raw watermark latency values:
1396 * in 0.1us units for WM0,
1397 * in 0.5us units for WM1+.
1400 uint16_t pri_latency
[5];
1402 uint16_t spr_latency
[5];
1404 uint16_t cur_latency
[5];
1407 struct i915_package_c8 pc8
;
1409 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1411 struct i915_dri1_state dri1
;
1412 /* Old ums support infrastructure, same warning applies. */
1413 struct i915_ums_state ums
;
1414 } drm_i915_private_t
;
1416 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1418 return dev
->dev_private
;
1421 /* Iterate over initialised rings */
1422 #define for_each_ring(ring__, dev_priv__, i__) \
1423 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1424 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1426 enum hdmi_force_audio
{
1427 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1428 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1429 HDMI_AUDIO_AUTO
, /* trust EDID */
1430 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1433 #define I915_GTT_OFFSET_NONE ((u32)-1)
1435 struct drm_i915_gem_object_ops
{
1436 /* Interface between the GEM object and its backing storage.
1437 * get_pages() is called once prior to the use of the associated set
1438 * of pages before to binding them into the GTT, and put_pages() is
1439 * called after we no longer need them. As we expect there to be
1440 * associated cost with migrating pages between the backing storage
1441 * and making them available for the GPU (e.g. clflush), we may hold
1442 * onto the pages after they are no longer referenced by the GPU
1443 * in case they may be used again shortly (for example migrating the
1444 * pages to a different memory domain within the GTT). put_pages()
1445 * will therefore most likely be called when the object itself is
1446 * being released or under memory pressure (where we attempt to
1447 * reap pages for the shrinker).
1449 int (*get_pages
)(struct drm_i915_gem_object
*);
1450 void (*put_pages
)(struct drm_i915_gem_object
*);
1453 struct drm_i915_gem_object
{
1454 struct drm_gem_object base
;
1456 const struct drm_i915_gem_object_ops
*ops
;
1458 /** List of VMAs backed by this object */
1459 struct list_head vma_list
;
1461 /** Stolen memory for this object, instead of being backed by shmem. */
1462 struct drm_mm_node
*stolen
;
1463 struct list_head global_list
;
1465 struct list_head ring_list
;
1466 /** Used in execbuf to temporarily hold a ref */
1467 struct list_head obj_exec_link
;
1470 * This is set if the object is on the active lists (has pending
1471 * rendering and so a non-zero seqno), and is not set if it i s on
1472 * inactive (ready to be unbound) list.
1474 unsigned int active
:1;
1477 * This is set if the object has been written to since last bound
1480 unsigned int dirty
:1;
1483 * Fence register bits (if any) for this object. Will be set
1484 * as needed when mapped into the GTT.
1485 * Protected by dev->struct_mutex.
1487 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1490 * Advice: are the backing pages purgeable?
1492 unsigned int madv
:2;
1495 * Current tiling mode for the object.
1497 unsigned int tiling_mode
:2;
1499 * Whether the tiling parameters for the currently associated fence
1500 * register have changed. Note that for the purposes of tracking
1501 * tiling changes we also treat the unfenced register, the register
1502 * slot that the object occupies whilst it executes a fenced
1503 * command (such as BLT on gen2/3), as a "fence".
1505 unsigned int fence_dirty
:1;
1507 /** How many users have pinned this object in GTT space. The following
1508 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1509 * (via user_pin_count), execbuffer (objects are not allowed multiple
1510 * times for the same batchbuffer), and the framebuffer code. When
1511 * switching/pageflipping, the framebuffer code has at most two buffers
1514 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1515 * bits with absolutely no headroom. So use 4 bits. */
1516 unsigned int pin_count
:4;
1517 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1520 * Is the object at the current location in the gtt mappable and
1521 * fenceable? Used to avoid costly recalculations.
1523 unsigned int map_and_fenceable
:1;
1526 * Whether the current gtt mapping needs to be mappable (and isn't just
1527 * mappable by accident). Track pin and fault separate for a more
1528 * accurate mappable working set.
1530 unsigned int fault_mappable
:1;
1531 unsigned int pin_mappable
:1;
1532 unsigned int pin_display
:1;
1535 * Is the GPU currently using a fence to access this buffer,
1537 unsigned int pending_fenced_gpu_access
:1;
1538 unsigned int fenced_gpu_access
:1;
1540 unsigned int cache_level
:3;
1542 unsigned int has_aliasing_ppgtt_mapping
:1;
1543 unsigned int has_global_gtt_mapping
:1;
1544 unsigned int has_dma_mapping
:1;
1546 struct sg_table
*pages
;
1547 int pages_pin_count
;
1549 /* prime dma-buf support */
1550 void *dma_buf_vmapping
;
1553 struct intel_ring_buffer
*ring
;
1555 /** Breadcrumb of last rendering to the buffer. */
1556 uint32_t last_read_seqno
;
1557 uint32_t last_write_seqno
;
1558 /** Breadcrumb of last fenced GPU access to the buffer. */
1559 uint32_t last_fenced_seqno
;
1561 /** Current tiling stride for the object, if it's tiled. */
1564 /** Record of address bit 17 of each page at last unbind. */
1565 unsigned long *bit_17
;
1567 /** User space pin count and filp owning the pin */
1568 uint32_t user_pin_count
;
1569 struct drm_file
*pin_filp
;
1571 /** for phy allocated objects */
1572 struct drm_i915_gem_phys_object
*phys_obj
;
1574 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1576 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1579 * Request queue structure.
1581 * The request queue allows us to note sequence numbers that have been emitted
1582 * and may be associated with active buffers to be retired.
1584 * By keeping this list, we can avoid having to do questionable
1585 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1586 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1588 struct drm_i915_gem_request
{
1589 /** On Which ring this request was generated */
1590 struct intel_ring_buffer
*ring
;
1592 /** GEM sequence number associated with this request. */
1595 /** Position in the ringbuffer of the start of the request */
1598 /** Position in the ringbuffer of the end of the request */
1601 /** Context related to this request */
1602 struct i915_hw_context
*ctx
;
1604 /** Batch buffer related to this request if any */
1605 struct drm_i915_gem_object
*batch_obj
;
1607 /** Time at which this request was emitted, in jiffies. */
1608 unsigned long emitted_jiffies
;
1610 /** global list entry for this request */
1611 struct list_head list
;
1613 struct drm_i915_file_private
*file_priv
;
1614 /** file_priv list entry for this request */
1615 struct list_head client_list
;
1618 struct drm_i915_file_private
{
1619 struct drm_i915_private
*dev_priv
;
1623 struct list_head request_list
;
1624 struct delayed_work idle_work
;
1626 struct idr context_idr
;
1628 struct i915_ctx_hang_stats hang_stats
;
1629 atomic_t rps_wait_boost
;
1632 #define INTEL_INFO(dev) (to_i915(dev)->info)
1634 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1635 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1636 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1637 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1638 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1639 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1640 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1641 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1642 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1643 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1644 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1645 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1646 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1647 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1648 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1649 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1650 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1651 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1652 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1653 (dev)->pdev->device == 0x0152 || \
1654 (dev)->pdev->device == 0x015a)
1655 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1656 (dev)->pdev->device == 0x0106 || \
1657 (dev)->pdev->device == 0x010A)
1658 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1659 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1660 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1661 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1662 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1663 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1664 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1665 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1666 ((dev)->pdev->device & 0x00F0) == 0x0020)
1667 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1670 * The genX designation typically refers to the render engine, so render
1671 * capability related checks should use IS_GEN, while display and other checks
1672 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1675 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1676 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1677 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1678 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1679 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1680 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1682 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1683 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1684 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1685 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1686 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1687 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1689 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1690 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1692 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1693 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1695 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1696 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1698 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1699 * rows, which changed the alignment requirements and fence programming.
1701 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1703 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1704 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1705 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1706 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1707 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1709 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1710 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1711 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1713 #define HAS_IPS(dev) (IS_ULT(dev))
1715 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1716 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1717 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1718 #define HAS_PSR(dev) (IS_HASWELL(dev))
1720 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1721 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1722 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1723 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1724 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1725 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1727 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1728 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1729 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1730 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1731 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1732 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1734 /* DPF == dynamic parity feature */
1735 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1736 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1738 #define GT_FREQUENCY_MULTIPLIER 50
1740 #include "i915_trace.h"
1743 * RC6 is a special power stage which allows the GPU to enter an very
1744 * low-voltage mode when idle, using down to 0V while at this stage. This
1745 * stage is entered automatically when the GPU is idle when RC6 support is
1746 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1748 * There are different RC6 modes available in Intel GPU, which differentiate
1749 * among each other with the latency required to enter and leave RC6 and
1750 * voltage consumed by the GPU in different states.
1752 * The combination of the following flags define which states GPU is allowed
1753 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1754 * RC6pp is deepest RC6. Their support by hardware varies according to the
1755 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1756 * which brings the most power savings; deeper states save more power, but
1757 * require higher latency to switch to and wake up.
1759 #define INTEL_RC6_ENABLE (1<<0)
1760 #define INTEL_RC6p_ENABLE (1<<1)
1761 #define INTEL_RC6pp_ENABLE (1<<2)
1763 extern const struct drm_ioctl_desc i915_ioctls
[];
1764 extern int i915_max_ioctl
;
1765 extern unsigned int i915_fbpercrtc __always_unused
;
1766 extern int i915_panel_ignore_lid __read_mostly
;
1767 extern unsigned int i915_powersave __read_mostly
;
1768 extern int i915_semaphores __read_mostly
;
1769 extern unsigned int i915_lvds_downclock __read_mostly
;
1770 extern int i915_lvds_channel_mode __read_mostly
;
1771 extern int i915_panel_use_ssc __read_mostly
;
1772 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1773 extern int i915_enable_rc6 __read_mostly
;
1774 extern int i915_enable_fbc __read_mostly
;
1775 extern bool i915_enable_hangcheck __read_mostly
;
1776 extern int i915_enable_ppgtt __read_mostly
;
1777 extern int i915_enable_psr __read_mostly
;
1778 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1779 extern int i915_disable_power_well __read_mostly
;
1780 extern int i915_enable_ips __read_mostly
;
1781 extern bool i915_fastboot __read_mostly
;
1782 extern int i915_enable_pc8 __read_mostly
;
1783 extern int i915_pc8_timeout __read_mostly
;
1784 extern bool i915_prefault_disable __read_mostly
;
1786 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1787 extern int i915_resume(struct drm_device
*dev
);
1788 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1789 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1792 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1793 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1794 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1795 extern int i915_driver_unload(struct drm_device
*);
1796 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1797 extern void i915_driver_lastclose(struct drm_device
* dev
);
1798 extern void i915_driver_preclose(struct drm_device
*dev
,
1799 struct drm_file
*file_priv
);
1800 extern void i915_driver_postclose(struct drm_device
*dev
,
1801 struct drm_file
*file_priv
);
1802 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1803 #ifdef CONFIG_COMPAT
1804 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1807 extern int i915_emit_box(struct drm_device
*dev
,
1808 struct drm_clip_rect
*box
,
1810 extern int intel_gpu_reset(struct drm_device
*dev
);
1811 extern int i915_reset(struct drm_device
*dev
);
1812 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1813 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1814 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1815 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1817 extern void intel_console_resume(struct work_struct
*work
);
1820 void i915_queue_hangcheck(struct drm_device
*dev
);
1821 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1823 extern void intel_irq_init(struct drm_device
*dev
);
1824 extern void intel_pm_init(struct drm_device
*dev
);
1825 extern void intel_hpd_init(struct drm_device
*dev
);
1826 extern void intel_pm_init(struct drm_device
*dev
);
1828 extern void intel_uncore_sanitize(struct drm_device
*dev
);
1829 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
1830 extern void intel_uncore_init(struct drm_device
*dev
);
1831 extern void intel_uncore_clear_errors(struct drm_device
*dev
);
1832 extern void intel_uncore_check_errors(struct drm_device
*dev
);
1833 extern void intel_uncore_fini(struct drm_device
*dev
);
1836 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1839 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1842 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1843 struct drm_file
*file_priv
);
1844 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1845 struct drm_file
*file_priv
);
1846 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1847 struct drm_file
*file_priv
);
1848 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1849 struct drm_file
*file_priv
);
1850 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1851 struct drm_file
*file_priv
);
1852 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1853 struct drm_file
*file_priv
);
1854 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1855 struct drm_file
*file_priv
);
1856 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1857 struct drm_file
*file_priv
);
1858 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1859 struct drm_file
*file_priv
);
1860 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1861 struct drm_file
*file_priv
);
1862 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1863 struct drm_file
*file_priv
);
1864 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1865 struct drm_file
*file_priv
);
1866 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1867 struct drm_file
*file_priv
);
1868 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1869 struct drm_file
*file
);
1870 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1871 struct drm_file
*file
);
1872 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1873 struct drm_file
*file_priv
);
1874 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1875 struct drm_file
*file_priv
);
1876 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1877 struct drm_file
*file_priv
);
1878 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1879 struct drm_file
*file_priv
);
1880 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1881 struct drm_file
*file_priv
);
1882 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1883 struct drm_file
*file_priv
);
1884 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1885 struct drm_file
*file_priv
);
1886 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1887 struct drm_file
*file_priv
);
1888 void i915_gem_load(struct drm_device
*dev
);
1889 void *i915_gem_object_alloc(struct drm_device
*dev
);
1890 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1891 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1892 const struct drm_i915_gem_object_ops
*ops
);
1893 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1895 void i915_gem_free_object(struct drm_gem_object
*obj
);
1896 void i915_gem_vma_destroy(struct i915_vma
*vma
);
1898 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1899 struct i915_address_space
*vm
,
1901 bool map_and_fenceable
,
1903 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1904 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
1905 int __must_check
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
);
1906 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1907 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1908 void i915_gem_lastclose(struct drm_device
*dev
);
1910 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1911 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1913 struct sg_page_iter sg_iter
;
1915 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1916 return sg_page_iter_page(&sg_iter
);
1920 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1922 BUG_ON(obj
->pages
== NULL
);
1923 obj
->pages_pin_count
++;
1925 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1927 BUG_ON(obj
->pages_pin_count
== 0);
1928 obj
->pages_pin_count
--;
1931 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1932 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1933 struct intel_ring_buffer
*to
);
1934 void i915_vma_move_to_active(struct i915_vma
*vma
,
1935 struct intel_ring_buffer
*ring
);
1936 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1937 struct drm_device
*dev
,
1938 struct drm_mode_create_dumb
*args
);
1939 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1940 uint32_t handle
, uint64_t *offset
);
1942 * Returns true if seq1 is later than seq2.
1945 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1947 return (int32_t)(seq1
- seq2
) >= 0;
1950 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1951 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1952 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1953 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1956 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1958 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1959 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1960 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1967 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1969 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1970 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1971 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
1972 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1976 bool i915_gem_retire_requests(struct drm_device
*dev
);
1977 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1978 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1979 bool interruptible
);
1980 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1982 return unlikely(atomic_read(&error
->reset_counter
)
1983 & I915_RESET_IN_PROGRESS_FLAG
);
1986 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1988 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1991 void i915_gem_reset(struct drm_device
*dev
);
1992 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
1993 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1994 int __must_check
i915_gem_init(struct drm_device
*dev
);
1995 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1996 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
);
1997 void i915_gem_init_swizzling(struct drm_device
*dev
);
1998 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1999 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2000 int __must_check
i915_gem_idle(struct drm_device
*dev
);
2001 int __i915_add_request(struct intel_ring_buffer
*ring
,
2002 struct drm_file
*file
,
2003 struct drm_i915_gem_object
*batch_obj
,
2005 #define i915_add_request(ring, seqno) \
2006 __i915_add_request(ring, NULL, NULL, seqno)
2007 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
2009 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2011 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2014 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2016 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2018 struct intel_ring_buffer
*pipelined
);
2019 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2020 int i915_gem_attach_phys_object(struct drm_device
*dev
,
2021 struct drm_i915_gem_object
*obj
,
2024 void i915_gem_detach_phys_object(struct drm_device
*dev
,
2025 struct drm_i915_gem_object
*obj
);
2026 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
2027 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2028 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2031 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2033 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2034 int tiling_mode
, bool fenced
);
2036 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2037 enum i915_cache_level cache_level
);
2039 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2040 struct dma_buf
*dma_buf
);
2042 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2043 struct drm_gem_object
*gem_obj
, int flags
);
2045 void i915_gem_restore_fences(struct drm_device
*dev
);
2047 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2048 struct i915_address_space
*vm
);
2049 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2050 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2051 struct i915_address_space
*vm
);
2052 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2053 struct i915_address_space
*vm
);
2054 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2055 struct i915_address_space
*vm
);
2057 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2058 struct i915_address_space
*vm
);
2060 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2062 /* Some GGTT VM helpers */
2063 #define obj_to_ggtt(obj) \
2064 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2065 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2067 struct i915_address_space
*ggtt
=
2068 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2072 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2074 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2077 static inline unsigned long
2078 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2080 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2083 static inline unsigned long
2084 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2086 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2089 static inline int __must_check
2090 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2092 bool map_and_fenceable
,
2095 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
,
2096 map_and_fenceable
, nonblocking
);
2099 /* i915_gem_context.c */
2100 void i915_gem_context_init(struct drm_device
*dev
);
2101 void i915_gem_context_fini(struct drm_device
*dev
);
2102 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2103 int i915_switch_context(struct intel_ring_buffer
*ring
,
2104 struct drm_file
*file
, int to_id
);
2105 void i915_gem_context_free(struct kref
*ctx_ref
);
2106 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
2108 kref_get(&ctx
->ref
);
2111 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
2113 kref_put(&ctx
->ref
, i915_gem_context_free
);
2116 struct i915_ctx_hang_stats
* __must_check
2117 i915_gem_context_get_hang_stats(struct drm_device
*dev
,
2118 struct drm_file
*file
,
2120 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2121 struct drm_file
*file
);
2122 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2123 struct drm_file
*file
);
2125 /* i915_gem_gtt.c */
2126 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
2127 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
2128 struct drm_i915_gem_object
*obj
,
2129 enum i915_cache_level cache_level
);
2130 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
2131 struct drm_i915_gem_object
*obj
);
2133 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
2134 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
2135 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
2136 enum i915_cache_level cache_level
);
2137 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
2138 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
2139 void i915_gem_init_global_gtt(struct drm_device
*dev
);
2140 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
2141 unsigned long mappable_end
, unsigned long end
);
2142 int i915_gem_gtt_init(struct drm_device
*dev
);
2143 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2145 if (INTEL_INFO(dev
)->gen
< 6)
2146 intel_gtt_chipset_flush();
2150 /* i915_gem_evict.c */
2151 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2152 struct i915_address_space
*vm
,
2155 unsigned cache_level
,
2158 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2159 int i915_gem_evict_everything(struct drm_device
*dev
);
2161 /* i915_gem_stolen.c */
2162 int i915_gem_init_stolen(struct drm_device
*dev
);
2163 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
2164 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2165 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2166 struct drm_i915_gem_object
*
2167 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2168 struct drm_i915_gem_object
*
2169 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2173 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2175 /* i915_gem_tiling.c */
2176 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2178 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2180 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2181 obj
->tiling_mode
!= I915_TILING_NONE
;
2184 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2185 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2186 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2188 /* i915_gem_debug.c */
2190 int i915_verify_lists(struct drm_device
*dev
);
2192 #define i915_verify_lists(dev) 0
2195 /* i915_debugfs.c */
2196 int i915_debugfs_init(struct drm_minor
*minor
);
2197 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2199 /* i915_gpu_error.c */
2201 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2202 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2203 const struct i915_error_state_file_priv
*error
);
2204 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2205 size_t count
, loff_t pos
);
2206 static inline void i915_error_state_buf_release(
2207 struct drm_i915_error_state_buf
*eb
)
2211 void i915_capture_error_state(struct drm_device
*dev
);
2212 void i915_error_state_get(struct drm_device
*dev
,
2213 struct i915_error_state_file_priv
*error_priv
);
2214 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2215 void i915_destroy_error_state(struct drm_device
*dev
);
2217 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2218 const char *i915_cache_level_str(int type
);
2220 /* i915_suspend.c */
2221 extern int i915_save_state(struct drm_device
*dev
);
2222 extern int i915_restore_state(struct drm_device
*dev
);
2225 void i915_save_display_reg(struct drm_device
*dev
);
2226 void i915_restore_display_reg(struct drm_device
*dev
);
2229 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2230 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2233 extern int intel_setup_gmbus(struct drm_device
*dev
);
2234 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2235 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2237 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2240 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2241 struct drm_i915_private
*dev_priv
, unsigned port
);
2242 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2243 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2244 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2246 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2248 extern void intel_i2c_reset(struct drm_device
*dev
);
2250 /* intel_opregion.c */
2251 struct intel_encoder
;
2252 extern int intel_opregion_setup(struct drm_device
*dev
);
2254 extern void intel_opregion_init(struct drm_device
*dev
);
2255 extern void intel_opregion_fini(struct drm_device
*dev
);
2256 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2257 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2259 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2262 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2263 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2264 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2266 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2271 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2279 extern void intel_register_dsm_handler(void);
2280 extern void intel_unregister_dsm_handler(void);
2282 static inline void intel_register_dsm_handler(void) { return; }
2283 static inline void intel_unregister_dsm_handler(void) { return; }
2284 #endif /* CONFIG_ACPI */
2287 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2288 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2289 extern void intel_modeset_init(struct drm_device
*dev
);
2290 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2291 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2292 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2293 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2294 bool force_restore
);
2295 extern void i915_redisable_vga(struct drm_device
*dev
);
2296 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2297 extern void intel_disable_fbc(struct drm_device
*dev
);
2298 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2299 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2300 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2301 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2302 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2303 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2304 extern void intel_detect_pch(struct drm_device
*dev
);
2305 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2306 extern int intel_enable_rc6(const struct drm_device
*dev
);
2308 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2309 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2310 struct drm_file
*file
);
2313 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2314 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2315 struct intel_overlay_error_state
*error
);
2317 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2318 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2319 struct drm_device
*dev
,
2320 struct intel_display_error_state
*error
);
2322 /* On SNB platform, before reading ring registers forcewake bit
2323 * must be set to prevent GT core from power down and stale values being
2326 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2327 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2329 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2330 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2332 /* intel_sideband.c */
2333 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2334 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2335 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2336 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2337 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2338 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2339 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2340 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2341 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2342 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2343 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2344 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2345 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2346 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2347 enum intel_sbi_destination destination
);
2348 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2349 enum intel_sbi_destination destination
);
2351 int vlv_gpu_freq(int ddr_freq
, int val
);
2352 int vlv_freq_opcode(int ddr_freq
, int val
);
2354 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2355 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2357 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2358 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2359 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2360 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2362 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2363 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2364 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2365 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2367 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2368 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2370 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2371 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2373 /* "Broadcast RGB" property */
2374 #define INTEL_BROADCAST_RGB_AUTO 0
2375 #define INTEL_BROADCAST_RGB_FULL 1
2376 #define INTEL_BROADCAST_RGB_LIMITED 2
2378 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2380 if (HAS_PCH_SPLIT(dev
))
2381 return CPU_VGACNTRL
;
2382 else if (IS_VALLEYVIEW(dev
))
2383 return VLV_VGACNTRL
;
2388 static inline void __user
*to_user_ptr(u64 address
)
2390 return (void __user
*)(uintptr_t)address
;
2393 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2395 unsigned long j
= msecs_to_jiffies(m
);
2397 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2400 static inline unsigned long
2401 timespec_to_jiffies_timeout(const struct timespec
*value
)
2403 unsigned long j
= timespec_to_jiffies(value
);
2405 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);