1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
53 #include "intel_guc.h"
55 /* General customization:
58 #define DRIVER_NAME "i915"
59 #define DRIVER_DESC "Intel Graphics"
60 #define DRIVER_DATE "20151010"
63 /* Many gcc seem to no see through this and fall over :( */
65 #define WARN_ON(x) ({ \
66 bool __i915_warn_cond = (x); \
67 if (__builtin_constant_p(__i915_warn_cond)) \
68 BUILD_BUG_ON(__i915_warn_cond); \
69 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
71 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
75 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
77 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
78 (long) (x), __func__);
80 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
82 * which may not necessarily be a user visible problem. This will either
83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
84 * enable distros and users to tailor their preferred amount of i915 abrt
87 #define I915_STATE_WARN(condition, format...) ({ \
88 int __ret_warn_on = !!(condition); \
89 if (unlikely(__ret_warn_on)) { \
90 if (i915.verbose_state_checks) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(condition) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) { \
101 if (i915.verbose_state_checks) \
102 WARN(1, "WARN_ON(" #condition ")\n"); \
104 DRM_ERROR("WARN_ON(" #condition ")\n"); \
106 unlikely(__ret_warn_on); \
109 static inline const char *yesno(bool v
)
111 return v
? "yes" : "no";
120 I915_MAX_PIPES
= _PIPE_EDP
122 #define pipe_name(p) ((p) + 'A')
131 #define transcoder_name(t) ((t) + 'A')
134 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
135 * number of planes per CRTC. Not all platforms really have this many planes,
136 * which means some arrays of size I915_MAX_PLANES may have unused entries
137 * between the topmost sprite plane and the cursor plane.
146 #define plane_name(p) ((p) + 'A')
148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
158 #define port_name(p) ((p) + 'A')
160 #define I915_NUM_PHYS_VLV 2
172 enum intel_display_power_domain
{
176 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
177 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
178 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
179 POWER_DOMAIN_TRANSCODER_A
,
180 POWER_DOMAIN_TRANSCODER_B
,
181 POWER_DOMAIN_TRANSCODER_C
,
182 POWER_DOMAIN_TRANSCODER_EDP
,
183 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
184 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
185 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
186 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
187 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
188 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
189 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
190 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
191 POWER_DOMAIN_PORT_DDI_E_2_LANES
,
192 POWER_DOMAIN_PORT_DSI
,
193 POWER_DOMAIN_PORT_CRT
,
194 POWER_DOMAIN_PORT_OTHER
,
207 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
208 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
209 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
210 #define POWER_DOMAIN_TRANSCODER(tran) \
211 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
212 (tran) + POWER_DOMAIN_TRANSCODER_A)
216 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
228 #define for_each_hpd_pin(__pin) \
229 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
231 struct i915_hotplug
{
232 struct work_struct hotplug_work
;
235 unsigned long last_jiffies
;
240 HPD_MARK_DISABLED
= 2
242 } stats
[HPD_NUM_PINS
];
244 struct delayed_work reenable_work
;
246 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
249 struct work_struct dig_port_work
;
252 * if we get a HPD irq from DP and a HPD irq from non-DP
253 * the non-DP HPD could block the workqueue on a mode config
254 * mutex getting, that userspace may have taken. However
255 * userspace is waiting on the DP workqueue to run which is
256 * blocked behind the non-DP one.
258 struct workqueue_struct
*dp_wq
;
261 #define I915_GEM_GPU_DOMAINS \
262 (I915_GEM_DOMAIN_RENDER | \
263 I915_GEM_DOMAIN_SAMPLER | \
264 I915_GEM_DOMAIN_COMMAND | \
265 I915_GEM_DOMAIN_INSTRUCTION | \
266 I915_GEM_DOMAIN_VERTEX)
268 #define for_each_pipe(__dev_priv, __p) \
269 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
270 #define for_each_plane(__dev_priv, __pipe, __p) \
272 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
274 #define for_each_sprite(__dev_priv, __p, __s) \
276 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
279 #define for_each_crtc(dev, crtc) \
280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
282 #define for_each_intel_plane(dev, intel_plane) \
283 list_for_each_entry(intel_plane, \
284 &dev->mode_config.plane_list, \
287 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
288 list_for_each_entry(intel_plane, \
289 &(dev)->mode_config.plane_list, \
291 if ((intel_plane)->pipe == (intel_crtc)->pipe)
293 #define for_each_intel_crtc(dev, intel_crtc) \
294 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
296 #define for_each_intel_encoder(dev, intel_encoder) \
297 list_for_each_entry(intel_encoder, \
298 &(dev)->mode_config.encoder_list, \
301 #define for_each_intel_connector(dev, intel_connector) \
302 list_for_each_entry(intel_connector, \
303 &dev->mode_config.connector_list, \
306 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
307 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
308 if ((intel_encoder)->base.crtc == (__crtc))
310 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
311 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
312 if ((intel_connector)->base.encoder == (__encoder))
314 #define for_each_power_domain(domain, mask) \
315 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
316 if ((1 << (domain)) & (mask))
318 struct drm_i915_private
;
319 struct i915_mm_struct
;
320 struct i915_mmu_object
;
322 struct drm_i915_file_private
{
323 struct drm_i915_private
*dev_priv
;
324 struct drm_file
*file
;
328 struct list_head request_list
;
329 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
330 * chosen to prevent the CPU getting more than a frame ahead of the GPU
331 * (when using lax throttling for the frontbuffer). We also use it to
332 * offer free GPU waitboosts for severely congested workloads.
334 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
336 struct idr context_idr
;
338 struct intel_rps_client
{
339 struct list_head link
;
343 struct intel_engine_cs
*bsd_ring
;
347 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
348 /* real shared dpll ids must be >= 0 */
349 DPLL_ID_PCH_PLL_A
= 0,
350 DPLL_ID_PCH_PLL_B
= 1,
355 DPLL_ID_SKL_DPLL1
= 0,
356 DPLL_ID_SKL_DPLL2
= 1,
357 DPLL_ID_SKL_DPLL3
= 2,
359 #define I915_NUM_PLLS 3
361 struct intel_dpll_hw_state
{
373 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
374 * lower part of ctrl1 and they get shifted into position when writing
375 * the register. This allows us to easily compare the state to share
379 /* HDMI only, 0 when used for DP */
380 uint32_t cfgcr1
, cfgcr2
;
383 uint32_t ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
,
387 struct intel_shared_dpll_config
{
388 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
389 struct intel_dpll_hw_state hw_state
;
392 struct intel_shared_dpll
{
393 struct intel_shared_dpll_config config
;
395 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
396 bool on
; /* is the PLL actually active? Disabled during modeset */
398 /* should match the index in the dev_priv->shared_dplls array */
399 enum intel_dpll_id id
;
400 /* The mode_set hook is optional and should be used together with the
401 * intel_prepare_shared_dpll function. */
402 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
403 struct intel_shared_dpll
*pll
);
404 void (*enable
)(struct drm_i915_private
*dev_priv
,
405 struct intel_shared_dpll
*pll
);
406 void (*disable
)(struct drm_i915_private
*dev_priv
,
407 struct intel_shared_dpll
*pll
);
408 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
409 struct intel_shared_dpll
*pll
,
410 struct intel_dpll_hw_state
*hw_state
);
418 /* Used by dp and fdi links */
419 struct intel_link_m_n
{
427 void intel_link_compute_m_n(int bpp
, int nlanes
,
428 int pixel_clock
, int link_clock
,
429 struct intel_link_m_n
*m_n
);
431 /* Interface history:
434 * 1.2: Add Power Management
435 * 1.3: Add vblank support
436 * 1.4: Fix cmdbuffer path, add heap destroy
437 * 1.5: Add vblank pipe configuration
438 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
439 * - Support vertical blank on secondary display pipe
441 #define DRIVER_MAJOR 1
442 #define DRIVER_MINOR 6
443 #define DRIVER_PATCHLEVEL 0
445 #define WATCH_LISTS 0
447 struct opregion_header
;
448 struct opregion_acpi
;
449 struct opregion_swsci
;
450 struct opregion_asle
;
452 struct intel_opregion
{
453 struct opregion_header
*header
;
454 struct opregion_acpi
*acpi
;
455 struct opregion_swsci
*swsci
;
456 u32 swsci_gbda_sub_functions
;
457 u32 swsci_sbcb_sub_functions
;
458 struct opregion_asle
*asle
;
461 struct work_struct asle_work
;
463 #define OPREGION_SIZE (8*1024)
465 struct intel_overlay
;
466 struct intel_overlay_error_state
;
468 #define I915_FENCE_REG_NONE -1
469 #define I915_MAX_NUM_FENCES 32
470 /* 32 fences + sign bit for FENCE_REG_NONE */
471 #define I915_MAX_NUM_FENCE_BITS 6
473 struct drm_i915_fence_reg
{
474 struct list_head lru_list
;
475 struct drm_i915_gem_object
*obj
;
479 struct sdvo_device_mapping
{
488 struct intel_display_error_state
;
490 struct drm_i915_error_state
{
499 /* Generic register state */
507 u32 error
; /* gen6+ */
508 u32 err_int
; /* gen7 */
509 u32 fault_data0
; /* gen8, gen9 */
510 u32 fault_data1
; /* gen8, gen9 */
516 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
517 u64 fence
[I915_MAX_NUM_FENCES
];
518 struct intel_overlay_error_state
*overlay
;
519 struct intel_display_error_state
*display
;
520 struct drm_i915_error_object
*semaphore_obj
;
522 struct drm_i915_error_ring
{
524 /* Software tracked state */
527 enum intel_ring_hangcheck_action hangcheck_action
;
530 /* our own tracking of ring head and tail */
534 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
553 u32 rc_psmi
; /* sleep state */
554 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
556 struct drm_i915_error_object
{
560 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
562 struct drm_i915_error_request
{
577 char comm
[TASK_COMM_LEN
];
578 } ring
[I915_NUM_RINGS
];
580 struct drm_i915_error_buffer
{
583 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
587 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
595 } **active_bo
, **pinned_bo
;
597 u32
*active_bo_count
, *pinned_bo_count
;
601 struct intel_connector
;
602 struct intel_encoder
;
603 struct intel_crtc_state
;
604 struct intel_initial_plane_config
;
609 struct drm_i915_display_funcs
{
610 int (*get_display_clock_speed
)(struct drm_device
*dev
);
611 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
613 * find_dpll() - Find the best values for the PLL
614 * @limit: limits for the PLL
615 * @crtc: current CRTC
616 * @target: target frequency in kHz
617 * @refclk: reference clock frequency in kHz
618 * @match_clock: if provided, @best_clock P divider must
619 * match the P divider from @match_clock
620 * used for LVDS downclocking
621 * @best_clock: best PLL values found
623 * Returns true on success, false on failure.
625 bool (*find_dpll
)(const struct intel_limit
*limit
,
626 struct intel_crtc_state
*crtc_state
,
627 int target
, int refclk
,
628 struct dpll
*match_clock
,
629 struct dpll
*best_clock
);
630 void (*update_wm
)(struct drm_crtc
*crtc
);
631 void (*update_sprite_wm
)(struct drm_plane
*plane
,
632 struct drm_crtc
*crtc
,
633 uint32_t sprite_width
, uint32_t sprite_height
,
634 int pixel_size
, bool enable
, bool scaled
);
635 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
636 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
637 /* Returns the active state of the crtc, and if the crtc is active,
638 * fills out the pipe-config with the hw state. */
639 bool (*get_pipe_config
)(struct intel_crtc
*,
640 struct intel_crtc_state
*);
641 void (*get_initial_plane_config
)(struct intel_crtc
*,
642 struct intel_initial_plane_config
*);
643 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
644 struct intel_crtc_state
*crtc_state
);
645 void (*crtc_enable
)(struct drm_crtc
*crtc
);
646 void (*crtc_disable
)(struct drm_crtc
*crtc
);
647 void (*audio_codec_enable
)(struct drm_connector
*connector
,
648 struct intel_encoder
*encoder
,
649 const struct drm_display_mode
*adjusted_mode
);
650 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
651 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
652 void (*init_clock_gating
)(struct drm_device
*dev
);
653 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
654 struct drm_framebuffer
*fb
,
655 struct drm_i915_gem_object
*obj
,
656 struct drm_i915_gem_request
*req
,
658 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
659 struct drm_framebuffer
*fb
,
661 void (*hpd_irq_setup
)(struct drm_device
*dev
);
662 /* clock updates for mode set */
664 /* render clock increase/decrease */
665 /* display clock increase/decrease */
666 /* pll clock increase/decrease */
669 enum forcewake_domain_id
{
670 FW_DOMAIN_ID_RENDER
= 0,
671 FW_DOMAIN_ID_BLITTER
,
677 enum forcewake_domains
{
678 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
679 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
680 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
681 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
686 struct intel_uncore_funcs
{
687 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
688 enum forcewake_domains domains
);
689 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
690 enum forcewake_domains domains
);
692 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
693 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
694 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
695 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
697 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
698 uint8_t val
, bool trace
);
699 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
700 uint16_t val
, bool trace
);
701 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
702 uint32_t val
, bool trace
);
703 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
704 uint64_t val
, bool trace
);
707 struct intel_uncore
{
708 spinlock_t lock
; /** lock is also taken in irq contexts. */
710 struct intel_uncore_funcs funcs
;
713 enum forcewake_domains fw_domains
;
715 struct intel_uncore_forcewake_domain
{
716 struct drm_i915_private
*i915
;
717 enum forcewake_domain_id id
;
719 struct timer_list timer
;
726 } fw_domain
[FW_DOMAIN_ID_COUNT
];
729 /* Iterate over initialised fw domains */
730 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
731 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
732 (i__) < FW_DOMAIN_ID_COUNT; \
733 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
734 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
736 #define for_each_fw_domain(domain__, dev_priv__, i__) \
737 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
740 FW_UNINITIALIZED
= 0,
747 uint32_t *dmc_payload
;
748 uint32_t dmc_fw_size
;
750 uint32_t mmioaddr
[8];
751 uint32_t mmiodata
[8];
752 enum csr_state state
;
755 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
756 func(is_mobile) sep \
759 func(is_i945gm) sep \
761 func(need_gfx_hws) sep \
763 func(is_pineview) sep \
764 func(is_broadwater) sep \
765 func(is_crestline) sep \
766 func(is_ivybridge) sep \
767 func(is_valleyview) sep \
768 func(is_haswell) sep \
769 func(is_skylake) sep \
770 func(is_preliminary) sep \
772 func(has_pipe_cxsr) sep \
773 func(has_hotplug) sep \
774 func(cursor_needs_physical) sep \
775 func(has_overlay) sep \
776 func(overlay_needs_physical) sep \
777 func(supports_tv) sep \
782 #define DEFINE_FLAG(name) u8 name:1
783 #define SEP_SEMICOLON ;
785 struct intel_device_info
{
786 u32 display_mmio_offset
;
789 u8 num_sprites
[I915_MAX_PIPES
];
791 u8 ring_mask
; /* Rings supported by the HW */
792 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
793 /* Register offsets for the various display pipes and transcoders */
794 int pipe_offsets
[I915_MAX_TRANSCODERS
];
795 int trans_offsets
[I915_MAX_TRANSCODERS
];
796 int palette_offsets
[I915_MAX_PIPES
];
797 int cursor_offsets
[I915_MAX_PIPES
];
799 /* Slice/subslice/EU info */
802 u8 subslice_per_slice
;
805 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
808 u8 has_subslice_pg
:1;
815 enum i915_cache_level
{
817 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
818 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
819 caches, eg sampler/render caches, and the
820 large Last-Level-Cache. LLC is coherent with
821 the CPU, but L3 is only visible to the GPU. */
822 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
825 struct i915_ctx_hang_stats
{
826 /* This context had batch pending when hang was declared */
827 unsigned batch_pending
;
829 /* This context had batch active when hang was declared */
830 unsigned batch_active
;
832 /* Time when this context was last blamed for a GPU reset */
833 unsigned long guilty_ts
;
835 /* If the contexts causes a second GPU hang within this time,
836 * it is permanently banned from submitting any more work.
838 unsigned long ban_period_seconds
;
840 /* This context is banned to submit more work */
844 /* This must match up with the value previously used for execbuf2.rsvd1. */
845 #define DEFAULT_CONTEXT_HANDLE 0
847 #define CONTEXT_NO_ZEROMAP (1<<0)
849 * struct intel_context - as the name implies, represents a context.
850 * @ref: reference count.
851 * @user_handle: userspace tracking identity for this context.
852 * @remap_slice: l3 row remapping information.
853 * @flags: context specific flags:
854 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
855 * @file_priv: filp associated with this context (NULL for global default
857 * @hang_stats: information about the role of this context in possible GPU
859 * @ppgtt: virtual memory space used by this context.
860 * @legacy_hw_ctx: render context backing object and whether it is correctly
861 * initialized (legacy ring submission mechanism only).
862 * @link: link in the global list of contexts.
864 * Contexts are memory images used by the hardware to store copies of their
867 struct intel_context
{
871 struct drm_i915_private
*i915
;
873 struct drm_i915_file_private
*file_priv
;
874 struct i915_ctx_hang_stats hang_stats
;
875 struct i915_hw_ppgtt
*ppgtt
;
877 /* Legacy ring buffer submission */
879 struct drm_i915_gem_object
*rcs_state
;
885 struct drm_i915_gem_object
*state
;
886 struct intel_ringbuffer
*ringbuf
;
888 } engine
[I915_NUM_RINGS
];
890 struct list_head link
;
902 /* This is always the inner lock when overlapping with struct_mutex and
903 * it's the outer lock when overlapping with stolen_lock. */
905 unsigned long uncompressed_size
;
908 unsigned int possible_framebuffer_bits
;
909 unsigned int busy_bits
;
910 struct intel_crtc
*crtc
;
913 struct drm_mm_node compressed_fb
;
914 struct drm_mm_node
*compressed_llb
;
918 /* Tracks whether the HW is actually enabled, not whether the feature is
922 struct intel_fbc_work
{
923 struct delayed_work work
;
924 struct intel_crtc
*crtc
;
925 struct drm_framebuffer
*fb
;
929 FBC_OK
, /* FBC is enabled */
930 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
931 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
932 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
933 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
934 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
935 FBC_BAD_PLANE
, /* fbc not supported on plane */
936 FBC_NOT_TILED
, /* buffer not tiled */
937 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
939 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
940 FBC_ROTATION
, /* rotation is not supported */
941 FBC_IN_DBG_MASTER
, /* kernel debugger is active */
942 FBC_BAD_STRIDE
, /* stride is not supported */
943 FBC_PIXEL_RATE
, /* pixel rate is too big */
944 FBC_PIXEL_FORMAT
/* pixel format is invalid */
947 bool (*fbc_enabled
)(struct drm_i915_private
*dev_priv
);
948 void (*enable_fbc
)(struct intel_crtc
*crtc
);
949 void (*disable_fbc
)(struct drm_i915_private
*dev_priv
);
953 * HIGH_RR is the highest eDP panel refresh rate read from EDID
954 * LOW_RR is the lowest eDP panel refresh rate found from EDID
955 * parsing for same resolution.
957 enum drrs_refresh_rate_type
{
960 DRRS_MAX_RR
, /* RR count */
963 enum drrs_support_type
{
964 DRRS_NOT_SUPPORTED
= 0,
965 STATIC_DRRS_SUPPORT
= 1,
966 SEAMLESS_DRRS_SUPPORT
= 2
972 struct delayed_work work
;
974 unsigned busy_frontbuffer_bits
;
975 enum drrs_refresh_rate_type refresh_rate_type
;
976 enum drrs_support_type type
;
983 struct intel_dp
*enabled
;
985 struct delayed_work work
;
986 unsigned busy_frontbuffer_bits
;
992 PCH_NONE
= 0, /* No PCH present */
993 PCH_IBX
, /* Ibexpeak PCH */
994 PCH_CPT
, /* Cougarpoint PCH */
995 PCH_LPT
, /* Lynxpoint PCH */
996 PCH_SPT
, /* Sunrisepoint PCH */
1000 enum intel_sbi_destination
{
1005 #define QUIRK_PIPEA_FORCE (1<<0)
1006 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1007 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1008 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1009 #define QUIRK_PIPEB_FORCE (1<<4)
1010 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1013 struct intel_fbc_work
;
1015 struct intel_gmbus
{
1016 struct i2c_adapter adapter
;
1020 struct i2c_algo_bit_data bit_algo
;
1021 struct drm_i915_private
*dev_priv
;
1024 struct i915_suspend_saved_registers
{
1027 u32 savePP_ON_DELAYS
;
1028 u32 savePP_OFF_DELAYS
;
1033 u32 saveFBC_CONTROL
;
1034 u32 saveCACHE_MODE_0
;
1035 u32 saveMI_ARB_STATE
;
1039 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1040 u32 savePCH_PORT_HOTPLUG
;
1044 struct vlv_s0ix_state
{
1051 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1052 u32 media_max_req_count
;
1053 u32 gfx_max_req_count
;
1079 u32 rp_down_timeout
;
1085 /* Display 1 CZ domain */
1090 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1092 /* GT SA CZ domain */
1099 /* Display 2 CZ domain */
1103 u32 clock_gate_dis2
;
1106 struct intel_rps_ei
{
1112 struct intel_gen6_power_mgmt
{
1114 * work, interrupts_enabled and pm_iir are protected by
1115 * dev_priv->irq_lock
1117 struct work_struct work
;
1118 bool interrupts_enabled
;
1121 /* Frequencies are stored in potentially platform dependent multiples.
1122 * In other words, *_freq needs to be multiplied by X to be interesting.
1123 * Soft limits are those which are used for the dynamic reclocking done
1124 * by the driver (raise frequencies under heavy loads, and lower for
1125 * lighter loads). Hard limits are those imposed by the hardware.
1127 * A distinction is made for overclocking, which is never enabled by
1128 * default, and is considered to be above the hard limit if it's
1131 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1132 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1133 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1134 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1135 u8 min_freq
; /* AKA RPn. Minimum frequency */
1136 u8 idle_freq
; /* Frequency to request when we are idle */
1137 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1138 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1139 u8 rp0_freq
; /* Non-overclocked max frequency. */
1141 u8 up_threshold
; /* Current %busy required to uplock */
1142 u8 down_threshold
; /* Current %busy required to downclock */
1145 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1147 spinlock_t client_lock
;
1148 struct list_head clients
;
1152 struct delayed_work delayed_resume_work
;
1155 struct intel_rps_client semaphores
, mmioflips
;
1157 /* manual wa residency calculations */
1158 struct intel_rps_ei up_ei
, down_ei
;
1161 * Protects RPS/RC6 register access and PCU communication.
1162 * Must be taken after struct_mutex if nested. Note that
1163 * this lock may be held for long periods of time when
1164 * talking to hw - so only take it when talking to hw!
1166 struct mutex hw_lock
;
1169 /* defined intel_pm.c */
1170 extern spinlock_t mchdev_lock
;
1172 struct intel_ilk_power_mgmt
{
1180 unsigned long last_time1
;
1181 unsigned long chipset_power
;
1184 unsigned long gfx_power
;
1191 struct drm_i915_private
;
1192 struct i915_power_well
;
1194 struct i915_power_well_ops
{
1196 * Synchronize the well's hw state to match the current sw state, for
1197 * example enable/disable it based on the current refcount. Called
1198 * during driver init and resume time, possibly after first calling
1199 * the enable/disable handlers.
1201 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1202 struct i915_power_well
*power_well
);
1204 * Enable the well and resources that depend on it (for example
1205 * interrupts located on the well). Called after the 0->1 refcount
1208 void (*enable
)(struct drm_i915_private
*dev_priv
,
1209 struct i915_power_well
*power_well
);
1211 * Disable the well and resources that depend on it. Called after
1212 * the 1->0 refcount transition.
1214 void (*disable
)(struct drm_i915_private
*dev_priv
,
1215 struct i915_power_well
*power_well
);
1216 /* Returns the hw enabled state. */
1217 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1218 struct i915_power_well
*power_well
);
1221 /* Power well structure for haswell */
1222 struct i915_power_well
{
1225 /* power well enable/disable usage count */
1227 /* cached hw enabled state */
1229 unsigned long domains
;
1231 const struct i915_power_well_ops
*ops
;
1234 struct i915_power_domains
{
1236 * Power wells needed for initialization at driver init and suspend
1237 * time are on. They are kept on until after the first modeset.
1241 int power_well_count
;
1244 int domain_use_count
[POWER_DOMAIN_NUM
];
1245 struct i915_power_well
*power_wells
;
1248 #define MAX_L3_SLICES 2
1249 struct intel_l3_parity
{
1250 u32
*remap_info
[MAX_L3_SLICES
];
1251 struct work_struct error_work
;
1255 struct i915_gem_mm
{
1256 /** Memory allocator for GTT stolen memory */
1257 struct drm_mm stolen
;
1258 /** Protects the usage of the GTT stolen memory allocator. This is
1259 * always the inner lock when overlapping with struct_mutex. */
1260 struct mutex stolen_lock
;
1262 /** List of all objects in gtt_space. Used to restore gtt
1263 * mappings on resume */
1264 struct list_head bound_list
;
1266 * List of objects which are not bound to the GTT (thus
1267 * are idle and not used by the GPU) but still have
1268 * (presumably uncached) pages still attached.
1270 struct list_head unbound_list
;
1272 /** Usable portion of the GTT for GEM */
1273 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1275 /** PPGTT used for aliasing the PPGTT with the GTT */
1276 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1278 struct notifier_block oom_notifier
;
1279 struct shrinker shrinker
;
1280 bool shrinker_no_lock_stealing
;
1282 /** LRU list of objects with fence regs on them. */
1283 struct list_head fence_list
;
1286 * We leave the user IRQ off as much as possible,
1287 * but this means that requests will finish and never
1288 * be retired once the system goes idle. Set a timer to
1289 * fire periodically while the ring is running. When it
1290 * fires, go retire requests.
1292 struct delayed_work retire_work
;
1295 * When we detect an idle GPU, we want to turn on
1296 * powersaving features. So once we see that there
1297 * are no more requests outstanding and no more
1298 * arrive within a small period of time, we fire
1299 * off the idle_work.
1301 struct delayed_work idle_work
;
1304 * Are we in a non-interruptible section of code like
1310 * Is the GPU currently considered idle, or busy executing userspace
1311 * requests? Whilst idle, we attempt to power down the hardware and
1312 * display clocks. In order to reduce the effect on performance, there
1313 * is a slight delay before we do so.
1317 /* the indicator for dispatch video commands on two BSD rings */
1318 int bsd_ring_dispatch_index
;
1320 /** Bit 6 swizzling required for X tiling */
1321 uint32_t bit_6_swizzle_x
;
1322 /** Bit 6 swizzling required for Y tiling */
1323 uint32_t bit_6_swizzle_y
;
1325 /* accounting, useful for userland debugging */
1326 spinlock_t object_stat_lock
;
1327 size_t object_memory
;
1331 struct drm_i915_error_state_buf
{
1332 struct drm_i915_private
*i915
;
1341 struct i915_error_state_file_priv
{
1342 struct drm_device
*dev
;
1343 struct drm_i915_error_state
*error
;
1346 struct i915_gpu_error
{
1347 /* For hangcheck timer */
1348 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1349 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1350 /* Hang gpu twice in this window and your context gets banned */
1351 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1353 struct workqueue_struct
*hangcheck_wq
;
1354 struct delayed_work hangcheck_work
;
1356 /* For reset and error_state handling. */
1358 /* Protected by the above dev->gpu_error.lock. */
1359 struct drm_i915_error_state
*first_error
;
1361 unsigned long missed_irq_rings
;
1364 * State variable controlling the reset flow and count
1366 * This is a counter which gets incremented when reset is triggered,
1367 * and again when reset has been handled. So odd values (lowest bit set)
1368 * means that reset is in progress and even values that
1369 * (reset_counter >> 1):th reset was successfully completed.
1371 * If reset is not completed succesfully, the I915_WEDGE bit is
1372 * set meaning that hardware is terminally sour and there is no
1373 * recovery. All waiters on the reset_queue will be woken when
1376 * This counter is used by the wait_seqno code to notice that reset
1377 * event happened and it needs to restart the entire ioctl (since most
1378 * likely the seqno it waited for won't ever signal anytime soon).
1380 * This is important for lock-free wait paths, where no contended lock
1381 * naturally enforces the correct ordering between the bail-out of the
1382 * waiter and the gpu reset work code.
1384 atomic_t reset_counter
;
1386 #define I915_RESET_IN_PROGRESS_FLAG 1
1387 #define I915_WEDGED (1 << 31)
1390 * Waitqueue to signal when the reset has completed. Used by clients
1391 * that wait for dev_priv->mm.wedged to settle.
1393 wait_queue_head_t reset_queue
;
1395 /* Userspace knobs for gpu hang simulation;
1396 * combines both a ring mask, and extra flags
1399 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1400 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1402 /* For missed irq/seqno simulation. */
1403 unsigned int test_irq_rings
;
1405 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1406 bool reload_in_reset
;
1409 enum modeset_restore
{
1410 MODESET_ON_LID_OPEN
,
1415 #define DP_AUX_A 0x40
1416 #define DP_AUX_B 0x10
1417 #define DP_AUX_C 0x20
1418 #define DP_AUX_D 0x30
1420 #define DDC_PIN_B 0x05
1421 #define DDC_PIN_C 0x04
1422 #define DDC_PIN_D 0x06
1424 struct ddi_vbt_port_info
{
1426 * This is an index in the HDMI/DVI DDI buffer translation table.
1427 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1428 * populate this field.
1430 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1431 uint8_t hdmi_level_shift
;
1433 uint8_t supports_dvi
:1;
1434 uint8_t supports_hdmi
:1;
1435 uint8_t supports_dp
:1;
1437 uint8_t alternate_aux_channel
;
1438 uint8_t alternate_ddc_pin
;
1440 uint8_t dp_boost_level
;
1441 uint8_t hdmi_boost_level
;
1444 enum psr_lines_to_wait
{
1445 PSR_0_LINES_TO_WAIT
= 0,
1447 PSR_4_LINES_TO_WAIT
,
1451 struct intel_vbt_data
{
1452 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1453 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1456 unsigned int int_tv_support
:1;
1457 unsigned int lvds_dither
:1;
1458 unsigned int lvds_vbt
:1;
1459 unsigned int int_crt_support
:1;
1460 unsigned int lvds_use_ssc
:1;
1461 unsigned int display_clock_mode
:1;
1462 unsigned int fdi_rx_polarity_inverted
:1;
1463 unsigned int has_mipi
:1;
1465 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1467 enum drrs_support_type drrs_type
;
1472 int edp_preemphasis
;
1474 bool edp_initialized
;
1477 struct edp_power_seq edp_pps
;
1481 bool require_aux_wakeup
;
1483 enum psr_lines_to_wait lines_to_wait
;
1484 int tp1_wakeup_time
;
1485 int tp2_tp3_wakeup_time
;
1491 bool active_low_pwm
;
1492 u8 min_brightness
; /* min_brightness/255 of max */
1499 struct mipi_config
*config
;
1500 struct mipi_pps_data
*pps
;
1504 u8
*sequence
[MIPI_SEQ_MAX
];
1510 union child_device_config
*child_dev
;
1512 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1515 enum intel_ddb_partitioning
{
1517 INTEL_DDB_PART_5_6
, /* IVB+ */
1520 struct intel_wm_level
{
1528 struct ilk_wm_values
{
1529 uint32_t wm_pipe
[3];
1531 uint32_t wm_lp_spr
[3];
1532 uint32_t wm_linetime
[3];
1534 enum intel_ddb_partitioning partitioning
;
1537 struct vlv_pipe_wm
{
1548 struct vlv_wm_values
{
1549 struct vlv_pipe_wm pipe
[3];
1550 struct vlv_sr_wm sr
;
1560 struct skl_ddb_entry
{
1561 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1564 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1566 return entry
->end
- entry
->start
;
1569 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1570 const struct skl_ddb_entry
*e2
)
1572 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1578 struct skl_ddb_allocation
{
1579 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1580 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1581 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1584 struct skl_wm_values
{
1585 bool dirty
[I915_MAX_PIPES
];
1586 struct skl_ddb_allocation ddb
;
1587 uint32_t wm_linetime
[I915_MAX_PIPES
];
1588 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1589 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1592 struct skl_wm_level
{
1593 bool plane_en
[I915_MAX_PLANES
];
1594 uint16_t plane_res_b
[I915_MAX_PLANES
];
1595 uint8_t plane_res_l
[I915_MAX_PLANES
];
1599 * This struct helps tracking the state needed for runtime PM, which puts the
1600 * device in PCI D3 state. Notice that when this happens, nothing on the
1601 * graphics device works, even register access, so we don't get interrupts nor
1604 * Every piece of our code that needs to actually touch the hardware needs to
1605 * either call intel_runtime_pm_get or call intel_display_power_get with the
1606 * appropriate power domain.
1608 * Our driver uses the autosuspend delay feature, which means we'll only really
1609 * suspend if we stay with zero refcount for a certain amount of time. The
1610 * default value is currently very conservative (see intel_runtime_pm_enable), but
1611 * it can be changed with the standard runtime PM files from sysfs.
1613 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1614 * goes back to false exactly before we reenable the IRQs. We use this variable
1615 * to check if someone is trying to enable/disable IRQs while they're supposed
1616 * to be disabled. This shouldn't happen and we'll print some error messages in
1619 * For more, read the Documentation/power/runtime_pm.txt.
1621 struct i915_runtime_pm
{
1626 enum intel_pipe_crc_source
{
1627 INTEL_PIPE_CRC_SOURCE_NONE
,
1628 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1629 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1630 INTEL_PIPE_CRC_SOURCE_PF
,
1631 INTEL_PIPE_CRC_SOURCE_PIPE
,
1632 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1633 INTEL_PIPE_CRC_SOURCE_TV
,
1634 INTEL_PIPE_CRC_SOURCE_DP_B
,
1635 INTEL_PIPE_CRC_SOURCE_DP_C
,
1636 INTEL_PIPE_CRC_SOURCE_DP_D
,
1637 INTEL_PIPE_CRC_SOURCE_AUTO
,
1638 INTEL_PIPE_CRC_SOURCE_MAX
,
1641 struct intel_pipe_crc_entry
{
1646 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1647 struct intel_pipe_crc
{
1649 bool opened
; /* exclusive access to the result file */
1650 struct intel_pipe_crc_entry
*entries
;
1651 enum intel_pipe_crc_source source
;
1653 wait_queue_head_t wq
;
1656 struct i915_frontbuffer_tracking
{
1660 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1667 struct i915_wa_reg
{
1670 /* bitmask representing WA bits */
1674 #define I915_MAX_WA_REGS 16
1676 struct i915_workarounds
{
1677 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1681 struct i915_virtual_gpu
{
1685 struct i915_execbuffer_params
{
1686 struct drm_device
*dev
;
1687 struct drm_file
*file
;
1688 uint32_t dispatch_flags
;
1689 uint32_t args_batch_start_offset
;
1690 uint64_t batch_obj_vm_offset
;
1691 struct intel_engine_cs
*ring
;
1692 struct drm_i915_gem_object
*batch_obj
;
1693 struct intel_context
*ctx
;
1694 struct drm_i915_gem_request
*request
;
1697 struct drm_i915_private
{
1698 struct drm_device
*dev
;
1699 struct kmem_cache
*objects
;
1700 struct kmem_cache
*vmas
;
1701 struct kmem_cache
*requests
;
1703 const struct intel_device_info info
;
1705 int relative_constants_mode
;
1709 struct intel_uncore uncore
;
1711 struct i915_virtual_gpu vgpu
;
1713 struct intel_guc guc
;
1715 struct intel_csr csr
;
1717 /* Display CSR-related protection */
1718 struct mutex csr_lock
;
1720 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1722 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1723 * controller on different i2c buses. */
1724 struct mutex gmbus_mutex
;
1727 * Base address of the gmbus and gpio block.
1729 uint32_t gpio_mmio_base
;
1731 /* MMIO base address for MIPI regs */
1732 uint32_t mipi_mmio_base
;
1734 wait_queue_head_t gmbus_wait_queue
;
1736 struct pci_dev
*bridge_dev
;
1737 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1738 struct drm_i915_gem_object
*semaphore_obj
;
1739 uint32_t last_seqno
, next_seqno
;
1741 struct drm_dma_handle
*status_page_dmah
;
1742 struct resource mch_res
;
1744 /* protects the irq masks */
1745 spinlock_t irq_lock
;
1747 /* protects the mmio flip data */
1748 spinlock_t mmio_flip_lock
;
1750 bool display_irqs_enabled
;
1752 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1753 struct pm_qos_request pm_qos
;
1755 /* Sideband mailbox protection */
1756 struct mutex sb_lock
;
1758 /** Cached value of IMR to avoid reads in updating the bitfield */
1761 u32 de_irq_mask
[I915_MAX_PIPES
];
1766 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1768 struct i915_hotplug hotplug
;
1769 struct i915_fbc fbc
;
1770 struct i915_drrs drrs
;
1771 struct intel_opregion opregion
;
1772 struct intel_vbt_data vbt
;
1774 bool preserve_bios_swizzle
;
1777 struct intel_overlay
*overlay
;
1779 /* backlight registers and fields in struct intel_panel */
1780 struct mutex backlight_lock
;
1783 bool no_aux_handshake
;
1785 /* protects panel power sequencer state */
1786 struct mutex pps_mutex
;
1788 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1789 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1790 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1792 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1793 unsigned int skl_boot_cdclk
;
1794 unsigned int cdclk_freq
, max_cdclk_freq
;
1795 unsigned int max_dotclk_freq
;
1796 unsigned int hpll_freq
;
1797 unsigned int czclk_freq
;
1800 * wq - Driver workqueue for GEM.
1802 * NOTE: Work items scheduled here are not allowed to grab any modeset
1803 * locks, for otherwise the flushing done in the pageflip code will
1804 * result in deadlocks.
1806 struct workqueue_struct
*wq
;
1808 /* Display functions */
1809 struct drm_i915_display_funcs display
;
1811 /* PCH chipset type */
1812 enum intel_pch pch_type
;
1813 unsigned short pch_id
;
1815 unsigned long quirks
;
1817 enum modeset_restore modeset_restore
;
1818 struct mutex modeset_restore_lock
;
1820 struct list_head vm_list
; /* Global list of all address spaces */
1821 struct i915_gtt gtt
; /* VM representing the global address space */
1823 struct i915_gem_mm mm
;
1824 DECLARE_HASHTABLE(mm_structs
, 7);
1825 struct mutex mm_lock
;
1827 /* Kernel Modesetting */
1829 struct sdvo_device_mapping sdvo_mappings
[2];
1831 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1832 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1833 wait_queue_head_t pending_flip_queue
;
1835 #ifdef CONFIG_DEBUG_FS
1836 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1839 int num_shared_dpll
;
1840 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1841 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1843 struct i915_workarounds workarounds
;
1845 /* Reclocking support */
1846 bool render_reclock_avail
;
1848 struct i915_frontbuffer_tracking fb_tracking
;
1852 bool mchbar_need_disable
;
1854 struct intel_l3_parity l3_parity
;
1856 /* Cannot be determined by PCIID. You must always read a register. */
1859 /* gen6+ rps state */
1860 struct intel_gen6_power_mgmt rps
;
1862 /* ilk-only ips/rps state. Everything in here is protected by the global
1863 * mchdev_lock in intel_pm.c */
1864 struct intel_ilk_power_mgmt ips
;
1866 struct i915_power_domains power_domains
;
1868 struct i915_psr psr
;
1870 struct i915_gpu_error gpu_error
;
1872 struct drm_i915_gem_object
*vlv_pctx
;
1874 #ifdef CONFIG_DRM_FBDEV_EMULATION
1875 /* list of fbdev register on this device */
1876 struct intel_fbdev
*fbdev
;
1877 struct work_struct fbdev_suspend_work
;
1880 struct drm_property
*broadcast_rgb_property
;
1881 struct drm_property
*force_audio_property
;
1883 /* hda/i915 audio component */
1884 struct i915_audio_component
*audio_component
;
1885 bool audio_component_registered
;
1887 * av_mutex - mutex for audio/video sync
1890 struct mutex av_mutex
;
1892 uint32_t hw_context_size
;
1893 struct list_head context_list
;
1897 u32 chv_phy_control
;
1900 struct i915_suspend_saved_registers regfile
;
1901 struct vlv_s0ix_state vlv_s0ix_state
;
1905 * Raw watermark latency values:
1906 * in 0.1us units for WM0,
1907 * in 0.5us units for WM1+.
1910 uint16_t pri_latency
[5];
1912 uint16_t spr_latency
[5];
1914 uint16_t cur_latency
[5];
1916 * Raw watermark memory latency values
1917 * for SKL for all 8 levels
1920 uint16_t skl_latency
[8];
1923 * The skl_wm_values structure is a bit too big for stack
1924 * allocation, so we keep the staging struct where we store
1925 * intermediate results here instead.
1927 struct skl_wm_values skl_results
;
1929 /* current hardware state */
1931 struct ilk_wm_values hw
;
1932 struct skl_wm_values skl_hw
;
1933 struct vlv_wm_values vlv
;
1939 struct i915_runtime_pm pm
;
1941 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1943 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1944 struct drm_i915_gem_execbuffer2
*args
,
1945 struct list_head
*vmas
);
1946 int (*init_rings
)(struct drm_device
*dev
);
1947 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1948 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1951 bool edp_low_vswing
;
1953 /* perform PHY state sanity checks? */
1954 bool chv_phy_assert
[2];
1957 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1958 * will be rejected. Instead look for a better place.
1962 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1964 return dev
->dev_private
;
1967 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1969 return to_i915(dev_get_drvdata(dev
));
1972 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
1974 return container_of(guc
, struct drm_i915_private
, guc
);
1977 /* Iterate over initialised rings */
1978 #define for_each_ring(ring__, dev_priv__, i__) \
1979 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1980 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1982 enum hdmi_force_audio
{
1983 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1984 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1985 HDMI_AUDIO_AUTO
, /* trust EDID */
1986 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1989 #define I915_GTT_OFFSET_NONE ((u32)-1)
1991 struct drm_i915_gem_object_ops
{
1992 /* Interface between the GEM object and its backing storage.
1993 * get_pages() is called once prior to the use of the associated set
1994 * of pages before to binding them into the GTT, and put_pages() is
1995 * called after we no longer need them. As we expect there to be
1996 * associated cost with migrating pages between the backing storage
1997 * and making them available for the GPU (e.g. clflush), we may hold
1998 * onto the pages after they are no longer referenced by the GPU
1999 * in case they may be used again shortly (for example migrating the
2000 * pages to a different memory domain within the GTT). put_pages()
2001 * will therefore most likely be called when the object itself is
2002 * being released or under memory pressure (where we attempt to
2003 * reap pages for the shrinker).
2005 int (*get_pages
)(struct drm_i915_gem_object
*);
2006 void (*put_pages
)(struct drm_i915_gem_object
*);
2007 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2008 void (*release
)(struct drm_i915_gem_object
*);
2012 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2013 * considered to be the frontbuffer for the given plane interface-wise. This
2014 * doesn't mean that the hw necessarily already scans it out, but that any
2015 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2017 * We have one bit per pipe and per scanout plane type.
2019 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2020 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2021 #define INTEL_FRONTBUFFER_BITS \
2022 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2023 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2024 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2025 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2026 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2027 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2028 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2029 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2030 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2031 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2032 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2034 struct drm_i915_gem_object
{
2035 struct drm_gem_object base
;
2037 const struct drm_i915_gem_object_ops
*ops
;
2039 /** List of VMAs backed by this object */
2040 struct list_head vma_list
;
2042 /** Stolen memory for this object, instead of being backed by shmem. */
2043 struct drm_mm_node
*stolen
;
2044 struct list_head global_list
;
2046 struct list_head ring_list
[I915_NUM_RINGS
];
2047 /** Used in execbuf to temporarily hold a ref */
2048 struct list_head obj_exec_link
;
2050 struct list_head batch_pool_link
;
2053 * This is set if the object is on the active lists (has pending
2054 * rendering and so a non-zero seqno), and is not set if it i s on
2055 * inactive (ready to be unbound) list.
2057 unsigned int active
:I915_NUM_RINGS
;
2060 * This is set if the object has been written to since last bound
2063 unsigned int dirty
:1;
2066 * Fence register bits (if any) for this object. Will be set
2067 * as needed when mapped into the GTT.
2068 * Protected by dev->struct_mutex.
2070 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2073 * Advice: are the backing pages purgeable?
2075 unsigned int madv
:2;
2078 * Current tiling mode for the object.
2080 unsigned int tiling_mode
:2;
2082 * Whether the tiling parameters for the currently associated fence
2083 * register have changed. Note that for the purposes of tracking
2084 * tiling changes we also treat the unfenced register, the register
2085 * slot that the object occupies whilst it executes a fenced
2086 * command (such as BLT on gen2/3), as a "fence".
2088 unsigned int fence_dirty
:1;
2091 * Is the object at the current location in the gtt mappable and
2092 * fenceable? Used to avoid costly recalculations.
2094 unsigned int map_and_fenceable
:1;
2097 * Whether the current gtt mapping needs to be mappable (and isn't just
2098 * mappable by accident). Track pin and fault separate for a more
2099 * accurate mappable working set.
2101 unsigned int fault_mappable
:1;
2104 * Is the object to be mapped as read-only to the GPU
2105 * Only honoured if hardware has relevant pte bit
2107 unsigned long gt_ro
:1;
2108 unsigned int cache_level
:3;
2109 unsigned int cache_dirty
:1;
2111 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2113 unsigned int pin_display
;
2115 struct sg_table
*pages
;
2116 int pages_pin_count
;
2118 struct scatterlist
*sg
;
2122 /* prime dma-buf support */
2123 void *dma_buf_vmapping
;
2126 /** Breadcrumb of last rendering to the buffer.
2127 * There can only be one writer, but we allow for multiple readers.
2128 * If there is a writer that necessarily implies that all other
2129 * read requests are complete - but we may only be lazily clearing
2130 * the read requests. A read request is naturally the most recent
2131 * request on a ring, so we may have two different write and read
2132 * requests on one ring where the write request is older than the
2133 * read request. This allows for the CPU to read from an active
2134 * buffer by only waiting for the write to complete.
2136 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2137 struct drm_i915_gem_request
*last_write_req
;
2138 /** Breadcrumb of last fenced GPU access to the buffer. */
2139 struct drm_i915_gem_request
*last_fenced_req
;
2141 /** Current tiling stride for the object, if it's tiled. */
2144 /** References from framebuffers, locks out tiling changes. */
2145 unsigned long framebuffer_references
;
2147 /** Record of address bit 17 of each page at last unbind. */
2148 unsigned long *bit_17
;
2151 /** for phy allocated objects */
2152 struct drm_dma_handle
*phys_handle
;
2154 struct i915_gem_userptr
{
2156 unsigned read_only
:1;
2157 unsigned workers
:4;
2158 #define I915_GEM_USERPTR_MAX_WORKERS 15
2160 struct i915_mm_struct
*mm
;
2161 struct i915_mmu_object
*mmu_object
;
2162 struct work_struct
*work
;
2166 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2168 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2169 struct drm_i915_gem_object
*new,
2170 unsigned frontbuffer_bits
);
2173 * Request queue structure.
2175 * The request queue allows us to note sequence numbers that have been emitted
2176 * and may be associated with active buffers to be retired.
2178 * By keeping this list, we can avoid having to do questionable sequence
2179 * number comparisons on buffer last_read|write_seqno. It also allows an
2180 * emission time to be associated with the request for tracking how far ahead
2181 * of the GPU the submission is.
2183 * The requests are reference counted, so upon creation they should have an
2184 * initial reference taken using kref_init
2186 struct drm_i915_gem_request
{
2189 /** On Which ring this request was generated */
2190 struct drm_i915_private
*i915
;
2191 struct intel_engine_cs
*ring
;
2193 /** GEM sequence number associated with this request. */
2196 /** Position in the ringbuffer of the start of the request */
2200 * Position in the ringbuffer of the start of the postfix.
2201 * This is required to calculate the maximum available ringbuffer
2202 * space without overwriting the postfix.
2206 /** Position in the ringbuffer of the end of the whole request */
2210 * Context and ring buffer related to this request
2211 * Contexts are refcounted, so when this request is associated with a
2212 * context, we must increment the context's refcount, to guarantee that
2213 * it persists while any request is linked to it. Requests themselves
2214 * are also refcounted, so the request will only be freed when the last
2215 * reference to it is dismissed, and the code in
2216 * i915_gem_request_free() will then decrement the refcount on the
2219 struct intel_context
*ctx
;
2220 struct intel_ringbuffer
*ringbuf
;
2222 /** Batch buffer related to this request if any (used for
2223 error state dump only) */
2224 struct drm_i915_gem_object
*batch_obj
;
2226 /** Time at which this request was emitted, in jiffies. */
2227 unsigned long emitted_jiffies
;
2229 /** global list entry for this request */
2230 struct list_head list
;
2232 struct drm_i915_file_private
*file_priv
;
2233 /** file_priv list entry for this request */
2234 struct list_head client_list
;
2236 /** process identifier submitting this request */
2240 * The ELSP only accepts two elements at a time, so we queue
2241 * context/tail pairs on a given queue (ring->execlist_queue) until the
2242 * hardware is available. The queue serves a double purpose: we also use
2243 * it to keep track of the up to 2 contexts currently in the hardware
2244 * (usually one in execution and the other queued up by the GPU): We
2245 * only remove elements from the head of the queue when the hardware
2246 * informs us that an element has been completed.
2248 * All accesses to the queue are mediated by a spinlock
2249 * (ring->execlist_lock).
2252 /** Execlist link in the submission queue.*/
2253 struct list_head execlist_link
;
2255 /** Execlists no. of times this request has been sent to the ELSP */
2260 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2261 struct intel_context
*ctx
,
2262 struct drm_i915_gem_request
**req_out
);
2263 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2264 void i915_gem_request_free(struct kref
*req_ref
);
2265 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2266 struct drm_file
*file
);
2268 static inline uint32_t
2269 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2271 return req
? req
->seqno
: 0;
2274 static inline struct intel_engine_cs
*
2275 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2277 return req
? req
->ring
: NULL
;
2280 static inline struct drm_i915_gem_request
*
2281 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2284 kref_get(&req
->ref
);
2289 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2291 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2292 kref_put(&req
->ref
, i915_gem_request_free
);
2296 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2298 struct drm_device
*dev
;
2303 dev
= req
->ring
->dev
;
2304 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2305 mutex_unlock(&dev
->struct_mutex
);
2308 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2309 struct drm_i915_gem_request
*src
)
2312 i915_gem_request_reference(src
);
2315 i915_gem_request_unreference(*pdst
);
2321 * XXX: i915_gem_request_completed should be here but currently needs the
2322 * definition of i915_seqno_passed() which is below. It will be moved in
2323 * a later patch when the call to i915_seqno_passed() is obsoleted...
2327 * A command that requires special handling by the command parser.
2329 struct drm_i915_cmd_descriptor
{
2331 * Flags describing how the command parser processes the command.
2333 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2334 * a length mask if not set
2335 * CMD_DESC_SKIP: The command is allowed but does not follow the
2336 * standard length encoding for the opcode range in
2338 * CMD_DESC_REJECT: The command is never allowed
2339 * CMD_DESC_REGISTER: The command should be checked against the
2340 * register whitelist for the appropriate ring
2341 * CMD_DESC_MASTER: The command is allowed if the submitting process
2345 #define CMD_DESC_FIXED (1<<0)
2346 #define CMD_DESC_SKIP (1<<1)
2347 #define CMD_DESC_REJECT (1<<2)
2348 #define CMD_DESC_REGISTER (1<<3)
2349 #define CMD_DESC_BITMASK (1<<4)
2350 #define CMD_DESC_MASTER (1<<5)
2353 * The command's unique identification bits and the bitmask to get them.
2354 * This isn't strictly the opcode field as defined in the spec and may
2355 * also include type, subtype, and/or subop fields.
2363 * The command's length. The command is either fixed length (i.e. does
2364 * not include a length field) or has a length field mask. The flag
2365 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2366 * a length mask. All command entries in a command table must include
2367 * length information.
2375 * Describes where to find a register address in the command to check
2376 * against the ring's register whitelist. Only valid if flags has the
2377 * CMD_DESC_REGISTER bit set.
2379 * A non-zero step value implies that the command may access multiple
2380 * registers in sequence (e.g. LRI), in that case step gives the
2381 * distance in dwords between individual offset fields.
2389 #define MAX_CMD_DESC_BITMASKS 3
2391 * Describes command checks where a particular dword is masked and
2392 * compared against an expected value. If the command does not match
2393 * the expected value, the parser rejects it. Only valid if flags has
2394 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2397 * If the check specifies a non-zero condition_mask then the parser
2398 * only performs the check when the bits specified by condition_mask
2405 u32 condition_offset
;
2407 } bits
[MAX_CMD_DESC_BITMASKS
];
2411 * A table of commands requiring special handling by the command parser.
2413 * Each ring has an array of tables. Each table consists of an array of command
2414 * descriptors, which must be sorted with command opcodes in ascending order.
2416 struct drm_i915_cmd_table
{
2417 const struct drm_i915_cmd_descriptor
*table
;
2421 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2422 #define __I915__(p) ({ \
2423 struct drm_i915_private *__p; \
2424 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2425 __p = (struct drm_i915_private *)p; \
2426 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2427 __p = to_i915((struct drm_device *)p); \
2432 #define INTEL_INFO(p) (&__I915__(p)->info)
2433 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2434 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2436 #define REVID_FOREVER 0xff
2438 * Return true if revision is in range [since,until] inclusive.
2440 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2442 #define IS_REVID(p, since, until) \
2443 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2445 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2446 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2447 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2448 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2449 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2450 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2451 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2452 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2453 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2454 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2455 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2456 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2457 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2458 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2459 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2460 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2461 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2462 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2463 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2464 INTEL_DEVID(dev) == 0x0152 || \
2465 INTEL_DEVID(dev) == 0x015a)
2466 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2467 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2468 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2469 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2470 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2471 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2472 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2473 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2474 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2475 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2476 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2477 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2478 (INTEL_DEVID(dev) & 0xf) == 0xe))
2479 /* ULX machines are also considered ULT. */
2480 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2481 (INTEL_DEVID(dev) & 0xf) == 0xe)
2482 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2483 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2484 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2485 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2486 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2487 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2488 /* ULX machines are also considered ULT. */
2489 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2490 INTEL_DEVID(dev) == 0x0A1E)
2491 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2492 INTEL_DEVID(dev) == 0x1913 || \
2493 INTEL_DEVID(dev) == 0x1916 || \
2494 INTEL_DEVID(dev) == 0x1921 || \
2495 INTEL_DEVID(dev) == 0x1926)
2496 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2497 INTEL_DEVID(dev) == 0x1915 || \
2498 INTEL_DEVID(dev) == 0x191E)
2499 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2500 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2501 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2502 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2504 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2506 #define SKL_REVID_A0 0x0
2507 #define SKL_REVID_B0 0x1
2508 #define SKL_REVID_C0 0x2
2509 #define SKL_REVID_D0 0x3
2510 #define SKL_REVID_E0 0x4
2511 #define SKL_REVID_F0 0x5
2513 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2515 #define BXT_REVID_A0 0x0
2516 #define BXT_REVID_A1 0x1
2517 #define BXT_REVID_B0 0x3
2518 #define BXT_REVID_C0 0x9
2520 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2523 * The genX designation typically refers to the render engine, so render
2524 * capability related checks should use IS_GEN, while display and other checks
2525 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2528 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2529 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2530 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2531 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2532 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2533 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2534 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2535 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2537 #define RENDER_RING (1<<RCS)
2538 #define BSD_RING (1<<VCS)
2539 #define BLT_RING (1<<BCS)
2540 #define VEBOX_RING (1<<VECS)
2541 #define BSD2_RING (1<<VCS2)
2542 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2543 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2544 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2545 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2546 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2547 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2548 __I915__(dev)->ellc_size)
2549 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2551 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2552 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2553 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2554 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2555 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2557 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2558 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2560 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2561 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2563 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2564 * even when in MSI mode. This results in spurious interrupt warnings if the
2565 * legacy irq no. is shared with another device. The kernel then disables that
2566 * interrupt source and so prevents the other device from working properly.
2568 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2569 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2571 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2572 * rows, which changed the alignment requirements and fence programming.
2574 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2576 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2577 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2579 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2580 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2581 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2583 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2585 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2586 INTEL_INFO(dev)->gen >= 9)
2588 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2589 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2590 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2591 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2593 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2594 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2596 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2597 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2599 #define HAS_CSR(dev) (IS_GEN9(dev))
2601 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2602 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2604 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2605 INTEL_INFO(dev)->gen >= 8)
2607 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2608 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2610 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2611 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2612 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2613 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2614 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2615 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2616 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2617 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2618 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2620 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2621 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2622 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2623 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2624 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2625 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2626 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2627 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2629 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2631 /* DPF == dynamic parity feature */
2632 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2633 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2635 #define GT_FREQUENCY_MULTIPLIER 50
2636 #define GEN9_FREQ_SCALER 3
2638 #include "i915_trace.h"
2640 extern const struct drm_ioctl_desc i915_ioctls
[];
2641 extern int i915_max_ioctl
;
2643 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2644 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2647 struct i915_params
{
2649 int panel_ignore_lid
;
2651 int lvds_channel_mode
;
2653 int vbt_sdvo_panel_type
;
2657 int enable_execlists
;
2659 unsigned int preliminary_hw_support
;
2660 int disable_power_well
;
2662 int invert_brightness
;
2663 int enable_cmd_parser
;
2664 /* leave bools at the end to not create holes */
2665 bool enable_hangcheck
;
2666 bool prefault_disable
;
2667 bool load_detect_test
;
2669 bool disable_display
;
2670 bool disable_vtd_wa
;
2671 bool enable_guc_submission
;
2675 bool verbose_state_checks
;
2676 bool nuclear_pageflip
;
2679 extern struct i915_params i915 __read_mostly
;
2682 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2683 extern int i915_driver_unload(struct drm_device
*);
2684 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2685 extern void i915_driver_lastclose(struct drm_device
* dev
);
2686 extern void i915_driver_preclose(struct drm_device
*dev
,
2687 struct drm_file
*file
);
2688 extern void i915_driver_postclose(struct drm_device
*dev
,
2689 struct drm_file
*file
);
2690 #ifdef CONFIG_COMPAT
2691 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2694 extern int intel_gpu_reset(struct drm_device
*dev
);
2695 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2696 extern int i915_reset(struct drm_device
*dev
);
2697 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2698 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2699 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2700 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2701 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2702 void i915_firmware_load_error_print(const char *fw_path
, int err
);
2704 /* intel_hotplug.c */
2705 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2706 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2707 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2708 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2709 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2712 void i915_queue_hangcheck(struct drm_device
*dev
);
2714 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2715 const char *fmt
, ...);
2717 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2718 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2719 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2721 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2722 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2723 bool restore_forcewake
);
2724 extern void intel_uncore_init(struct drm_device
*dev
);
2725 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2726 extern void intel_uncore_fini(struct drm_device
*dev
);
2727 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2728 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2729 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2730 enum forcewake_domains domains
);
2731 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2732 enum forcewake_domains domains
);
2733 /* Like above but the caller must manage the uncore.lock itself.
2734 * Must be used with I915_READ_FW and friends.
2736 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2737 enum forcewake_domains domains
);
2738 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2739 enum forcewake_domains domains
);
2740 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2741 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2743 return to_i915(dev
)->vgpu
.active
;
2747 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2751 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2754 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2755 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2756 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2760 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2762 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2763 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2764 uint32_t interrupt_mask
,
2765 uint32_t enabled_irq_mask
);
2766 #define ibx_enable_display_interrupt(dev_priv, bits) \
2767 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2768 #define ibx_disable_display_interrupt(dev_priv, bits) \
2769 ibx_display_interrupt_update((dev_priv), (bits), 0)
2772 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2773 struct drm_file
*file_priv
);
2774 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2775 struct drm_file
*file_priv
);
2776 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2777 struct drm_file
*file_priv
);
2778 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2779 struct drm_file
*file_priv
);
2780 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2781 struct drm_file
*file_priv
);
2782 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2783 struct drm_file
*file_priv
);
2784 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2785 struct drm_file
*file_priv
);
2786 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2787 struct drm_i915_gem_request
*req
);
2788 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2789 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2790 struct drm_i915_gem_execbuffer2
*args
,
2791 struct list_head
*vmas
);
2792 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2793 struct drm_file
*file_priv
);
2794 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2795 struct drm_file
*file_priv
);
2796 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2797 struct drm_file
*file_priv
);
2798 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2799 struct drm_file
*file
);
2800 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2801 struct drm_file
*file
);
2802 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2803 struct drm_file
*file_priv
);
2804 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2805 struct drm_file
*file_priv
);
2806 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2807 struct drm_file
*file_priv
);
2808 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2809 struct drm_file
*file_priv
);
2810 int i915_gem_init_userptr(struct drm_device
*dev
);
2811 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2812 struct drm_file
*file
);
2813 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2814 struct drm_file
*file_priv
);
2815 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2816 struct drm_file
*file_priv
);
2817 void i915_gem_load(struct drm_device
*dev
);
2818 void *i915_gem_object_alloc(struct drm_device
*dev
);
2819 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2820 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2821 const struct drm_i915_gem_object_ops
*ops
);
2822 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2824 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2825 struct drm_device
*dev
, const void *data
, size_t size
);
2826 void i915_gem_free_object(struct drm_gem_object
*obj
);
2827 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2829 /* Flags used by pin/bind&friends. */
2830 #define PIN_MAPPABLE (1<<0)
2831 #define PIN_NONBLOCK (1<<1)
2832 #define PIN_GLOBAL (1<<2)
2833 #define PIN_OFFSET_BIAS (1<<3)
2834 #define PIN_USER (1<<4)
2835 #define PIN_UPDATE (1<<5)
2836 #define PIN_ZONE_4G (1<<6)
2837 #define PIN_HIGH (1<<7)
2838 #define PIN_OFFSET_MASK (~4095)
2840 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2841 struct i915_address_space
*vm
,
2845 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2846 const struct i915_ggtt_view
*view
,
2850 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2852 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2854 * BEWARE: Do not use the function below unless you can _absolutely_
2855 * _guarantee_ VMA in question is _not in use_ anywhere.
2857 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
2858 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2859 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2860 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2862 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2863 int *needs_clflush
);
2865 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2867 static inline int __sg_page_count(struct scatterlist
*sg
)
2869 return sg
->length
>> PAGE_SHIFT
;
2872 static inline struct page
*
2873 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2875 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2878 if (n
< obj
->get_page
.last
) {
2879 obj
->get_page
.sg
= obj
->pages
->sgl
;
2880 obj
->get_page
.last
= 0;
2883 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2884 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2885 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2886 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2889 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2892 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2894 BUG_ON(obj
->pages
== NULL
);
2895 obj
->pages_pin_count
++;
2897 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2899 BUG_ON(obj
->pages_pin_count
== 0);
2900 obj
->pages_pin_count
--;
2903 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2904 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2905 struct intel_engine_cs
*to
,
2906 struct drm_i915_gem_request
**to_req
);
2907 void i915_vma_move_to_active(struct i915_vma
*vma
,
2908 struct drm_i915_gem_request
*req
);
2909 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2910 struct drm_device
*dev
,
2911 struct drm_mode_create_dumb
*args
);
2912 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2913 uint32_t handle
, uint64_t *offset
);
2915 * Returns true if seq1 is later than seq2.
2918 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2920 return (int32_t)(seq1
- seq2
) >= 0;
2923 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2924 bool lazy_coherency
)
2928 BUG_ON(req
== NULL
);
2930 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2932 return i915_seqno_passed(seqno
, req
->seqno
);
2935 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2936 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2938 struct drm_i915_gem_request
*
2939 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2941 bool i915_gem_retire_requests(struct drm_device
*dev
);
2942 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2943 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2944 bool interruptible
);
2946 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2948 return unlikely(atomic_read(&error
->reset_counter
)
2949 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2952 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2954 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2957 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2959 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2962 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2964 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2965 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2968 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2970 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2971 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2974 void i915_gem_reset(struct drm_device
*dev
);
2975 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2976 int __must_check
i915_gem_init(struct drm_device
*dev
);
2977 int i915_gem_init_rings(struct drm_device
*dev
);
2978 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2979 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
2980 void i915_gem_init_swizzling(struct drm_device
*dev
);
2981 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2982 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2983 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2984 void __i915_add_request(struct drm_i915_gem_request
*req
,
2985 struct drm_i915_gem_object
*batch_obj
,
2987 #define i915_add_request(req) \
2988 __i915_add_request(req, NULL, true)
2989 #define i915_add_request_no_flush(req) \
2990 __i915_add_request(req, NULL, false)
2991 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2992 unsigned reset_counter
,
2995 struct intel_rps_client
*rps
);
2996 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2997 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2999 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3002 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3005 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3007 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3009 struct intel_engine_cs
*pipelined
,
3010 struct drm_i915_gem_request
**pipelined_request
,
3011 const struct i915_ggtt_view
*view
);
3012 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3013 const struct i915_ggtt_view
*view
);
3014 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3016 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3017 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3020 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3022 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3023 int tiling_mode
, bool fenced
);
3025 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3026 enum i915_cache_level cache_level
);
3028 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3029 struct dma_buf
*dma_buf
);
3031 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3032 struct drm_gem_object
*gem_obj
, int flags
);
3034 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3035 const struct i915_ggtt_view
*view
);
3036 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3037 struct i915_address_space
*vm
);
3039 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3041 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3044 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3045 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3046 const struct i915_ggtt_view
*view
);
3047 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3048 struct i915_address_space
*vm
);
3050 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3051 struct i915_address_space
*vm
);
3053 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3054 struct i915_address_space
*vm
);
3056 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3057 const struct i915_ggtt_view
*view
);
3060 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3061 struct i915_address_space
*vm
);
3063 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3064 const struct i915_ggtt_view
*view
);
3066 static inline struct i915_vma
*
3067 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3069 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3071 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3073 /* Some GGTT VM helpers */
3074 #define i915_obj_to_ggtt(obj) \
3075 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3076 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
3078 struct i915_address_space
*ggtt
=
3079 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
3083 static inline struct i915_hw_ppgtt
*
3084 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3086 WARN_ON(i915_is_ggtt(vm
));
3088 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3092 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3094 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3097 static inline unsigned long
3098 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3100 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3103 static inline int __must_check
3104 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3108 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3109 alignment
, flags
| PIN_GLOBAL
);
3113 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3115 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3118 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3119 const struct i915_ggtt_view
*view
);
3121 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3123 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3126 /* i915_gem_fence.c */
3127 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3128 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3130 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3131 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3133 void i915_gem_restore_fences(struct drm_device
*dev
);
3135 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3136 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3137 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3139 /* i915_gem_context.c */
3140 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3141 void i915_gem_context_fini(struct drm_device
*dev
);
3142 void i915_gem_context_reset(struct drm_device
*dev
);
3143 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3144 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3145 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3146 int i915_switch_context(struct drm_i915_gem_request
*req
);
3147 struct intel_context
*
3148 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3149 void i915_gem_context_free(struct kref
*ctx_ref
);
3150 struct drm_i915_gem_object
*
3151 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3152 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3154 kref_get(&ctx
->ref
);
3157 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3159 kref_put(&ctx
->ref
, i915_gem_context_free
);
3162 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3164 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3167 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3168 struct drm_file
*file
);
3169 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3170 struct drm_file
*file
);
3171 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3172 struct drm_file
*file_priv
);
3173 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3174 struct drm_file
*file_priv
);
3176 /* i915_gem_evict.c */
3177 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3178 struct i915_address_space
*vm
,
3181 unsigned cache_level
,
3182 unsigned long start
,
3185 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3187 /* belongs in i915_gem_gtt.h */
3188 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3190 if (INTEL_INFO(dev
)->gen
< 6)
3191 intel_gtt_chipset_flush();
3194 /* i915_gem_stolen.c */
3195 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3196 struct drm_mm_node
*node
, u64 size
,
3197 unsigned alignment
);
3198 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3199 struct drm_mm_node
*node
, u64 size
,
3200 unsigned alignment
, u64 start
,
3202 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3203 struct drm_mm_node
*node
);
3204 int i915_gem_init_stolen(struct drm_device
*dev
);
3205 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3206 struct drm_i915_gem_object
*
3207 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3208 struct drm_i915_gem_object
*
3209 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3214 /* i915_gem_shrinker.c */
3215 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3216 unsigned long target
,
3218 #define I915_SHRINK_PURGEABLE 0x1
3219 #define I915_SHRINK_UNBOUND 0x2
3220 #define I915_SHRINK_BOUND 0x4
3221 #define I915_SHRINK_ACTIVE 0x8
3222 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3223 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3226 /* i915_gem_tiling.c */
3227 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3229 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3231 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3232 obj
->tiling_mode
!= I915_TILING_NONE
;
3235 /* i915_gem_debug.c */
3237 int i915_verify_lists(struct drm_device
*dev
);
3239 #define i915_verify_lists(dev) 0
3242 /* i915_debugfs.c */
3243 int i915_debugfs_init(struct drm_minor
*minor
);
3244 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3245 #ifdef CONFIG_DEBUG_FS
3246 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3247 void intel_display_crc_init(struct drm_device
*dev
);
3249 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3251 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3254 /* i915_gpu_error.c */
3256 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3257 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3258 const struct i915_error_state_file_priv
*error
);
3259 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3260 struct drm_i915_private
*i915
,
3261 size_t count
, loff_t pos
);
3262 static inline void i915_error_state_buf_release(
3263 struct drm_i915_error_state_buf
*eb
)
3267 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3268 const char *error_msg
);
3269 void i915_error_state_get(struct drm_device
*dev
,
3270 struct i915_error_state_file_priv
*error_priv
);
3271 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3272 void i915_destroy_error_state(struct drm_device
*dev
);
3274 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3275 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3277 /* i915_cmd_parser.c */
3278 int i915_cmd_parser_get_version(void);
3279 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3280 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3281 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3282 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3283 struct drm_i915_gem_object
*batch_obj
,
3284 struct drm_i915_gem_object
*shadow_batch_obj
,
3285 u32 batch_start_offset
,
3289 /* i915_suspend.c */
3290 extern int i915_save_state(struct drm_device
*dev
);
3291 extern int i915_restore_state(struct drm_device
*dev
);
3294 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3295 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3298 extern int intel_setup_gmbus(struct drm_device
*dev
);
3299 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3300 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3303 extern struct i2c_adapter
*
3304 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3305 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3306 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3307 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3309 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3311 extern void intel_i2c_reset(struct drm_device
*dev
);
3313 /* intel_opregion.c */
3315 extern int intel_opregion_setup(struct drm_device
*dev
);
3316 extern void intel_opregion_init(struct drm_device
*dev
);
3317 extern void intel_opregion_fini(struct drm_device
*dev
);
3318 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3319 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3321 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3324 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3325 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3326 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3327 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3329 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3334 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3342 extern void intel_register_dsm_handler(void);
3343 extern void intel_unregister_dsm_handler(void);
3345 static inline void intel_register_dsm_handler(void) { return; }
3346 static inline void intel_unregister_dsm_handler(void) { return; }
3347 #endif /* CONFIG_ACPI */
3350 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3351 extern void intel_modeset_init(struct drm_device
*dev
);
3352 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3353 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3354 extern void intel_connector_unregister(struct intel_connector
*);
3355 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3356 extern void intel_display_resume(struct drm_device
*dev
);
3357 extern void i915_redisable_vga(struct drm_device
*dev
);
3358 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3359 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3360 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3361 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3362 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3364 extern void intel_detect_pch(struct drm_device
*dev
);
3365 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3366 extern int intel_enable_rc6(const struct drm_device
*dev
);
3368 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3369 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3370 struct drm_file
*file
);
3371 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3372 struct drm_file
*file
);
3375 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3376 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3377 struct intel_overlay_error_state
*error
);
3379 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3380 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3381 struct drm_device
*dev
,
3382 struct intel_display_error_state
*error
);
3384 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3385 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3387 /* intel_sideband.c */
3388 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3389 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3390 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3391 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3392 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3393 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3394 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3395 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3396 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3397 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3398 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3399 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3400 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3401 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3402 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3403 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3404 enum intel_sbi_destination destination
);
3405 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3406 enum intel_sbi_destination destination
);
3407 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3408 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3410 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3411 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3413 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3414 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3416 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3417 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3418 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3419 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3421 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3422 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3423 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3424 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3426 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3427 * will be implemented using 2 32-bit writes in an arbitrary order with
3428 * an arbitrary delay between them. This can cause the hardware to
3429 * act upon the intermediate value, possibly leading to corruption and
3430 * machine death. You have been warned.
3432 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3433 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3435 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3436 u32 upper, lower, old_upper, loop = 0; \
3437 upper = I915_READ(upper_reg); \
3439 old_upper = upper; \
3440 lower = I915_READ(lower_reg); \
3441 upper = I915_READ(upper_reg); \
3442 } while (upper != old_upper && loop++ < 2); \
3443 (u64)upper << 32 | lower; })
3445 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3446 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3448 /* These are untraced mmio-accessors that are only valid to be used inside
3449 * criticial sections inside IRQ handlers where forcewake is explicitly
3451 * Think twice, and think again, before using these.
3452 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3453 * intel_uncore_forcewake_irqunlock().
3455 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3456 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3457 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3459 /* "Broadcast RGB" property */
3460 #define INTEL_BROADCAST_RGB_AUTO 0
3461 #define INTEL_BROADCAST_RGB_FULL 1
3462 #define INTEL_BROADCAST_RGB_LIMITED 2
3464 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3466 if (IS_VALLEYVIEW(dev
))
3467 return VLV_VGACNTRL
;
3468 else if (INTEL_INFO(dev
)->gen
>= 5)
3469 return CPU_VGACNTRL
;
3474 static inline void __user
*to_user_ptr(u64 address
)
3476 return (void __user
*)(uintptr_t)address
;
3479 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3481 unsigned long j
= msecs_to_jiffies(m
);
3483 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3486 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3488 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3491 static inline unsigned long
3492 timespec_to_jiffies_timeout(const struct timespec
*value
)
3494 unsigned long j
= timespec_to_jiffies(value
);
3496 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3500 * If you need to wait X milliseconds between events A and B, but event B
3501 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3502 * when event A happened, then just before event B you call this function and
3503 * pass the timestamp as the first argument, and X as the second argument.
3506 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3508 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3511 * Don't re-read the value of "jiffies" every time since it may change
3512 * behind our back and break the math.
3514 tmp_jiffies
= jiffies
;
3515 target_jiffies
= timestamp_jiffies
+
3516 msecs_to_jiffies_timeout(to_wait_ms
);
3518 if (time_after(target_jiffies
, tmp_jiffies
)) {
3519 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3520 while (remaining_jiffies
)
3522 schedule_timeout_uninterruptible(remaining_jiffies
);
3526 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3527 struct drm_i915_gem_request
*req
)
3529 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3530 i915_gem_request_assign(&ring
->trace_irq_req
, req
);