projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
drm/i915: Introduce mapping of user pages into video memory (userptr) ioctl
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "i915_gem_gtt.h"
39 #include <linux/io-mapping.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <drm/intel-gtt.h>
43 #include <linux/backlight.h>
44 #include <linux/hashtable.h>
45 #include <linux/intel-iommu.h>
46 #include <linux/kref.h>
47 #include <linux/pm_qos.h>
48
49 /* General customization:
50 */
51
52 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
53
54 #define DRIVER_NAME "i915"
55 #define DRIVER_DESC "Intel Graphics"
56 #define DRIVER_DATE "20080730"
57
58 enum pipe {
59 INVALID_PIPE = -1,
60 PIPE_A = 0,
61 PIPE_B,
62 PIPE_C,
63 _PIPE_EDP,
64 I915_MAX_PIPES = _PIPE_EDP
65 };
66 #define pipe_name(p) ((p) + 'A')
67
68 enum transcoder {
69 TRANSCODER_A = 0,
70 TRANSCODER_B,
71 TRANSCODER_C,
72 TRANSCODER_EDP,
73 I915_MAX_TRANSCODERS
74 };
75 #define transcoder_name(t) ((t) + 'A')
76
77 enum plane {
78 PLANE_A = 0,
79 PLANE_B,
80 PLANE_C,
81 };
82 #define plane_name(p) ((p) + 'A')
83
84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
85
86 enum port {
87 PORT_A = 0,
88 PORT_B,
89 PORT_C,
90 PORT_D,
91 PORT_E,
92 I915_MAX_PORTS
93 };
94 #define port_name(p) ((p) + 'A')
95
96 #define I915_NUM_PHYS_VLV 2
97
98 enum dpio_channel {
99 DPIO_CH0,
100 DPIO_CH1
101 };
102
103 enum dpio_phy {
104 DPIO_PHY0,
105 DPIO_PHY1
106 };
107
108 enum intel_display_power_domain {
109 POWER_DOMAIN_PIPE_A,
110 POWER_DOMAIN_PIPE_B,
111 POWER_DOMAIN_PIPE_C,
112 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
114 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
115 POWER_DOMAIN_TRANSCODER_A,
116 POWER_DOMAIN_TRANSCODER_B,
117 POWER_DOMAIN_TRANSCODER_C,
118 POWER_DOMAIN_TRANSCODER_EDP,
119 POWER_DOMAIN_PORT_DDI_A_2_LANES,
120 POWER_DOMAIN_PORT_DDI_A_4_LANES,
121 POWER_DOMAIN_PORT_DDI_B_2_LANES,
122 POWER_DOMAIN_PORT_DDI_B_4_LANES,
123 POWER_DOMAIN_PORT_DDI_C_2_LANES,
124 POWER_DOMAIN_PORT_DDI_C_4_LANES,
125 POWER_DOMAIN_PORT_DDI_D_2_LANES,
126 POWER_DOMAIN_PORT_DDI_D_4_LANES,
127 POWER_DOMAIN_PORT_DSI,
128 POWER_DOMAIN_PORT_CRT,
129 POWER_DOMAIN_PORT_OTHER,
130 POWER_DOMAIN_VGA,
131 POWER_DOMAIN_AUDIO,
132 POWER_DOMAIN_INIT,
133
134 POWER_DOMAIN_NUM,
135 };
136
137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
140 #define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
143
144 enum hpd_pin {
145 HPD_NONE = 0,
146 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
147 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
148 HPD_CRT,
149 HPD_SDVO_B,
150 HPD_SDVO_C,
151 HPD_PORT_B,
152 HPD_PORT_C,
153 HPD_PORT_D,
154 HPD_NUM_PINS
155 };
156
157 #define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
163
164 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
165 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
166
167 #define for_each_crtc(dev, crtc) \
168 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
169
170 #define for_each_intel_crtc(dev, intel_crtc) \
171 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
172
173 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
174 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
175 if ((intel_encoder)->base.crtc == (__crtc))
176
177 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
178 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
179 if ((intel_connector)->base.encoder == (__encoder))
180
181 struct drm_i915_private;
182 struct i915_mmu_object;
183
184 enum intel_dpll_id {
185 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
186 /* real shared dpll ids must be >= 0 */
187 DPLL_ID_PCH_PLL_A,
188 DPLL_ID_PCH_PLL_B,
189 };
190 #define I915_NUM_PLLS 2
191
192 struct intel_dpll_hw_state {
193 uint32_t dpll;
194 uint32_t dpll_md;
195 uint32_t fp0;
196 uint32_t fp1;
197 };
198
199 struct intel_shared_dpll {
200 int refcount; /* count of number of CRTCs sharing this PLL */
201 int active; /* count of number of active CRTCs (i.e. DPMS on) */
202 bool on; /* is the PLL actually active? Disabled during modeset */
203 const char *name;
204 /* should match the index in the dev_priv->shared_dplls array */
205 enum intel_dpll_id id;
206 struct intel_dpll_hw_state hw_state;
207 void (*mode_set)(struct drm_i915_private *dev_priv,
208 struct intel_shared_dpll *pll);
209 void (*enable)(struct drm_i915_private *dev_priv,
210 struct intel_shared_dpll *pll);
211 void (*disable)(struct drm_i915_private *dev_priv,
212 struct intel_shared_dpll *pll);
213 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
214 struct intel_shared_dpll *pll,
215 struct intel_dpll_hw_state *hw_state);
216 };
217
218 /* Used by dp and fdi links */
219 struct intel_link_m_n {
220 uint32_t tu;
221 uint32_t gmch_m;
222 uint32_t gmch_n;
223 uint32_t link_m;
224 uint32_t link_n;
225 };
226
227 void intel_link_compute_m_n(int bpp, int nlanes,
228 int pixel_clock, int link_clock,
229 struct intel_link_m_n *m_n);
230
231 struct intel_ddi_plls {
232 int spll_refcount;
233 int wrpll1_refcount;
234 int wrpll2_refcount;
235 };
236
237 /* Interface history:
238 *
239 * 1.1: Original.
240 * 1.2: Add Power Management
241 * 1.3: Add vblank support
242 * 1.4: Fix cmdbuffer path, add heap destroy
243 * 1.5: Add vblank pipe configuration
244 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
245 * - Support vertical blank on secondary display pipe
246 */
247 #define DRIVER_MAJOR 1
248 #define DRIVER_MINOR 6
249 #define DRIVER_PATCHLEVEL 0
250
251 #define WATCH_LISTS 0
252 #define WATCH_GTT 0
253
254 #define I915_GEM_PHYS_CURSOR_0 1
255 #define I915_GEM_PHYS_CURSOR_1 2
256 #define I915_GEM_PHYS_OVERLAY_REGS 3
257 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
258
259 struct drm_i915_gem_phys_object {
260 int id;
261 struct page **page_list;
262 drm_dma_handle_t *handle;
263 struct drm_i915_gem_object *cur_obj;
264 };
265
266 struct opregion_header;
267 struct opregion_acpi;
268 struct opregion_swsci;
269 struct opregion_asle;
270
271 struct intel_opregion {
272 struct opregion_header __iomem *header;
273 struct opregion_acpi __iomem *acpi;
274 struct opregion_swsci __iomem *swsci;
275 u32 swsci_gbda_sub_functions;
276 u32 swsci_sbcb_sub_functions;
277 struct opregion_asle __iomem *asle;
278 void __iomem *vbt;
279 u32 __iomem *lid_state;
280 struct work_struct asle_work;
281 };
282 #define OPREGION_SIZE (8*1024)
283
284 struct intel_overlay;
285 struct intel_overlay_error_state;
286
287 struct drm_i915_master_private {
288 drm_local_map_t *sarea;
289 struct _drm_i915_sarea *sarea_priv;
290 };
291 #define I915_FENCE_REG_NONE -1
292 #define I915_MAX_NUM_FENCES 32
293 /* 32 fences + sign bit for FENCE_REG_NONE */
294 #define I915_MAX_NUM_FENCE_BITS 6
295
296 struct drm_i915_fence_reg {
297 struct list_head lru_list;
298 struct drm_i915_gem_object *obj;
299 int pin_count;
300 };
301
302 struct sdvo_device_mapping {
303 u8 initialized;
304 u8 dvo_port;
305 u8 slave_addr;
306 u8 dvo_wiring;
307 u8 i2c_pin;
308 u8 ddc_pin;
309 };
310
311 struct intel_display_error_state;
312
313 struct drm_i915_error_state {
314 struct kref ref;
315 struct timeval time;
316
317 char error_msg[128];
318 u32 reset_count;
319 u32 suspend_count;
320
321 /* Generic register state */
322 u32 eir;
323 u32 pgtbl_er;
324 u32 ier;
325 u32 ccid;
326 u32 derrmr;
327 u32 forcewake;
328 u32 error; /* gen6+ */
329 u32 err_int; /* gen7 */
330 u32 done_reg;
331 u32 gac_eco;
332 u32 gam_ecochk;
333 u32 gab_ctl;
334 u32 gfx_mode;
335 u32 extra_instdone[I915_NUM_INSTDONE_REG];
336 u64 fence[I915_MAX_NUM_FENCES];
337 struct intel_overlay_error_state *overlay;
338 struct intel_display_error_state *display;
339
340 struct drm_i915_error_ring {
341 bool valid;
342 /* Software tracked state */
343 bool waiting;
344 int hangcheck_score;
345 enum intel_ring_hangcheck_action hangcheck_action;
346 int num_requests;
347
348 /* our own tracking of ring head and tail */
349 u32 cpu_ring_head;
350 u32 cpu_ring_tail;
351
352 u32 semaphore_seqno[I915_NUM_RINGS - 1];
353
354 /* Register state */
355 u32 tail;
356 u32 head;
357 u32 ctl;
358 u32 hws;
359 u32 ipeir;
360 u32 ipehr;
361 u32 instdone;
362 u32 bbstate;
363 u32 instpm;
364 u32 instps;
365 u32 seqno;
366 u64 bbaddr;
367 u64 acthd;
368 u32 fault_reg;
369 u64 faddr;
370 u32 rc_psmi; /* sleep state */
371 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
372
373 struct drm_i915_error_object {
374 int page_count;
375 u32 gtt_offset;
376 u32 *pages[0];
377 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
378
379 struct drm_i915_error_request {
380 long jiffies;
381 u32 seqno;
382 u32 tail;
383 } *requests;
384
385 struct {
386 u32 gfx_mode;
387 union {
388 u64 pdp[4];
389 u32 pp_dir_base;
390 };
391 } vm_info;
392
393 pid_t pid;
394 char comm[TASK_COMM_LEN];
395 } ring[I915_NUM_RINGS];
396 struct drm_i915_error_buffer {
397 u32 size;
398 u32 name;
399 u32 rseqno, wseqno;
400 u32 gtt_offset;
401 u32 read_domains;
402 u32 write_domain;
403 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
404 s32 pinned:2;
405 u32 tiling:2;
406 u32 dirty:1;
407 u32 purgeable:1;
408 u32 userptr:1;
409 s32 ring:4;
410 u32 cache_level:3;
411 } **active_bo, **pinned_bo;
412
413 u32 *active_bo_count, *pinned_bo_count;
414 };
415
416 struct intel_connector;
417 struct intel_crtc_config;
418 struct intel_plane_config;
419 struct intel_crtc;
420 struct intel_limit;
421 struct dpll;
422
423 struct drm_i915_display_funcs {
424 bool (*fbc_enabled)(struct drm_device *dev);
425 void (*enable_fbc)(struct drm_crtc *crtc);
426 void (*disable_fbc)(struct drm_device *dev);
427 int (*get_display_clock_speed)(struct drm_device *dev);
428 int (*get_fifo_size)(struct drm_device *dev, int plane);
429 /**
430 * find_dpll() - Find the best values for the PLL
431 * @limit: limits for the PLL
432 * @crtc: current CRTC
433 * @target: target frequency in kHz
434 * @refclk: reference clock frequency in kHz
435 * @match_clock: if provided, @best_clock P divider must
436 * match the P divider from @match_clock
437 * used for LVDS downclocking
438 * @best_clock: best PLL values found
439 *
440 * Returns true on success, false on failure.
441 */
442 bool (*find_dpll)(const struct intel_limit *limit,
443 struct drm_crtc *crtc,
444 int target, int refclk,
445 struct dpll *match_clock,
446 struct dpll *best_clock);
447 void (*update_wm)(struct drm_crtc *crtc);
448 void (*update_sprite_wm)(struct drm_plane *plane,
449 struct drm_crtc *crtc,
450 uint32_t sprite_width, int pixel_size,
451 bool enable, bool scaled);
452 void (*modeset_global_resources)(struct drm_device *dev);
453 /* Returns the active state of the crtc, and if the crtc is active,
454 * fills out the pipe-config with the hw state. */
455 bool (*get_pipe_config)(struct intel_crtc *,
456 struct intel_crtc_config *);
457 void (*get_plane_config)(struct intel_crtc *,
458 struct intel_plane_config *);
459 int (*crtc_mode_set)(struct drm_crtc *crtc,
460 int x, int y,
461 struct drm_framebuffer *old_fb);
462 void (*crtc_enable)(struct drm_crtc *crtc);
463 void (*crtc_disable)(struct drm_crtc *crtc);
464 void (*off)(struct drm_crtc *crtc);
465 void (*write_eld)(struct drm_connector *connector,
466 struct drm_crtc *crtc,
467 struct drm_display_mode *mode);
468 void (*fdi_link_train)(struct drm_crtc *crtc);
469 void (*init_clock_gating)(struct drm_device *dev);
470 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
471 struct drm_framebuffer *fb,
472 struct drm_i915_gem_object *obj,
473 uint32_t flags);
474 int (*update_primary_plane)(struct drm_crtc *crtc,
475 struct drm_framebuffer *fb,
476 int x, int y);
477 void (*hpd_irq_setup)(struct drm_device *dev);
478 /* clock updates for mode set */
479 /* cursor updates */
480 /* render clock increase/decrease */
481 /* display clock increase/decrease */
482 /* pll clock increase/decrease */
483
484 int (*setup_backlight)(struct intel_connector *connector);
485 uint32_t (*get_backlight)(struct intel_connector *connector);
486 void (*set_backlight)(struct intel_connector *connector,
487 uint32_t level);
488 void (*disable_backlight)(struct intel_connector *connector);
489 void (*enable_backlight)(struct intel_connector *connector);
490 };
491
492 struct intel_uncore_funcs {
493 void (*force_wake_get)(struct drm_i915_private *dev_priv,
494 int fw_engine);
495 void (*force_wake_put)(struct drm_i915_private *dev_priv,
496 int fw_engine);
497
498 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
499 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
500 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
501 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
502
503 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
504 uint8_t val, bool trace);
505 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
506 uint16_t val, bool trace);
507 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
508 uint32_t val, bool trace);
509 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
510 uint64_t val, bool trace);
511 };
512
513 struct intel_uncore {
514 spinlock_t lock; /** lock is also taken in irq contexts. */
515
516 struct intel_uncore_funcs funcs;
517
518 unsigned fifo_count;
519 unsigned forcewake_count;
520
521 unsigned fw_rendercount;
522 unsigned fw_mediacount;
523
524 struct timer_list force_wake_timer;
525 };
526
527 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
528 func(is_mobile) sep \
529 func(is_i85x) sep \
530 func(is_i915g) sep \
531 func(is_i945gm) sep \
532 func(is_g33) sep \
533 func(need_gfx_hws) sep \
534 func(is_g4x) sep \
535 func(is_pineview) sep \
536 func(is_broadwater) sep \
537 func(is_crestline) sep \
538 func(is_ivybridge) sep \
539 func(is_valleyview) sep \
540 func(is_haswell) sep \
541 func(is_preliminary) sep \
542 func(has_fbc) sep \
543 func(has_pipe_cxsr) sep \
544 func(has_hotplug) sep \
545 func(cursor_needs_physical) sep \
546 func(has_overlay) sep \
547 func(overlay_needs_physical) sep \
548 func(supports_tv) sep \
549 func(has_llc) sep \
550 func(has_ddi) sep \
551 func(has_fpga_dbg)
552
553 #define DEFINE_FLAG(name) u8 name:1
554 #define SEP_SEMICOLON ;
555
556 struct intel_device_info {
557 u32 display_mmio_offset;
558 u8 num_pipes:3;
559 u8 num_sprites[I915_MAX_PIPES];
560 u8 gen;
561 u8 ring_mask; /* Rings supported by the HW */
562 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
563 /* Register offsets for the various display pipes and transcoders */
564 int pipe_offsets[I915_MAX_TRANSCODERS];
565 int trans_offsets[I915_MAX_TRANSCODERS];
566 int dpll_offsets[I915_MAX_PIPES];
567 int dpll_md_offsets[I915_MAX_PIPES];
568 int palette_offsets[I915_MAX_PIPES];
569 };
570
571 #undef DEFINE_FLAG
572 #undef SEP_SEMICOLON
573
574 enum i915_cache_level {
575 I915_CACHE_NONE = 0,
576 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
577 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
578 caches, eg sampler/render caches, and the
579 large Last-Level-Cache. LLC is coherent with
580 the CPU, but L3 is only visible to the GPU. */
581 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
582 };
583
584 struct i915_ctx_hang_stats {
585 /* This context had batch pending when hang was declared */
586 unsigned batch_pending;
587
588 /* This context had batch active when hang was declared */
589 unsigned batch_active;
590
591 /* Time when this context was last blamed for a GPU reset */
592 unsigned long guilty_ts;
593
594 /* This context is banned to submit more work */
595 bool banned;
596 };
597
598 /* This must match up with the value previously used for execbuf2.rsvd1. */
599 #define DEFAULT_CONTEXT_ID 0
600 struct i915_hw_context {
601 struct kref ref;
602 int id;
603 bool is_initialized;
604 uint8_t remap_slice;
605 struct drm_i915_file_private *file_priv;
606 struct intel_ring_buffer *last_ring;
607 struct drm_i915_gem_object *obj;
608 struct i915_ctx_hang_stats hang_stats;
609 struct i915_address_space *vm;
610
611 struct list_head link;
612 };
613
614 struct i915_fbc {
615 unsigned long size;
616 unsigned int fb_id;
617 enum plane plane;
618 int y;
619
620 struct drm_mm_node *compressed_fb;
621 struct drm_mm_node *compressed_llb;
622
623 struct intel_fbc_work {
624 struct delayed_work work;
625 struct drm_crtc *crtc;
626 struct drm_framebuffer *fb;
627 } *fbc_work;
628
629 enum no_fbc_reason {
630 FBC_OK, /* FBC is enabled */
631 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
632 FBC_NO_OUTPUT, /* no outputs enabled to compress */
633 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
634 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
635 FBC_MODE_TOO_LARGE, /* mode too large for compression */
636 FBC_BAD_PLANE, /* fbc not supported on plane */
637 FBC_NOT_TILED, /* buffer not tiled */
638 FBC_MULTIPLE_PIPES, /* more than one pipe active */
639 FBC_MODULE_PARAM,
640 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
641 } no_fbc_reason;
642 };
643
644 struct i915_drrs {
645 struct intel_connector *connector;
646 };
647
648 struct i915_psr {
649 bool sink_support;
650 bool source_ok;
651 };
652
653 enum intel_pch {
654 PCH_NONE = 0, /* No PCH present */
655 PCH_IBX, /* Ibexpeak PCH */
656 PCH_CPT, /* Cougarpoint PCH */
657 PCH_LPT, /* Lynxpoint PCH */
658 PCH_NOP,
659 };
660
661 enum intel_sbi_destination {
662 SBI_ICLK,
663 SBI_MPHY,
664 };
665
666 #define QUIRK_PIPEA_FORCE (1<<0)
667 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
668 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
669
670 struct intel_fbdev;
671 struct intel_fbc_work;
672
673 struct intel_gmbus {
674 struct i2c_adapter adapter;
675 u32 force_bit;
676 u32 reg0;
677 u32 gpio_reg;
678 struct i2c_algo_bit_data bit_algo;
679 struct drm_i915_private *dev_priv;
680 };
681
682 struct i915_suspend_saved_registers {
683 u8 saveLBB;
684 u32 saveDSPACNTR;
685 u32 saveDSPBCNTR;
686 u32 saveDSPARB;
687 u32 savePIPEACONF;
688 u32 savePIPEBCONF;
689 u32 savePIPEASRC;
690 u32 savePIPEBSRC;
691 u32 saveFPA0;
692 u32 saveFPA1;
693 u32 saveDPLL_A;
694 u32 saveDPLL_A_MD;
695 u32 saveHTOTAL_A;
696 u32 saveHBLANK_A;
697 u32 saveHSYNC_A;
698 u32 saveVTOTAL_A;
699 u32 saveVBLANK_A;
700 u32 saveVSYNC_A;
701 u32 saveBCLRPAT_A;
702 u32 saveTRANSACONF;
703 u32 saveTRANS_HTOTAL_A;
704 u32 saveTRANS_HBLANK_A;
705 u32 saveTRANS_HSYNC_A;
706 u32 saveTRANS_VTOTAL_A;
707 u32 saveTRANS_VBLANK_A;
708 u32 saveTRANS_VSYNC_A;
709 u32 savePIPEASTAT;
710 u32 saveDSPASTRIDE;
711 u32 saveDSPASIZE;
712 u32 saveDSPAPOS;
713 u32 saveDSPAADDR;
714 u32 saveDSPASURF;
715 u32 saveDSPATILEOFF;
716 u32 savePFIT_PGM_RATIOS;
717 u32 saveBLC_HIST_CTL;
718 u32 saveBLC_PWM_CTL;
719 u32 saveBLC_PWM_CTL2;
720 u32 saveBLC_HIST_CTL_B;
721 u32 saveBLC_CPU_PWM_CTL;
722 u32 saveBLC_CPU_PWM_CTL2;
723 u32 saveFPB0;
724 u32 saveFPB1;
725 u32 saveDPLL_B;
726 u32 saveDPLL_B_MD;
727 u32 saveHTOTAL_B;
728 u32 saveHBLANK_B;
729 u32 saveHSYNC_B;
730 u32 saveVTOTAL_B;
731 u32 saveVBLANK_B;
732 u32 saveVSYNC_B;
733 u32 saveBCLRPAT_B;
734 u32 saveTRANSBCONF;
735 u32 saveTRANS_HTOTAL_B;
736 u32 saveTRANS_HBLANK_B;
737 u32 saveTRANS_HSYNC_B;
738 u32 saveTRANS_VTOTAL_B;
739 u32 saveTRANS_VBLANK_B;
740 u32 saveTRANS_VSYNC_B;
741 u32 savePIPEBSTAT;
742 u32 saveDSPBSTRIDE;
743 u32 saveDSPBSIZE;
744 u32 saveDSPBPOS;
745 u32 saveDSPBADDR;
746 u32 saveDSPBSURF;
747 u32 saveDSPBTILEOFF;
748 u32 saveVGA0;
749 u32 saveVGA1;
750 u32 saveVGA_PD;
751 u32 saveVGACNTRL;
752 u32 saveADPA;
753 u32 saveLVDS;
754 u32 savePP_ON_DELAYS;
755 u32 savePP_OFF_DELAYS;
756 u32 saveDVOA;
757 u32 saveDVOB;
758 u32 saveDVOC;
759 u32 savePP_ON;
760 u32 savePP_OFF;
761 u32 savePP_CONTROL;
762 u32 savePP_DIVISOR;
763 u32 savePFIT_CONTROL;
764 u32 save_palette_a[256];
765 u32 save_palette_b[256];
766 u32 saveFBC_CONTROL;
767 u32 saveIER;
768 u32 saveIIR;
769 u32 saveIMR;
770 u32 saveDEIER;
771 u32 saveDEIMR;
772 u32 saveGTIER;
773 u32 saveGTIMR;
774 u32 saveFDI_RXA_IMR;
775 u32 saveFDI_RXB_IMR;
776 u32 saveCACHE_MODE_0;
777 u32 saveMI_ARB_STATE;
778 u32 saveSWF0[16];
779 u32 saveSWF1[16];
780 u32 saveSWF2[3];
781 u8 saveMSR;
782 u8 saveSR[8];
783 u8 saveGR[25];
784 u8 saveAR_INDEX;
785 u8 saveAR[21];
786 u8 saveDACMASK;
787 u8 saveCR[37];
788 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
789 u32 saveCURACNTR;
790 u32 saveCURAPOS;
791 u32 saveCURABASE;
792 u32 saveCURBCNTR;
793 u32 saveCURBPOS;
794 u32 saveCURBBASE;
795 u32 saveCURSIZE;
796 u32 saveDP_B;
797 u32 saveDP_C;
798 u32 saveDP_D;
799 u32 savePIPEA_GMCH_DATA_M;
800 u32 savePIPEB_GMCH_DATA_M;
801 u32 savePIPEA_GMCH_DATA_N;
802 u32 savePIPEB_GMCH_DATA_N;
803 u32 savePIPEA_DP_LINK_M;
804 u32 savePIPEB_DP_LINK_M;
805 u32 savePIPEA_DP_LINK_N;
806 u32 savePIPEB_DP_LINK_N;
807 u32 saveFDI_RXA_CTL;
808 u32 saveFDI_TXA_CTL;
809 u32 saveFDI_RXB_CTL;
810 u32 saveFDI_TXB_CTL;
811 u32 savePFA_CTL_1;
812 u32 savePFB_CTL_1;
813 u32 savePFA_WIN_SZ;
814 u32 savePFB_WIN_SZ;
815 u32 savePFA_WIN_POS;
816 u32 savePFB_WIN_POS;
817 u32 savePCH_DREF_CONTROL;
818 u32 saveDISP_ARB_CTL;
819 u32 savePIPEA_DATA_M1;
820 u32 savePIPEA_DATA_N1;
821 u32 savePIPEA_LINK_M1;
822 u32 savePIPEA_LINK_N1;
823 u32 savePIPEB_DATA_M1;
824 u32 savePIPEB_DATA_N1;
825 u32 savePIPEB_LINK_M1;
826 u32 savePIPEB_LINK_N1;
827 u32 saveMCHBAR_RENDER_STANDBY;
828 u32 savePCH_PORT_HOTPLUG;
829 };
830
831 struct vlv_s0ix_state {
832 /* GAM */
833 u32 wr_watermark;
834 u32 gfx_prio_ctrl;
835 u32 arb_mode;
836 u32 gfx_pend_tlb0;
837 u32 gfx_pend_tlb1;
838 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
839 u32 media_max_req_count;
840 u32 gfx_max_req_count;
841 u32 render_hwsp;
842 u32 ecochk;
843 u32 bsd_hwsp;
844 u32 blt_hwsp;
845 u32 tlb_rd_addr;
846
847 /* MBC */
848 u32 g3dctl;
849 u32 gsckgctl;
850 u32 mbctl;
851
852 /* GCP */
853 u32 ucgctl1;
854 u32 ucgctl3;
855 u32 rcgctl1;
856 u32 rcgctl2;
857 u32 rstctl;
858 u32 misccpctl;
859
860 /* GPM */
861 u32 gfxpause;
862 u32 rpdeuhwtc;
863 u32 rpdeuc;
864 u32 ecobus;
865 u32 pwrdwnupctl;
866 u32 rp_down_timeout;
867 u32 rp_deucsw;
868 u32 rcubmabdtmr;
869 u32 rcedata;
870 u32 spare2gh;
871
872 /* Display 1 CZ domain */
873 u32 gt_imr;
874 u32 gt_ier;
875 u32 pm_imr;
876 u32 pm_ier;
877 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
878
879 /* GT SA CZ domain */
880 u32 tilectl;
881 u32 gt_fifoctl;
882 u32 gtlc_wake_ctrl;
883 u32 gtlc_survive;
884 u32 pmwgicz;
885
886 /* Display 2 CZ domain */
887 u32 gu_ctl0;
888 u32 gu_ctl1;
889 u32 clock_gate_dis2;
890 };
891
892 struct intel_gen6_power_mgmt {
893 /* work and pm_iir are protected by dev_priv->irq_lock */
894 struct work_struct work;
895 u32 pm_iir;
896
897 /* Frequencies are stored in potentially platform dependent multiples.
898 * In other words, *_freq needs to be multiplied by X to be interesting.
899 * Soft limits are those which are used for the dynamic reclocking done
900 * by the driver (raise frequencies under heavy loads, and lower for
901 * lighter loads). Hard limits are those imposed by the hardware.
902 *
903 * A distinction is made for overclocking, which is never enabled by
904 * default, and is considered to be above the hard limit if it's
905 * possible at all.
906 */
907 u8 cur_freq; /* Current frequency (cached, may not == HW) */
908 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
909 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
910 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
911 u8 min_freq; /* AKA RPn. Minimum frequency */
912 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
913 u8 rp1_freq; /* "less than" RP0 power/freqency */
914 u8 rp0_freq; /* Non-overclocked max frequency. */
915
916 int last_adj;
917 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
918
919 bool enabled;
920 struct delayed_work delayed_resume_work;
921
922 /*
923 * Protects RPS/RC6 register access and PCU communication.
924 * Must be taken after struct_mutex if nested.
925 */
926 struct mutex hw_lock;
927 };
928
929 /* defined intel_pm.c */
930 extern spinlock_t mchdev_lock;
931
932 struct intel_ilk_power_mgmt {
933 u8 cur_delay;
934 u8 min_delay;
935 u8 max_delay;
936 u8 fmax;
937 u8 fstart;
938
939 u64 last_count1;
940 unsigned long last_time1;
941 unsigned long chipset_power;
942 u64 last_count2;
943 struct timespec last_time2;
944 unsigned long gfx_power;
945 u8 corr;
946
947 int c_m;
948 int r_t;
949
950 struct drm_i915_gem_object *pwrctx;
951 struct drm_i915_gem_object *renderctx;
952 };
953
954 struct drm_i915_private;
955 struct i915_power_well;
956
957 struct i915_power_well_ops {
958 /*
959 * Synchronize the well's hw state to match the current sw state, for
960 * example enable/disable it based on the current refcount. Called
961 * during driver init and resume time, possibly after first calling
962 * the enable/disable handlers.
963 */
964 void (*sync_hw)(struct drm_i915_private *dev_priv,
965 struct i915_power_well *power_well);
966 /*
967 * Enable the well and resources that depend on it (for example
968 * interrupts located on the well). Called after the 0->1 refcount
969 * transition.
970 */
971 void (*enable)(struct drm_i915_private *dev_priv,
972 struct i915_power_well *power_well);
973 /*
974 * Disable the well and resources that depend on it. Called after
975 * the 1->0 refcount transition.
976 */
977 void (*disable)(struct drm_i915_private *dev_priv,
978 struct i915_power_well *power_well);
979 /* Returns the hw enabled state. */
980 bool (*is_enabled)(struct drm_i915_private *dev_priv,
981 struct i915_power_well *power_well);
982 };
983
984 /* Power well structure for haswell */
985 struct i915_power_well {
986 const char *name;
987 bool always_on;
988 /* power well enable/disable usage count */
989 int count;
990 unsigned long domains;
991 unsigned long data;
992 const struct i915_power_well_ops *ops;
993 };
994
995 struct i915_power_domains {
996 /*
997 * Power wells needed for initialization at driver init and suspend
998 * time are on. They are kept on until after the first modeset.
999 */
1000 bool init_power_on;
1001 bool initializing;
1002 int power_well_count;
1003
1004 struct mutex lock;
1005 int domain_use_count[POWER_DOMAIN_NUM];
1006 struct i915_power_well *power_wells;
1007 };
1008
1009 struct i915_dri1_state {
1010 unsigned allow_batchbuffer : 1;
1011 u32 __iomem *gfx_hws_cpu_addr;
1012
1013 unsigned int cpp;
1014 int back_offset;
1015 int front_offset;
1016 int current_page;
1017 int page_flipping;
1018
1019 uint32_t counter;
1020 };
1021
1022 struct i915_ums_state {
1023 /**
1024 * Flag if the X Server, and thus DRM, is not currently in
1025 * control of the device.
1026 *
1027 * This is set between LeaveVT and EnterVT. It needs to be
1028 * replaced with a semaphore. It also needs to be
1029 * transitioned away from for kernel modesetting.
1030 */
1031 int mm_suspended;
1032 };
1033
1034 #define MAX_L3_SLICES 2
1035 struct intel_l3_parity {
1036 u32 *remap_info[MAX_L3_SLICES];
1037 struct work_struct error_work;
1038 int which_slice;
1039 };
1040
1041 struct i915_gem_mm {
1042 /** Memory allocator for GTT stolen memory */
1043 struct drm_mm stolen;
1044 /** List of all objects in gtt_space. Used to restore gtt
1045 * mappings on resume */
1046 struct list_head bound_list;
1047 /**
1048 * List of objects which are not bound to the GTT (thus
1049 * are idle and not used by the GPU) but still have
1050 * (presumably uncached) pages still attached.
1051 */
1052 struct list_head unbound_list;
1053
1054 /** Usable portion of the GTT for GEM */
1055 unsigned long stolen_base; /* limited to low memory (32-bit) */
1056
1057 /** PPGTT used for aliasing the PPGTT with the GTT */
1058 struct i915_hw_ppgtt *aliasing_ppgtt;
1059
1060 struct shrinker inactive_shrinker;
1061 bool shrinker_no_lock_stealing;
1062
1063 /** LRU list of objects with fence regs on them. */
1064 struct list_head fence_list;
1065
1066 /**
1067 * We leave the user IRQ off as much as possible,
1068 * but this means that requests will finish and never
1069 * be retired once the system goes idle. Set a timer to
1070 * fire periodically while the ring is running. When it
1071 * fires, go retire requests.
1072 */
1073 struct delayed_work retire_work;
1074
1075 /**
1076 * When we detect an idle GPU, we want to turn on
1077 * powersaving features. So once we see that there
1078 * are no more requests outstanding and no more
1079 * arrive within a small period of time, we fire
1080 * off the idle_work.
1081 */
1082 struct delayed_work idle_work;
1083
1084 /**
1085 * Are we in a non-interruptible section of code like
1086 * modesetting?
1087 */
1088 bool interruptible;
1089
1090 /**
1091 * Is the GPU currently considered idle, or busy executing userspace
1092 * requests? Whilst idle, we attempt to power down the hardware and
1093 * display clocks. In order to reduce the effect on performance, there
1094 * is a slight delay before we do so.
1095 */
1096 bool busy;
1097
1098 /** Bit 6 swizzling required for X tiling */
1099 uint32_t bit_6_swizzle_x;
1100 /** Bit 6 swizzling required for Y tiling */
1101 uint32_t bit_6_swizzle_y;
1102
1103 /* storage for physical objects */
1104 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1105
1106 /* accounting, useful for userland debugging */
1107 spinlock_t object_stat_lock;
1108 size_t object_memory;
1109 u32 object_count;
1110 };
1111
1112 struct drm_i915_error_state_buf {
1113 unsigned bytes;
1114 unsigned size;
1115 int err;
1116 u8 *buf;
1117 loff_t start;
1118 loff_t pos;
1119 };
1120
1121 struct i915_error_state_file_priv {
1122 struct drm_device *dev;
1123 struct drm_i915_error_state *error;
1124 };
1125
1126 struct i915_gpu_error {
1127 /* For hangcheck timer */
1128 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1129 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1130 /* Hang gpu twice in this window and your context gets banned */
1131 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1132
1133 struct timer_list hangcheck_timer;
1134
1135 /* For reset and error_state handling. */
1136 spinlock_t lock;
1137 /* Protected by the above dev->gpu_error.lock. */
1138 struct drm_i915_error_state *first_error;
1139 struct work_struct work;
1140
1141
1142 unsigned long missed_irq_rings;
1143
1144 /**
1145 * State variable controlling the reset flow and count
1146 *
1147 * This is a counter which gets incremented when reset is triggered,
1148 * and again when reset has been handled. So odd values (lowest bit set)
1149 * means that reset is in progress and even values that
1150 * (reset_counter >> 1):th reset was successfully completed.
1151 *
1152 * If reset is not completed succesfully, the I915_WEDGE bit is
1153 * set meaning that hardware is terminally sour and there is no
1154 * recovery. All waiters on the reset_queue will be woken when
1155 * that happens.
1156 *
1157 * This counter is used by the wait_seqno code to notice that reset
1158 * event happened and it needs to restart the entire ioctl (since most
1159 * likely the seqno it waited for won't ever signal anytime soon).
1160 *
1161 * This is important for lock-free wait paths, where no contended lock
1162 * naturally enforces the correct ordering between the bail-out of the
1163 * waiter and the gpu reset work code.
1164 */
1165 atomic_t reset_counter;
1166
1167 #define I915_RESET_IN_PROGRESS_FLAG 1
1168 #define I915_WEDGED (1 << 31)
1169
1170 /**
1171 * Waitqueue to signal when the reset has completed. Used by clients
1172 * that wait for dev_priv->mm.wedged to settle.
1173 */
1174 wait_queue_head_t reset_queue;
1175
1176 /* Userspace knobs for gpu hang simulation;
1177 * combines both a ring mask, and extra flags
1178 */
1179 u32 stop_rings;
1180 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1181 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1182
1183 /* For missed irq/seqno simulation. */
1184 unsigned int test_irq_rings;
1185 };
1186
1187 enum modeset_restore {
1188 MODESET_ON_LID_OPEN,
1189 MODESET_DONE,
1190 MODESET_SUSPENDED,
1191 };
1192
1193 struct ddi_vbt_port_info {
1194 uint8_t hdmi_level_shift;
1195
1196 uint8_t supports_dvi:1;
1197 uint8_t supports_hdmi:1;
1198 uint8_t supports_dp:1;
1199 };
1200
1201 enum drrs_support_type {
1202 DRRS_NOT_SUPPORTED = 0,
1203 STATIC_DRRS_SUPPORT = 1,
1204 SEAMLESS_DRRS_SUPPORT = 2
1205 };
1206
1207 struct intel_vbt_data {
1208 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1209 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1210
1211 /* Feature bits */
1212 unsigned int int_tv_support:1;
1213 unsigned int lvds_dither:1;
1214 unsigned int lvds_vbt:1;
1215 unsigned int int_crt_support:1;
1216 unsigned int lvds_use_ssc:1;
1217 unsigned int display_clock_mode:1;
1218 unsigned int fdi_rx_polarity_inverted:1;
1219 int lvds_ssc_freq;
1220 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1221
1222 enum drrs_support_type drrs_type;
1223
1224 /* eDP */
1225 int edp_rate;
1226 int edp_lanes;
1227 int edp_preemphasis;
1228 int edp_vswing;
1229 bool edp_initialized;
1230 bool edp_support;
1231 int edp_bpp;
1232 struct edp_power_seq edp_pps;
1233
1234 struct {
1235 u16 pwm_freq_hz;
1236 bool present;
1237 bool active_low_pwm;
1238 } backlight;
1239
1240 /* MIPI DSI */
1241 struct {
1242 u16 panel_id;
1243 struct mipi_config *config;
1244 struct mipi_pps_data *pps;
1245 u8 seq_version;
1246 u32 size;
1247 u8 *data;
1248 u8 *sequence[MIPI_SEQ_MAX];
1249 } dsi;
1250
1251 int crt_ddc_pin;
1252
1253 int child_dev_num;
1254 union child_device_config *child_dev;
1255
1256 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1257 };
1258
1259 enum intel_ddb_partitioning {
1260 INTEL_DDB_PART_1_2,
1261 INTEL_DDB_PART_5_6, /* IVB+ */
1262 };
1263
1264 struct intel_wm_level {
1265 bool enable;
1266 uint32_t pri_val;
1267 uint32_t spr_val;
1268 uint32_t cur_val;
1269 uint32_t fbc_val;
1270 };
1271
1272 struct ilk_wm_values {
1273 uint32_t wm_pipe[3];
1274 uint32_t wm_lp[3];
1275 uint32_t wm_lp_spr[3];
1276 uint32_t wm_linetime[3];
1277 bool enable_fbc_wm;
1278 enum intel_ddb_partitioning partitioning;
1279 };
1280
1281 /*
1282 * This struct helps tracking the state needed for runtime PM, which puts the
1283 * device in PCI D3 state. Notice that when this happens, nothing on the
1284 * graphics device works, even register access, so we don't get interrupts nor
1285 * anything else.
1286 *
1287 * Every piece of our code that needs to actually touch the hardware needs to
1288 * either call intel_runtime_pm_get or call intel_display_power_get with the
1289 * appropriate power domain.
1290 *
1291 * Our driver uses the autosuspend delay feature, which means we'll only really
1292 * suspend if we stay with zero refcount for a certain amount of time. The
1293 * default value is currently very conservative (see intel_init_runtime_pm), but
1294 * it can be changed with the standard runtime PM files from sysfs.
1295 *
1296 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1297 * goes back to false exactly before we reenable the IRQs. We use this variable
1298 * to check if someone is trying to enable/disable IRQs while they're supposed
1299 * to be disabled. This shouldn't happen and we'll print some error messages in
1300 * case it happens.
1301 *
1302 * For more, read the Documentation/power/runtime_pm.txt.
1303 */
1304 struct i915_runtime_pm {
1305 bool suspended;
1306 bool irqs_disabled;
1307 };
1308
1309 enum intel_pipe_crc_source {
1310 INTEL_PIPE_CRC_SOURCE_NONE,
1311 INTEL_PIPE_CRC_SOURCE_PLANE1,
1312 INTEL_PIPE_CRC_SOURCE_PLANE2,
1313 INTEL_PIPE_CRC_SOURCE_PF,
1314 INTEL_PIPE_CRC_SOURCE_PIPE,
1315 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1316 INTEL_PIPE_CRC_SOURCE_TV,
1317 INTEL_PIPE_CRC_SOURCE_DP_B,
1318 INTEL_PIPE_CRC_SOURCE_DP_C,
1319 INTEL_PIPE_CRC_SOURCE_DP_D,
1320 INTEL_PIPE_CRC_SOURCE_AUTO,
1321 INTEL_PIPE_CRC_SOURCE_MAX,
1322 };
1323
1324 struct intel_pipe_crc_entry {
1325 uint32_t frame;
1326 uint32_t crc[5];
1327 };
1328
1329 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1330 struct intel_pipe_crc {
1331 spinlock_t lock;
1332 bool opened; /* exclusive access to the result file */
1333 struct intel_pipe_crc_entry *entries;
1334 enum intel_pipe_crc_source source;
1335 int head, tail;
1336 wait_queue_head_t wq;
1337 };
1338
1339 struct drm_i915_private {
1340 struct drm_device *dev;
1341 struct kmem_cache *slab;
1342
1343 const struct intel_device_info info;
1344
1345 int relative_constants_mode;
1346
1347 void __iomem *regs;
1348
1349 struct intel_uncore uncore;
1350
1351 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1352
1353
1354 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1355 * controller on different i2c buses. */
1356 struct mutex gmbus_mutex;
1357
1358 /**
1359 * Base address of the gmbus and gpio block.
1360 */
1361 uint32_t gpio_mmio_base;
1362
1363 wait_queue_head_t gmbus_wait_queue;
1364
1365 struct pci_dev *bridge_dev;
1366 struct intel_ring_buffer ring[I915_NUM_RINGS];
1367 uint32_t last_seqno, next_seqno;
1368
1369 drm_dma_handle_t *status_page_dmah;
1370 struct resource mch_res;
1371
1372 /* protects the irq masks */
1373 spinlock_t irq_lock;
1374
1375 bool display_irqs_enabled;
1376
1377 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1378 struct pm_qos_request pm_qos;
1379
1380 /* DPIO indirect register protection */
1381 struct mutex dpio_lock;
1382
1383 /** Cached value of IMR to avoid reads in updating the bitfield */
1384 union {
1385 u32 irq_mask;
1386 u32 de_irq_mask[I915_MAX_PIPES];
1387 };
1388 u32 gt_irq_mask;
1389 u32 pm_irq_mask;
1390 u32 pm_rps_events;
1391 u32 pipestat_irq_mask[I915_MAX_PIPES];
1392
1393 struct work_struct hotplug_work;
1394 bool enable_hotplug_processing;
1395 struct {
1396 unsigned long hpd_last_jiffies;
1397 int hpd_cnt;
1398 enum {
1399 HPD_ENABLED = 0,
1400 HPD_DISABLED = 1,
1401 HPD_MARK_DISABLED = 2
1402 } hpd_mark;
1403 } hpd_stats[HPD_NUM_PINS];
1404 u32 hpd_event_bits;
1405 struct timer_list hotplug_reenable_timer;
1406
1407 struct i915_fbc fbc;
1408 struct i915_drrs drrs;
1409 struct intel_opregion opregion;
1410 struct intel_vbt_data vbt;
1411
1412 /* overlay */
1413 struct intel_overlay *overlay;
1414
1415 /* backlight registers and fields in struct intel_panel */
1416 spinlock_t backlight_lock;
1417
1418 /* LVDS info */
1419 bool no_aux_handshake;
1420
1421 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1422 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1423 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1424
1425 unsigned int fsb_freq, mem_freq, is_ddr3;
1426 unsigned int vlv_cdclk_freq;
1427
1428 /**
1429 * wq - Driver workqueue for GEM.
1430 *
1431 * NOTE: Work items scheduled here are not allowed to grab any modeset
1432 * locks, for otherwise the flushing done in the pageflip code will
1433 * result in deadlocks.
1434 */
1435 struct workqueue_struct *wq;
1436
1437 /* Display functions */
1438 struct drm_i915_display_funcs display;
1439
1440 /* PCH chipset type */
1441 enum intel_pch pch_type;
1442 unsigned short pch_id;
1443
1444 unsigned long quirks;
1445
1446 enum modeset_restore modeset_restore;
1447 struct mutex modeset_restore_lock;
1448
1449 struct list_head vm_list; /* Global list of all address spaces */
1450 struct i915_gtt gtt; /* VM representing the global address space */
1451
1452 struct i915_gem_mm mm;
1453 #if defined(CONFIG_MMU_NOTIFIER)
1454 DECLARE_HASHTABLE(mmu_notifiers, 7);
1455 #endif
1456
1457 /* Kernel Modesetting */
1458
1459 struct sdvo_device_mapping sdvo_mappings[2];
1460
1461 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1462 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1463 wait_queue_head_t pending_flip_queue;
1464
1465 #ifdef CONFIG_DEBUG_FS
1466 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1467 #endif
1468
1469 int num_shared_dpll;
1470 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1471 struct intel_ddi_plls ddi_plls;
1472 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1473
1474 /* Reclocking support */
1475 bool render_reclock_avail;
1476 bool lvds_downclock_avail;
1477 /* indicates the reduced downclock for LVDS*/
1478 int lvds_downclock;
1479 u16 orig_clock;
1480
1481 bool mchbar_need_disable;
1482
1483 struct intel_l3_parity l3_parity;
1484
1485 /* Cannot be determined by PCIID. You must always read a register. */
1486 size_t ellc_size;
1487
1488 /* gen6+ rps state */
1489 struct intel_gen6_power_mgmt rps;
1490
1491 /* ilk-only ips/rps state. Everything in here is protected by the global
1492 * mchdev_lock in intel_pm.c */
1493 struct intel_ilk_power_mgmt ips;
1494
1495 struct i915_power_domains power_domains;
1496
1497 struct i915_psr psr;
1498
1499 struct i915_gpu_error gpu_error;
1500
1501 struct drm_i915_gem_object *vlv_pctx;
1502
1503 #ifdef CONFIG_DRM_I915_FBDEV
1504 /* list of fbdev register on this device */
1505 struct intel_fbdev *fbdev;
1506 #endif
1507
1508 /*
1509 * The console may be contended at resume, but we don't
1510 * want it to block on it.
1511 */
1512 struct work_struct console_resume_work;
1513
1514 struct drm_property *broadcast_rgb_property;
1515 struct drm_property *force_audio_property;
1516
1517 uint32_t hw_context_size;
1518 struct list_head context_list;
1519
1520 u32 fdi_rx_config;
1521
1522 u32 suspend_count;
1523 struct i915_suspend_saved_registers regfile;
1524 struct vlv_s0ix_state vlv_s0ix_state;
1525
1526 struct {
1527 /*
1528 * Raw watermark latency values:
1529 * in 0.1us units for WM0,
1530 * in 0.5us units for WM1+.
1531 */
1532 /* primary */
1533 uint16_t pri_latency[5];
1534 /* sprite */
1535 uint16_t spr_latency[5];
1536 /* cursor */
1537 uint16_t cur_latency[5];
1538
1539 /* current hardware state */
1540 struct ilk_wm_values hw;
1541 } wm;
1542
1543 struct i915_runtime_pm pm;
1544
1545 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1546 * here! */
1547 struct i915_dri1_state dri1;
1548 /* Old ums support infrastructure, same warning applies. */
1549 struct i915_ums_state ums;
1550 /* the indicator for dispatch video commands on two BSD rings */
1551 int ring_index;
1552 };
1553
1554 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1555 {
1556 return dev->dev_private;
1557 }
1558
1559 /* Iterate over initialised rings */
1560 #define for_each_ring(ring__, dev_priv__, i__) \
1561 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1562 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1563
1564 enum hdmi_force_audio {
1565 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1566 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1567 HDMI_AUDIO_AUTO, /* trust EDID */
1568 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1569 };
1570
1571 #define I915_GTT_OFFSET_NONE ((u32)-1)
1572
1573 struct drm_i915_gem_object_ops {
1574 /* Interface between the GEM object and its backing storage.
1575 * get_pages() is called once prior to the use of the associated set
1576 * of pages before to binding them into the GTT, and put_pages() is
1577 * called after we no longer need them. As we expect there to be
1578 * associated cost with migrating pages between the backing storage
1579 * and making them available for the GPU (e.g. clflush), we may hold
1580 * onto the pages after they are no longer referenced by the GPU
1581 * in case they may be used again shortly (for example migrating the
1582 * pages to a different memory domain within the GTT). put_pages()
1583 * will therefore most likely be called when the object itself is
1584 * being released or under memory pressure (where we attempt to
1585 * reap pages for the shrinker).
1586 */
1587 int (*get_pages)(struct drm_i915_gem_object *);
1588 void (*put_pages)(struct drm_i915_gem_object *);
1589 int (*dmabuf_export)(struct drm_i915_gem_object *);
1590 void (*release)(struct drm_i915_gem_object *);
1591 };
1592
1593 struct drm_i915_gem_object {
1594 struct drm_gem_object base;
1595
1596 const struct drm_i915_gem_object_ops *ops;
1597
1598 /** List of VMAs backed by this object */
1599 struct list_head vma_list;
1600
1601 /** Stolen memory for this object, instead of being backed by shmem. */
1602 struct drm_mm_node *stolen;
1603 struct list_head global_list;
1604
1605 struct list_head ring_list;
1606 /** Used in execbuf to temporarily hold a ref */
1607 struct list_head obj_exec_link;
1608
1609 /**
1610 * This is set if the object is on the active lists (has pending
1611 * rendering and so a non-zero seqno), and is not set if it i s on
1612 * inactive (ready to be unbound) list.
1613 */
1614 unsigned int active:1;
1615
1616 /**
1617 * This is set if the object has been written to since last bound
1618 * to the GTT
1619 */
1620 unsigned int dirty:1;
1621
1622 /**
1623 * Fence register bits (if any) for this object. Will be set
1624 * as needed when mapped into the GTT.
1625 * Protected by dev->struct_mutex.
1626 */
1627 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1628
1629 /**
1630 * Advice: are the backing pages purgeable?
1631 */
1632 unsigned int madv:2;
1633
1634 /**
1635 * Current tiling mode for the object.
1636 */
1637 unsigned int tiling_mode:2;
1638 /**
1639 * Whether the tiling parameters for the currently associated fence
1640 * register have changed. Note that for the purposes of tracking
1641 * tiling changes we also treat the unfenced register, the register
1642 * slot that the object occupies whilst it executes a fenced
1643 * command (such as BLT on gen2/3), as a "fence".
1644 */
1645 unsigned int fence_dirty:1;
1646
1647 /**
1648 * Is the object at the current location in the gtt mappable and
1649 * fenceable? Used to avoid costly recalculations.
1650 */
1651 unsigned int map_and_fenceable:1;
1652
1653 /**
1654 * Whether the current gtt mapping needs to be mappable (and isn't just
1655 * mappable by accident). Track pin and fault separate for a more
1656 * accurate mappable working set.
1657 */
1658 unsigned int fault_mappable:1;
1659 unsigned int pin_mappable:1;
1660 unsigned int pin_display:1;
1661
1662 /*
1663 * Is the GPU currently using a fence to access this buffer,
1664 */
1665 unsigned int pending_fenced_gpu_access:1;
1666 unsigned int fenced_gpu_access:1;
1667
1668 unsigned int cache_level:3;
1669
1670 unsigned int has_aliasing_ppgtt_mapping:1;
1671 unsigned int has_global_gtt_mapping:1;
1672 unsigned int has_dma_mapping:1;
1673
1674 struct sg_table *pages;
1675 int pages_pin_count;
1676
1677 /* prime dma-buf support */
1678 void *dma_buf_vmapping;
1679 int vmapping_count;
1680
1681 struct intel_ring_buffer *ring;
1682
1683 /** Breadcrumb of last rendering to the buffer. */
1684 uint32_t last_read_seqno;
1685 uint32_t last_write_seqno;
1686 /** Breadcrumb of last fenced GPU access to the buffer. */
1687 uint32_t last_fenced_seqno;
1688
1689 /** Current tiling stride for the object, if it's tiled. */
1690 uint32_t stride;
1691
1692 /** References from framebuffers, locks out tiling changes. */
1693 unsigned long framebuffer_references;
1694
1695 /** Record of address bit 17 of each page at last unbind. */
1696 unsigned long *bit_17;
1697
1698 /** User space pin count and filp owning the pin */
1699 unsigned long user_pin_count;
1700 struct drm_file *pin_filp;
1701
1702 /** for phy allocated objects */
1703 struct drm_i915_gem_phys_object *phys_obj;
1704
1705 union {
1706 struct i915_gem_userptr {
1707 uintptr_t ptr;
1708 unsigned read_only :1;
1709 unsigned workers :4;
1710 #define I915_GEM_USERPTR_MAX_WORKERS 15
1711
1712 struct mm_struct *mm;
1713 struct i915_mmu_object *mn;
1714 struct work_struct *work;
1715 } userptr;
1716 };
1717 };
1718 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1719
1720 /**
1721 * Request queue structure.
1722 *
1723 * The request queue allows us to note sequence numbers that have been emitted
1724 * and may be associated with active buffers to be retired.
1725 *
1726 * By keeping this list, we can avoid having to do questionable
1727 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1728 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1729 */
1730 struct drm_i915_gem_request {
1731 /** On Which ring this request was generated */
1732 struct intel_ring_buffer *ring;
1733
1734 /** GEM sequence number associated with this request. */
1735 uint32_t seqno;
1736
1737 /** Position in the ringbuffer of the start of the request */
1738 u32 head;
1739
1740 /** Position in the ringbuffer of the end of the request */
1741 u32 tail;
1742
1743 /** Context related to this request */
1744 struct i915_hw_context *ctx;
1745
1746 /** Batch buffer related to this request if any */
1747 struct drm_i915_gem_object *batch_obj;
1748
1749 /** Time at which this request was emitted, in jiffies. */
1750 unsigned long emitted_jiffies;
1751
1752 /** global list entry for this request */
1753 struct list_head list;
1754
1755 struct drm_i915_file_private *file_priv;
1756 /** file_priv list entry for this request */
1757 struct list_head client_list;
1758 };
1759
1760 struct drm_i915_file_private {
1761 struct drm_i915_private *dev_priv;
1762 struct drm_file *file;
1763
1764 struct {
1765 spinlock_t lock;
1766 struct list_head request_list;
1767 struct delayed_work idle_work;
1768 } mm;
1769 struct idr context_idr;
1770
1771 struct i915_hw_context *private_default_ctx;
1772 atomic_t rps_wait_boost;
1773 struct intel_ring_buffer *bsd_ring;
1774 };
1775
1776 /*
1777 * A command that requires special handling by the command parser.
1778 */
1779 struct drm_i915_cmd_descriptor {
1780 /*
1781 * Flags describing how the command parser processes the command.
1782 *
1783 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1784 * a length mask if not set
1785 * CMD_DESC_SKIP: The command is allowed but does not follow the
1786 * standard length encoding for the opcode range in
1787 * which it falls
1788 * CMD_DESC_REJECT: The command is never allowed
1789 * CMD_DESC_REGISTER: The command should be checked against the
1790 * register whitelist for the appropriate ring
1791 * CMD_DESC_MASTER: The command is allowed if the submitting process
1792 * is the DRM master
1793 */
1794 u32 flags;
1795 #define CMD_DESC_FIXED (1<<0)
1796 #define CMD_DESC_SKIP (1<<1)
1797 #define CMD_DESC_REJECT (1<<2)
1798 #define CMD_DESC_REGISTER (1<<3)
1799 #define CMD_DESC_BITMASK (1<<4)
1800 #define CMD_DESC_MASTER (1<<5)
1801
1802 /*
1803 * The command's unique identification bits and the bitmask to get them.
1804 * This isn't strictly the opcode field as defined in the spec and may
1805 * also include type, subtype, and/or subop fields.
1806 */
1807 struct {
1808 u32 value;
1809 u32 mask;
1810 } cmd;
1811
1812 /*
1813 * The command's length. The command is either fixed length (i.e. does
1814 * not include a length field) or has a length field mask. The flag
1815 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1816 * a length mask. All command entries in a command table must include
1817 * length information.
1818 */
1819 union {
1820 u32 fixed;
1821 u32 mask;
1822 } length;
1823
1824 /*
1825 * Describes where to find a register address in the command to check
1826 * against the ring's register whitelist. Only valid if flags has the
1827 * CMD_DESC_REGISTER bit set.
1828 */
1829 struct {
1830 u32 offset;
1831 u32 mask;
1832 } reg;
1833
1834 #define MAX_CMD_DESC_BITMASKS 3
1835 /*
1836 * Describes command checks where a particular dword is masked and
1837 * compared against an expected value. If the command does not match
1838 * the expected value, the parser rejects it. Only valid if flags has
1839 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1840 * are valid.
1841 *
1842 * If the check specifies a non-zero condition_mask then the parser
1843 * only performs the check when the bits specified by condition_mask
1844 * are non-zero.
1845 */
1846 struct {
1847 u32 offset;
1848 u32 mask;
1849 u32 expected;
1850 u32 condition_offset;
1851 u32 condition_mask;
1852 } bits[MAX_CMD_DESC_BITMASKS];
1853 };
1854
1855 /*
1856 * A table of commands requiring special handling by the command parser.
1857 *
1858 * Each ring has an array of tables. Each table consists of an array of command
1859 * descriptors, which must be sorted with command opcodes in ascending order.
1860 */
1861 struct drm_i915_cmd_table {
1862 const struct drm_i915_cmd_descriptor *table;
1863 int count;
1864 };
1865
1866 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1867
1868 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1869 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1870 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1871 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1872 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1873 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1874 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1875 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1876 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1877 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1878 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1879 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1880 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1881 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1882 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1883 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1884 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1885 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1886 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1887 (dev)->pdev->device == 0x0152 || \
1888 (dev)->pdev->device == 0x015a)
1889 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1890 (dev)->pdev->device == 0x0106 || \
1891 (dev)->pdev->device == 0x010A)
1892 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1893 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1894 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1895 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1896 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1897 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1898 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1899 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1900 (((dev)->pdev->device & 0xf) == 0x2 || \
1901 ((dev)->pdev->device & 0xf) == 0x6 || \
1902 ((dev)->pdev->device & 0xf) == 0xe))
1903 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1904 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1905 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1906 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1907 ((dev)->pdev->device & 0x00F0) == 0x0020)
1908 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1909
1910 /*
1911 * The genX designation typically refers to the render engine, so render
1912 * capability related checks should use IS_GEN, while display and other checks
1913 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1914 * chips, etc.).
1915 */
1916 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1917 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1918 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1919 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1920 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1921 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1922 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1923
1924 #define RENDER_RING (1<<RCS)
1925 #define BSD_RING (1<<VCS)
1926 #define BLT_RING (1<<BCS)
1927 #define VEBOX_RING (1<<VECS)
1928 #define BSD2_RING (1<<VCS2)
1929 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1930 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
1931 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1932 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1933 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1934 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
1935 to_i915(dev)->ellc_size)
1936 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1937
1938 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1939 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && \
1940 (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
1941 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 \
1942 && !IS_GEN8(dev))
1943 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1944 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1945
1946 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1947 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1948
1949 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1950 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1951 /*
1952 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1953 * even when in MSI mode. This results in spurious interrupt warnings if the
1954 * legacy irq no. is shared with another device. The kernel then disables that
1955 * interrupt source and so prevents the other device from working properly.
1956 */
1957 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1958 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1959
1960 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1961 * rows, which changed the alignment requirements and fence programming.
1962 */
1963 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1964 IS_I915GM(dev)))
1965 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1966 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1967 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1968 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1969 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1970
1971 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1972 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1973 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1974
1975 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1976
1977 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1978 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1979 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1980 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
1981 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
1982
1983 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1984 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1985 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1986 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1987 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1988 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1989
1990 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1991 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1992 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1993 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1994 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1995 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1996
1997 /* DPF == dynamic parity feature */
1998 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1999 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2000
2001 #define GT_FREQUENCY_MULTIPLIER 50
2002
2003 #include "i915_trace.h"
2004
2005 extern const struct drm_ioctl_desc i915_ioctls[];
2006 extern int i915_max_ioctl;
2007
2008 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2009 extern int i915_resume(struct drm_device *dev);
2010 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2011 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2012
2013 /* i915_params.c */
2014 struct i915_params {
2015 int modeset;
2016 int panel_ignore_lid;
2017 unsigned int powersave;
2018 int semaphores;
2019 unsigned int lvds_downclock;
2020 int lvds_channel_mode;
2021 int panel_use_ssc;
2022 int vbt_sdvo_panel_type;
2023 int enable_rc6;
2024 int enable_fbc;
2025 int enable_ppgtt;
2026 int enable_psr;
2027 unsigned int preliminary_hw_support;
2028 int disable_power_well;
2029 int enable_ips;
2030 int invert_brightness;
2031 int enable_cmd_parser;
2032 /* leave bools at the end to not create holes */
2033 bool enable_hangcheck;
2034 bool fastboot;
2035 bool prefault_disable;
2036 bool reset;
2037 bool disable_display;
2038 bool disable_vtd_wa;
2039 };
2040 extern struct i915_params i915 __read_mostly;
2041
2042 /* i915_dma.c */
2043 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2044 extern void i915_kernel_lost_context(struct drm_device * dev);
2045 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2046 extern int i915_driver_unload(struct drm_device *);
2047 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2048 extern void i915_driver_lastclose(struct drm_device * dev);
2049 extern void i915_driver_preclose(struct drm_device *dev,
2050 struct drm_file *file_priv);
2051 extern void i915_driver_postclose(struct drm_device *dev,
2052 struct drm_file *file_priv);
2053 extern int i915_driver_device_is_agp(struct drm_device * dev);
2054 #ifdef CONFIG_COMPAT
2055 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2056 unsigned long arg);
2057 #endif
2058 extern int i915_emit_box(struct drm_device *dev,
2059 struct drm_clip_rect *box,
2060 int DR1, int DR4);
2061 extern int intel_gpu_reset(struct drm_device *dev);
2062 extern int i915_reset(struct drm_device *dev);
2063 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2064 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2065 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2066 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2067 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2068
2069 extern void intel_console_resume(struct work_struct *work);
2070
2071 /* i915_irq.c */
2072 void i915_queue_hangcheck(struct drm_device *dev);
2073 __printf(3, 4)
2074 void i915_handle_error(struct drm_device *dev, bool wedged,
2075 const char *fmt, ...);
2076
2077 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2078 int new_delay);
2079 extern void intel_irq_init(struct drm_device *dev);
2080 extern void intel_hpd_init(struct drm_device *dev);
2081
2082 extern void intel_uncore_sanitize(struct drm_device *dev);
2083 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2084 extern void intel_uncore_init(struct drm_device *dev);
2085 extern void intel_uncore_check_errors(struct drm_device *dev);
2086 extern void intel_uncore_fini(struct drm_device *dev);
2087
2088 void
2089 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2090 u32 status_mask);
2091
2092 void
2093 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2094 u32 status_mask);
2095
2096 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2097 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2098
2099 /* i915_gem.c */
2100 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2101 struct drm_file *file_priv);
2102 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2103 struct drm_file *file_priv);
2104 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
2110 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *file_priv);
2114 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *file_priv);
2116 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
2118 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2119 struct drm_file *file_priv);
2120 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2121 struct drm_file *file_priv);
2122 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2123 struct drm_file *file_priv);
2124 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *file_priv);
2126 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *file);
2128 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *file);
2130 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2131 struct drm_file *file_priv);
2132 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2133 struct drm_file *file_priv);
2134 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2135 struct drm_file *file_priv);
2136 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2137 struct drm_file *file_priv);
2138 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2139 struct drm_file *file_priv);
2140 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2141 struct drm_file *file_priv);
2142 int i915_gem_init_userptr(struct drm_device *dev);
2143 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2144 struct drm_file *file);
2145 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2146 struct drm_file *file_priv);
2147 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *file_priv);
2149 void i915_gem_load(struct drm_device *dev);
2150 void *i915_gem_object_alloc(struct drm_device *dev);
2151 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2152 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2153 const struct drm_i915_gem_object_ops *ops);
2154 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2155 size_t size);
2156 void i915_init_vm(struct drm_i915_private *dev_priv,
2157 struct i915_address_space *vm);
2158 void i915_gem_free_object(struct drm_gem_object *obj);
2159 void i915_gem_vma_destroy(struct i915_vma *vma);
2160
2161 #define PIN_MAPPABLE 0x1
2162 #define PIN_NONBLOCK 0x2
2163 #define PIN_GLOBAL 0x4
2164 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2165 struct i915_address_space *vm,
2166 uint32_t alignment,
2167 unsigned flags);
2168 int __must_check i915_vma_unbind(struct i915_vma *vma);
2169 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2170 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2171 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2172 void i915_gem_lastclose(struct drm_device *dev);
2173
2174 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2175 int *needs_clflush);
2176
2177 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2178 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2179 {
2180 struct sg_page_iter sg_iter;
2181
2182 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2183 return sg_page_iter_page(&sg_iter);
2184
2185 return NULL;
2186 }
2187 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2188 {
2189 BUG_ON(obj->pages == NULL);
2190 obj->pages_pin_count++;
2191 }
2192 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2193 {
2194 BUG_ON(obj->pages_pin_count == 0);
2195 obj->pages_pin_count--;
2196 }
2197
2198 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2199 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2200 struct intel_ring_buffer *to);
2201 void i915_vma_move_to_active(struct i915_vma *vma,
2202 struct intel_ring_buffer *ring);
2203 int i915_gem_dumb_create(struct drm_file *file_priv,
2204 struct drm_device *dev,
2205 struct drm_mode_create_dumb *args);
2206 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2207 uint32_t handle, uint64_t *offset);
2208 /**
2209 * Returns true if seq1 is later than seq2.
2210 */
2211 static inline bool
2212 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2213 {
2214 return (int32_t)(seq1 - seq2) >= 0;
2215 }
2216
2217 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2218 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2219 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2220 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2221
2222 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2223 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2224
2225 struct drm_i915_gem_request *
2226 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2227
2228 bool i915_gem_retire_requests(struct drm_device *dev);
2229 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2230 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2231 bool interruptible);
2232 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2233 {
2234 return unlikely(atomic_read(&error->reset_counter)
2235 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2236 }
2237
2238 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2239 {
2240 return atomic_read(&error->reset_counter) & I915_WEDGED;
2241 }
2242
2243 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2244 {
2245 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2246 }
2247
2248 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2249 {
2250 return dev_priv->gpu_error.stop_rings == 0 ||
2251 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2252 }
2253
2254 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2255 {
2256 return dev_priv->gpu_error.stop_rings == 0 ||
2257 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2258 }
2259
2260 void i915_gem_reset(struct drm_device *dev);
2261 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2262 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2263 int __must_check i915_gem_init(struct drm_device *dev);
2264 int __must_check i915_gem_init_hw(struct drm_device *dev);
2265 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2266 void i915_gem_init_swizzling(struct drm_device *dev);
2267 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2268 int __must_check i915_gpu_idle(struct drm_device *dev);
2269 int __must_check i915_gem_suspend(struct drm_device *dev);
2270 int __i915_add_request(struct intel_ring_buffer *ring,
2271 struct drm_file *file,
2272 struct drm_i915_gem_object *batch_obj,
2273 u32 *seqno);
2274 #define i915_add_request(ring, seqno) \
2275 __i915_add_request(ring, NULL, NULL, seqno)
2276 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2277 uint32_t seqno);
2278 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2279 int __must_check
2280 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2281 bool write);
2282 int __must_check
2283 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2284 int __must_check
2285 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2286 u32 alignment,
2287 struct intel_ring_buffer *pipelined);
2288 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2289 int i915_gem_attach_phys_object(struct drm_device *dev,
2290 struct drm_i915_gem_object *obj,
2291 int id,
2292 int align);
2293 void i915_gem_detach_phys_object(struct drm_device *dev,
2294 struct drm_i915_gem_object *obj);
2295 void i915_gem_free_all_phys_object(struct drm_device *dev);
2296 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2297 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2298
2299 uint32_t
2300 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2301 uint32_t
2302 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2303 int tiling_mode, bool fenced);
2304
2305 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2306 enum i915_cache_level cache_level);
2307
2308 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2309 struct dma_buf *dma_buf);
2310
2311 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2312 struct drm_gem_object *gem_obj, int flags);
2313
2314 void i915_gem_restore_fences(struct drm_device *dev);
2315
2316 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2317 struct i915_address_space *vm);
2318 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2319 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2320 struct i915_address_space *vm);
2321 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2322 struct i915_address_space *vm);
2323 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2324 struct i915_address_space *vm);
2325 struct i915_vma *
2326 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2327 struct i915_address_space *vm);
2328
2329 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2330 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2331 struct i915_vma *vma;
2332 list_for_each_entry(vma, &obj->vma_list, vma_link)
2333 if (vma->pin_count > 0)
2334 return true;
2335 return false;
2336 }
2337
2338 /* Some GGTT VM helpers */
2339 #define obj_to_ggtt(obj) \
2340 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2341 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2342 {
2343 struct i915_address_space *ggtt =
2344 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2345 return vm == ggtt;
2346 }
2347
2348 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2349 {
2350 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2351 }
2352
2353 static inline unsigned long
2354 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2355 {
2356 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2357 }
2358
2359 static inline unsigned long
2360 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2361 {
2362 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2363 }
2364
2365 static inline int __must_check
2366 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2367 uint32_t alignment,
2368 unsigned flags)
2369 {
2370 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2371 }
2372
2373 static inline int
2374 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2375 {
2376 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2377 }
2378
2379 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2380
2381 /* i915_gem_context.c */
2382 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2383 int __must_check i915_gem_context_init(struct drm_device *dev);
2384 void i915_gem_context_fini(struct drm_device *dev);
2385 void i915_gem_context_reset(struct drm_device *dev);
2386 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2387 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2388 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2389 int i915_switch_context(struct intel_ring_buffer *ring,
2390 struct i915_hw_context *to);
2391 struct i915_hw_context *
2392 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2393 void i915_gem_context_free(struct kref *ctx_ref);
2394 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2395 {
2396 kref_get(&ctx->ref);
2397 }
2398
2399 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2400 {
2401 kref_put(&ctx->ref, i915_gem_context_free);
2402 }
2403
2404 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2405 {
2406 return c->id == DEFAULT_CONTEXT_ID;
2407 }
2408
2409 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2410 struct drm_file *file);
2411 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2412 struct drm_file *file);
2413
2414 /* i915_gem_render_state.c */
2415 int i915_gem_render_state_init(struct intel_ring_buffer *ring);
2416 /* i915_gem_evict.c */
2417 int __must_check i915_gem_evict_something(struct drm_device *dev,
2418 struct i915_address_space *vm,
2419 int min_size,
2420 unsigned alignment,
2421 unsigned cache_level,
2422 unsigned flags);
2423 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2424 int i915_gem_evict_everything(struct drm_device *dev);
2425
2426 /* belongs in i915_gem_gtt.h */
2427 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2428 {
2429 if (INTEL_INFO(dev)->gen < 6)
2430 intel_gtt_chipset_flush();
2431 }
2432
2433 /* i915_gem_stolen.c */
2434 int i915_gem_init_stolen(struct drm_device *dev);
2435 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2436 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2437 void i915_gem_cleanup_stolen(struct drm_device *dev);
2438 struct drm_i915_gem_object *
2439 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2440 struct drm_i915_gem_object *
2441 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2442 u32 stolen_offset,
2443 u32 gtt_offset,
2444 u32 size);
2445 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2446
2447 /* i915_gem_tiling.c */
2448 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2449 {
2450 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2451
2452 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2453 obj->tiling_mode != I915_TILING_NONE;
2454 }
2455
2456 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2457 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2458 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2459
2460 /* i915_gem_debug.c */
2461 #if WATCH_LISTS
2462 int i915_verify_lists(struct drm_device *dev);
2463 #else
2464 #define i915_verify_lists(dev) 0
2465 #endif
2466
2467 /* i915_debugfs.c */
2468 int i915_debugfs_init(struct drm_minor *minor);
2469 void i915_debugfs_cleanup(struct drm_minor *minor);
2470 #ifdef CONFIG_DEBUG_FS
2471 void intel_display_crc_init(struct drm_device *dev);
2472 #else
2473 static inline void intel_display_crc_init(struct drm_device *dev) {}
2474 #endif
2475
2476 /* i915_gpu_error.c */
2477 __printf(2, 3)
2478 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2479 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2480 const struct i915_error_state_file_priv *error);
2481 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2482 size_t count, loff_t pos);
2483 static inline void i915_error_state_buf_release(
2484 struct drm_i915_error_state_buf *eb)
2485 {
2486 kfree(eb->buf);
2487 }
2488 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2489 const char *error_msg);
2490 void i915_error_state_get(struct drm_device *dev,
2491 struct i915_error_state_file_priv *error_priv);
2492 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2493 void i915_destroy_error_state(struct drm_device *dev);
2494
2495 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2496 const char *i915_cache_level_str(int type);
2497
2498 /* i915_cmd_parser.c */
2499 int i915_cmd_parser_get_version(void);
2500 int i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2501 void i915_cmd_parser_fini_ring(struct intel_ring_buffer *ring);
2502 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2503 int i915_parse_cmds(struct intel_ring_buffer *ring,
2504 struct drm_i915_gem_object *batch_obj,
2505 u32 batch_start_offset,
2506 bool is_master);
2507
2508 /* i915_suspend.c */
2509 extern int i915_save_state(struct drm_device *dev);
2510 extern int i915_restore_state(struct drm_device *dev);
2511
2512 /* i915_ums.c */
2513 void i915_save_display_reg(struct drm_device *dev);
2514 void i915_restore_display_reg(struct drm_device *dev);
2515
2516 /* i915_sysfs.c */
2517 void i915_setup_sysfs(struct drm_device *dev_priv);
2518 void i915_teardown_sysfs(struct drm_device *dev_priv);
2519
2520 /* intel_i2c.c */
2521 extern int intel_setup_gmbus(struct drm_device *dev);
2522 extern void intel_teardown_gmbus(struct drm_device *dev);
2523 static inline bool intel_gmbus_is_port_valid(unsigned port)
2524 {
2525 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2526 }
2527
2528 extern struct i2c_adapter *intel_gmbus_get_adapter(
2529 struct drm_i915_private *dev_priv, unsigned port);
2530 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2531 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2532 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2533 {
2534 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2535 }
2536 extern void intel_i2c_reset(struct drm_device *dev);
2537
2538 /* intel_opregion.c */
2539 struct intel_encoder;
2540 #ifdef CONFIG_ACPI
2541 extern int intel_opregion_setup(struct drm_device *dev);
2542 extern void intel_opregion_init(struct drm_device *dev);
2543 extern void intel_opregion_fini(struct drm_device *dev);
2544 extern void intel_opregion_asle_intr(struct drm_device *dev);
2545 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2546 bool enable);
2547 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2548 pci_power_t state);
2549 #else
2550 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2551 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2552 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2553 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2554 static inline int
2555 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2556 {
2557 return 0;
2558 }
2559 static inline int
2560 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2561 {
2562 return 0;
2563 }
2564 #endif
2565
2566 /* intel_acpi.c */
2567 #ifdef CONFIG_ACPI
2568 extern void intel_register_dsm_handler(void);
2569 extern void intel_unregister_dsm_handler(void);
2570 #else
2571 static inline void intel_register_dsm_handler(void) { return; }
2572 static inline void intel_unregister_dsm_handler(void) { return; }
2573 #endif /* CONFIG_ACPI */
2574
2575 /* modesetting */
2576 extern void intel_modeset_init_hw(struct drm_device *dev);
2577 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2578 extern void intel_modeset_init(struct drm_device *dev);
2579 extern void intel_modeset_gem_init(struct drm_device *dev);
2580 extern void intel_modeset_cleanup(struct drm_device *dev);
2581 extern void intel_connector_unregister(struct intel_connector *);
2582 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2583 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2584 bool force_restore);
2585 extern void i915_redisable_vga(struct drm_device *dev);
2586 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2587 extern bool intel_fbc_enabled(struct drm_device *dev);
2588 extern void intel_disable_fbc(struct drm_device *dev);
2589 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2590 extern void intel_init_pch_refclk(struct drm_device *dev);
2591 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2592 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2593 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2594 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2595 extern void intel_detect_pch(struct drm_device *dev);
2596 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2597 extern int intel_enable_rc6(const struct drm_device *dev);
2598
2599 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2600 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2601 struct drm_file *file);
2602 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2603 struct drm_file *file);
2604
2605 /* overlay */
2606 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2607 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2608 struct intel_overlay_error_state *error);
2609
2610 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2611 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2612 struct drm_device *dev,
2613 struct intel_display_error_state *error);
2614
2615 /* On SNB platform, before reading ring registers forcewake bit
2616 * must be set to prevent GT core from power down and stale values being
2617 * returned.
2618 */
2619 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2620 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2621 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2622
2623 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2624 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2625
2626 /* intel_sideband.c */
2627 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2628 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2629 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2630 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2631 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2632 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2633 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2634 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2635 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2636 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2637 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2638 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2639 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2640 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2641 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2642 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2643 enum intel_sbi_destination destination);
2644 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2645 enum intel_sbi_destination destination);
2646 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2647 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2648
2649 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2650 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2651
2652 #define FORCEWAKE_RENDER (1 << 0)
2653 #define FORCEWAKE_MEDIA (1 << 1)
2654 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2655
2656
2657 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2658 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2659
2660 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2661 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2662 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2663 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2664
2665 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2666 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2667 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2668 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2669
2670 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2671 * will be implemented using 2 32-bit writes in an arbitrary order with
2672 * an arbitrary delay between them. This can cause the hardware to
2673 * act upon the intermediate value, possibly leading to corruption and
2674 * machine death. You have been warned.
2675 */
2676 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2677 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2678
2679 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2680 u32 upper = I915_READ(upper_reg); \
2681 u32 lower = I915_READ(lower_reg); \
2682 u32 tmp = I915_READ(upper_reg); \
2683 if (upper != tmp) { \
2684 upper = tmp; \
2685 lower = I915_READ(lower_reg); \
2686 WARN_ON(I915_READ(upper_reg) != upper); \
2687 } \
2688 (u64)upper << 32 | lower; })
2689
2690 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2691 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2692
2693 /* "Broadcast RGB" property */
2694 #define INTEL_BROADCAST_RGB_AUTO 0
2695 #define INTEL_BROADCAST_RGB_FULL 1
2696 #define INTEL_BROADCAST_RGB_LIMITED 2
2697
2698 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2699 {
2700 if (HAS_PCH_SPLIT(dev))
2701 return CPU_VGACNTRL;
2702 else if (IS_VALLEYVIEW(dev))
2703 return VLV_VGACNTRL;
2704 else
2705 return VGACNTRL;
2706 }
2707
2708 static inline void __user *to_user_ptr(u64 address)
2709 {
2710 return (void __user *)(uintptr_t)address;
2711 }
2712
2713 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2714 {
2715 unsigned long j = msecs_to_jiffies(m);
2716
2717 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2718 }
2719
2720 static inline unsigned long
2721 timespec_to_jiffies_timeout(const struct timespec *value)
2722 {
2723 unsigned long j = timespec_to_jiffies(value);
2724
2725 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2726 }
2727
2728 /*
2729 * If you need to wait X milliseconds between events A and B, but event B
2730 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2731 * when event A happened, then just before event B you call this function and
2732 * pass the timestamp as the first argument, and X as the second argument.
2733 */
2734 static inline void
2735 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2736 {
2737 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2738
2739 /*
2740 * Don't re-read the value of "jiffies" every time since it may change
2741 * behind our back and break the math.
2742 */
2743 tmp_jiffies = jiffies;
2744 target_jiffies = timestamp_jiffies +
2745 msecs_to_jiffies_timeout(to_wait_ms);
2746
2747 if (time_after(target_jiffies, tmp_jiffies)) {
2748 remaining_jiffies = target_jiffies - tmp_jiffies;
2749 while (remaining_jiffies)
2750 remaining_jiffies =
2751 schedule_timeout_uninterruptible(remaining_jiffies);
2752 }
2753 }
2754
2755 #endif
Linux kernel - Deliverables
This page took 0.123434 seconds and 5 git commands to generate.