1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
38 /* General customization:
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
57 #define I915_NUM_PIPE 2
59 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
64 * 1.2: Add Power Management
65 * 1.3: Add vblank support
66 * 1.4: Fix cmdbuffer path, add heap destroy
67 * 1.5: Add vblank pipe configuration
68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
69 * - Support vertical blank on secondary display pipe
71 #define DRIVER_MAJOR 1
72 #define DRIVER_MINOR 6
73 #define DRIVER_PATCHLEVEL 0
75 #define WATCH_COHERENCY 0
80 #define WATCH_INACTIVE 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object
{
90 struct page
**page_list
;
91 drm_dma_handle_t
*handle
;
92 struct drm_gem_object
*cur_obj
;
96 struct mem_block
*next
;
97 struct mem_block
*prev
;
100 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header
;
104 struct opregion_acpi
;
105 struct opregion_swsci
;
106 struct opregion_asle
;
108 struct intel_opregion
{
109 struct opregion_header
*header
;
110 struct opregion_acpi
*acpi
;
111 struct opregion_swsci
*swsci
;
112 struct opregion_asle
*asle
;
116 struct drm_i915_master_private
{
117 drm_local_map_t
*sarea
;
118 struct _drm_i915_sarea
*sarea_priv
;
120 #define I915_FENCE_REG_NONE -1
122 struct drm_i915_fence_reg
{
123 struct drm_gem_object
*obj
;
124 struct list_head lru_list
;
127 struct sdvo_device_mapping
{
135 struct drm_i915_error_state
{
150 struct drm_i915_error_object
{
154 } *ringbuffer
, *batchbuffer
[2];
155 struct drm_i915_error_buffer
{
171 struct drm_i915_display_funcs
{
172 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
173 bool (*fbc_enabled
)(struct drm_device
*dev
);
174 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
175 void (*disable_fbc
)(struct drm_device
*dev
);
176 int (*get_display_clock_speed
)(struct drm_device
*dev
);
177 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
178 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
179 int planeb_clock
, int sr_hdisplay
, int pixel_size
);
180 /* clock updates for mode set */
182 /* render clock increase/decrease */
183 /* display clock increase/decrease */
184 /* pll clock increase/decrease */
185 /* clock gating init */
188 struct intel_overlay
;
190 struct intel_device_info
{
207 u8 has_pipe_cxsr
: 1;
209 u8 cursor_needs_physical
: 1;
213 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
214 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
215 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
216 FBC_BAD_PLANE
, /* fbc not supported on plane */
217 FBC_NOT_TILED
, /* buffer not tiled */
221 PCH_IBX
, /* Ibexpeak PCH */
222 PCH_CPT
, /* Cougarpoint PCH */
227 typedef struct drm_i915_private
{
228 struct drm_device
*dev
;
230 const struct intel_device_info
*info
;
236 struct pci_dev
*bridge_dev
;
237 struct intel_ring_buffer render_ring
;
238 struct intel_ring_buffer bsd_ring
;
240 drm_dma_handle_t
*status_page_dmah
;
242 dma_addr_t dma_status_page
;
244 unsigned int seqno_gfx_addr
;
245 drm_local_map_t hws_map
;
246 struct drm_gem_object
*seqno_obj
;
247 struct drm_gem_object
*pwrctx
;
249 struct resource mch_res
;
257 wait_queue_head_t irq_queue
;
258 atomic_t irq_received
;
259 /** Protects user_irq_refcount and irq_mask_reg */
260 spinlock_t user_irq_lock
;
262 /** Cached value of IMR to avoid reads in updating the bitfield */
265 /** splitted irq regs for graphics and display engine on Ironlake,
266 irq_mask_reg is still used for display irq. */
268 u32 gt_irq_enable_reg
;
269 u32 de_irq_enable_reg
;
270 u32 pch_irq_mask_reg
;
271 u32 pch_irq_enable_reg
;
273 u32 hotplug_supported_mask
;
274 struct work_struct hotplug_work
;
276 int tex_lru_log_granularity
;
277 int allow_batchbuffer
;
278 struct mem_block
*agp_heap
;
279 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
283 /* For hangcheck timer */
284 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
285 struct timer_list hangcheck_timer
;
291 unsigned long cfb_size
;
292 unsigned long cfb_pitch
;
298 struct intel_opregion opregion
;
301 struct intel_overlay
*overlay
;
304 int backlight_duty_cycle
; /* restore backlight to this value */
305 bool panel_wants_dither
;
306 struct drm_display_mode
*panel_fixed_mode
;
307 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
308 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
310 /* Feature bits from the VBIOS */
311 unsigned int int_tv_support
:1;
312 unsigned int lvds_dither
:1;
313 unsigned int lvds_vbt
:1;
314 unsigned int int_crt_support
:1;
315 unsigned int lvds_use_ssc
:1;
316 unsigned int edp_support
:1;
320 struct notifier_block lid_notifier
;
322 int crt_ddc_bus
; /* 0 = unknown, else GPIO to use for CRT DDC */
323 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
324 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
325 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
327 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
329 spinlock_t error_lock
;
330 struct drm_i915_error_state
*first_error
;
331 struct work_struct error_work
;
332 struct workqueue_struct
*wq
;
334 /* Display functions */
335 struct drm_i915_display_funcs display
;
337 /* PCH chipset type */
338 enum intel_pch pch_type
;
363 u32 saveTRANS_HTOTAL_A
;
364 u32 saveTRANS_HBLANK_A
;
365 u32 saveTRANS_HSYNC_A
;
366 u32 saveTRANS_VTOTAL_A
;
367 u32 saveTRANS_VBLANK_A
;
368 u32 saveTRANS_VSYNC_A
;
376 u32 savePFIT_PGM_RATIOS
;
377 u32 saveBLC_HIST_CTL
;
379 u32 saveBLC_PWM_CTL2
;
380 u32 saveBLC_CPU_PWM_CTL
;
381 u32 saveBLC_CPU_PWM_CTL2
;
394 u32 saveTRANS_HTOTAL_B
;
395 u32 saveTRANS_HBLANK_B
;
396 u32 saveTRANS_HSYNC_B
;
397 u32 saveTRANS_VTOTAL_B
;
398 u32 saveTRANS_VBLANK_B
;
399 u32 saveTRANS_VSYNC_B
;
413 u32 savePP_ON_DELAYS
;
414 u32 savePP_OFF_DELAYS
;
422 u32 savePFIT_CONTROL
;
423 u32 save_palette_a
[256];
424 u32 save_palette_b
[256];
425 u32 saveDPFC_CB_BASE
;
426 u32 saveFBC_CFB_BASE
;
429 u32 saveFBC_CONTROL2
;
439 u32 saveCACHE_MODE_0
;
440 u32 saveMI_ARB_STATE
;
451 uint64_t saveFENCE
[16];
462 u32 savePIPEA_GMCH_DATA_M
;
463 u32 savePIPEB_GMCH_DATA_M
;
464 u32 savePIPEA_GMCH_DATA_N
;
465 u32 savePIPEB_GMCH_DATA_N
;
466 u32 savePIPEA_DP_LINK_M
;
467 u32 savePIPEB_DP_LINK_M
;
468 u32 savePIPEA_DP_LINK_N
;
469 u32 savePIPEB_DP_LINK_N
;
480 u32 savePCH_DREF_CONTROL
;
481 u32 saveDISP_ARB_CTL
;
482 u32 savePIPEA_DATA_M1
;
483 u32 savePIPEA_DATA_N1
;
484 u32 savePIPEA_LINK_M1
;
485 u32 savePIPEA_LINK_N1
;
486 u32 savePIPEB_DATA_M1
;
487 u32 savePIPEB_DATA_N1
;
488 u32 savePIPEB_LINK_M1
;
489 u32 savePIPEB_LINK_N1
;
490 u32 saveMCHBAR_RENDER_STANDBY
;
493 struct drm_mm gtt_space
;
495 struct io_mapping
*gtt_mapping
;
499 * Membership on list of all loaded devices, used to evict
500 * inactive buffers under memory pressure.
502 * Modifications should only be done whilst holding the
503 * shrink_list_lock spinlock.
505 struct list_head shrink_list
;
507 spinlock_t active_list_lock
;
510 * List of objects which are not in the ringbuffer but which
511 * still have a write_domain which needs to be flushed before
514 * last_rendering_seqno is 0 while an object is in this list.
516 * A reference is held on the buffer while on this list.
518 struct list_head flushing_list
;
521 * List of objects currently pending a GPU write flush.
523 * All elements on this list will belong to either the
524 * active_list or flushing_list, last_rendering_seqno can
525 * be used to differentiate between the two elements.
527 struct list_head gpu_write_list
;
530 * LRU list of objects which are not in the ringbuffer and
531 * are ready to unbind, but are still in the GTT.
533 * last_rendering_seqno is 0 while an object is in this list.
535 * A reference is not held on the buffer while on this list,
536 * as merely being GTT-bound shouldn't prevent its being
537 * freed, and we'll pull it off the list in the free path.
539 struct list_head inactive_list
;
541 /** LRU list of objects with fence regs on them. */
542 struct list_head fence_list
;
545 * We leave the user IRQ off as much as possible,
546 * but this means that requests will finish and never
547 * be retired once the system goes idle. Set a timer to
548 * fire periodically while the ring is running. When it
549 * fires, go retire requests.
551 struct delayed_work retire_work
;
553 uint32_t next_gem_seqno
;
556 * Waiting sequence number, if any
558 uint32_t waiting_gem_seqno
;
561 * Last seq seen at irq time
563 uint32_t irq_gem_seqno
;
566 * Flag if the X Server, and thus DRM, is not currently in
567 * control of the device.
569 * This is set between LeaveVT and EnterVT. It needs to be
570 * replaced with a semaphore. It also needs to be
571 * transitioned away from for kernel modesetting.
576 * Flag if the hardware appears to be wedged.
578 * This is set when attempts to idle the device timeout.
579 * It prevents command submission from occuring and makes
580 * every pending request fail
584 /** Bit 6 swizzling required for X tiling */
585 uint32_t bit_6_swizzle_x
;
586 /** Bit 6 swizzling required for Y tiling */
587 uint32_t bit_6_swizzle_y
;
589 /* storage for physical objects */
590 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
592 struct sdvo_device_mapping sdvo_mappings
[2];
593 /* indicate whether the LVDS_BORDER should be enabled or not */
594 unsigned int lvds_border_bits
;
596 struct drm_crtc
*plane_to_crtc_mapping
[2];
597 struct drm_crtc
*pipe_to_crtc_mapping
[2];
598 wait_queue_head_t pending_flip_queue
;
599 bool flip_pending_is_done
;
601 /* Reclocking support */
602 bool render_reclock_avail
;
603 bool lvds_downclock_avail
;
604 /* indicate whether the LVDS EDID is OK */
606 /* indicates the reduced downclock for LVDS*/
608 struct work_struct idle_work
;
609 struct timer_list idle_timer
;
613 struct child_device_config
*child_dev
;
614 struct drm_connector
*int_lvds_connector
;
616 bool mchbar_need_disable
;
625 unsigned long last_time1
;
627 struct timespec last_time2
;
628 unsigned long gfx_power
;
632 spinlock_t
*mchdev_lock
;
634 enum no_fbc_reason no_fbc_reason
;
636 struct drm_mm_node
*compressed_fb
;
637 struct drm_mm_node
*compressed_llb
;
639 /* list of fbdev register on this device */
640 struct intel_fbdev
*fbdev
;
641 } drm_i915_private_t
;
643 /** driver private structure attached to each drm_gem_object */
644 struct drm_i915_gem_object
{
645 struct drm_gem_object base
;
647 /** Current space allocated to this object in the GTT, if any. */
648 struct drm_mm_node
*gtt_space
;
650 /** This object's place on the active/flushing/inactive lists */
651 struct list_head list
;
652 /** This object's place on GPU write list */
653 struct list_head gpu_write_list
;
656 * This is set if the object is on the active or flushing lists
657 * (has pending rendering), and is not set if it's on inactive (ready
660 unsigned int active
: 1;
663 * This is set if the object has been written to since last bound
666 unsigned int dirty
: 1;
669 * Fence register bits (if any) for this object. Will be set
670 * as needed when mapped into the GTT.
671 * Protected by dev->struct_mutex.
673 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
678 * Used for checking the object doesn't appear more than once
679 * in an execbuffer object list.
681 unsigned int in_execbuffer
: 1;
684 * Advice: are the backing pages purgeable?
686 unsigned int madv
: 2;
689 * Refcount for the pages array. With the current locking scheme, there
690 * are at most two concurrent users: Binding a bo to the gtt and
691 * pwrite/pread using physical addresses. So two bits for a maximum
692 * of two users are enough.
694 unsigned int pages_refcount
: 2;
695 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
698 * Current tiling mode for the object.
700 unsigned int tiling_mode
: 2;
702 /** How many users have pinned this object in GTT space. The following
703 * users can each hold at most one reference: pwrite/pread, pin_ioctl
704 * (via user_pin_count), execbuffer (objects are not allowed multiple
705 * times for the same batchbuffer), and the framebuffer code. When
706 * switching/pageflipping, the framebuffer code has at most two buffers
709 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
710 * bits with absolutely no headroom. So use 4 bits. */
712 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
714 /** AGP memory structure for our GTT binding. */
715 DRM_AGP_MEM
*agp_mem
;
720 * Current offset of the object in GTT space.
722 * This is the same as gtt_space->start
726 /* Which ring is refering to is this object */
727 struct intel_ring_buffer
*ring
;
730 * Fake offset for use by mmap(2)
732 uint64_t mmap_offset
;
734 /** Breadcrumb of last rendering to the buffer. */
735 uint32_t last_rendering_seqno
;
737 /** Current tiling stride for the object, if it's tiled. */
740 /** Record of address bit 17 of each page at last unbind. */
743 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
747 * If present, while GEM_DOMAIN_CPU is in the read domain this array
748 * flags which individual pages are valid.
750 uint8_t *page_cpu_valid
;
752 /** User space pin count and filp owning the pin */
753 uint32_t user_pin_count
;
754 struct drm_file
*pin_filp
;
756 /** for phy allocated objects */
757 struct drm_i915_gem_phys_object
*phys_obj
;
760 * Number of crtcs where this object is currently the fb, but
761 * will be page flipped away on the next vblank. When it
762 * reaches 0, dev_priv->pending_flip_queue will be woken up.
764 atomic_t pending_flip
;
767 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
770 * Request queue structure.
772 * The request queue allows us to note sequence numbers that have been emitted
773 * and may be associated with active buffers to be retired.
775 * By keeping this list, we can avoid having to do questionable
776 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
777 * an emission time with seqnos for tracking how far ahead of the GPU we are.
779 struct drm_i915_gem_request
{
780 /** On Which ring this request was generated */
781 struct intel_ring_buffer
*ring
;
783 /** GEM sequence number associated with this request. */
786 /** Time at which this request was emitted, in jiffies. */
787 unsigned long emitted_jiffies
;
789 /** global list entry for this request */
790 struct list_head list
;
792 /** file_priv list entry for this request */
793 struct list_head client_list
;
796 struct drm_i915_file_private
{
798 struct list_head request_list
;
802 enum intel_chip_family
{
809 extern struct drm_ioctl_desc i915_ioctls
[];
810 extern int i915_max_ioctl
;
811 extern unsigned int i915_fbpercrtc
;
812 extern unsigned int i915_powersave
;
813 extern unsigned int i915_lvds_downclock
;
815 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
816 extern int i915_resume(struct drm_device
*dev
);
817 extern void i915_save_display(struct drm_device
*dev
);
818 extern void i915_restore_display(struct drm_device
*dev
);
819 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
820 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
823 extern void i915_kernel_lost_context(struct drm_device
* dev
);
824 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
825 extern int i915_driver_unload(struct drm_device
*);
826 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
827 extern void i915_driver_lastclose(struct drm_device
* dev
);
828 extern void i915_driver_preclose(struct drm_device
*dev
,
829 struct drm_file
*file_priv
);
830 extern void i915_driver_postclose(struct drm_device
*dev
,
831 struct drm_file
*file_priv
);
832 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
833 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
835 extern int i915_emit_box(struct drm_device
*dev
,
836 struct drm_clip_rect
*boxes
,
837 int i
, int DR1
, int DR4
);
838 extern int i965_reset(struct drm_device
*dev
, u8 flags
);
839 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
840 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
841 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
842 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
846 void i915_hangcheck_elapsed(unsigned long data
);
847 void i915_destroy_error_state(struct drm_device
*dev
);
848 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
849 struct drm_file
*file_priv
);
850 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
851 struct drm_file
*file_priv
);
852 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
853 extern void i915_enable_interrupt (struct drm_device
*dev
);
855 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
856 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
857 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
858 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
859 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
860 struct drm_file
*file_priv
);
861 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
862 struct drm_file
*file_priv
);
863 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
864 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
865 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
866 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
867 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
868 struct drm_file
*file_priv
);
869 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
870 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
871 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
873 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
877 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
880 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
882 void intel_enable_asle (struct drm_device
*dev
);
886 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
887 struct drm_file
*file_priv
);
888 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
889 struct drm_file
*file_priv
);
890 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
891 struct drm_file
*file_priv
);
892 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
893 struct drm_file
*file_priv
);
894 extern void i915_mem_takedown(struct mem_block
**heap
);
895 extern void i915_mem_release(struct drm_device
* dev
,
896 struct drm_file
*file_priv
, struct mem_block
*heap
);
898 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
899 struct drm_file
*file_priv
);
900 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
901 struct drm_file
*file_priv
);
902 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
903 struct drm_file
*file_priv
);
904 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
905 struct drm_file
*file_priv
);
906 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
907 struct drm_file
*file_priv
);
908 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
909 struct drm_file
*file_priv
);
910 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
911 struct drm_file
*file_priv
);
912 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
913 struct drm_file
*file_priv
);
914 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
915 struct drm_file
*file_priv
);
916 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
917 struct drm_file
*file_priv
);
918 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
919 struct drm_file
*file_priv
);
920 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
921 struct drm_file
*file_priv
);
922 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
923 struct drm_file
*file_priv
);
924 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
925 struct drm_file
*file_priv
);
926 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
927 struct drm_file
*file_priv
);
928 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
929 struct drm_file
*file_priv
);
930 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
931 struct drm_file
*file_priv
);
932 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
933 struct drm_file
*file_priv
);
934 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
935 struct drm_file
*file_priv
);
936 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
937 struct drm_file
*file_priv
);
938 void i915_gem_load(struct drm_device
*dev
);
939 int i915_gem_init_object(struct drm_gem_object
*obj
);
940 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
942 void i915_gem_free_object(struct drm_gem_object
*obj
);
943 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
944 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
945 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
946 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
947 void i915_gem_lastclose(struct drm_device
*dev
);
948 uint32_t i915_get_gem_seqno(struct drm_device
*dev
,
949 struct intel_ring_buffer
*ring
);
950 bool i915_seqno_passed(uint32_t seq1
, uint32_t seq2
);
951 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
);
952 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
);
953 void i915_gem_retire_requests(struct drm_device
*dev
,
954 struct intel_ring_buffer
*ring
);
955 void i915_gem_retire_work_handler(struct work_struct
*work
);
956 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
957 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
958 uint32_t read_domains
,
959 uint32_t write_domain
);
960 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
961 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
962 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
964 int i915_gem_idle(struct drm_device
*dev
);
965 uint32_t i915_add_request(struct drm_device
*dev
,
966 struct drm_file
*file_priv
,
967 uint32_t flush_domains
,
968 struct intel_ring_buffer
*ring
);
969 int i915_do_wait_request(struct drm_device
*dev
,
970 uint32_t seqno
, int interruptible
,
971 struct intel_ring_buffer
*ring
);
972 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
973 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
975 int i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
);
976 int i915_gem_attach_phys_object(struct drm_device
*dev
,
977 struct drm_gem_object
*obj
, int id
);
978 void i915_gem_detach_phys_object(struct drm_device
*dev
,
979 struct drm_gem_object
*obj
);
980 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
981 int i915_gem_object_get_pages(struct drm_gem_object
*obj
, gfp_t gfpmask
);
982 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
983 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
984 void i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
);
986 void i915_gem_shrinker_init(void);
987 void i915_gem_shrinker_exit(void);
989 /* i915_gem_tiling.c */
990 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
991 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
992 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
993 bool i915_tiling_ok(struct drm_device
*dev
, int stride
, int size
,
995 bool i915_gem_object_fence_offset_ok(struct drm_gem_object
*obj
,
998 /* i915_gem_debug.c */
999 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1000 const char *where
, uint32_t mark
);
1002 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
1004 #define i915_verify_inactive(dev, file, line)
1006 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
1007 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1008 const char *where
, uint32_t mark
);
1009 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
1011 /* i915_debugfs.c */
1012 int i915_debugfs_init(struct drm_minor
*minor
);
1013 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1015 /* i915_suspend.c */
1016 extern int i915_save_state(struct drm_device
*dev
);
1017 extern int i915_restore_state(struct drm_device
*dev
);
1019 /* i915_suspend.c */
1020 extern int i915_save_state(struct drm_device
*dev
);
1021 extern int i915_restore_state(struct drm_device
*dev
);
1024 /* i915_opregion.c */
1025 extern int intel_opregion_init(struct drm_device
*dev
, int resume
);
1026 extern void intel_opregion_free(struct drm_device
*dev
, int suspend
);
1027 extern void opregion_asle_intr(struct drm_device
*dev
);
1028 extern void ironlake_opregion_gse_intr(struct drm_device
*dev
);
1029 extern void opregion_enable_asle(struct drm_device
*dev
);
1031 static inline int intel_opregion_init(struct drm_device
*dev
, int resume
) { return 0; }
1032 static inline void intel_opregion_free(struct drm_device
*dev
, int suspend
) { return; }
1033 static inline void opregion_asle_intr(struct drm_device
*dev
) { return; }
1034 static inline void ironlake_opregion_gse_intr(struct drm_device
*dev
) { return; }
1035 static inline void opregion_enable_asle(struct drm_device
*dev
) { return; }
1039 extern void intel_modeset_init(struct drm_device
*dev
);
1040 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1041 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1042 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1043 extern void g4x_disable_fbc(struct drm_device
*dev
);
1044 extern void intel_disable_fbc(struct drm_device
*dev
);
1045 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1046 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1047 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1048 extern void intel_detect_pch (struct drm_device
*dev
);
1049 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1052 * Lock test for when it's just for synchronization of ring access.
1054 * In that case, we don't need to do it when GEM is initialized as nobody else
1055 * has access to the ring.
1057 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1058 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1060 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1063 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1064 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1065 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1066 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1067 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1068 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1069 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1070 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1071 #define POSTING_READ(reg) (void)I915_READ(reg)
1072 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1074 #define I915_VERBOSE 0
1076 #define BEGIN_LP_RING(n) do { \
1077 drm_i915_private_t *dev_priv = dev->dev_private; \
1079 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1080 intel_ring_begin(dev, &dev_priv->render_ring, (n)); \
1084 #define OUT_RING(x) do { \
1085 drm_i915_private_t *dev_priv = dev->dev_private; \
1087 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1088 intel_ring_emit(dev, &dev_priv->render_ring, x); \
1091 #define ADVANCE_LP_RING() do { \
1092 drm_i915_private_t *dev_priv = dev->dev_private; \
1094 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1095 dev_priv->render_ring.tail); \
1096 intel_ring_advance(dev, &dev_priv->render_ring); \
1100 * Reads a dword out of the status page, which is written to from the command
1101 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1102 * MI_STORE_DATA_IMM.
1104 * The following dwords have a reserved meaning:
1105 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1106 * 0x04: ring 0 head pointer
1107 * 0x05: ring 1 head pointer (915-class)
1108 * 0x06: ring 2 head pointer (915-class)
1109 * 0x10-0x1b: Context status DWords (GM45)
1110 * 0x1f: Last written status offset. (GM45)
1112 * The area from dword 0x20 to 0x3ff is available for driver usage.
1114 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1115 (dev_priv->render_ring.status_page.page_addr))[reg])
1116 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1117 #define I915_GEM_HWS_INDEX 0x20
1118 #define I915_BREADCRUMB_INDEX 0x21
1120 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1122 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1123 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1124 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1125 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1126 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1127 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1128 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1129 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1130 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1131 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1132 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1133 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1134 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1135 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1136 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1137 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1138 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1139 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1140 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1141 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1142 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1143 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1144 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1146 #define IS_GEN3(dev) (IS_I915G(dev) || \
1152 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1153 (dev)->pci_device == 0x2982 || \
1154 (dev)->pci_device == 0x2992 || \
1155 (dev)->pci_device == 0x29A2 || \
1156 (dev)->pci_device == 0x2A02 || \
1157 (dev)->pci_device == 0x2A12 || \
1158 (dev)->pci_device == 0x2E02 || \
1159 (dev)->pci_device == 0x2E12 || \
1160 (dev)->pci_device == 0x2E22 || \
1161 (dev)->pci_device == 0x2E32 || \
1162 (dev)->pci_device == 0x2A42 || \
1163 (dev)->pci_device == 0x2E42)
1165 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1166 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1168 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1169 * rows, which changed the alignment requirements and fence programming.
1171 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1173 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1174 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1175 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1176 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1177 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1178 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1180 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1181 /* dsparb controlled by hw only */
1182 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1184 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1185 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1186 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1187 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1189 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1191 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1193 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1194 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1196 #define PRIMARY_RINGBUFFER_SIZE (128*1024)