1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
,
108 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
110 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
111 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
112 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
113 #define POWER_DOMAIN_TRANSCODER(tran) \
114 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
115 (tran) + POWER_DOMAIN_TRANSCODER_A)
117 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
118 BIT(POWER_DOMAIN_PIPE_A) | \
119 BIT(POWER_DOMAIN_TRANSCODER_EDP))
123 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
124 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
134 #define I915_GEM_GPU_DOMAINS \
135 (I915_GEM_DOMAIN_RENDER | \
136 I915_GEM_DOMAIN_SAMPLER | \
137 I915_GEM_DOMAIN_COMMAND | \
138 I915_GEM_DOMAIN_INSTRUCTION | \
139 I915_GEM_DOMAIN_VERTEX)
141 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
143 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
144 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
145 if ((intel_encoder)->base.crtc == (__crtc))
147 struct drm_i915_private
;
150 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
151 /* real shared dpll ids must be >= 0 */
155 #define I915_NUM_PLLS 2
157 struct intel_dpll_hw_state
{
164 struct intel_shared_dpll
{
165 int refcount
; /* count of number of CRTCs sharing this PLL */
166 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
167 bool on
; /* is the PLL actually active? Disabled during modeset */
169 /* should match the index in the dev_priv->shared_dplls array */
170 enum intel_dpll_id id
;
171 struct intel_dpll_hw_state hw_state
;
172 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
173 struct intel_shared_dpll
*pll
);
174 void (*enable
)(struct drm_i915_private
*dev_priv
,
175 struct intel_shared_dpll
*pll
);
176 void (*disable
)(struct drm_i915_private
*dev_priv
,
177 struct intel_shared_dpll
*pll
);
178 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
179 struct intel_shared_dpll
*pll
,
180 struct intel_dpll_hw_state
*hw_state
);
183 /* Used by dp and fdi links */
184 struct intel_link_m_n
{
192 void intel_link_compute_m_n(int bpp
, int nlanes
,
193 int pixel_clock
, int link_clock
,
194 struct intel_link_m_n
*m_n
);
196 struct intel_ddi_plls
{
202 /* Interface history:
205 * 1.2: Add Power Management
206 * 1.3: Add vblank support
207 * 1.4: Fix cmdbuffer path, add heap destroy
208 * 1.5: Add vblank pipe configuration
209 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
210 * - Support vertical blank on secondary display pipe
212 #define DRIVER_MAJOR 1
213 #define DRIVER_MINOR 6
214 #define DRIVER_PATCHLEVEL 0
216 #define WATCH_LISTS 0
219 #define I915_GEM_PHYS_CURSOR_0 1
220 #define I915_GEM_PHYS_CURSOR_1 2
221 #define I915_GEM_PHYS_OVERLAY_REGS 3
222 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
224 struct drm_i915_gem_phys_object
{
226 struct page
**page_list
;
227 drm_dma_handle_t
*handle
;
228 struct drm_i915_gem_object
*cur_obj
;
231 struct opregion_header
;
232 struct opregion_acpi
;
233 struct opregion_swsci
;
234 struct opregion_asle
;
236 struct intel_opregion
{
237 struct opregion_header __iomem
*header
;
238 struct opregion_acpi __iomem
*acpi
;
239 struct opregion_swsci __iomem
*swsci
;
240 u32 swsci_gbda_sub_functions
;
241 u32 swsci_sbcb_sub_functions
;
242 struct opregion_asle __iomem
*asle
;
244 u32 __iomem
*lid_state
;
246 #define OPREGION_SIZE (8*1024)
248 struct intel_overlay
;
249 struct intel_overlay_error_state
;
251 struct drm_i915_master_private
{
252 drm_local_map_t
*sarea
;
253 struct _drm_i915_sarea
*sarea_priv
;
255 #define I915_FENCE_REG_NONE -1
256 #define I915_MAX_NUM_FENCES 32
257 /* 32 fences + sign bit for FENCE_REG_NONE */
258 #define I915_MAX_NUM_FENCE_BITS 6
260 struct drm_i915_fence_reg
{
261 struct list_head lru_list
;
262 struct drm_i915_gem_object
*obj
;
266 struct sdvo_device_mapping
{
275 struct intel_display_error_state
;
277 struct drm_i915_error_state
{
285 bool waiting
[I915_NUM_RINGS
];
286 u32 pipestat
[I915_MAX_PIPES
];
287 u32 tail
[I915_NUM_RINGS
];
288 u32 head
[I915_NUM_RINGS
];
289 u32 ctl
[I915_NUM_RINGS
];
290 u32 ipeir
[I915_NUM_RINGS
];
291 u32 ipehr
[I915_NUM_RINGS
];
292 u32 instdone
[I915_NUM_RINGS
];
293 u32 acthd
[I915_NUM_RINGS
];
294 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
295 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
296 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
297 /* our own tracking of ring head and tail */
298 u32 cpu_ring_head
[I915_NUM_RINGS
];
299 u32 cpu_ring_tail
[I915_NUM_RINGS
];
300 u32 error
; /* gen6+ */
301 u32 err_int
; /* gen7 */
302 u32 bbstate
[I915_NUM_RINGS
];
303 u32 instpm
[I915_NUM_RINGS
];
304 u32 instps
[I915_NUM_RINGS
];
305 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
306 u32 seqno
[I915_NUM_RINGS
];
308 u32 fault_reg
[I915_NUM_RINGS
];
310 u32 faddr
[I915_NUM_RINGS
];
311 u64 fence
[I915_MAX_NUM_FENCES
];
313 struct drm_i915_error_ring
{
314 struct drm_i915_error_object
{
318 } *ringbuffer
, *batchbuffer
, *ctx
;
319 struct drm_i915_error_request
{
325 } ring
[I915_NUM_RINGS
];
326 struct drm_i915_error_buffer
{
333 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
340 } **active_bo
, **pinned_bo
;
341 u32
*active_bo_count
, *pinned_bo_count
;
342 struct intel_overlay_error_state
*overlay
;
343 struct intel_display_error_state
*display
;
344 int hangcheck_score
[I915_NUM_RINGS
];
345 enum intel_ring_hangcheck_action hangcheck_action
[I915_NUM_RINGS
];
348 struct intel_crtc_config
;
353 struct drm_i915_display_funcs
{
354 bool (*fbc_enabled
)(struct drm_device
*dev
);
355 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
356 void (*disable_fbc
)(struct drm_device
*dev
);
357 int (*get_display_clock_speed
)(struct drm_device
*dev
);
358 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
360 * find_dpll() - Find the best values for the PLL
361 * @limit: limits for the PLL
362 * @crtc: current CRTC
363 * @target: target frequency in kHz
364 * @refclk: reference clock frequency in kHz
365 * @match_clock: if provided, @best_clock P divider must
366 * match the P divider from @match_clock
367 * used for LVDS downclocking
368 * @best_clock: best PLL values found
370 * Returns true on success, false on failure.
372 bool (*find_dpll
)(const struct intel_limit
*limit
,
373 struct drm_crtc
*crtc
,
374 int target
, int refclk
,
375 struct dpll
*match_clock
,
376 struct dpll
*best_clock
);
377 void (*update_wm
)(struct drm_crtc
*crtc
);
378 void (*update_sprite_wm
)(struct drm_plane
*plane
,
379 struct drm_crtc
*crtc
,
380 uint32_t sprite_width
, int pixel_size
,
381 bool enable
, bool scaled
);
382 void (*modeset_global_resources
)(struct drm_device
*dev
);
383 /* Returns the active state of the crtc, and if the crtc is active,
384 * fills out the pipe-config with the hw state. */
385 bool (*get_pipe_config
)(struct intel_crtc
*,
386 struct intel_crtc_config
*);
387 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
389 struct drm_framebuffer
*old_fb
);
390 void (*crtc_enable
)(struct drm_crtc
*crtc
);
391 void (*crtc_disable
)(struct drm_crtc
*crtc
);
392 void (*off
)(struct drm_crtc
*crtc
);
393 void (*write_eld
)(struct drm_connector
*connector
,
394 struct drm_crtc
*crtc
,
395 struct drm_display_mode
*mode
);
396 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
397 void (*init_clock_gating
)(struct drm_device
*dev
);
398 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
399 struct drm_framebuffer
*fb
,
400 struct drm_i915_gem_object
*obj
,
402 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
404 void (*hpd_irq_setup
)(struct drm_device
*dev
);
405 /* clock updates for mode set */
407 /* render clock increase/decrease */
408 /* display clock increase/decrease */
409 /* pll clock increase/decrease */
412 struct intel_uncore_funcs
{
413 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
414 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
416 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
417 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
418 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
419 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
421 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
422 uint8_t val
, bool trace
);
423 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
424 uint16_t val
, bool trace
);
425 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
426 uint32_t val
, bool trace
);
427 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
428 uint64_t val
, bool trace
);
431 struct intel_uncore
{
432 spinlock_t lock
; /** lock is also taken in irq contexts. */
434 struct intel_uncore_funcs funcs
;
437 unsigned forcewake_count
;
439 struct delayed_work force_wake_work
;
442 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
443 func(is_mobile) sep \
446 func(is_i945gm) sep \
448 func(need_gfx_hws) sep \
450 func(is_pineview) sep \
451 func(is_broadwater) sep \
452 func(is_crestline) sep \
453 func(is_ivybridge) sep \
454 func(is_valleyview) sep \
455 func(is_haswell) sep \
456 func(is_preliminary) sep \
458 func(has_pipe_cxsr) sep \
459 func(has_hotplug) sep \
460 func(cursor_needs_physical) sep \
461 func(has_overlay) sep \
462 func(overlay_needs_physical) sep \
463 func(supports_tv) sep \
468 #define DEFINE_FLAG(name) u8 name:1
469 #define SEP_SEMICOLON ;
471 struct intel_device_info
{
472 u32 display_mmio_offset
;
475 u8 ring_mask
; /* Rings supported by the HW */
476 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
482 enum i915_cache_level
{
484 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
485 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
486 caches, eg sampler/render caches, and the
487 large Last-Level-Cache. LLC is coherent with
488 the CPU, but L3 is only visible to the GPU. */
489 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
492 typedef uint32_t gen6_gtt_pte_t
;
494 struct i915_address_space
{
496 struct drm_device
*dev
;
497 struct list_head global_link
;
498 unsigned long start
; /* Start offset always 0 for dri2 */
499 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
507 * List of objects currently involved in rendering.
509 * Includes buffers having the contents of their GPU caches
510 * flushed, not necessarily primitives. last_rendering_seqno
511 * represents when the rendering involved will be completed.
513 * A reference is held on the buffer while on this list.
515 struct list_head active_list
;
518 * LRU list of objects which are not in the ringbuffer and
519 * are ready to unbind, but are still in the GTT.
521 * last_rendering_seqno is 0 while an object is in this list.
523 * A reference is not held on the buffer while on this list,
524 * as merely being GTT-bound shouldn't prevent its being
525 * freed, and we'll pull it off the list in the free path.
527 struct list_head inactive_list
;
529 /* FIXME: Need a more generic return type */
530 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
531 enum i915_cache_level level
,
532 bool valid
); /* Create a valid PTE */
533 void (*clear_range
)(struct i915_address_space
*vm
,
534 unsigned int first_entry
,
535 unsigned int num_entries
,
537 void (*insert_entries
)(struct i915_address_space
*vm
,
539 unsigned int first_entry
,
540 enum i915_cache_level cache_level
);
541 void (*cleanup
)(struct i915_address_space
*vm
);
544 /* The Graphics Translation Table is the way in which GEN hardware translates a
545 * Graphics Virtual Address into a Physical Address. In addition to the normal
546 * collateral associated with any va->pa translations GEN hardware also has a
547 * portion of the GTT which can be mapped by the CPU and remain both coherent
548 * and correct (in cases like swizzling). That region is referred to as GMADR in
552 struct i915_address_space base
;
553 size_t stolen_size
; /* Total size of stolen memory */
555 unsigned long mappable_end
; /* End offset that we can CPU map */
556 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
557 phys_addr_t mappable_base
; /* PA of our GMADR */
559 /** "Graphics Stolen Memory" holds the global PTEs */
567 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
568 size_t *stolen
, phys_addr_t
*mappable_base
,
569 unsigned long *mappable_end
);
571 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
573 struct i915_hw_ppgtt
{
574 struct i915_address_space base
;
575 unsigned num_pd_entries
;
576 struct page
**pt_pages
;
578 dma_addr_t
*pt_dma_addr
;
580 int (*enable
)(struct drm_device
*dev
);
584 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
585 * VMA's presence cannot be guaranteed before binding, or after unbinding the
586 * object into/from the address space.
588 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
589 * will always be <= an objects lifetime. So object refcounting should cover us.
592 struct drm_mm_node node
;
593 struct drm_i915_gem_object
*obj
;
594 struct i915_address_space
*vm
;
596 /** This object's place on the active/inactive lists */
597 struct list_head mm_list
;
599 struct list_head vma_link
; /* Link in the object's VMA list */
601 /** This vma's place in the batchbuffer or on the eviction list */
602 struct list_head exec_list
;
605 * Used for performing relocations during execbuffer insertion.
607 struct hlist_node exec_node
;
608 unsigned long exec_handle
;
609 struct drm_i915_gem_exec_object2
*exec_entry
;
613 struct i915_ctx_hang_stats
{
614 /* This context had batch pending when hang was declared */
615 unsigned batch_pending
;
617 /* This context had batch active when hang was declared */
618 unsigned batch_active
;
620 /* Time when this context was last blamed for a GPU reset */
621 unsigned long guilty_ts
;
623 /* This context is banned to submit more work */
627 /* This must match up with the value previously used for execbuf2.rsvd1. */
628 #define DEFAULT_CONTEXT_ID 0
629 struct i915_hw_context
{
634 struct drm_i915_file_private
*file_priv
;
635 struct intel_ring_buffer
*ring
;
636 struct drm_i915_gem_object
*obj
;
637 struct i915_ctx_hang_stats hang_stats
;
639 struct list_head link
;
648 struct drm_mm_node
*compressed_fb
;
649 struct drm_mm_node
*compressed_llb
;
651 struct intel_fbc_work
{
652 struct delayed_work work
;
653 struct drm_crtc
*crtc
;
654 struct drm_framebuffer
*fb
;
659 FBC_OK
, /* FBC is enabled */
660 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
661 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
662 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
663 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
664 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
665 FBC_BAD_PLANE
, /* fbc not supported on plane */
666 FBC_NOT_TILED
, /* buffer not tiled */
667 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
669 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
679 PCH_NONE
= 0, /* No PCH present */
680 PCH_IBX
, /* Ibexpeak PCH */
681 PCH_CPT
, /* Cougarpoint PCH */
682 PCH_LPT
, /* Lynxpoint PCH */
686 enum intel_sbi_destination
{
691 #define QUIRK_PIPEA_FORCE (1<<0)
692 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
693 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
694 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
697 struct intel_fbc_work
;
700 struct i2c_adapter adapter
;
704 struct i2c_algo_bit_data bit_algo
;
705 struct drm_i915_private
*dev_priv
;
708 struct i915_suspend_saved_registers
{
729 u32 saveTRANS_HTOTAL_A
;
730 u32 saveTRANS_HBLANK_A
;
731 u32 saveTRANS_HSYNC_A
;
732 u32 saveTRANS_VTOTAL_A
;
733 u32 saveTRANS_VBLANK_A
;
734 u32 saveTRANS_VSYNC_A
;
742 u32 savePFIT_PGM_RATIOS
;
743 u32 saveBLC_HIST_CTL
;
745 u32 saveBLC_PWM_CTL2
;
746 u32 saveBLC_CPU_PWM_CTL
;
747 u32 saveBLC_CPU_PWM_CTL2
;
760 u32 saveTRANS_HTOTAL_B
;
761 u32 saveTRANS_HBLANK_B
;
762 u32 saveTRANS_HSYNC_B
;
763 u32 saveTRANS_VTOTAL_B
;
764 u32 saveTRANS_VBLANK_B
;
765 u32 saveTRANS_VSYNC_B
;
779 u32 savePP_ON_DELAYS
;
780 u32 savePP_OFF_DELAYS
;
788 u32 savePFIT_CONTROL
;
789 u32 save_palette_a
[256];
790 u32 save_palette_b
[256];
791 u32 saveDPFC_CB_BASE
;
792 u32 saveFBC_CFB_BASE
;
795 u32 saveFBC_CONTROL2
;
805 u32 saveCACHE_MODE_0
;
806 u32 saveMI_ARB_STATE
;
817 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
828 u32 savePIPEA_GMCH_DATA_M
;
829 u32 savePIPEB_GMCH_DATA_M
;
830 u32 savePIPEA_GMCH_DATA_N
;
831 u32 savePIPEB_GMCH_DATA_N
;
832 u32 savePIPEA_DP_LINK_M
;
833 u32 savePIPEB_DP_LINK_M
;
834 u32 savePIPEA_DP_LINK_N
;
835 u32 savePIPEB_DP_LINK_N
;
846 u32 savePCH_DREF_CONTROL
;
847 u32 saveDISP_ARB_CTL
;
848 u32 savePIPEA_DATA_M1
;
849 u32 savePIPEA_DATA_N1
;
850 u32 savePIPEA_LINK_M1
;
851 u32 savePIPEA_LINK_N1
;
852 u32 savePIPEB_DATA_M1
;
853 u32 savePIPEB_DATA_N1
;
854 u32 savePIPEB_LINK_M1
;
855 u32 savePIPEB_LINK_N1
;
856 u32 saveMCHBAR_RENDER_STANDBY
;
857 u32 savePCH_PORT_HOTPLUG
;
860 struct intel_gen6_power_mgmt
{
861 /* work and pm_iir are protected by dev_priv->irq_lock */
862 struct work_struct work
;
865 /* The below variables an all the rps hw state are protected by
866 * dev->struct mutext. */
876 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
879 struct delayed_work delayed_resume_work
;
882 * Protects RPS/RC6 register access and PCU communication.
883 * Must be taken after struct_mutex if nested.
885 struct mutex hw_lock
;
888 /* defined intel_pm.c */
889 extern spinlock_t mchdev_lock
;
891 struct intel_ilk_power_mgmt
{
899 unsigned long last_time1
;
900 unsigned long chipset_power
;
902 struct timespec last_time2
;
903 unsigned long gfx_power
;
909 struct drm_i915_gem_object
*pwrctx
;
910 struct drm_i915_gem_object
*renderctx
;
913 /* Power well structure for haswell */
914 struct i915_power_well
{
915 /* power well enable/disable usage count */
919 #define I915_MAX_POWER_WELLS 1
921 struct i915_power_domains
{
923 * Power wells needed for initialization at driver init and suspend
924 * time are on. They are kept on until after the first modeset.
929 struct i915_power_well power_wells
[I915_MAX_POWER_WELLS
];
932 struct i915_dri1_state
{
933 unsigned allow_batchbuffer
: 1;
934 u32 __iomem
*gfx_hws_cpu_addr
;
945 struct i915_ums_state
{
947 * Flag if the X Server, and thus DRM, is not currently in
948 * control of the device.
950 * This is set between LeaveVT and EnterVT. It needs to be
951 * replaced with a semaphore. It also needs to be
952 * transitioned away from for kernel modesetting.
957 #define MAX_L3_SLICES 2
958 struct intel_l3_parity
{
959 u32
*remap_info
[MAX_L3_SLICES
];
960 struct work_struct error_work
;
965 /** Memory allocator for GTT stolen memory */
966 struct drm_mm stolen
;
967 /** List of all objects in gtt_space. Used to restore gtt
968 * mappings on resume */
969 struct list_head bound_list
;
971 * List of objects which are not bound to the GTT (thus
972 * are idle and not used by the GPU) but still have
973 * (presumably uncached) pages still attached.
975 struct list_head unbound_list
;
977 /** Usable portion of the GTT for GEM */
978 unsigned long stolen_base
; /* limited to low memory (32-bit) */
980 /** PPGTT used for aliasing the PPGTT with the GTT */
981 struct i915_hw_ppgtt
*aliasing_ppgtt
;
983 struct shrinker inactive_shrinker
;
984 bool shrinker_no_lock_stealing
;
986 /** LRU list of objects with fence regs on them. */
987 struct list_head fence_list
;
990 * We leave the user IRQ off as much as possible,
991 * but this means that requests will finish and never
992 * be retired once the system goes idle. Set a timer to
993 * fire periodically while the ring is running. When it
994 * fires, go retire requests.
996 struct delayed_work retire_work
;
999 * When we detect an idle GPU, we want to turn on
1000 * powersaving features. So once we see that there
1001 * are no more requests outstanding and no more
1002 * arrive within a small period of time, we fire
1003 * off the idle_work.
1005 struct delayed_work idle_work
;
1008 * Are we in a non-interruptible section of code like
1013 /** Bit 6 swizzling required for X tiling */
1014 uint32_t bit_6_swizzle_x
;
1015 /** Bit 6 swizzling required for Y tiling */
1016 uint32_t bit_6_swizzle_y
;
1018 /* storage for physical objects */
1019 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
1021 /* accounting, useful for userland debugging */
1022 spinlock_t object_stat_lock
;
1023 size_t object_memory
;
1027 struct drm_i915_error_state_buf
{
1036 struct i915_error_state_file_priv
{
1037 struct drm_device
*dev
;
1038 struct drm_i915_error_state
*error
;
1041 struct i915_gpu_error
{
1042 /* For hangcheck timer */
1043 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1044 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1045 /* Hang gpu twice in this window and your context gets banned */
1046 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1048 struct timer_list hangcheck_timer
;
1050 /* For reset and error_state handling. */
1052 /* Protected by the above dev->gpu_error.lock. */
1053 struct drm_i915_error_state
*first_error
;
1054 struct work_struct work
;
1057 unsigned long missed_irq_rings
;
1060 * State variable and reset counter controlling the reset flow
1062 * Upper bits are for the reset counter. This counter is used by the
1063 * wait_seqno code to race-free noticed that a reset event happened and
1064 * that it needs to restart the entire ioctl (since most likely the
1065 * seqno it waited for won't ever signal anytime soon).
1067 * This is important for lock-free wait paths, where no contended lock
1068 * naturally enforces the correct ordering between the bail-out of the
1069 * waiter and the gpu reset work code.
1071 * Lowest bit controls the reset state machine: Set means a reset is in
1072 * progress. This state will (presuming we don't have any bugs) decay
1073 * into either unset (successful reset) or the special WEDGED value (hw
1074 * terminally sour). All waiters on the reset_queue will be woken when
1077 atomic_t reset_counter
;
1080 * Special values/flags for reset_counter
1082 * Note that the code relies on
1083 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1086 #define I915_RESET_IN_PROGRESS_FLAG 1
1087 #define I915_WEDGED 0xffffffff
1090 * Waitqueue to signal when the reset has completed. Used by clients
1091 * that wait for dev_priv->mm.wedged to settle.
1093 wait_queue_head_t reset_queue
;
1095 /* For gpu hang simulation. */
1096 unsigned int stop_rings
;
1098 /* For missed irq/seqno simulation. */
1099 unsigned int test_irq_rings
;
1102 enum modeset_restore
{
1103 MODESET_ON_LID_OPEN
,
1108 struct ddi_vbt_port_info
{
1109 uint8_t hdmi_level_shift
;
1111 uint8_t supports_dvi
:1;
1112 uint8_t supports_hdmi
:1;
1113 uint8_t supports_dp
:1;
1116 struct intel_vbt_data
{
1117 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1118 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1121 unsigned int int_tv_support
:1;
1122 unsigned int lvds_dither
:1;
1123 unsigned int lvds_vbt
:1;
1124 unsigned int int_crt_support
:1;
1125 unsigned int lvds_use_ssc
:1;
1126 unsigned int display_clock_mode
:1;
1127 unsigned int fdi_rx_polarity_inverted
:1;
1129 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1134 int edp_preemphasis
;
1136 bool edp_initialized
;
1139 struct edp_power_seq edp_pps
;
1149 union child_device_config
*child_dev
;
1151 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1154 enum intel_ddb_partitioning
{
1156 INTEL_DDB_PART_5_6
, /* IVB+ */
1159 struct intel_wm_level
{
1167 struct hsw_wm_values
{
1168 uint32_t wm_pipe
[3];
1170 uint32_t wm_lp_spr
[3];
1171 uint32_t wm_linetime
[3];
1173 enum intel_ddb_partitioning partitioning
;
1177 * This struct tracks the state needed for the Package C8+ feature.
1179 * Package states C8 and deeper are really deep PC states that can only be
1180 * reached when all the devices on the system allow it, so even if the graphics
1181 * device allows PC8+, it doesn't mean the system will actually get to these
1184 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1185 * is disabled and the GPU is idle. When these conditions are met, we manually
1186 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1189 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1190 * the state of some registers, so when we come back from PC8+ we need to
1191 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1192 * need to take care of the registers kept by RC6.
1194 * The interrupt disabling is part of the requirements. We can only leave the
1195 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1196 * can lock the machine.
1198 * Ideally every piece of our code that needs PC8+ disabled would call
1199 * hsw_disable_package_c8, which would increment disable_count and prevent the
1200 * system from reaching PC8+. But we don't have a symmetric way to do this for
1201 * everything, so we have the requirements_met and gpu_idle variables. When we
1202 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1203 * increase it in the opposite case. The requirements_met variable is true when
1204 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1205 * variable is true when the GPU is idle.
1207 * In addition to everything, we only actually enable PC8+ if disable_count
1208 * stays at zero for at least some seconds. This is implemented with the
1209 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1210 * consecutive times when all screens are disabled and some background app
1211 * queries the state of our connectors, or we have some application constantly
1212 * waking up to use the GPU. Only after the enable_work function actually
1213 * enables PC8+ the "enable" variable will become true, which means that it can
1214 * be false even if disable_count is 0.
1216 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1217 * goes back to false exactly before we reenable the IRQs. We use this variable
1218 * to check if someone is trying to enable/disable IRQs while they're supposed
1219 * to be disabled. This shouldn't happen and we'll print some error messages in
1220 * case it happens, but if it actually happens we'll also update the variables
1221 * inside struct regsave so when we restore the IRQs they will contain the
1222 * latest expected values.
1224 * For more, read "Display Sequences for Package C8" on our documentation.
1226 struct i915_package_c8
{
1227 bool requirements_met
;
1230 /* Only true after the delayed work task actually enables it. */
1234 struct delayed_work enable_work
;
1241 uint32_t gen6_pmimr
;
1245 enum intel_pipe_crc_source
{
1246 INTEL_PIPE_CRC_SOURCE_NONE
,
1247 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1248 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1249 INTEL_PIPE_CRC_SOURCE_PF
,
1250 INTEL_PIPE_CRC_SOURCE_PIPE
,
1251 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1252 INTEL_PIPE_CRC_SOURCE_TV
,
1253 INTEL_PIPE_CRC_SOURCE_DP_B
,
1254 INTEL_PIPE_CRC_SOURCE_DP_C
,
1255 INTEL_PIPE_CRC_SOURCE_DP_D
,
1256 INTEL_PIPE_CRC_SOURCE_AUTO
,
1257 INTEL_PIPE_CRC_SOURCE_MAX
,
1260 struct intel_pipe_crc_entry
{
1265 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1266 struct intel_pipe_crc
{
1268 bool opened
; /* exclusive access to the result file */
1269 struct intel_pipe_crc_entry
*entries
;
1270 enum intel_pipe_crc_source source
;
1272 wait_queue_head_t wq
;
1275 typedef struct drm_i915_private
{
1276 struct drm_device
*dev
;
1277 struct kmem_cache
*slab
;
1279 const struct intel_device_info
*info
;
1281 int relative_constants_mode
;
1285 struct intel_uncore uncore
;
1287 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1290 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1291 * controller on different i2c buses. */
1292 struct mutex gmbus_mutex
;
1295 * Base address of the gmbus and gpio block.
1297 uint32_t gpio_mmio_base
;
1299 wait_queue_head_t gmbus_wait_queue
;
1301 struct pci_dev
*bridge_dev
;
1302 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1303 uint32_t last_seqno
, next_seqno
;
1305 drm_dma_handle_t
*status_page_dmah
;
1306 struct resource mch_res
;
1308 atomic_t irq_received
;
1310 /* protects the irq masks */
1311 spinlock_t irq_lock
;
1313 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1314 struct pm_qos_request pm_qos
;
1316 /* DPIO indirect register protection */
1317 struct mutex dpio_lock
;
1319 /** Cached value of IMR to avoid reads in updating the bitfield */
1324 struct work_struct hotplug_work
;
1325 bool enable_hotplug_processing
;
1327 unsigned long hpd_last_jiffies
;
1332 HPD_MARK_DISABLED
= 2
1334 } hpd_stats
[HPD_NUM_PINS
];
1336 struct timer_list hotplug_reenable_timer
;
1340 struct i915_fbc fbc
;
1341 struct intel_opregion opregion
;
1342 struct intel_vbt_data vbt
;
1345 struct intel_overlay
*overlay
;
1346 unsigned int sprite_scaling_enabled
;
1352 spinlock_t lock
; /* bl registers and the above bl fields */
1353 struct backlight_device
*device
;
1357 bool no_aux_handshake
;
1359 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1360 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1361 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1363 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1366 * wq - Driver workqueue for GEM.
1368 * NOTE: Work items scheduled here are not allowed to grab any modeset
1369 * locks, for otherwise the flushing done in the pageflip code will
1370 * result in deadlocks.
1372 struct workqueue_struct
*wq
;
1374 /* Display functions */
1375 struct drm_i915_display_funcs display
;
1377 /* PCH chipset type */
1378 enum intel_pch pch_type
;
1379 unsigned short pch_id
;
1381 unsigned long quirks
;
1383 enum modeset_restore modeset_restore
;
1384 struct mutex modeset_restore_lock
;
1386 struct list_head vm_list
; /* Global list of all address spaces */
1387 struct i915_gtt gtt
; /* VMA representing the global address space */
1389 struct i915_gem_mm mm
;
1391 /* Kernel Modesetting */
1393 struct sdvo_device_mapping sdvo_mappings
[2];
1395 struct drm_crtc
*plane_to_crtc_mapping
[3];
1396 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1397 wait_queue_head_t pending_flip_queue
;
1399 #ifdef CONFIG_DEBUG_FS
1400 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1403 int num_shared_dpll
;
1404 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1405 struct intel_ddi_plls ddi_plls
;
1407 /* Reclocking support */
1408 bool render_reclock_avail
;
1409 bool lvds_downclock_avail
;
1410 /* indicates the reduced downclock for LVDS*/
1414 bool mchbar_need_disable
;
1416 struct intel_l3_parity l3_parity
;
1418 /* Cannot be determined by PCIID. You must always read a register. */
1421 /* gen6+ rps state */
1422 struct intel_gen6_power_mgmt rps
;
1424 /* ilk-only ips/rps state. Everything in here is protected by the global
1425 * mchdev_lock in intel_pm.c */
1426 struct intel_ilk_power_mgmt ips
;
1428 struct i915_power_domains power_domains
;
1430 struct i915_psr psr
;
1432 struct i915_gpu_error gpu_error
;
1434 struct drm_i915_gem_object
*vlv_pctx
;
1436 #ifdef CONFIG_DRM_I915_FBDEV
1437 /* list of fbdev register on this device */
1438 struct intel_fbdev
*fbdev
;
1442 * The console may be contended at resume, but we don't
1443 * want it to block on it.
1445 struct work_struct console_resume_work
;
1447 struct drm_property
*broadcast_rgb_property
;
1448 struct drm_property
*force_audio_property
;
1450 uint32_t hw_context_size
;
1451 struct list_head context_list
;
1455 struct i915_suspend_saved_registers regfile
;
1459 * Raw watermark latency values:
1460 * in 0.1us units for WM0,
1461 * in 0.5us units for WM1+.
1464 uint16_t pri_latency
[5];
1466 uint16_t spr_latency
[5];
1468 uint16_t cur_latency
[5];
1470 /* current hardware state */
1471 struct hsw_wm_values hw
;
1474 struct i915_package_c8 pc8
;
1476 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1478 struct i915_dri1_state dri1
;
1479 /* Old ums support infrastructure, same warning applies. */
1480 struct i915_ums_state ums
;
1481 } drm_i915_private_t
;
1483 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1485 return dev
->dev_private
;
1488 /* Iterate over initialised rings */
1489 #define for_each_ring(ring__, dev_priv__, i__) \
1490 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1491 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1493 enum hdmi_force_audio
{
1494 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1495 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1496 HDMI_AUDIO_AUTO
, /* trust EDID */
1497 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1500 #define I915_GTT_OFFSET_NONE ((u32)-1)
1502 struct drm_i915_gem_object_ops
{
1503 /* Interface between the GEM object and its backing storage.
1504 * get_pages() is called once prior to the use of the associated set
1505 * of pages before to binding them into the GTT, and put_pages() is
1506 * called after we no longer need them. As we expect there to be
1507 * associated cost with migrating pages between the backing storage
1508 * and making them available for the GPU (e.g. clflush), we may hold
1509 * onto the pages after they are no longer referenced by the GPU
1510 * in case they may be used again shortly (for example migrating the
1511 * pages to a different memory domain within the GTT). put_pages()
1512 * will therefore most likely be called when the object itself is
1513 * being released or under memory pressure (where we attempt to
1514 * reap pages for the shrinker).
1516 int (*get_pages
)(struct drm_i915_gem_object
*);
1517 void (*put_pages
)(struct drm_i915_gem_object
*);
1520 struct drm_i915_gem_object
{
1521 struct drm_gem_object base
;
1523 const struct drm_i915_gem_object_ops
*ops
;
1525 /** List of VMAs backed by this object */
1526 struct list_head vma_list
;
1528 /** Stolen memory for this object, instead of being backed by shmem. */
1529 struct drm_mm_node
*stolen
;
1530 struct list_head global_list
;
1532 struct list_head ring_list
;
1533 /** Used in execbuf to temporarily hold a ref */
1534 struct list_head obj_exec_link
;
1537 * This is set if the object is on the active lists (has pending
1538 * rendering and so a non-zero seqno), and is not set if it i s on
1539 * inactive (ready to be unbound) list.
1541 unsigned int active
:1;
1544 * This is set if the object has been written to since last bound
1547 unsigned int dirty
:1;
1550 * Fence register bits (if any) for this object. Will be set
1551 * as needed when mapped into the GTT.
1552 * Protected by dev->struct_mutex.
1554 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1557 * Advice: are the backing pages purgeable?
1559 unsigned int madv
:2;
1562 * Current tiling mode for the object.
1564 unsigned int tiling_mode
:2;
1566 * Whether the tiling parameters for the currently associated fence
1567 * register have changed. Note that for the purposes of tracking
1568 * tiling changes we also treat the unfenced register, the register
1569 * slot that the object occupies whilst it executes a fenced
1570 * command (such as BLT on gen2/3), as a "fence".
1572 unsigned int fence_dirty
:1;
1574 /** How many users have pinned this object in GTT space. The following
1575 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1576 * (via user_pin_count), execbuffer (objects are not allowed multiple
1577 * times for the same batchbuffer), and the framebuffer code. When
1578 * switching/pageflipping, the framebuffer code has at most two buffers
1581 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1582 * bits with absolutely no headroom. So use 4 bits. */
1583 unsigned int pin_count
:4;
1584 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1587 * Is the object at the current location in the gtt mappable and
1588 * fenceable? Used to avoid costly recalculations.
1590 unsigned int map_and_fenceable
:1;
1593 * Whether the current gtt mapping needs to be mappable (and isn't just
1594 * mappable by accident). Track pin and fault separate for a more
1595 * accurate mappable working set.
1597 unsigned int fault_mappable
:1;
1598 unsigned int pin_mappable
:1;
1599 unsigned int pin_display
:1;
1602 * Is the GPU currently using a fence to access this buffer,
1604 unsigned int pending_fenced_gpu_access
:1;
1605 unsigned int fenced_gpu_access
:1;
1607 unsigned int cache_level
:3;
1609 unsigned int has_aliasing_ppgtt_mapping
:1;
1610 unsigned int has_global_gtt_mapping
:1;
1611 unsigned int has_dma_mapping
:1;
1613 struct sg_table
*pages
;
1614 int pages_pin_count
;
1616 /* prime dma-buf support */
1617 void *dma_buf_vmapping
;
1620 struct intel_ring_buffer
*ring
;
1622 /** Breadcrumb of last rendering to the buffer. */
1623 uint32_t last_read_seqno
;
1624 uint32_t last_write_seqno
;
1625 /** Breadcrumb of last fenced GPU access to the buffer. */
1626 uint32_t last_fenced_seqno
;
1628 /** Current tiling stride for the object, if it's tiled. */
1631 /** References from framebuffers, locks out tiling changes. */
1632 unsigned long framebuffer_references
;
1634 /** Record of address bit 17 of each page at last unbind. */
1635 unsigned long *bit_17
;
1637 /** User space pin count and filp owning the pin */
1638 unsigned long user_pin_count
;
1639 struct drm_file
*pin_filp
;
1641 /** for phy allocated objects */
1642 struct drm_i915_gem_phys_object
*phys_obj
;
1644 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1646 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1649 * Request queue structure.
1651 * The request queue allows us to note sequence numbers that have been emitted
1652 * and may be associated with active buffers to be retired.
1654 * By keeping this list, we can avoid having to do questionable
1655 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1656 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1658 struct drm_i915_gem_request
{
1659 /** On Which ring this request was generated */
1660 struct intel_ring_buffer
*ring
;
1662 /** GEM sequence number associated with this request. */
1665 /** Position in the ringbuffer of the start of the request */
1668 /** Position in the ringbuffer of the end of the request */
1671 /** Context related to this request */
1672 struct i915_hw_context
*ctx
;
1674 /** Batch buffer related to this request if any */
1675 struct drm_i915_gem_object
*batch_obj
;
1677 /** Time at which this request was emitted, in jiffies. */
1678 unsigned long emitted_jiffies
;
1680 /** global list entry for this request */
1681 struct list_head list
;
1683 struct drm_i915_file_private
*file_priv
;
1684 /** file_priv list entry for this request */
1685 struct list_head client_list
;
1688 struct drm_i915_file_private
{
1689 struct drm_i915_private
*dev_priv
;
1693 struct list_head request_list
;
1694 struct delayed_work idle_work
;
1696 struct idr context_idr
;
1698 struct i915_ctx_hang_stats hang_stats
;
1699 atomic_t rps_wait_boost
;
1702 #define INTEL_INFO(dev) (to_i915(dev)->info)
1704 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1705 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1706 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1707 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1708 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1709 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1710 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1711 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1712 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1713 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1714 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1715 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1716 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1717 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1718 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1719 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1720 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1721 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1722 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1723 (dev)->pdev->device == 0x0152 || \
1724 (dev)->pdev->device == 0x015a)
1725 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1726 (dev)->pdev->device == 0x0106 || \
1727 (dev)->pdev->device == 0x010A)
1728 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1729 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1730 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1731 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1732 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1733 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1734 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1735 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1736 ((dev)->pdev->device & 0x00F0) == 0x0020)
1737 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1740 * The genX designation typically refers to the render engine, so render
1741 * capability related checks should use IS_GEN, while display and other checks
1742 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1745 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1746 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1747 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1748 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1749 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1750 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1752 #define RENDER_RING (1<<RCS)
1753 #define BSD_RING (1<<VCS)
1754 #define BLT_RING (1<<BCS)
1755 #define VEBOX_RING (1<<VECS)
1756 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1757 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1758 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1759 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1760 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1761 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1763 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1764 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1766 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1767 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1769 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1770 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1772 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1773 * rows, which changed the alignment requirements and fence programming.
1775 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1777 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1778 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1779 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1780 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1781 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1783 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1784 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1785 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1787 #define HAS_IPS(dev) (IS_ULT(dev))
1789 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1790 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1791 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1792 #define HAS_PSR(dev) (IS_HASWELL(dev))
1794 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1795 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1796 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1797 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1798 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1799 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1801 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1802 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1803 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1804 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1805 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1806 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1808 /* DPF == dynamic parity feature */
1809 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1810 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1812 #define GT_FREQUENCY_MULTIPLIER 50
1814 #include "i915_trace.h"
1816 extern const struct drm_ioctl_desc i915_ioctls
[];
1817 extern int i915_max_ioctl
;
1818 extern unsigned int i915_fbpercrtc __always_unused
;
1819 extern int i915_panel_ignore_lid __read_mostly
;
1820 extern unsigned int i915_powersave __read_mostly
;
1821 extern int i915_semaphores __read_mostly
;
1822 extern unsigned int i915_lvds_downclock __read_mostly
;
1823 extern int i915_lvds_channel_mode __read_mostly
;
1824 extern int i915_panel_use_ssc __read_mostly
;
1825 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1826 extern int i915_enable_rc6 __read_mostly
;
1827 extern int i915_enable_fbc __read_mostly
;
1828 extern bool i915_enable_hangcheck __read_mostly
;
1829 extern int i915_enable_ppgtt __read_mostly
;
1830 extern int i915_enable_psr __read_mostly
;
1831 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1832 extern int i915_disable_power_well __read_mostly
;
1833 extern int i915_enable_ips __read_mostly
;
1834 extern bool i915_fastboot __read_mostly
;
1835 extern int i915_enable_pc8 __read_mostly
;
1836 extern int i915_pc8_timeout __read_mostly
;
1837 extern bool i915_prefault_disable __read_mostly
;
1839 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1840 extern int i915_resume(struct drm_device
*dev
);
1841 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1842 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1845 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1846 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1847 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1848 extern int i915_driver_unload(struct drm_device
*);
1849 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1850 extern void i915_driver_lastclose(struct drm_device
* dev
);
1851 extern void i915_driver_preclose(struct drm_device
*dev
,
1852 struct drm_file
*file_priv
);
1853 extern void i915_driver_postclose(struct drm_device
*dev
,
1854 struct drm_file
*file_priv
);
1855 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1856 #ifdef CONFIG_COMPAT
1857 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1860 extern int i915_emit_box(struct drm_device
*dev
,
1861 struct drm_clip_rect
*box
,
1863 extern int intel_gpu_reset(struct drm_device
*dev
);
1864 extern int i915_reset(struct drm_device
*dev
);
1865 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1866 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1867 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1868 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1870 extern void intel_console_resume(struct work_struct
*work
);
1873 void i915_queue_hangcheck(struct drm_device
*dev
);
1874 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1876 extern void intel_irq_init(struct drm_device
*dev
);
1877 extern void intel_pm_init(struct drm_device
*dev
);
1878 extern void intel_hpd_init(struct drm_device
*dev
);
1879 extern void intel_pm_init(struct drm_device
*dev
);
1881 extern void intel_uncore_sanitize(struct drm_device
*dev
);
1882 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
1883 extern void intel_uncore_init(struct drm_device
*dev
);
1884 extern void intel_uncore_clear_errors(struct drm_device
*dev
);
1885 extern void intel_uncore_check_errors(struct drm_device
*dev
);
1886 extern void intel_uncore_fini(struct drm_device
*dev
);
1889 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
, u32 mask
);
1892 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, enum pipe pipe
, u32 mask
);
1895 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1896 struct drm_file
*file_priv
);
1897 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1898 struct drm_file
*file_priv
);
1899 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1900 struct drm_file
*file_priv
);
1901 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1902 struct drm_file
*file_priv
);
1903 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1904 struct drm_file
*file_priv
);
1905 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1906 struct drm_file
*file_priv
);
1907 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1908 struct drm_file
*file_priv
);
1909 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1910 struct drm_file
*file_priv
);
1911 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1912 struct drm_file
*file_priv
);
1913 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1914 struct drm_file
*file_priv
);
1915 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1916 struct drm_file
*file_priv
);
1917 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1918 struct drm_file
*file_priv
);
1919 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1920 struct drm_file
*file_priv
);
1921 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1922 struct drm_file
*file
);
1923 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1924 struct drm_file
*file
);
1925 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1926 struct drm_file
*file_priv
);
1927 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1928 struct drm_file
*file_priv
);
1929 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1930 struct drm_file
*file_priv
);
1931 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1932 struct drm_file
*file_priv
);
1933 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1934 struct drm_file
*file_priv
);
1935 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1936 struct drm_file
*file_priv
);
1937 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1938 struct drm_file
*file_priv
);
1939 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1940 struct drm_file
*file_priv
);
1941 void i915_gem_load(struct drm_device
*dev
);
1942 void *i915_gem_object_alloc(struct drm_device
*dev
);
1943 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1944 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1945 const struct drm_i915_gem_object_ops
*ops
);
1946 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1948 void i915_gem_free_object(struct drm_gem_object
*obj
);
1949 void i915_gem_vma_destroy(struct i915_vma
*vma
);
1951 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1952 struct i915_address_space
*vm
,
1954 bool map_and_fenceable
,
1956 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1957 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
1958 int __must_check
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
);
1959 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1960 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1961 void i915_gem_lastclose(struct drm_device
*dev
);
1963 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1964 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1966 struct sg_page_iter sg_iter
;
1968 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1969 return sg_page_iter_page(&sg_iter
);
1973 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1975 BUG_ON(obj
->pages
== NULL
);
1976 obj
->pages_pin_count
++;
1978 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1980 BUG_ON(obj
->pages_pin_count
== 0);
1981 obj
->pages_pin_count
--;
1984 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1985 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1986 struct intel_ring_buffer
*to
);
1987 void i915_vma_move_to_active(struct i915_vma
*vma
,
1988 struct intel_ring_buffer
*ring
);
1989 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1990 struct drm_device
*dev
,
1991 struct drm_mode_create_dumb
*args
);
1992 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1993 uint32_t handle
, uint64_t *offset
);
1995 * Returns true if seq1 is later than seq2.
1998 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2000 return (int32_t)(seq1
- seq2
) >= 0;
2003 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2004 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2005 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2006 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2009 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
2011 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2012 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2013 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
2020 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
2022 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2023 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2024 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
2025 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
2029 bool i915_gem_retire_requests(struct drm_device
*dev
);
2030 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
2031 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2032 bool interruptible
);
2033 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2035 return unlikely(atomic_read(&error
->reset_counter
)
2036 & I915_RESET_IN_PROGRESS_FLAG
);
2039 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2041 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
2044 void i915_gem_reset(struct drm_device
*dev
);
2045 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2046 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2047 int __must_check
i915_gem_init(struct drm_device
*dev
);
2048 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2049 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
);
2050 void i915_gem_init_swizzling(struct drm_device
*dev
);
2051 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2052 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2053 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2054 int __i915_add_request(struct intel_ring_buffer
*ring
,
2055 struct drm_file
*file
,
2056 struct drm_i915_gem_object
*batch_obj
,
2058 #define i915_add_request(ring, seqno) \
2059 __i915_add_request(ring, NULL, NULL, seqno)
2060 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
2062 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2064 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2067 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2069 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2071 struct intel_ring_buffer
*pipelined
);
2072 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2073 int i915_gem_attach_phys_object(struct drm_device
*dev
,
2074 struct drm_i915_gem_object
*obj
,
2077 void i915_gem_detach_phys_object(struct drm_device
*dev
,
2078 struct drm_i915_gem_object
*obj
);
2079 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
2080 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2081 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2084 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2086 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2087 int tiling_mode
, bool fenced
);
2089 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2090 enum i915_cache_level cache_level
);
2092 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2093 struct dma_buf
*dma_buf
);
2095 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2096 struct drm_gem_object
*gem_obj
, int flags
);
2098 void i915_gem_restore_fences(struct drm_device
*dev
);
2100 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2101 struct i915_address_space
*vm
);
2102 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2103 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2104 struct i915_address_space
*vm
);
2105 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2106 struct i915_address_space
*vm
);
2107 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2108 struct i915_address_space
*vm
);
2110 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2111 struct i915_address_space
*vm
);
2113 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2115 /* Some GGTT VM helpers */
2116 #define obj_to_ggtt(obj) \
2117 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2118 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2120 struct i915_address_space
*ggtt
=
2121 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2125 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2127 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2130 static inline unsigned long
2131 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2133 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2136 static inline unsigned long
2137 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2139 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2142 static inline int __must_check
2143 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2145 bool map_and_fenceable
,
2148 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
,
2149 map_and_fenceable
, nonblocking
);
2152 /* i915_gem_context.c */
2153 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2154 void i915_gem_context_fini(struct drm_device
*dev
);
2155 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2156 int i915_switch_context(struct intel_ring_buffer
*ring
,
2157 struct drm_file
*file
, int to_id
);
2158 void i915_gem_context_free(struct kref
*ctx_ref
);
2159 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
2161 kref_get(&ctx
->ref
);
2164 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
2166 kref_put(&ctx
->ref
, i915_gem_context_free
);
2169 struct i915_ctx_hang_stats
* __must_check
2170 i915_gem_context_get_hang_stats(struct drm_device
*dev
,
2171 struct drm_file
*file
,
2173 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2174 struct drm_file
*file
);
2175 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2176 struct drm_file
*file
);
2178 /* i915_gem_gtt.c */
2179 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
2180 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
2181 struct drm_i915_gem_object
*obj
,
2182 enum i915_cache_level cache_level
);
2183 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
2184 struct drm_i915_gem_object
*obj
);
2186 void i915_check_and_clear_faults(struct drm_device
*dev
);
2187 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
);
2188 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
2189 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
2190 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
2191 enum i915_cache_level cache_level
);
2192 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
2193 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
2194 void i915_gem_init_global_gtt(struct drm_device
*dev
);
2195 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
2196 unsigned long mappable_end
, unsigned long end
);
2197 int i915_gem_gtt_init(struct drm_device
*dev
);
2198 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2200 if (INTEL_INFO(dev
)->gen
< 6)
2201 intel_gtt_chipset_flush();
2205 /* i915_gem_evict.c */
2206 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2207 struct i915_address_space
*vm
,
2210 unsigned cache_level
,
2213 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2214 int i915_gem_evict_everything(struct drm_device
*dev
);
2216 /* i915_gem_stolen.c */
2217 int i915_gem_init_stolen(struct drm_device
*dev
);
2218 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
2219 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2220 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2221 struct drm_i915_gem_object
*
2222 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2223 struct drm_i915_gem_object
*
2224 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2228 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2230 /* i915_gem_tiling.c */
2231 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2233 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2235 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2236 obj
->tiling_mode
!= I915_TILING_NONE
;
2239 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2240 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2241 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2243 /* i915_gem_debug.c */
2245 int i915_verify_lists(struct drm_device
*dev
);
2247 #define i915_verify_lists(dev) 0
2250 /* i915_debugfs.c */
2251 int i915_debugfs_init(struct drm_minor
*minor
);
2252 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2253 #ifdef CONFIG_DEBUG_FS
2254 void intel_display_crc_init(struct drm_device
*dev
);
2256 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2259 /* i915_gpu_error.c */
2261 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2262 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2263 const struct i915_error_state_file_priv
*error
);
2264 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2265 size_t count
, loff_t pos
);
2266 static inline void i915_error_state_buf_release(
2267 struct drm_i915_error_state_buf
*eb
)
2271 void i915_capture_error_state(struct drm_device
*dev
);
2272 void i915_error_state_get(struct drm_device
*dev
,
2273 struct i915_error_state_file_priv
*error_priv
);
2274 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2275 void i915_destroy_error_state(struct drm_device
*dev
);
2277 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2278 const char *i915_cache_level_str(int type
);
2280 /* i915_suspend.c */
2281 extern int i915_save_state(struct drm_device
*dev
);
2282 extern int i915_restore_state(struct drm_device
*dev
);
2285 void i915_save_display_reg(struct drm_device
*dev
);
2286 void i915_restore_display_reg(struct drm_device
*dev
);
2289 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2290 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2293 extern int intel_setup_gmbus(struct drm_device
*dev
);
2294 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2295 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2297 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2300 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2301 struct drm_i915_private
*dev_priv
, unsigned port
);
2302 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2303 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2304 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2306 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2308 extern void intel_i2c_reset(struct drm_device
*dev
);
2310 /* intel_opregion.c */
2311 struct intel_encoder
;
2312 extern int intel_opregion_setup(struct drm_device
*dev
);
2314 extern void intel_opregion_init(struct drm_device
*dev
);
2315 extern void intel_opregion_fini(struct drm_device
*dev
);
2316 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2317 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2319 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2322 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2323 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2324 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2326 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2331 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2339 extern void intel_register_dsm_handler(void);
2340 extern void intel_unregister_dsm_handler(void);
2342 static inline void intel_register_dsm_handler(void) { return; }
2343 static inline void intel_unregister_dsm_handler(void) { return; }
2344 #endif /* CONFIG_ACPI */
2347 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2348 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2349 extern void intel_modeset_init(struct drm_device
*dev
);
2350 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2351 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2352 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2353 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2354 bool force_restore
);
2355 extern void i915_redisable_vga(struct drm_device
*dev
);
2356 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2357 extern void intel_disable_fbc(struct drm_device
*dev
);
2358 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2359 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2360 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2361 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2362 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2363 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2364 extern void intel_detect_pch(struct drm_device
*dev
);
2365 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2366 extern int intel_enable_rc6(const struct drm_device
*dev
);
2368 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2369 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2370 struct drm_file
*file
);
2373 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2374 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2375 struct intel_overlay_error_state
*error
);
2377 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2378 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2379 struct drm_device
*dev
,
2380 struct intel_display_error_state
*error
);
2382 /* On SNB platform, before reading ring registers forcewake bit
2383 * must be set to prevent GT core from power down and stale values being
2386 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2387 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2389 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2390 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2392 /* intel_sideband.c */
2393 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2394 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2395 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2396 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2397 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2398 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2399 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2400 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2401 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2402 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2403 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2404 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2405 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2406 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2407 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2408 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2409 enum intel_sbi_destination destination
);
2410 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2411 enum intel_sbi_destination destination
);
2413 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2414 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2416 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2417 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2419 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2420 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2421 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2422 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2424 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2425 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2426 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2427 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2429 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2430 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2432 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2433 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2435 /* "Broadcast RGB" property */
2436 #define INTEL_BROADCAST_RGB_AUTO 0
2437 #define INTEL_BROADCAST_RGB_FULL 1
2438 #define INTEL_BROADCAST_RGB_LIMITED 2
2440 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2442 if (HAS_PCH_SPLIT(dev
))
2443 return CPU_VGACNTRL
;
2444 else if (IS_VALLEYVIEW(dev
))
2445 return VLV_VGACNTRL
;
2450 static inline void __user
*to_user_ptr(u64 address
)
2452 return (void __user
*)(uintptr_t)address
;
2455 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2457 unsigned long j
= msecs_to_jiffies(m
);
2459 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2462 static inline unsigned long
2463 timespec_to_jiffies_timeout(const struct timespec
*value
)
2465 unsigned long j
= timespec_to_jiffies(value
);
2467 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);